JP2006120834A - ウェーハの分割方法 - Google Patents
ウェーハの分割方法 Download PDFInfo
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- JP2006120834A JP2006120834A JP2004306747A JP2004306747A JP2006120834A JP 2006120834 A JP2006120834 A JP 2006120834A JP 2004306747 A JP2004306747 A JP 2004306747A JP 2004306747 A JP2004306747 A JP 2004306747A JP 2006120834 A JP2006120834 A JP 2006120834A
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- 238000000034 method Methods 0.000 title claims abstract description 61
- 238000000227 grinding Methods 0.000 claims description 56
- 239000007789 gas Substances 0.000 claims description 43
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims description 10
- 229910052731 fluorine Inorganic materials 0.000 claims description 10
- 239000011737 fluorine Substances 0.000 claims description 10
- 239000007888 film coating Substances 0.000 claims description 6
- 238000009501 film coating Methods 0.000 claims description 6
- 230000001681 protective effect Effects 0.000 claims description 5
- 239000011248 coating agent Substances 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 2
- 229910052760 oxygen Inorganic materials 0.000 claims description 2
- 239000001301 oxygen Substances 0.000 claims description 2
- 238000001020 plasma etching Methods 0.000 abstract description 16
- 238000005520 cutting process Methods 0.000 abstract description 9
- 238000005530 etching Methods 0.000 description 21
- 238000005452 bending Methods 0.000 description 5
- 238000001816 cooling Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000005498 polishing Methods 0.000 description 4
- -1 SF 6 Chemical compound 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 230000003467 diminishing effect Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000003028 elevating effect Effects 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67132—Apparatus for placing on an insulating substrate, e.g. tape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67092—Apparatus for mechanical treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
- H01L21/31138—Etching organic layers by chemical means by dry-etching
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Dicing (AREA)
Abstract
【解決手段】ウェーハWの表面W1のうち、ストリート対応部W1S以外にレジスト膜Rを被覆し、ストリート対応部W1Sにプラズマエッチングによりデバイスの仕上がり厚さに対応する溝Gを形成し、ウェーハWの裏面W2を研削して溝Gを裏面側から表出させて個々のデバイスDに分割する。切削を行わないため欠けが生じず品質が向上し、すべてのストリートを一度に分離させるため効率的である。
【選択図】図1
Description
W1:表面
D:デバイス S:ストリート W1S:ストリート対応部
W2:裏面
P:保護部材 R:レジスト膜 B:支持部材
1:研削装置
10:チャックテーブル
11:研削手段
110:スピンドル 111:駆動源 112:ホイールマウント
113:研削ホイール 114:研削砥石 115:ポリッシングパッド
12:研削送り手段
120:壁部 121:ガイドレール 122:ボールネジ
123:パルスモータ 124:支持部
2:フォトマスク
2a:マスクパターン
3:スピンコータ
30:保持テーブル 31:ノズル
50:プラズマエッチング装置
51:ガス供給部 52:エッチング処理部 53…チャンバ
54:エッチングガス供給手段 55:チャックテーブル 56:軸受け
57:ガス流通孔 57a:噴出部 58:モータ 59:ボールネジ
60:昇降部 61:軸受け 62:吸引源 63:吸引路 64:冷却部
65:冷却路 66:開口部 67:シャッター 68:シリンダ 69:ピストン
70:ガス排出部 71:排気口 72:高周波電源
Claims (5)
- ストリートによって区画されて複数のデバイスが表面に形成されたウェーハを個々のデバイスに分割するウェーハの分割方法であって、
ウェーハの表面のうち、ストリートに対応する領域以外にレジスト膜を被覆するレジスト膜被覆工程と、
フッ素系安定ガスをプラズマ化して該ウェーハの表面に供給し、該ストリートに対応する領域にデバイスの仕上がり厚さに相当する深さの溝を形成する溝形成工程と、
該表面側に保護部材を貼着し、該ウェーハの裏面を研削して該溝を該裏面側から露出させる研削工程と
から構成されるウェーハの分割方法。 - 前記溝形成工程の後であって前記研削工程の前に、前記ウェーハの表面から前記レジスト膜を除去するレジスト膜除去工程が遂行される
請求項1に記載のウェーハの分割方法。 - 前記研削工程後に、前記ウェーハの裏面に残存している研削歪みを除去するストレスリリーフ工程が遂行される請求項1または2に記載のウェーハの分割方法。
- 前記フッ素系安定ガスは、SF6、CF4、C2F6、C2F4、CHF3のいずれかである請求項1、2または3に記載のウェーハの分割方法。
- 前記レジスト膜除去工程では、酸素をプラズマ化して前記レジスト膜に供給し、該レジスト膜を灰化させて除去する2、3または4に記載のウェーハの分割方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004306747A JP2006120834A (ja) | 2004-10-21 | 2004-10-21 | ウェーハの分割方法 |
US11/251,933 US20060088983A1 (en) | 2004-10-21 | 2005-10-18 | Method of dividing wafer |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004306747A JP2006120834A (ja) | 2004-10-21 | 2004-10-21 | ウェーハの分割方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2006120834A true JP2006120834A (ja) | 2006-05-11 |
Family
ID=36206699
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004306747A Pending JP2006120834A (ja) | 2004-10-21 | 2004-10-21 | ウェーハの分割方法 |
Country Status (2)
Country | Link |
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US (1) | US20060088983A1 (ja) |
JP (1) | JP2006120834A (ja) |
Cited By (9)
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WO2009119064A1 (ja) * | 2008-03-25 | 2009-10-01 | パナソニック株式会社 | 基板の加工方法および半導体チップの製造方法ならびに樹脂接着層付き半導体チップの製造方法 |
WO2010116767A1 (ja) * | 2009-04-10 | 2010-10-14 | パナソニック株式会社 | 基板の加工方法および半導体チップの製造方法ならびに樹脂接着層付き半導体チップの製造方法 |
WO2010116766A1 (ja) * | 2009-04-10 | 2010-10-14 | パナソニック株式会社 | 基板の加工方法および半導体チップの製造方法ならびに樹脂接着層付き半導体チップの製造方法 |
US9112019B2 (en) | 2013-11-25 | 2015-08-18 | Disco Corporation | Wafer processing utilizing a frame with a plurality of partitions |
US9123797B2 (en) | 2013-11-21 | 2015-09-01 | Disco Corporation | Resin powder wafer processing utilizing a frame with a plurality of partitions |
JP2015528212A (ja) * | 2012-07-13 | 2015-09-24 | アプライド マテリアルズ インコーポレイテッドApplied Materials,Incorporated | ウェハダイシングのためのレーザ、プラズマエッチング、及び裏面研削プロセス |
JP2016040795A (ja) * | 2014-08-12 | 2016-03-24 | 株式会社ディスコ | ウエーハの分割方法 |
US10679897B2 (en) | 2016-11-22 | 2020-06-09 | Disco Corporation | Device wafer processing method |
US10691090B2 (en) | 2017-09-12 | 2020-06-23 | Disco Corporation | Method of processing device wafer |
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US7473589B2 (en) * | 2005-12-09 | 2009-01-06 | Macronix International Co., Ltd. | Stacked thin film transistor, non-volatile memory devices and methods for fabricating the same |
US7315474B2 (en) | 2005-01-03 | 2008-01-01 | Macronix International Co., Ltd | Non-volatile memory cells, memory arrays including the same and methods of operating cells and arrays |
US8482052B2 (en) | 2005-01-03 | 2013-07-09 | Macronix International Co., Ltd. | Silicon on insulator and thin film transistor bandgap engineered split gate memory |
US7763927B2 (en) * | 2005-12-15 | 2010-07-27 | Macronix International Co., Ltd. | Non-volatile memory device having a nitride-oxide dielectric layer |
US7907450B2 (en) * | 2006-05-08 | 2011-03-15 | Macronix International Co., Ltd. | Methods and apparatus for implementing bit-by-bit erase of a flash memory device |
US8772858B2 (en) * | 2006-10-11 | 2014-07-08 | Macronix International Co., Ltd. | Vertical channel memory and manufacturing method thereof and operating method using the same |
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-
2004
- 2004-10-21 JP JP2004306747A patent/JP2006120834A/ja active Pending
-
2005
- 2005-10-18 US US11/251,933 patent/US20060088983A1/en not_active Abandoned
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