JP2006060173A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

A semiconductor device including a MIS transistor having two or more types of gate insulating films and gate electrodes on the same semiconductor substrate and a method for manufacturing the same are provided.
A first NMIS transistor formation area AreaA of a semiconductor substrate 11 includes a gate insulating film 21a made of a metal oxide film such as a hafnium oxide film and a gate electrode 22a made of a metal film such as a tungsten film. One NMIS transistor is formed. In the second NMIS transistor formation area AreaC of the semiconductor substrate 11, a second NMIS transistor having a gate insulating film 13 made of a silicon oxide film and a gate electrode 14c made of a semiconductor material such as a polysilicon film is formed. . The gate electrode 22a has a damascene structure formed by embedding a metal film in a gate electrode formation opening 20a provided by removing the first dummy gate electrode 14a formed simultaneously with the gate electrode 14c.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a plurality of types of MIS transistors having different gate electrode materials on the same semiconductor substrate and a manufacturing method thereof.

  In the MIS transistor, it is essential to shorten the gate dimension in order to improve the performance of the element. However, the silicon oxide film currently used as the gate insulating film has a low dielectric constant and has reached its limit. In addition, the polysilicon used as the gate electrode has a high resistivity, and there is a problem that the resistance of the gate electrode cannot be reduced.

  Therefore, in recent years, it has been proposed to use a high dielectric material for the gate insulating film and a metal material for the gate electrode in order to solve these problems (for example, see Patent Document 1).

  Hereinafter, a method for manufacturing a semiconductor device using a conventional damascene gate technique will be described with reference to the drawings.

  FIG. 5A to FIG. 5F are cross-sectional views showing a manufacturing process of a semiconductor device using a conventional damascene gate technique. In the drawing, the left region shows the NMIS transistor formation region AreaA, and the right region shows the PMIS transistor formation region AreaB.

  First, in the step shown in FIG. 5A, the P well region 101a is formed in the NMIS transistor formation region AreaA of the semiconductor substrate 101, and the N well region 101b is formed in the PMIS transistor formation region AreaB of the semiconductor substrate 101. Then, a trench type element isolation region 102 surrounding the active region of each element formation region is formed on the semiconductor substrate 101.

  Next, in the step shown in FIG. 5B, an insulating film 103 made of a silicon oxide film and a polysilicon film are sequentially formed on the semiconductor substrate 101. Thereafter, the polysilicon film is patterned to form a first dummy gate electrode 104a in the NMIS transistor formation area AreaA, and a second dummy gate electrode 104b in the PMIS transistor formation area AreaB. Thereafter, ion implantation of n-type impurities is performed in the NMIS transistor formation area AreaA using the first dummy gate electrode 104a and a resist (not shown) as a mask to form an n-type LDD region 105a. In the PMIS transistor formation area AreaB, p-type LDD regions 105b are formed by ion implantation of p-type impurities using the second dummy gate electrode 104b and a resist (not shown) as a mask.

  Next, in the step shown in FIG. 5C, after the silicon oxide film is formed on the entire surface of the substrate, the silicon oxide film is etched back to thereby form the first dummy gate electrode 104a and the second dummy gate. Insulating sidewalls 106a and 106b are formed on the side surfaces of the electrode 104b. After that, n-type impurity ions are implanted into the NMIS transistor formation area AreaA by using the first dummy gate electrode 104a, the sidewall 106a, and a resist (not shown) as a mask to form the n-type source / drain region 107a. Form. Further, in the PMIS transistor formation area AreaB, p-type impurity ions are implanted using the second dummy gate electrode 104b, the sidewall 106b, and a resist (not shown) as a mask to form a p-type source / drain region 107b. Form. Thereafter, heat treatment is performed on the substrate to activate the implanted impurities.

  Next, in the step shown in FIG. 5D, after the silicon oxide film is formed on the entire surface of the semiconductor substrate 101, the upper surfaces of the first dummy gate electrode 104a and the second dummy gate electrode 104b are formed by CMP. The silicon oxide film is planarized until it is exposed, and an interlayer insulating film 108 is formed in the NMIS transistor formation area AreaA and the PMIS transistor formation area AreaB.

  Next, in the step shown in FIG. 5E, the first dummy gate electrode 104a and the second dummy gate electrode 104b whose upper surfaces are exposed and the insulating film 103 formed immediately below the first dummy gate electrode 104a are selectively removed. Thus, gate electrode formation openings 109a and 109b are formed.

  Next, in the process shown in FIG. 5F, an insulating film and a metal film are sequentially formed on the entire surface of the semiconductor substrate 101. Thereafter, unnecessary metal films and insulating films on the interlayer insulating film 108 are removed by CMP, and a gate insulating film 110a made of an insulating film and a gate electrode 111a made of a metal film are formed in the gate electrode forming opening 109a. A gate insulating film 110b made of an insulating film and a gate electrode 111b made of a metal film are formed in the gate electrode forming opening 109b.

According to this method, the gate insulating film and the gate electrode can be formed after the activation annealing step of the source / drain region which is a high temperature heat treatment.
JP 2000-315789 A

  However, in the method of manufacturing a semiconductor device using the conventional damascene gate technology as described above, when a gate insulating film having two or more kinds of film thickness is formed on the same substrate, a state in which an opening for forming a gate electrode is formed Therefore, there is a problem that a resist residue is generated in a minute opening for forming a gate electrode.

  In addition, when two types of gate insulating films having different insulating materials are formed by a conventional manufacturing method, one gate insulating film is formed of a single layer film, while the other gate insulating film is formed of a laminated film. . For this reason, in the case of a gate insulating film made of a laminated film, there arises a problem that the reliability is inferior compared to a gate insulating film made of a single layer film.

  Furthermore, the conventional manufacturing method has a problem that it is difficult to form a MIS transistor having a high-resistance gate electrode used in an electrostatic discharge (ESD) protection circuit or the like on the same substrate.

  An object of the present invention is to provide a semiconductor device capable of easily forming a MIS transistor having two or more types of gate insulating films and gate electrodes on the same semiconductor substrate, and a method for manufacturing the same.

  A semiconductor device according to the present invention includes a first MIS type transistor formed in a first transistor formation region on a semiconductor substrate and a second MIS type transistor formed in a second transistor formation region on the semiconductor substrate. In the semiconductor device provided, the first MIS transistor includes a first gate insulating film made of the first insulating film formed on the semiconductor substrate and a metal material formed on the first gate insulating film. The second MIS type transistor is formed on the second gate insulating film made of the second insulating film formed on the semiconductor substrate, and on the second gate insulating film. And a second gate electrode made of a semiconductor material.

  In the semiconductor device, the first MIS transistor includes a first sidewall formed on a side surface of the first gate electrode, and a semiconductor substrate in the first transistor formation region. A first interlayer insulating film formed at substantially the same height as the upper surface, and the second MIS transistor includes a second sidewall formed on the side surface of the second gate electrode, A second interlayer insulating film formed on the semiconductor substrate in the second transistor formation region so as to cover the upper surfaces of the second gate electrode and the second sidewall is further provided.

  In the semiconductor device, the first MIS transistor includes a first gate electrode formed on a first sidewall formed on a lower side surface of the first gate electrode and a semiconductor substrate in a first transistor formation region. And an interlayer insulating film formed at substantially the same height as the upper surface of the second MIS transistor. The second MIS transistor includes a second sidewall formed on the side surface of the second gate electrode, And an interlayer insulating film formed on the semiconductor substrate in the transistor formation region so as to cover the upper surfaces of the second gate electrode and the second sidewall, and the upper surface of the first gate electrode is The first sidewall and the second sidewall are formed at a height equal to or lower than the upper surface of the second gate electrode.

  In the semiconductor device, the first MIS transistor includes a first gate electrode formed on a first sidewall formed on a lower side surface of the first gate electrode and a semiconductor substrate in a first transistor formation region. The second MIS transistor is a flash memory transistor in which the second gate electrode is a floating gate electrode, and is provided with a floating gate electrode. A second sidewall formed on the side surface of the capacitor, a capacitor insulating film made of the first insulating film formed on the floating gate electrode, and a control gate electrode made of a metal material formed on the capacitor insulating film; And an interlayer insulating film formed on the semiconductor substrate in the second transistor formation region at substantially the same height as the upper surface of the control gate electrode. The first gate electrode The upper surface is formed at substantially the same height as the upper surface of the control gate electrode, and the first sidewall and the second sidewall are formed at a height equal to or lower than the upper surface of the floating gate electrode. .

  In the semiconductor device, the first gate electrode has a wider pattern width in the upper region located above the first sidewall than in the lower region sandwiched between the first sidewalls.

  In the semiconductor device, a first gate insulating film is formed between the first gate electrode and the first sidewall.

  In the semiconductor device, the first gate insulating film is a high dielectric film.

  The method for manufacturing a semiconductor device according to the present invention includes a first MIS transistor having a first gate electrode formed in a first transistor formation region on a semiconductor substrate, and a second transistor formation region on a semiconductor substrate. In a method for manufacturing a semiconductor device including a second MIS transistor having a formed second gate electrode, a step (a) of forming a second insulating film on a semiconductor substrate, and a first transistor formation region Forming a dummy gate electrode made of a semiconductor material on the second insulating film and forming a second gate electrode made of a semiconductor material on the second insulating film in the second transistor formation region (b) Then, after the step (b), the step (c) of selectively removing the dummy gate electrode in the first transistor formation region and the second insulating film located thereunder, and the step (c) (D) forming a first gate insulating film made of the first insulating film on the semiconductor substrate of the first transistor formation region from which the second insulating film has been removed; And a step (e) of forming a first gate electrode made of a metal material on the film, and a second gate insulating film made of the second insulating film is formed under the second gate electrode. Yes.

  In the method of manufacturing the semiconductor device, after the step (b) and before the step (c), the first sidewall is formed on the side surface of the dummy gate electrode, and the first side wall is formed on the side surface of the second gate electrode. A first step of forming the second sidewall, and after the first step, the second gate electrode and the second sidewall are covered on the semiconductor substrate in the second transistor formation region so as to cover the upper surface of the second sidewall. A second step of forming the second interlayer insulating film, and a second step having a height substantially the same as the upper surface of the first gate electrode on the semiconductor substrate in the first transistor formation region after the second step. And a third step of forming one interlayer insulating film.

  In the method of manufacturing the semiconductor device, after the step (b) and before the step (c), the first sidewall is formed on the side surface of the dummy gate electrode, and the first side wall is formed on the side surface of the second gate electrode. A first step of forming the second sidewall, and a second step of forming an interlayer insulating film on the semiconductor substrate so as to cover the upper surfaces of the dummy gate electrode and the second gate electrode after the first step. And a third step of forming a first opening reaching the dummy gate electrode by removing the interlayer insulating film on the dummy gate electrode after the second step.

  In the semiconductor device manufacturing method, the second MIS transistor is a flash memory transistor having the second gate electrode as a floating gate electrode, and a dummy gate is provided after step (b) and before step (c). A first step of forming a first sidewall on the side surface of the electrode and a second sidewall on the side surface of the second gate electrode; and after the first step, on the semiconductor substrate, A second step of forming an interlayer insulating film so as to cover the upper surfaces of the dummy gate electrode and the second gate electrode; and after the second step, the interlayer insulating film on the dummy gate electrode is removed and the dummy gate electrode Forming a first opening reaching the first opening, and in the step (c), a dummy gate electrode exposed in the first opening and a second insulating film located thereunder are selectively formed. Remove and process ( ) And before the step (d), there is a step of removing the interlayer insulating film on the second gate electrode to form a second opening reaching the second gate electrode, In d), a first gate insulating film made of the first insulating film is formed on the semiconductor substrate exposed in the first opening, and on the second gate electrode exposed in the second opening. A capacitor insulating film made of a first insulating film is formed. In step (e), a first gate electrode made of a metal material is formed on the first gate insulating film, and a metal material is formed on the capacitor insulating film. A control gate electrode is formed.

  According to the present invention, two or more types of gate insulating films are formed on the same semiconductor substrate by forming the second gate electrode simultaneously with the dummy gate electrode for forming the first gate electrode having the damascene structure. In addition, a MIS transistor having a gate electrode can be easily formed.

(First embodiment)
Hereinafter, a semiconductor device manufacturing method according to a first embodiment of the present invention will be described with reference to the drawings.

  FIG. 1A to FIG. 1F are cross-sectional views showing a manufacturing process of a semiconductor device according to the first embodiment of the present invention. In the figure, the left region shows the first NMIS transistor formation region AreaA, the central region shows the PMIS transistor formation region AreaB, and the right region shows the second NMIS transistor formation region AreaC.

  First, in the step shown in FIG. 1A, the P well region 11a is formed in the first NMIS transistor formation area AreaA and the second NMIS transistor formation area AreaC of the semiconductor substrate 11, and the PMIS transistor formation area of the semiconductor substrate 11 is formed. An N well region 11b is formed in AreaB. Then, a trench type element isolation region 12 surrounding the active region of each element formation region is formed in the semiconductor substrate 11.

  Next, in the step shown in FIG. 1B, an insulating film 13 made of a silicon oxide film having a thickness of 7 nm and a polysilicon film having a thickness of 200 nm are sequentially formed on the semiconductor substrate 11. Thereafter, the polysilicon film is patterned to form the first dummy gate electrode 14a in the first NMIS transistor formation area AreaA, the second dummy gate electrode 14b in the PMIS transistor formation area AreaB, and the second dummy gate electrode 14b. A gate electrode 14c is formed in the NMIS transistor formation region AreaC. Thereafter, n-type impurity ions are implanted into the first NMIS transistor formation area AreaA and the second NMIS transistor formation area AreaC using the first dummy gate electrode 14a, the gate electrode 14c, and a resist (not shown) as a mask. To form a first n-type diffusion region 15a and a second n-type diffusion region 15c to be an n-type LDD region or an n-type extension region. The PMIS transistor formation area AreaB becomes a p-type LDD region or a p-type extension region by ion implantation of p-type impurities using the second dummy gate electrode 14b and a resist (not shown) as a mask. A p-type diffusion region 15b is formed.

  Next, in the step shown in FIG. 1C, a silicon oxide film having a thickness of 15 nm is formed on the entire surface of the substrate, and then the silicon oxide film is etched back, whereby the first dummy gate electrode 14a, Insulating sidewalls 16a, 16b, and 16c are formed on the side surfaces of the second dummy gate electrode 14b and the gate electrode 14c. Thereafter, the first dummy gate electrode 14a, the gate electrode 14c, the sidewalls 16a and 16c, and a resist (not shown) are used as a mask in the first NMIS transistor formation area AreaA and the second NMIS transistor formation area AreaC. N-type impurity ions are implanted to form the first n-type source / drain region 17a and the second n-type source / drain region 17c. Further, in the PMIS transistor formation area AreaB, ion implantation of p-type impurities is performed using the second dummy gate electrode 14b, the sidewall 16b, and a resist (not shown) as a mask to form a p-type source / drain region 17b. Form. Thereafter, the substrate is heat-treated at 1000 ° C. to activate the implanted impurities.

  Next, in a step shown in FIG. 1D, after a silicon nitride film having a thickness of 300 nm is formed on the entire surface of the semiconductor substrate 11, the surface of the silicon nitride film is planarized by CMP or the like. Thereafter, a resist (not shown) is formed on the silicon nitride film, covering the second NMIS transistor formation area AreaC and having openings in the first NMIS transistor formation area AreaA and the PMIS transistor formation area AreaB. Thereafter, using the resist as a mask, the silicon nitride film is selectively etched to form a first interlayer insulating film 18 in the second NMIS transistor formation area AreaC. Thereafter, a BPSG film 19A having a thickness of 600 nm is formed on the entire surface of the semiconductor substrate 11.

  Next, in the step shown in FIG. 1E, the BPSG film 19A on the first interlayer insulating film 18 is removed by CMP and the first dummy gate electrode 14a and the second dummy gate electrode 14b are removed. The BPSG film 19A is planarized until the upper surface is exposed, and the second interlayer insulating film 19 is formed in the first NMIS transistor formation area AreaA and the PMIS transistor formation area AreaB. In this CMP, even if the upper surfaces of the first dummy gate electrode 14a and the second dummy gate electrode 14b are exposed by performing the BPSG film at a higher polishing rate than the silicon nitride film, the gate electrode The first interlayer insulating film 18 can remain on 14c. Thereafter, the first dummy gate electrode 14a and the second dummy gate electrode 14b whose upper surfaces are exposed and the insulating film 13 formed immediately below the gate electrode formation openings 20a and 20b are selectively removed. Form.

  Next, in the step shown in FIG. 1F, a 5 nm-thick hafnium oxide film is formed on the entire surface of the semiconductor substrate 11, and then a 250-nm-thick tungsten film is formed on the hafnium oxide film. Thereafter, unnecessary tungsten film and hafnium oxide film on the first interlayer insulating film 18 and the second interlayer insulating film 19 are removed by CMP, and the gate electrode forming opening 20a is made of a hafnium oxide film. A gate electrode 22a having a damascene structure made of a gate insulating film 21a and a tungsten film is formed, and a gate insulating film 21b made of a hafnium oxide film and a damascene gate electrode 22b made of a tungsten film are formed in the gate electrode formation opening 20b. To do. In the second NMIS transistor formation area AreaC, the insulating film 13 located under the gate electrode 14c among the remaining insulating film 13 becomes the gate insulating film as it is.

  By the method as described above, the first NMIS transistor having the damascene gate electrode 22a made of the tungsten film formed on the gate insulating film 21a made of the hafnium oxide film is formed in the first NMIS transistor formation region AreaA. A PMIS transistor having a damascene gate electrode 22b made of a tungsten film formed on a gate insulating film 21b made of a hafnium oxide film is formed in the PMIS transistor formation area AreaB, and is formed in the second NMIS transistor formation area AreaC. A second NMIS transistor having a gate electrode 14c made of a polysilicon film formed on the gate insulating film 13 made of a silicon oxide film is formed.

  According to the present embodiment, the first NMIS transistor having the gate insulating film 21a made of a metal oxide film such as a hafnium oxide film and the gate electrode 22a made of a metal film such as a tungsten film on the same semiconductor substrate 11. And a second NMIS transistor having a gate insulating film 13 made of a silicon oxide film and a gate electrode 14c made of a semiconductor film such as a polysilicon film can be formed. In addition, a metal oxide film such as a hafnium oxide film that becomes the gate insulating films 21a and 21b is formed after activation annealing for activating the implanted impurities in the source / drain regions 17a, 17b, and 17c that are subjected to high-temperature heat treatment. Degradation of the metal oxide film due to high-temperature heat treatment can be avoided. In addition, since the gate electrode 14c made of a semiconductor film is formed simultaneously with the dummy gate electrodes 14a, 14b for forming the gate electrodes 22a, 22b made of a metal film, an increase in manufacturing steps can be suppressed. Furthermore, since the gate insulating films 21a and 21b made of a metal oxide film are formed separately from the step of forming the gate insulating film 13 made of a silicon oxide film, the reliability of the gate insulating film can be improved.

(Second Embodiment)
A semiconductor device manufacturing method according to the second embodiment of the present invention will be described below with reference to the drawings.

  FIG. 2A to FIG. 2F are cross-sectional views showing a manufacturing process of a semiconductor device according to the second embodiment of the present invention. In the figure, the left region shows the first NMIS transistor formation region AreaA, the central region shows the PMIS transistor formation region AreaB, and the right region shows the second NMIS transistor formation region AreaC. In addition, the same code | symbol is attached | subjected to the same component as 1st Embodiment.

  First, in the step shown in FIG. 2A, the P well region 11a is formed in the first NMIS transistor forming area AreaA and the second NMIS transistor forming area AreaC of the semiconductor substrate 11, and the PMIS transistor forming area of the semiconductor substrate 11 is formed. An N well region 11b is formed in AreaB. Then, a trench type element isolation region 12 surrounding the active region of each element formation region is formed in the semiconductor substrate 11.

  Next, in the step shown in FIG. 2B, an insulating film 13 made of a silicon oxide film having a thickness of 7 nm and a polysilicon film having a thickness of 200 nm are sequentially formed on the semiconductor substrate 11. Thereafter, the polysilicon film is patterned to form the first dummy gate electrode 14a in the first NMIS transistor formation area AreaA, the second dummy gate electrode 14b in the PMIS transistor formation area AreaB, and the second dummy gate electrode 14b. A gate electrode 14c is formed in the NMIS transistor formation region AreaC. Thereafter, n-type impurity ions are implanted into the first NMIS transistor formation area AreaA and the second NMIS transistor formation area AreaC using the first dummy gate electrode 14a, the gate electrode 14c, and a resist (not shown) as a mask. To form a first n-type diffusion region 15a and a second n-type diffusion region 15c to be an n-type LDD region or an n-type extension region. The PMIS transistor formation area AreaB becomes a p-type LDD region or a p-type extension region by ion implantation of p-type impurities using the second dummy gate electrode 14b and a resist (not shown) as a mask. A p-type diffusion region 15b is formed.

  Next, in the step shown in FIG. 2C, a silicon oxide film having a thickness of 15 nm is formed on the entire surface of the substrate, and then the silicon oxide film is etched back, whereby the first dummy gate electrode 14a, Insulating sidewalls 16a, 16b, and 16c are formed on the side surfaces of the second dummy gate electrode 14b and the gate electrode 14c. Thereafter, the first dummy gate electrode 14a, the gate electrode 14c, the sidewalls 16a and 16c, and a resist (not shown) are used as a mask in the first NMIS transistor formation area AreaA and the second NMIS transistor formation area AreaC. N-type impurity ions are implanted to form the first n-type source / drain region 17a and the second n-type source / drain region 17c. Further, in the PMIS transistor formation area AreaB, ion implantation of p-type impurities is performed using the second dummy gate electrode 14b, the sidewall 16b, and a resist (not shown) as a mask to form a p-type source / drain region 17b. Form. Thereafter, the substrate is heat-treated at 1000 ° C. to activate the implanted impurities.

  Next, in the step shown in FIG. 2D, after forming a BPSG film having a thickness of 500 nm on the entire surface of the semiconductor substrate 11, the surface of the BPSG film is planarized by CMP or the like to form an interlayer insulating film 23. To do. Thereafter, a resist (not shown) having an opening is formed on the interlayer insulating film 23 on the first dummy gate electrode 14a and the second dummy gate electrode 14b. Thereafter, using the resist as a mask, the interlayer insulating film 23 is selectively etched to form openings 24A and 24B reaching the first dummy gate electrode 14a and the second dummy gate electrode 14b. At this time, the openings 24A and 24B are formed with substantially the same pattern width as that of the first dummy gate electrode 14a and the second dummy gate electrode 14b.

  Next, in the step shown in FIG. 2E, the first dummy gate electrode 14a and the second dummy gate electrode 14b exposed in the openings 24A and 24B and the insulating film 13 formed immediately below the first dummy gate electrode 14a and the second dummy gate electrode 14b. Are selectively removed to form gate electrode formation openings 24a and 24b.

  Next, in a step shown in FIG. 2F, a 5 nm-thick hafnium oxide film is formed on the entire surface of the semiconductor substrate 11, and then a 250-nm-thick tungsten film is formed on the hafnium oxide film. Thereafter, an unnecessary tungsten film and hafnium oxide film on the interlayer insulating film 23 are removed by CMP, and a gate insulating film 25a made of a hafnium oxide film and a damascene structure made of a tungsten film are formed in the gate electrode formation opening 24a. The gate electrode 26a is formed, and a gate insulating film 25b made of a hafnium oxide film and a damascene gate electrode 26b made of a tungsten film are formed in the gate electrode formation opening 24b. In the second NMIS transistor formation area AreaC, the insulating film 13 located under the gate electrode 14c among the remaining insulating film 13 becomes the gate insulating film as it is.

  By the above method, the first NMIS transistor having the damascene gate electrode 26a made of the tungsten film formed on the gate insulating film 25a made of the hafnium oxide film is formed in the first NMIS transistor formation region AreaA. A PMIS transistor having a damascene gate electrode 26b made of a tungsten film formed on a gate insulating film 25b made of a hafnium oxide film is formed in the PMIS transistor formation area AreaB, and is formed in the second NMIS transistor formation area AreaC. A second NMIS transistor having a gate electrode 14c made of a polysilicon film formed on the gate insulating film 13 made of a silicon oxide film is formed.

  According to this embodiment, as in the first embodiment, a damascene made of a gate insulating film 25a made of a metal oxide film such as a hafnium oxide film and a metal film such as a tungsten film on the same semiconductor substrate 11. A semiconductor device comprising a first NMIS transistor having a gate electrode 26a having a structure, and a second NMIS transistor having a gate insulating film 13 made of a silicon oxide film and a gate electrode 14c made of a semiconductor film such as a polysilicon film. Can be formed. Moreover, a metal oxide film such as a hafnium oxide film that becomes the gate insulating films 25a and 25b is formed after activation annealing for activating the implanted impurities in the source / drain regions 17a, 17b, and 17c, which are subjected to high-temperature heat treatment. Degradation of the metal oxide film due to high-temperature heat treatment can be avoided. Further, since the gate electrode 14c made of a semiconductor film is formed simultaneously with the dummy gate electrodes 14a, 14b for forming the gate electrodes 26a, 26b made of a metal film, an increase in the manufacturing process can be suppressed. Further, since the gate insulating films 25a and 25b made of a metal oxide film are formed separately from the step of forming the gate insulating film 13 made of a silicon oxide film, the reliability of the gate insulating film can be improved.

(Third embodiment)
A method for manufacturing a semiconductor device according to the third embodiment of the present invention will be described below with reference to the drawings.

  FIG. 3A to FIG. 3F are cross-sectional views showing manufacturing steps of the semiconductor device according to the third embodiment of the present invention. In the figure, the left region shows the first NMIS transistor formation region AreaA, the central region shows the PMIS transistor formation region AreaB, and the right region shows the second NMIS transistor formation region AreaC. In addition, the same code | symbol is attached | subjected to the same component as 1st Embodiment.

  First, in the step shown in FIG. 3A, the P well region 11a is formed in the first NMIS transistor forming area AreaA and the second NMIS transistor forming area AreaC of the semiconductor substrate 11, and the PMIS transistor forming area of the semiconductor substrate 11 is formed. An N well region 11b is formed in AreaB. Then, a trench type element isolation region 12 surrounding the active region of each element formation region is formed in the semiconductor substrate 11.

  Next, in the step shown in FIG. 3B, an insulating film 13 made of a silicon oxide film having a thickness of 7 nm and a polysilicon film having a thickness of 200 nm are sequentially formed on the semiconductor substrate 11. Thereafter, the polysilicon film is patterned to form the first dummy gate electrode 14a in the first NMIS transistor formation area AreaA, the second dummy gate electrode 14b in the PMIS transistor formation area AreaB, and the second dummy gate electrode 14b. A gate electrode 14c is formed in the NMIS transistor formation region AreaC. Thereafter, n-type impurity ions are implanted into the first NMIS transistor formation area AreaA and the second NMIS transistor formation area AreaC using the first dummy gate electrode 14a, the gate electrode 14c, and a resist (not shown) as a mask. To form a first n-type diffusion region 15a and a second n-type diffusion region 15c to be an n-type LDD region or an n-type extension region. The PMIS transistor formation area AreaB becomes a p-type LDD region or a p-type extension region by ion implantation of p-type impurities using the second dummy gate electrode 14b and a resist (not shown) as a mask. A p-type diffusion region 15b is formed.

  Next, in the step shown in FIG. 3C, a silicon oxide film having a thickness of 15 nm is formed on the entire surface of the substrate, and then the silicon oxide film is etched back, whereby the first dummy gate electrode 14a, Insulating sidewalls 16a, 16b, and 16c are formed on the side surfaces of the second dummy gate electrode 14b and the gate electrode 14c. Thereafter, the first dummy gate electrode 14a, the gate electrode 14c, the sidewalls 16a and 16c, and a resist (not shown) are used as a mask in the first NMIS transistor formation area AreaA and the second NMIS transistor formation area AreaC. N-type impurity ions are implanted to form the first n-type source / drain region 17a and the second n-type source / drain region 17c. Further, in the PMIS transistor formation area AreaB, ion implantation of p-type impurities is performed using the second dummy gate electrode 14b, the sidewall 16b, and a resist (not shown) as a mask to form a p-type source / drain region 17b. Form. Thereafter, the substrate is heat-treated at 1000 ° C. to activate the implanted impurities.

  Next, in the step shown in FIG. 3D, after forming a BPSG film having a thickness of 500 nm on the entire surface of the semiconductor substrate 11, the surface of the BPSG film is planarized by CMP or the like to form the interlayer insulating film 27. To do. Thereafter, a resist (not shown) having openings on the first dummy gate electrode 14 a and the second dummy gate electrode 14 b is formed on the interlayer insulating film 27. Thereafter, using the resist as a mask, the interlayer insulating film 27 is selectively etched to form openings 28A and 28B reaching the first dummy gate electrode 14a and the second dummy gate electrode 14b. At this time, the openings 28A and 28B are formed to have a wider pattern width than the first dummy gate electrode 14a and the second dummy gate electrode 14b.

  Next, in the step shown in FIG. 3E, the first dummy gate electrode 14a and the second dummy gate electrode 14b exposed in the openings 28A and 28B and the insulating film 13 formed immediately therebelow. Are selectively removed to form gate electrode formation openings 28a and 28b.

  Next, in the step shown in FIG. 3F, a 5 nm-thick hafnium oxide film is formed on the entire surface of the semiconductor substrate 11, and then a 250-nm-thick tungsten film is formed on the hafnium oxide film. Thereafter, unnecessary tungsten film and hafnium oxide film on the interlayer insulating film 27 are removed by CMP, and a gate insulating film 29a made of a hafnium oxide film and a damascene structure made of a tungsten film are formed in the gate electrode formation opening 28a. The gate electrode 30a is formed, and a gate insulating film 29b made of a hafnium oxide film and a damascene gate electrode 30b made of a tungsten film are formed in the gate electrode formation opening 28b. In the second NMIS transistor formation region AreaC, the insulating film 13 located under the gate electrode 14c among the remaining insulating film 13 becomes the gate insulating film as it is.

  By the above method, the first NMIS transistor having the damascene gate electrode 30a made of the tungsten film formed on the gate insulating film 29a made of the hafnium oxide film is formed in the first NMIS transistor formation region AreaA. In the PMIS transistor formation area AreaB, a PMIS transistor having a damascene gate electrode 30b made of a tungsten film formed on the gate insulating film 29b made of a hafnium oxide film is formed, and is formed in the second NMIS transistor formation area AreaC. A second NMIS transistor having a gate electrode 14c made of a polysilicon film formed on the gate insulating film 13 made of a silicon oxide film is formed.

  According to this embodiment, as in the first and second embodiments, the gate insulating film 29a made of a metal oxide film such as a hafnium oxide film and a metal film such as a tungsten film are formed on the same semiconductor substrate 11. A first NMIS transistor having a damascene gate electrode 30a, and a second NMIS transistor having a gate insulating film 13 made of a silicon oxide film and a gate electrode 14c made of a semiconductor film such as a polysilicon film. A semiconductor device can be formed. Moreover, a metal oxide film such as a hafnium oxide film that becomes the gate insulating films 29a and 29b is formed after activation annealing for activating the implanted impurities in the source / drain regions 17a, 17b, and 17c, which are subjected to high-temperature heat treatment. Degradation of the metal oxide film due to high-temperature heat treatment can be avoided. In addition, since the gate electrode 14c made of a semiconductor film is formed simultaneously with the dummy gate electrodes 14a, 14b for forming the gate electrodes 30a, 30b made of a metal film, an increase in manufacturing steps can be suppressed. Further, since the gate insulating films 29a and 29b made of the metal oxide film are formed separately from the step of forming the gate insulating film 13 made of the silicon oxide film, the reliability of the gate insulating film can be improved.

  Furthermore, the gate electrodes 30a and 30b of this embodiment have a wider pattern width in the upper region located above the sidewalls 16a and 16b than in the lower region sandwiched between the sidewalls 16a and 16b. As compared with the second embodiment, the resistance of the gate electrode can be reduced.

  Further, by combining this embodiment and the second embodiment, two types of MIS transistors having different gate electrode cross-sectional structures can be formed on the same semiconductor substrate in the same manufacturing process.

(Fourth embodiment)
A semiconductor device manufacturing method according to the fourth embodiment of the present invention will be described below with reference to the drawings.

  FIG. 4A to FIG. 4F are cross-sectional views showing manufacturing steps of the semiconductor device according to the fourth embodiment of the present invention. In the drawing, the left side region shows the first NMIS transistor formation region AreaA, the central region shows the PMIS transistor formation region AreaB, and the right side region shows the flash memory cell formation region AreaD. In addition, the same code | symbol is attached | subjected to the same component as 2nd Embodiment.

  First, in the step shown in FIG. 4A, the P well region 11a is formed in the first NMIS transistor forming area AreaA and the flash memory cell forming area AreaD of the semiconductor substrate 11, and the PMIS transistor forming area AreaB of the semiconductor substrate 11 is formed. N well region 11b is formed. Then, a trench type element isolation region 12 surrounding the active region of each element formation region is formed in the semiconductor substrate 11.

  Next, in a step shown in FIG. 4B, an insulating film 31 made of a silicon oxide film having a thickness of 9 nm and an n-type doped polysilicon film having a thickness of 200 nm are sequentially formed on the semiconductor substrate 11. Thereafter, the n-type doped polysilicon film is patterned to form a first dummy gate electrode 32a in the first NMIS transistor formation area AreaA, and a second dummy gate electrode 32b in the PMIS transistor formation area AreaB. A floating gate electrode 32c is formed in the flash memory cell formation area AreaD. Thereafter, n-type impurity ions are implanted into the first NMIS transistor formation area AreaA and the flash memory cell formation area AreaD using the first dummy gate electrode 32a, the floating gate electrode 32c, and a resist (not shown) as a mask. As a result, a first n-type diffusion region 15a and a second n-type diffusion region 15c to be an n-type LDD region or an n-type extension region are formed. The PMIS transistor formation area AreaB becomes a p-type LDD region or a p-type extension region by ion implantation of p-type impurities using the second dummy gate electrode 32b and a resist (not shown) as a mask. A p-type diffusion region 15b is formed.

  Next, in the step shown in FIG. 4C, a silicon oxide film having a thickness of 15 nm is formed on the entire surface of the substrate, and then the silicon oxide film is etched back, whereby the first dummy gate electrode 32a, Insulating sidewalls 16a, 16b, and 16c are formed on the side surfaces of the second dummy gate electrode 32b and the floating gate electrode 32c. Thereafter, the first dummy gate electrode 32a, the floating gate electrode 32c, the sidewalls 16a and 16c, and the resist (not shown) are used as masks in the first NMIS transistor formation area AreaA and the flash memory cell formation area AreaD. The first n-type source / drain region 17a and the second n-type source / drain region 17c are formed by ion implantation of the type impurity. Also, in the PMIS transistor formation area AreaB, p-type impurity ions are implanted using the second dummy gate electrode 32b, the sidewall 16b, and a resist (not shown) as a mask to form a p-type source / drain region 17b. Form. Thereafter, the substrate is heat-treated at 1000 ° C. to activate the implanted impurities.

  Next, in the step shown in FIG. 4D, after forming a BPSG film having a thickness of 400 nm on the entire surface of the semiconductor substrate 11, the surface of the BPSG film is planarized by CMP or the like to form the interlayer insulating film 23. To do. Thereafter, a resist (not shown) having an opening is formed on the interlayer insulating film 23 on the first dummy gate electrode 32a and the second dummy gate electrode 32b. Thereafter, using the resist as a mask, the interlayer insulating film 23 is selectively etched to form openings 24A and 24B reaching the first dummy gate electrode 32a and the second dummy gate electrode 32b. At this time, the openings 24A and 24B are formed with substantially the same pattern width as the first dummy gate electrode 32a and the second dummy gate electrode 32b.

  Next, in the step shown in FIG. 4E, the first dummy gate electrode 32a and the second dummy gate electrode 32b exposed in the openings 24A and 24B are selectively removed to form a gate electrode. Openings 24a and 24b are formed. At this time, the insulating film 31 formed under the first dummy gate electrode 32a and the second dummy gate electrode 32b is left without being etched. Thereafter, a resist (not shown) having an opening on the floating gate electrode 32 c is formed on the interlayer insulating film 23. Thereafter, using the resist as a mask, the interlayer insulating film 23 is selectively etched to form a gate electrode formation opening 24c reaching the floating gate electrode 32c.

  4F, after removing the insulating film 31 exposed in the gate electrode formation openings 24a and 24b, a hafnium oxide film having a thickness of 5 nm is formed on the entire surface of the semiconductor substrate 11. Then, as shown in FIG. Then, a tungsten film having a thickness of 250 nm is formed on the hafnium oxide film. Thereafter, an unnecessary tungsten film and hafnium oxide film on the interlayer insulating film 23 are removed by CMP, and a gate insulating film 25a made of a hafnium oxide film and a damascene structure made of a tungsten film are formed in the gate electrode formation opening 24a. A gate insulating film 25b made of a hafnium oxide film and a damascene gate electrode 26b made of a tungsten film are formed in the gate electrode forming opening 24b, and a gate electrode forming opening 24c is formed in the gate electrode forming opening 24c. A capacitive insulating film 25c made of a hafnium oxide film and a damascene control gate electrode 26c made of a tungsten film are formed. In the flash memory cell formation area AreaD, the insulating film 31 located below the floating gate electrode 32c among the remaining insulating film 31 is directly used as a tunnel insulating film.

  By the above method, the first NMIS transistor having the damascene gate electrode 26a made of the tungsten film formed on the gate insulating film 25a made of the hafnium oxide film is formed in the first NMIS transistor formation region AreaA. A PMIS transistor having a damascene gate electrode 26b made of a tungsten film formed on a gate insulating film 25b made of a hafnium oxide film is formed in the PMIS transistor forming area AreaB, and a silicon memory is formed in the flash memory cell forming area AreaD. A flash memory cell having a floating gate electrode 32c formed of a polysilicon film, a capacitive insulating film 25c formed of a hafnium oxide film, and a control gate electrode 26c formed of a damascene structure formed of a tungsten film formed on the tunnel insulating film 31 formed of an oxide film. It is made.

  According to the present embodiment, the first semiconductor substrate 11 includes the gate insulating film 25a made of a metal oxide film such as a hafnium oxide film and the gate electrode 26a having a damascene structure made of a metal film such as a tungsten film. NMIS transistor, tunnel insulating film 31 made of silicon oxide film, floating gate electrode 32c made of semiconductor film such as polysilicon film, capacitive insulating film 25c made of metal oxide film such as hafnium oxide film, and tungsten film A semiconductor device including a flash memory cell having a damascene control gate electrode 26c made of a simple metal film can be formed. In addition, the metal oxide film such as the hafnium oxide film that becomes the gate insulating films 25a and 25b or the capacitive insulating film 25c is activated to activate the implanted impurities in the source / drain regions 17a, 17b, and 17c that are subjected to high-temperature heat treatment. Since it is formed after annealing, deterioration of the metal oxide film due to high-temperature heat treatment can be avoided. In addition, since the floating gate electrode 32c made of a semiconductor film is formed at the same time as the dummy gate electrodes 32a and 32b for forming the gate electrodes 26a and 26b made of a metal film, an increase in manufacturing steps can be suppressed. Furthermore, since the gate insulating films 25a and 25b made of a metal oxide film are formed separately from the step of forming the tunnel insulating film 31 made of a silicon oxide film, the reliability of the gate insulating film can be improved.

  In the present embodiment, the pattern width of the gate electrodes 26a and 26b is formed so that the upper region and the lower region are the same. However, as in the third embodiment, the pattern of the upper region compared to the lower region. You may form wide. Furthermore, by combining with the third embodiment, a MIS transistor having a gate insulating film made of a silicon oxide film and a gate electrode made of a semiconductor film such as a polysilicon film may be formed on the same semiconductor substrate. .

  In the first to third embodiments, the description has been given using the n-type MIS transistor having the gate electrode made of the polysilicon film formed at the same time as the dummy gate electrode. However, by the same method, the polysilicon formed at the same time as the dummy gate electrode is used. A p-type MIS transistor having a gate electrode made of a silicon film may be formed.

  As described above, the present invention is useful for forming two or more MIS type transistors having different gate electrode materials on the same semiconductor substrate.

(A)-(f) is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. (A)-(f) is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 2nd Embodiment of this invention. (A)-(f) is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 3rd Embodiment of this invention. (A)-(f) is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 4th Embodiment of this invention. (A)-(f) is sectional drawing which shows the manufacturing process of the conventional semiconductor device.

Explanation of symbols

11 Semiconductor substrate 11a P well region 11b N well region 12 Element isolation region 13 Insulating film 14a First dummy gate electrode 14b Second dummy gate electrode 14c Gate electrode 15a First n type diffusion region 15b P type diffusion region 15c First 2 n-type diffusion regions 16a, 16b, 16c Side wall 17a First n-type source / drain region 17b P-type source / drain region 17c Second n-type source / drain region 18 First interlayer insulating film 19 Second Interlayer insulation film 19A BPSG film 20a, 20b Gate electrode formation opening 21a, 21b Gate insulation film 22a, 22b Gate electrode 23 Interlayer insulation film 24A, 24B Opening 24a, 24b, 24c Gate electrode formation opening 25a, 25b Gate insulation Film 25c Capacitance insulating film 26a, 26b Gate Electrode 26c Control gate electrode 27 Interlayer insulating film 28A, 28B Opening 28a, 28b Gate electrode forming opening 29a, 29b Gate insulating film 30a, 30b Gate electrode 31 Insulating film 32a First dummy gate electrode 32b Second dummy gate electrode 32c Floating gate electrode

Claims (11)

In a semiconductor device comprising: a first MIS transistor formed in a first transistor formation region on a semiconductor substrate; and a second MIS transistor formed in a second transistor formation region on the semiconductor substrate.
The first MIS transistor is
A first gate insulating film made of a first insulating film formed on the semiconductor substrate;
A first gate electrode made of a metal material formed on the first gate insulating film,
The second MIS type transistor is:
A second gate insulating film made of a second insulating film formed on the semiconductor substrate;
A semiconductor device comprising: a second gate electrode made of a semiconductor material formed on the second gate insulating film. The semiconductor device according to claim 1,
The first MIS transistor is
A first sidewall formed on a side surface of the first gate electrode;
A first interlayer insulating film formed on the semiconductor substrate in the first transistor formation region and substantially at the same height as the upper surface of the first gate electrode;
The second MIS type transistor is:
A second sidewall formed on a side surface of the second gate electrode;
And a second interlayer insulating film formed on the semiconductor substrate in the second transistor formation region so as to cover the upper surface of the second gate electrode and the second sidewall. A featured semiconductor device. The semiconductor device according to claim 1,
The first MIS transistor is
A first sidewall formed on a lower side surface of the first gate electrode;
An interlayer insulating film formed on the semiconductor substrate in the first transistor formation region and substantially at the same height as the upper surface of the first gate electrode;
The second MIS type transistor is:
A second sidewall formed on a side surface of the second gate electrode;
The interlayer insulating film formed on the semiconductor substrate in the second transistor formation region so as to cover the upper surfaces of the second gate electrode and the second sidewall;
The upper surface of the first gate electrode is formed higher than the upper surface of the second gate electrode;
The semiconductor device according to claim 1, wherein the first sidewall and the second sidewall are formed at a height equal to or lower than an upper surface of the second gate electrode. The semiconductor device according to claim 1,
The first MIS transistor is
A first sidewall formed on a lower side surface of the first gate electrode;
An interlayer insulating film formed on the semiconductor substrate in the first transistor formation region and at substantially the same height as the upper surface of the first gate electrode;
The second MIS type transistor is:
A flash memory transistor having the second gate electrode as a floating gate electrode;
A second sidewall formed on a side surface of the floating gate electrode;
A capacitive insulating film made of the first insulating film formed on the floating gate electrode;
A control gate electrode made of the metal material formed on the capacitive insulating film;
The interlayer insulating film formed on the semiconductor substrate in the second transistor formation region, substantially at the same height as the upper surface of the control gate electrode,
The upper surface of the first gate electrode is formed at substantially the same height as the upper surface of the control gate electrode,
The semiconductor device according to claim 1, wherein the first sidewall and the second sidewall are formed at a height equal to or less than an upper surface of the floating gate electrode. The semiconductor device according to claim 3 or 4,
In the first gate electrode, the pattern width of the upper region located above the first sidewall is wider than the lower region sandwiched between the first sidewalls. Semiconductor device. The semiconductor device according to any one of claims 2 to 5,
The semiconductor device, wherein the first gate insulating film is formed between the first gate electrode and the first sidewall. The semiconductor device according to any one of claims 1 to 6,
The semiconductor device according to claim 1, wherein the first gate insulating film is a high dielectric film. A first MIS transistor having a first gate electrode formed in a first transistor formation region on a semiconductor substrate; and a second gate electrode formed in a second transistor formation region on the semiconductor substrate. In a manufacturing method of a semiconductor device including a second MIS transistor having
A step (a) of forming a second insulating film on the semiconductor substrate;
A dummy gate electrode made of a semiconductor material is formed on the second insulating film in the first transistor formation region, and the semiconductor material is made on the second insulating film in the second transistor formation region. Forming a second gate electrode (b);
After the step (b), a step (c) of selectively removing the dummy gate electrode in the first transistor formation region and the second insulating film located thereunder;
After the step (c), a step of forming a first gate insulating film made of a first insulating film on the semiconductor substrate in the first transistor formation region from which the second insulating film has been removed ( d) and
And (e) forming the first gate electrode made of a metal material on the first gate insulating film,
2. A method of manufacturing a semiconductor device, comprising: forming a second gate insulating film made of the second insulating film under the second gate electrode. The method of manufacturing a semiconductor device according to claim 8.
After the step (b) and before the step (c),
Forming a first sidewall on the side surface of the dummy gate electrode and forming a second sidewall on the side surface of the second gate electrode;
After the first step, a second interlayer insulating film is formed on the semiconductor substrate in the second transistor formation region so as to cover the upper surfaces of the second gate electrode and the second sidewall. A second step;
After the second step, a third interlayer insulating film having a height substantially the same as the upper surface of the first gate electrode is formed on the semiconductor substrate in the first transistor formation region. A method for manufacturing a semiconductor device comprising the steps of: The method of manufacturing a semiconductor device according to claim 8.
After the step (b) and before the step (c),
Forming a first sidewall on the side surface of the dummy gate electrode and forming a second sidewall on the side surface of the second gate electrode;
A second step of forming an interlayer insulating film on the semiconductor substrate so as to cover the upper surfaces of the dummy gate electrode and the second gate electrode after the first step;
And a third step of forming a first opening reaching the dummy gate electrode by removing the interlayer insulating film on the dummy gate electrode after the second step. A method for manufacturing a semiconductor device. The method of manufacturing a semiconductor device according to claim 8.
The second MIS transistor is a flash memory transistor having the second gate electrode as a floating gate electrode,
After the step (b) and before the step (c),
Forming a first sidewall on the side surface of the dummy gate electrode and forming a second sidewall on the side surface of the second gate electrode;
A second step of forming an interlayer insulating film on the semiconductor substrate so as to cover the upper surfaces of the dummy gate electrode and the second gate electrode after the first step;
A third step of removing the interlayer insulating film on the dummy gate electrode and forming a first opening reaching the dummy gate electrode after the second step;
In the step (c), the dummy gate electrode exposed in the first opening and the second insulating film located under the dummy gate electrode are selectively removed,
After the step (c) and before the step (d), the interlayer insulating film on the second gate electrode is removed to form a second opening reaching the second gate electrode. And having a process of
In the step (d), the first gate insulating film made of the first insulating film is formed on the semiconductor substrate exposed in the first opening, and is exposed in the second opening. Forming a capacitor insulating film made of the first insulating film on the second gate electrode;
In the step (e), the first gate electrode made of the metal material is formed on the first gate insulating film, and the control gate electrode made of the metal material is formed on the capacitor insulating film. A method of manufacturing a semiconductor device.

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