JP2006048793A - Memory cell, and semiconductor memory apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory cell in which the destruction of memory data by electrical influence from bit lines can be made hard to occur, and and a semiconductor memory apparatus using this. <P>SOLUTION: Even in any case at the time of read-out and at the time of write-in, since nodes N1, N2 and bit lines BL, XBL are not connected electrically and directly by transistor switches as a conventional 6 transistor type SRAM cell and they are separated electrically by high impedance between a gate and a drain of MOS transistors Q1, Q3, Q5 and Q7, or between a gate and a source, the destruction of memory data by an electrical influence from these bit lines can be made hard to occur. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor memory cell such as an SRAM (Static Random Access Memory) and a semiconductor memory device using the same.

  SRAMs can perform high-speed read / write operations, and do not require refresh operations for stored data like DRAM (Dynamic RAM), and can simplify peripheral circuits. In addition, it is widely used as a relatively small-capacity storage device that requires simplicity and simplicity.

  As a basic configuration of an SRAM memory cell (hereinafter referred to as an SRAM cell), a six-transistor SRAM cell using six transistors is generally known.

  FIG. 7 is a circuit diagram showing a 6-transistor type SRAM cell. The SRAM cell shown in FIG. 7 includes n-channel MOS transistors Q102, Q104, Q105, and Q106 and p-channel MOS transistors Q101 and Q103.

  Transistors Q101 and Q102 have their drains connected to node Na and their gates connected to node Nb. The source of the transistor Q101 is connected to the power supply voltage VDD, and the source of the transistor Q102 is connected to the reference potential G. Transistors Q101 and Q102 constitute one CMOS inverter having node Nb as input and node Na as output.

  Transistors Q103 and Q104 have their drains connected to node Nb and their gates connected to node Na. The source of the transistor Q103 is connected to the power supply voltage VDD, and the source of the transistor Q104 is connected to the reference potential G. Transistors Q103 and Q104 constitute one CMOS inverter having node Na as an input and node Nb as an output.

  In the two CMOS inverters described above, the inputs and outputs of each other are connected in a ring shape to form one memory circuit.

  Transistor Q105 is connected between bit line BL and node Na, and transistor Q106 is connected between bit line XBL and node Nb. Transistors Q105 and Q106 have gates connected to word line WL, and are turned on or off in common according to the level of word line WL.

The operation of the 6-transistor SRAM cell having the above-described configuration will be described.
In a memory circuit using CMOS inverters connected in a ring shape, the signal levels of nodes Na and Nb are held at complementary levels. That is, when the node Na is at a high level, the node Nb is at a low level, and when the node Na is at a low level, the node Nb is at a high level. Therefore, 1-bit data corresponding to the signal levels of the nodes Na and Nb is stored in this storage circuit.

  In the period in which the memory circuit holds data, the word line WL is set to a low level. Thus, transistors Q105 and Q106 are turned off, and nodes Na and Nb of the memory circuit and bit lines BL and XBL are separated.

  When reading data from the memory circuit, first, the bit lines BL and XBL are previously pulled up to the power supply voltage VDD by a pull-up circuit (not shown), and the parasitic capacitances of the bit lines BL and XBL are charged to the power supply voltage VDD. Next, after releasing the pull-up to the power supply voltage VDD, a high level signal is input to the word line WL, and the nodes Na and Nb of the memory circuit and the bit lines BL and XBL are connected. Thereby, the voltage of the bit line BL or XBL changes according to the signal levels of the nodes Na and Nb.

  For example, when the node Na is at a high level and the node Nb is at a low level, the bit line BL and the node Na are at substantially the same voltage, so that no current flows through the transistor Q105 and the potential of the bit line BL remains unchanged at the power supply voltage VDD. Since the voltage of the bit line XBL is higher than that of the node Nb, a current flows from the bit line XBL to the node Nb, and the potential of the bit line XBL decreases. The potential difference (or current difference) between the bit lines BL and XBL is amplified by a sense amplifier (not shown) and read as data of the memory circuit.

  On the other hand, when data is written to the memory circuit, one of the bit lines BL and XBL is pulled down to the reference potential G according to the value of the data to be written, and the other is pulled up to the power supply voltage VDD. A high level signal is input to WL. Thereby, the potentials of the node Na and the node Nb become equal to the potentials of the bit lines BL and XBL, respectively, and the data in the memory circuit is rewritten.

Japanese Patent Application Laid-Open No. 07-302847

  By the way, in recent years, processing dimensions of semiconductor circuits have been miniaturized, and power supply voltage tends to decrease. When the power supply voltage is lowered, the threshold voltage of the transistor is also lowered. Therefore, in the above-described 6-transistor type SRAM, unintended storage data is easily destroyed.

  For example, when reading is performed by pulling up the bit lines BL and XBL to the power supply voltage VDD, current flows from the bit line to the node holding the low-level signal, so that the node voltage slightly increases from the low level. . When the threshold voltage of the transistor is low, the signal level of the node is easily inverted from the low level to the high level by this slight voltage increase.

  In addition, as the threshold voltage of the transistor decreases, the leakage current flowing through the off-state transistor has become a non-negligible magnitude, which increases the power consumption.

  For example, assume that the word line WL is set to a low level and the bit lines BL and XBL are set to a high level in a standby state where no memory access is performed. In this standby state, if a high level signal is held at the node Na and a low level signal is held at the node Nb, the leakage currents ILa, ILb, ILc are respectively supplied to the three transistors Q102, Q103, Q106 as shown in FIG. Flows constantly. When such a leak current flows in each memory cell, the entire SRAM causes a very large power loss.

  The present invention has been made in view of such circumstances, and an object of the present invention is to provide a memory cell that can hardly cause destruction of stored data due to an electrical influence from a bit line, and a semiconductor memory device using the memory cell. There is to do.

  To achieve the above object, a memory cell according to a first aspect of the present invention is connected between a memory circuit holding a signal level of a first node, a first bit line, and a reference potential, and the first node The first transistor that is turned on or off according to the signal level of the first and the first bit line or the wiring connecting the reference potential and the first transistor is inserted, and in accordance with the input read control signal And a second transistor that is turned on or off.

According to the first aspect of the invention, when the storage data of the storage circuit is read, the second transistor is turned on in response to the read control signal, and the first bit line and the reference potential are The connection is made through the first transistor. The first transistor is turned on or off in accordance with the signal level of the first node held in the memory circuit, so that the first bit line corresponds to the data stored in the memory circuit. It is connected to the reference potential or disconnected from the reference potential.
At this time, if an electric signal is input to the first bit line, for example, the first bit line is precharged to a predetermined voltage, or the first bit line is driven at a constant current, the first bit line is Information on the connection state between the first bit line and the reference potential (that is, data stored in the memory circuit) is obtained from the line as an electrical signal.
At the time of reading, since the electric signal of the first bit line is not directly input to the first node, the stored data is hardly destroyed due to the electric influence from the first bit line.

  Note that the memory circuit may hold the signal level of the second node at a level complementary to the signal level of the first node. The first invention is connected between the second bit line and the reference potential, and is turned on or off complementarily with the first transistor in accordance with the signal level of the second node. 3 and the second bit line or a wiring connecting the reference potential and the third transistor, and is turned on or off in common with the second transistor according to the read control signal. A fourth transistor may be further included.

In reading data stored in the memory circuit in the above configuration, the fourth transistor is also turned on together with the second transistor in accordance with the read control signal. As a result, the second bit line and the reference potential are connected via the third transistor. The third transistor is turned on or off according to the signal level of the second node that is complementary to the signal level of the first node, so that the first and second bit lines are Depending on the data stored in the memory circuit, the reference potential is complementarily connected. That is, one bit line is connected to the reference potential, and the other bit line is disconnected from the reference voltage.
At this time, for example, the first and second bit lines are precharged to a predetermined voltage, or the first and second bit lines are driven with a constant current. Is inputted, information on the connection state between the first and second bit lines and the reference potential (that is, data stored in the memory circuit) is obtained as an electrical signal from the first and second bit lines. .
At the time of reading, the first and second nodes and the first and second bit lines are not directly electrically connected by a switch or the like, and therefore, due to an electrical influence from these bit lines. Destruction of stored data is unlikely to occur.

  In the first invention, a fifth transistor is connected between the first node and the reference potential and is turned on or off in response to a write signal input from the first bit line. A sixth transistor which is inserted on a wiring connecting the first node or the reference potential and the fifth transistor and which is turned on or off in accordance with an input write control signal; and the second node; A seventh transistor connected between the reference potential and turned on or off in a complementary manner to the fifth transistor in response to a write signal input from the second bit line; and the second node or Inserted on a wiring connecting the reference potential and the seventh transistor, and is turned on or off in common with the sixth transistor in accordance with the write control signal. It may further have a eighth transistor.

In the above configuration, when data is written to the memory circuit, both the sixth and eighth transistors are turned on in accordance with the write control signal. As a result, the first node and the reference potential are connected via the fifth transistor, and the second node and the reference potential are connected via the seventh transistor. It will be in the state. Since the fifth and seventh transistors are complementarily turned on or off in accordance with the write signals input from the first and second bit lines, the first and second nodes are connected to the write signal. And the reference potential is connected in a complementary manner. That is, one node is connected to the reference potential and the other node is disconnected from the reference voltage. As a result, the signal levels of the first and second nodes are set to signal levels corresponding to the write signals input from the first and second bit lines.
According to the above configuration, the first and second nodes and the first and second bit lines are not directly electrically connected by a switch or the like in both reading and writing. The stored data is less likely to be destroyed due to electrical influences from these bit lines.

The semiconductor memory device of the second invention is connected to the plurality of memory cells arranged in a matrix, the plurality of first word lines connected to the memory cells in the same row, and the memory cells in the same column, respectively. A plurality of first bit lines, wherein the memory cell has a configuration similar to that of the first invention. However, the read control signal is input from the first word line to the memory cell.
According to the second aspect of the invention, when reading data from the memory circuit, since the electric signal of the first bit line is not directly input to the first node, the signal from the first bit line is not input. Destruction of stored data due to electrical influence is less likely to occur.

The second aspect of the invention may include a plurality of second bit lines connected to the memory cells in the same column. The memory circuit may hold the signal level of the second node at a level complementary to the signal level of the first node. The memory cell may further include the third transistor and the fourth transistor, as in the first invention.
According to the above configuration, when reading data from the memory circuit, the first and second nodes and the first and second bit lines are not directly electrically connected by a switch or the like. The stored data is less likely to be destroyed due to electrical influences from these bit lines.

The second invention may include a plurality of second word lines connected to the memory cells in the same row. Similar to the first invention, the memory cell may include the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor.
According to the above configuration, the first and second nodes and the first and second bit lines are not directly electrically connected by a switch or the like in both reading and writing. The stored data is less likely to be destroyed due to electrical influences from these bit lines.

The second invention has a bit line control circuit for setting the potentials of the first bit line and the second bit line to the reference potential when the memory cell is not accessed. Also good.
When the potentials of the first bit line and the second bit line are set to the reference potential, the potentials at both ends of the first and second transistors and the potentials at both ends of the third and fourth transistors are either Since this becomes equal to the reference potential, almost no leakage current flows through these transistors.

Further, the fifth transistor is turned off when the potential of the first bit line is the reference potential, and the seventh transistor is turned off when the potential of the second bit line is the reference potential. It may be turned off.
Thus, when the first and second bit lines are set to the reference potential by the bit line control circuit, both the fifth and seventh transistors are turned off in the memory cell connected to the bit line. become. As a result, both the fifth and sixth transistors connected between the first node and the reference potential are turned off, and the leakage current flowing through these transistors becomes very small. In this memory cell, since the seventh and eighth transistors connected between the second node and the reference potential are both turned off, the leakage current flowing through these transistors is very small. Become.

  According to the present invention, it is possible to make it difficult to cause destruction of stored data due to an electrical influence from a bit line.

  FIG. 1 is a diagram showing an example of a configuration of a semiconductor memory device according to an embodiment of the present invention.

The semiconductor memory device shown in FIG. 1 includes a control circuit 1, a row decode circuit 2, a data input / output circuit 3, a bit line control circuit 4, and a memory cell array MA.
The bit line control circuit 4 is an embodiment of the bit line control circuit of the present invention.

Memory cell array MA includes a plurality of memory cells MC arranged in a matrix.
The memory cells in the same row are connected to a common read word line RWL and a common write word line WWL, respectively.
The memory cells in the same column are respectively connected to a common bit line pair (BL, XBL).
Memory cell MC is an embodiment of the memory cell of the present invention.
The read word line RWL is an embodiment of the first word line of the present invention.
The write word line WWL is an embodiment of the second word line of the present invention.
Bit line BL is an embodiment of the first bit line of the present invention.
Bit line XBL is an embodiment of the second bit line of the present invention.

  The control circuit 1 generates various control signals necessary for executing a read operation and a write operation on the memory cell array MA, and supplies the control signals to the row decode circuit 2, the data input / output circuit 3, and the bit line control circuit 4. . For example, in response to the selection signal R / W, whether to perform a read or write operation is selected, and when the enable signal EN is set to an active state, various control signals for executing the selected operation Is generated.

  The row decoding circuit 2 decodes the address data ADD1 in accordance with the control signal from the control circuit 1 at the time of data reading, and the plurality of read word lines RWL connected to the plurality of memory cells MC according to the decoding result. Select one of them and activate it. At the time of data writing, address data ADD1 is decoded according to a control signal from control circuit 1, and one of a plurality of write word lines WWL connected to a plurality of memory cells MC is selected according to the decoding result. Select and activate.

The data input / output circuit 3 decodes the address data ADD2 in accordance with a control signal from the control circuit 1 when reading or writing data, and a plurality of bits connected to the plurality of memory cells MC according to the decoding result. A group of bit line pairs corresponding to data of a predetermined data length (for example, 1 byte) is selected from line pairs (BL, XBL).
When data is read, a sense amplifier incorporating a voltage difference or a current difference generated between the bit lines of the selected bit line pair is amplified and output as read data Dout.
When data is written, the built-in write buffer circuit drives the two bit lines of the selected bit line pair in a complementary manner based on the input write data Din. That is, according to the value of each bit of the write data Din, one of the selected bit line pairs is driven to a high level and the other is driven to a low level.

The bit line control circuit 4 controls the voltage and current supplied to the bit line pair (BL, XBL) according to the control signal from the control circuit 1.
For example, when reading data, before activating the read word line RWL, the bit line pair (BL, XBL) is pulled up to the power supply voltage VDD to supply the parasitic capacitance of the bit line pair (BL, XBL) as a power source. Charge to voltage VDD. Thereafter, the pull-up is canceled and the read word line RWL is activated, so that a potential difference corresponding to the data stored in the memory cell MC is generated between the bit lines BL and XBL. The sense amplifier of the data input / output circuit 3 amplifies the potential difference generated between the bit lines.

  Alternatively, the bit line control circuit 4 may drive each bit line of the bit line pair at a constant current during the activation period of the read word line RWL during data reading. In this case, a current difference corresponding to the storage data of the memory cell MC is generated between the bit lines of the bit line pair. The sense amplifier of the data input / output circuit 3 amplifies a current difference generated between the bit lines.

  Further, the bit line control circuit 4 sets the bit line pair (BL, XBL) of each column to the reference potential G when the memory access is not performed. As a result, as will be described in detail later, a leak current flowing from the bit line pair (BL, XBL) to the memory cell MC is reduced, and power loss is suppressed.

Next, a detailed configuration of the memory cell MC will be described.
FIG. 2 is a diagram showing an example of the configuration of the memory cell MC according to the embodiment of the present invention.

The memory cell MC shown in FIG. 2 has n-channel MOS transistors Q1,..., Q8, Q10, Q12 and p-channel MOS transistors Q9 and Q11.
Transistor Q1 is an embodiment of the first transistor of the present invention.
Transistor Q2 is an embodiment of the second transistor of the present invention.
Transistor Q3 is an embodiment of the third transistor of the present invention.
Transistor Q4 is an embodiment of the fourth transistor of the present invention.
Transistor Q5 is an embodiment of the fifth transistor of the present invention.
Transistor Q6 is an embodiment of the sixth transistor of the present invention.
Transistor Q7 is an embodiment of the seventh transistor of the present invention.
Transistor Q8 is an embodiment of an eighth transistor of the present invention.
A circuit including the transistors Q9 to Q12 is an embodiment of the memory circuit of the present invention.

Transistors Q9 and Q10 have their drains connected to node N1 and their gates connected to node N2. The source of the transistor Q9 is connected to the power supply voltage VDD, and the source of the transistor Q10 is connected to the reference potential G. Transistors Q9 and Q10 constitute one CMOS inverter having node N2 as an input and node N1 as an output.
Transistors Q11 and Q12 have their drains connected to node N2 and their gates connected to node N1. The source of the transistor Q11 is connected to the power supply voltage VDD, and the source of the transistor Q12 is connected to the reference potential G. The transistors Q11 and Q12 constitute one CMOS inverter having the node N1 as an input and the node N2 as an output.

In the two CMOS inverters described above, the inputs and outputs of each other are connected in a ring shape to form one memory circuit.
This memory circuit holds the signal levels of nodes N1 and N2 at complementary levels. That is, one of the two nodes is held at a high level and the other is held at a low level.

  The transistor Q1 is connected between the bit line BL and the reference potential G, and is turned on or off according to the signal level of the node N1. That is, it turns on when the node N1 is at a high level and turns off when it is at a low level.

  The transistor Q2 is inserted on a wiring connecting the bit line BL and the transistor Q1, and is turned on or off according to a read control signal input from the read word line RWL. That is, it is turned on when the read word line RWL is at a high level and turned off when it is at a low level.

  In the example of FIG. 2, the transistor Q2 has a drain connected to the bit line BL, a source connected to the drain of the transistor Q1, and a gate connected to the read word line RWL. The source of transistor Q1 is connected to reference potential G, and its gate is connected to node N1.

  The transistor Q3 is connected between the bit line XBL and the reference potential G, and is turned on or off according to the signal level of the node N2. That is, it turns on when the node N2 is at a high level and turns off when it is at a low level.

  Since the memory circuits of the transistors Q9 to Q12 hold complementary level signals at the nodes N1 and N2, the transistors Q1 and Q3 that operate in response to the signals at the nodes N1 and N2 are complementarily turned on or off. Turn off. That is, the transistor Q3 is turned off when the transistor Q1 is on, and the transistor Q3 is turned on when the transistor Q1 is off.

  The transistor Q4 is inserted on a wiring connecting the bit line XBL and the transistor Q3, and is turned on or off according to a read control signal input from the read word line RWL. That is, it is turned on when the read word line RWL is at a high level and turned off when it is at a low level.

  In the example of FIG. 2, the drain of the transistor Q4 is connected to the bit line XBL, its source is connected to the drain of the transistor Q3, and its gate is connected to the read word line RWL. The source of transistor Q3 is connected to reference potential G, and its gate is connected to node N2.

  The transistor Q5 is connected between the node N1 and the reference potential G, and is turned on or off according to a write signal input from the bit line BL. That is, it is turned on when the bit line BL is at a high level and turned off when it is at a low level.

  The transistor Q6 is inserted on a wiring connecting the node N1 and the transistor Q5, and is turned on or off in accordance with a write control signal input from the write word line WWL. That is, it is turned on when the write word line WWL is at a high level and turned off when it is at a low level.

  In the example of FIG. 2, the drain of the transistor Q6 is connected to the node N1, its source is connected to the drain of the transistor Q5, and its gate is connected to the write word line WWL. The source of the transistor Q5 is connected to the reference potential G, and the gate thereof is connected to the bit line BL.

  The transistor Q7 is connected between the node N2 and the reference potential G, and is turned on or off according to a write signal input from the bit line XBL. That is, it is turned on when the bit line XBL is at a high level and turned off when it is at a low level.

  However, when data is written, the signal levels of the bit lines BL and XBL are set to complementary levels by the data input / output circuit 3. Therefore, transistors Q5 and Q7 are complementarily turned on or off when data is written. That is, the transistor Q5 is turned on and the transistor Q7 is turned off, or the transistor Q5 is turned off and the transistor Q7 is turned on.

  The transistor Q8 is inserted on a wiring connecting the node N2 and the transistor Q7, and is turned on or off according to a write control signal input from the write word line WWL. That is, it is turned on when the write word line WWL is at a high level and turned off when it is at a low level.

  In the example of FIG. 2, the drain of the transistor Q8 is connected to the node N2, its source is connected to the drain of the transistor Q7, and its gate is connected to the write word line WWL. The source of the transistor Q7 is connected to the reference potential G, and the gate thereof is connected to the bit line XBL.

  Here, the operation of the semiconductor memory device shown in FIG. 1 having the above-described configuration will be described.

  First, an operation in the case where the bit line is precharged at the time of reading by the bit line control circuit 4 will be described with reference to an example of a signal waveform shown in FIG.

(When writing)
When the data write operation is selected by the selection signal R / W and the enable signal EN is set to the active state, the row decoder circuit 2 selects one row from the plurality of rows of the memory cell array MA according to the address data ADD1. Then, the write word line WWL of the selected row is set to a high level (FIG. 3A).

  At this time, in the data input / output circuit 3, a group of bit line pairs is selected from the plurality of bit lines (BL, XBL) according to the address data ADD2, and driven by the write buffer circuit. That is, in the selected bit line pair (BL, XBL), one bit line is set to the high level and the other bit line is set to the low level according to the value of each bit of the input data Din (FIG. 3 ( C), (D)).

Thereby, transistors Q6 and Q8 are turned on in memory cell MC of the row selected by row decoder circuit 2. In addition, in the memory cell MC of the column selected by the data input / output circuit 3 among the memory cells MC in one row, one of the transistors Q5 and Q7 is turned on according to the value of each bit of the input data Din, and the other Turns off.
As a result, in the group of memory cells MC selected as a write target by the row decoder circuit 2 and the data input / output circuit 3, one of the nodes N1 and N2 has a reference potential depending on the value of each bit of the input data Din. Connected to G and forcedly set to low level. The other node is set to a high level by the memory circuit of the transistors Q9 to Q12 (FIGS. 3E and 3F).

  In this way, the nodes N1 and N2 of the group of memory cells MC specified by the addresses ADD1 and ADD2 are set to signal levels corresponding to the value of the write data Din.

(When reading)
When the data read operation is selected by the selection signal R / W and the enable signal EN is set to the active state, first, the bit line control circuit 4 sets the bit line pair (BL, XBL) of each column to the power supply voltage VDD. Precharge is performed (FIGS. 3C and 3D).

  After the precharge, the bit line control circuit 4 disconnects the bit line pair (BL, XBL) from the power supply voltage VDD. Next, the row decoder circuit 2 selects one row from the plurality of rows of the memory cell array MA according to the address data ADD1, and the read word line RWL of the selected row is set to the high level ( FIG. 3 (B)). Thereby, transistors Q2 and Q4 are turned on in each memory cell MC connected to this read word line RWL.

  Since one of the transistors Q1 and Q3 of each memory cell MC is turned on according to the signal levels of the nodes N1 and N2, when the transistors Q2 and Q4 are turned on, the node N1 of the bit lines BL and XBL is turned on. One of the bit lines corresponding to the signal levels of N2 and N2 is connected to the reference potential G. As a result, the voltage of the bit line connected to the reference potential G gradually decreases from the power supply voltage VDD, and the bit line not connected to the reference potential G is held at the power supply voltage VDD (FIGS. 3C and 3D). )).

  After a certain time has elapsed since the read word line RWL was set to the high level, the data input / output circuit 3 selects a group of bit line pairs corresponding to the address data ADD2, and the potential difference between the bit lines is sensed. Amplified by an amplifier.

  In this manner, data Dout corresponding to the signal levels of the nodes N1 and N2 is read from the group of memory cells MC specified by the addresses ADD1 and ADD2.

(When not accessing)
At the time of non-access when neither reading nor writing is performed, both the bit lines BL and XBL are set to the low level, that is, the reference potential G.
Thereby, both ends of the transistors Q1 and Q2 connected in series and both ends of the transistors Q3 and Q4 in each memory cell MC become the reference potential G, so that almost no leakage current flows through these transistors.

  In this case, since the reference potential G is applied to the gates of the transistors Q5 and Q7, these transistors are also turned off. As a result, transistors Q5 and Q6 connected between node N1 and reference potential G are both turned off, and transistors Q7 and Q8 connected between node N2 and reference potential G are both turned off. . In general, the more the transistors in the off state are stacked in multiple stages, the smaller the leakage current. Therefore, the leakage current flowing through the transistors Q5 and Q6 and the leakage current flowing through the transistors Q7 and Q8 are both extremely small.

  Next, the operation when the bit line is driven with a constant current at the time of reading by the bit line control circuit 4 will be described with reference to the signal waveform example of FIG. Since operations at the time of writing and at the time of non-access are the same as those described above, only the operation at the time of reading will be described here.

(When reading)
When the data read operation is selected by the selection signal R / W and the enable signal EN is set to the active state, the row decoder circuit 2 selects one row from the plurality of rows of the memory cell array MA according to the address data ADD1. Then, the read word line RWL of the selected row is set to a high level (FIG. 4B). Thereby, transistors Q2 and Q4 are turned on in each memory cell MC connected to this read word line RWL. Since either one of the transistors Q1 and Q3 of each memory cell MC is turned on according to the signal levels of the nodes N1 and N2, when the transistors Q2 and Q4 are turned on, either the bit line BL or XBL is turned on. Is connected to the reference potential G.
That is, the bit line pair (BL, XBL) of each column has two bits according to the signal level state (ie, stored data) of the nodes N1 and N2 in the memory cell MC of the row selected by the row decoder circuit 2. Either one of the lines is connected to the reference potential G.

  In this state, the bit line pair (BL, XBL) in each column is driven with a constant current by the bit line control circuit 4 (FIGS. 4C and 4D). Then, a constant current from the bit line control circuit 4 flows into one bit line connected to the reference potential G, and this constant current does not flow into the other bit line not connected to the reference potential G. Current difference occurs. Further, since the potential of the bit line through which the constant current flows is lower than that of the bit line through which the constant current does not flow, a potential difference is generated between the bit lines.

After a predetermined time has elapsed since the read word line RWL is set to the high level and the bit line pair (BL, XBL) of each column is driven with a constant current, the data input / output circuit 3 corresponds to the address data ADD2. A group of bit line pairs is selected, and the current difference or potential difference between the bit lines is amplified by the sense amplifier.
In this manner, data Dout corresponding to the signal levels of the nodes N1 and N2 is read from the group of memory cells MC specified by the addresses ADD1 and ADD2.

  As described above, according to the present embodiment, the nodes N1 and N2 and the bit lines BL and XBL are directly electrically connected by transistor switches or the like as in the conventional example shown in FIG. Are not electrically connected and are electrically isolated by a high impedance between the gate and the drain of the MOS transistor, so that it is difficult to cause destruction of stored data due to an electrical influence from these bit lines. .

When the memory cell MC is not accessed, the bit line control circuit 4 sets the potentials of the bit lines BL and XBL to the reference potential G, whereby the potentials at both ends of the transistors Q1 and Q2 and the transistors Q3 and Q4 are set. Since the potentials at both ends of the transistor are equal to the reference potential G, almost no leakage current can flow through these transistors.
Further, by setting the potential of the bit line BL to the reference potential G and turning off the transistor Q5, both the two-stage transistors Q5 and Q6 connected between the node N1 and the reference potential G can be turned off. Therefore, the leak current flowing through these transistors can be made very small. The two-stage transistors Q7 and Q8 connected between the node N2 and the reference potential G can also be turned off by setting the bit line XBL to the reference potential G. Therefore, the leakage current flowing through these transistors is also reduced. Can be very small.
Therefore, in the case where access to the memory cell is not performed, any leakage current of the transistor related to the access between the bit line and the memory circuit can be extremely reduced. For example, when the node N1 is at a high level and the node N2 is at a low level, the leakage current IL1 flows through the transistor Q10 and the leakage current IL2 flows through the transistor Q11 of the memory circuit, but almost no leakage current flows through the other transistors.
Therefore, according to the memory cell MC shown in FIG. 2, the power loss due to the leakage current can be reduced as compared with the conventional memory cell shown in FIG. 7 in which the leakage current constantly flows through the three transistors.

In the conventional memory cell shown in FIG. 7, the n-channel MOS transistors Q102 and Q104 constituting the memory circuit have a role of drawing current from the bit line at the time of reading. If the driving capability of the transistor is too low, there is a problem that the reading speed is lowered. On the other hand, in the memory cell MC shown in FIG. 2, the reading speed is mainly determined by the driving capability of the transistors Q1 to Q4 and is not greatly affected by the driving capability of the transistors Q9 to Q12 constituting the memory circuit.
Therefore, according to the memory cell MC shown in FIG. 2, it is possible to use a low-leakage current transistor having a small size as the transistors Q9 to Q12 constituting the memory circuit while maintaining a required reading speed. The power loss due to the leakage current can be further reduced.

  Compared to the conventional memory cell shown in FIG. 7, six transistors are added to the memory cell MC shown in FIG. 2, but these are formed in a relatively small size as shown in the example of FIG. By using a possible n-channel MOS transistor, an increase in circuit area can be suppressed.

  As mentioned above, although embodiment of this invention was described, this invention is not limited only to said form, Various modifications are included.

  In the memory cell shown in FIG. 2, the stored data is read by driving the two bit lines in the transistors Q1 and Q2 and the transistors Q3 and Q4 in a complementary manner. For example, as shown in FIG. Only one bit line may be driven to read data.

In the memory cell shown in FIG. 5, transistors Q3 and Q4 in the memory cell shown in FIG. 2 are omitted.
Even with such a configuration, data stored in the memory cell can be read in accordance with the current and voltage of the bit line BL.

  In the memory cell shown in FIG. 2, data is written by connecting either one of the nodes N1 and N2 to the reference potential G by two-stage transistors (Q5 and Q6, Q7 and Q8). For example, as shown in FIG. 6, data may be written by connecting nodes N1 and N2 to bit lines BL and XBL.

In the memory cell shown in FIG. 6, the transistors Q5 to Q8 in the memory cell shown in FIG. 2 are omitted, and n-channel MOS transistors Q13 and Q14 are provided instead.
Transistor Q13 is connected between node N1 and bit line BL, and transistor Q14 is connected between node N2 and bit line XBL. The gates of the transistors Q13 and Q14 are both connected to the write word line WWL.
Even when the memory cell has such a configuration, the nodes N1 and N2 and the bit lines BL and XBL are electrically separated with high impedance at the time of data reading, so that the stored data is destroyed due to the data reading. There is an advantage to make it difficult to wake up.

  However, when the memory cell having this configuration is used, the transistors Q13 and Q14 are turned on in all the memory cells in the row in which the write word line WWL is set to the high level, and the nodes N1 and N2 and the bit lines BL and XBL Therefore, in the data input / output circuit 3, it is desirable to write data to all the memory cells in the selected row.

  In the memory cell shown in FIG. 2, complementary levels of signals are held at the two nodes N1 and N2 by the memory circuits Q9 to Q12. For example, the signal level of one node is held as in a DRAM cell. The present invention can also be applied to the memory circuit.

  In the memory cell shown in FIG. 2, as a circuit for accessing the memory circuit from the bit lines BL and XBL, series circuits of n-channel MOS transistors (Q1 and Q2, Q3 and Q4, Q5 and Q6, Q7 and Q8) is used, but the connection relationship between the transistors in this series circuit may be arbitrary. For example, the drain of the transistor Q1 may be connected to the bit line BL, the source thereof may be connected to the drain of the transistor Q2, and the source of the transistor Q2 may be connected to the reference potential G.

  In the above-described embodiment, a memory cell configured using a MOS transistor is taken as an example. However, the present invention is not limited to this, and is configured using other various types of transistors (for example, bipolar transistors). The present invention is also applicable to a memory cell to be used.

It is a figure which shows an example of a structure of the semiconductor memory device which concerns on embodiment of this invention. It is a figure which shows an example of a structure of the memory cell which concerns on embodiment of this invention. It is a figure which shows the example of the signal waveform of each part in the case of precharging a bit line before reading data. It is a figure which shows an example of the signal waveform of each part in the case of reading by driving a bit line with a constant current. It is a figure which shows the 1st modification of the memory cell which concerns on embodiment of this invention. It is a figure which shows the 2nd modification of the memory cell which concerns on embodiment of this invention. It is a figure which shows the structural example of a general 6 transistor type SRAM cell.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Control circuit, 2 ... Row decoding circuit, 3 ... Data input / output circuit, 4 ... Bit line control circuit, MA ... Memory cell array, MC ... Memory cell, Q1-Q8, Q10, Q12-Q14 ... N channel MOS type transistor Q9, Q11... P-channel MOS transistor, RWL... Read word line, WWL... Write word line, BL, XBL.

Claims (9)

A storage circuit for holding the signal level of the first node;
A first transistor connected between the first bit line and a reference potential and turned on or off according to the signal level of the first node;
A second transistor inserted on the first bit line or a wiring connecting the reference potential and the first transistor, and turned on or off in accordance with an input read control signal;
A memory cell. The memory circuit holds the signal level of the second node at a level complementary to the signal level of the first node;
A third transistor connected between the second bit line and the reference potential and turned on or off complementarily with the first transistor in accordance with the signal level of the second node;
A fourth transistor inserted on the second bit line or a wiring connecting the reference potential and the third transistor, and turned on or off in common with the second transistor in response to the read control signal; Having
The memory cell according to claim 1. A fifth transistor connected between the first node and the reference potential and turned on or off in response to a write signal input from the first bit line;
A sixth transistor which is inserted on a wiring connecting the first node or the reference potential and the fifth transistor and which is turned on or off according to an input write control signal;
A seventh transistor connected between the second node and the reference potential and turned on or off complementarily with the fifth transistor in response to a write signal input from the second bit line;
An eighth transistor inserted on a wiring connecting the second node or the reference potential and the seventh transistor, and turned on or off in common with the sixth transistor in response to the write control signal; Having
The memory cell according to claim 2. A plurality of memory cells arranged in a matrix;
A plurality of first word lines respectively connected to memory cells in the same row;
A plurality of first bit lines respectively connected to memory cells in the same column;
A semiconductor memory device comprising:
The memory cell
A storage circuit for holding the signal level of the first node;
A first transistor connected between the first bit line and a reference potential and turned on or off in accordance with a signal level of the first node;
A second transistor inserted on the first bit line or a wiring connecting the reference potential and the first transistor, and turned on or off in response to a read control signal input from the first word line When,
including,
Semiconductor memory device. A plurality of second bit lines respectively connected to memory cells in the same column;
The memory circuit holds the signal level of the second node at a level complementary to the signal level of the first node;
The memory cell
A third transistor connected between the second bit line and the reference potential and turned on or off complementarily with the first transistor in accordance with a signal level of the second node;
A fourth transistor inserted on the second bit line or a wiring connecting the reference potential and the third transistor, and turned on or off in common with the second transistor in response to the read control signal; ,including,
The semiconductor memory device according to claim 4. A plurality of second word lines respectively connected to memory cells in the same row;
The memory cell
A fifth transistor connected between the first node and the reference potential and turned on or off in response to a write signal input from the first bit line;
A sixth transistor inserted on the first node or a wiring connecting the reference potential and the fifth transistor, and turned on or off in response to a write control signal input from the second word line; ,
A seventh transistor connected between the second node and the reference potential and turned on or off complementarily with the fifth transistor in response to a write signal inputted from the second bit line;
An eighth transistor inserted on a wiring connecting the second node or the reference potential and the seventh transistor, and turned on or off in common with the sixth transistor in response to the write control signal; including,
The semiconductor memory device according to claim 5. A bit line control circuit that sets the potentials of the first bit line and the second bit line to the reference potential when the memory cell is not accessed;
The semiconductor memory device according to claim 6. The fifth transistor is turned off when the potential of the first bit line is the reference potential,
The seventh transistor is turned off when the potential of the second bit line is the reference potential.
The semiconductor memory device according to claim 7. The fifth transistor and the seventh transistor are shared by a plurality of memory cells connected to the common first bit line and second bit line.
The semiconductor memory device according to claim 6.

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