JP2001202775A - Rewrite pseudo SRAM and rewrite method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a hidden rewrite 2P2N pseudo-SRAM with low power consumption, which prevents data confusion when turning on a plurality of word lines simultaneously. A hidden rewrite 2P2N pseudo SRAM with an array of memory cells is provided. Each memory cell includes a cross pair latch and two PMOS access transistors. The cross-pair latch includes two NMOS transistors that are connected to each other and store a pair of signals. The NMOS transistor has a source connected to a negative power supply voltage, and a drain and a gate crossing and connected to each other. PMOS
The transistors are controlled by word lines and access the NMOS transistors of the cross-pair latch and a pair of bit lines. The PMOS transistor has a source connected to the pair of bit lines and a drain connected to the drain of the NMOS transistor.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer memory, and more particularly to a hidden rewrite 2P2N pseudo SRAM.
(Hidden refresh 2P2N pseudo static random access
memory) and a method of rewriting the hidden pseudo SRAM.

[0002]

2. Description of the Related Art Memory is an integral part of the computer industry. Generally, a memory is a DRAM (dynamic random access) depending on its data storage capacity.
memory) and SRAM (static random access memory)
Classified as DRAMs are small, but require periodic rewriting to prevent data loss due to leakage current. On the other hand, SRAM is simple in operation, but occupies a large chip area.

FIG. 4A (prior art) is a circuit diagram showing a conventional 1T1C (1 transistor 1 capacitor) memory cell of a DRAM. As shown in FIG.
1T1C memory cells known in the art include:
It includes an access transistor T1 and a storage capacitor CS. The access transistor T1 has a source connected to the storage capacitor CS, a gate connected to the word line WL, and a drain connected to the bit line BL.

FIG. 4B is a cross-sectional view showing the 1T1C memory cell shown in FIG. 4A formed on a semiconductor substrate. As shown in FIG.
A parasitic diode D1 (PN junction) is formed between the access transistor T1 and the storage capacitor CS. Therefore, the charge of the logic "1" signal stored in the storage capacitor CS gradually decreases even when the access transistor T1 whose word line WL is "0" is turned off. DRAM to prevent data loss
Is periodically rewritten. That is, the logic "1" signal stored in the storage capacitor CS is read, and the logic "1" signal is amplified and rewritten by the sense amplifier (not shown) connected to the bit line BL.

FIG. 5 (Prior Art) shows a conventional 3D DRAM.
FIG. 3 is a circuit diagram illustrating a T (three element) memory cell. This figure 5
As shown in FIG.
The memory cell includes a read transistor T2, a storage transistor T3, and a write transistor T4. The read transistor T2 includes a gate connected to a read word line RWL, a read bit line RBL.
And a drain connected to the source. The storage transistor T3 has a gate, a drain connected to the source of the read transistor T2, and a source connected to the negative power supply voltage of the DRAM. The write transistor T4 has a gate connected to the write word line WWL, a drain connected to the word / bit line WBL, and a source connected to the gate of the storage transistor T3. Similar to the 1T1C memory cell in FIGS. 4A and 4B, the storage transistor T3
Of the logic "1" signal stored in the memory cell is reduced due to leakage current. DRAM to prevent data loss
Is periodically rewritten. That is, the logic "1" signal stored in the storage transistor T3 is read through the read word line RWL, and the logic "1" signal is amplified by the sense amplifier (not shown) connected to the bit line BL to write the write word. The signal amplified through the line WWL is rewritten.

FIG. 6 (Prior Art) shows a conventional 4 DRAM.
FIG. 3 is a circuit diagram showing a T (4 element) memory cell. This figure 6
As shown in FIG.
The memory cell has four NMOS transistors N1, N
2, N3 and N4. Of these, NMOS
Each of the transistors N1 and N2 has a source connected to a negative power supply voltage, and a gate and a drain connected in a crossing manner to form a crossed-pair latch for storing a pair of signals S / S '. The NMOS transistor N
Reference numerals 3 and N4 denote a gate connected to the word line WL and a pair of signals stored in the cross-pair latch by being connected to the pair of bit lines BL / BL 'and the drains of the NMOS transistors N1 and N2, respectively. It has a drain and a source for accessing S / S '. Signal S /
The swing (swing) of the stored data in S ′ is caused by the NMOS transistors N1, N2, N3,
This is obtained by subtracting the threshold voltage of N4 (VDD-VTN). The NMOS transistors N3 and N4 are off (closed) (eg, the word line WL is "0"), and the signal S / S 'of the cross pair latch is "0" / "1".
When (VDD−VTN), the signal S ′ is in a floating state while the signal S is not in a floating state. Therefore, FIGS. 4A and 4B
As in the 1T1C memory cell in the above, the periodic rewriting to prevent data loss in the signal S ′ is performed to ensure that the load L connected to the bit lines BL / BL ′ provides a sufficient rewriting current. , The word line WL may be turned on (open) for a short time. Load L is DRA
The power consumption is reduced by being controlled to act only when performing the M pre-charging and rewriting operations.

[0007] 4T memory cells are manufactured by standard CMOS processes known in the art, as compared to 1T1C memory cells manufactured by a stack or trench process. Furthermore, 4T
The memory cell stores data differentially (a pair of signals S / S ′).
) And have high noise margin and fast access speed. Therefore, most of the pseudo SRAMs are configured with 4T memory cells manufactured by a standard CMOS process.

FIGS. 7A and 7B (known art)
Is the SRAM 6T (6) known in the art.
FIG. 3 is a circuit diagram illustrating a memory cell. In order to prevent the floating state of the differential signal S / S 'in the 4T memory cell of FIG.
By being included in the memory cell, an SRAM cell which operates as a 4T memory cell is obtained as shown in FIG. The PMOS transistors P1 and P2 have a source connected to the positive power supply voltage of the SRAM, a gate connected to the drains of the NMOS transistors N1 and N2, and NM.
And a drain connected to the drains of the OS transistors N1 and N2. Further, FIG.
NMOS transistors N3 and N at
4 can be replaced with PMOS transistors P3 and P4, as shown in FIG. In this case, the PMOS transistors P1 and P2 form a cross pair latch, and the NMOS transistors N1 and N2
Is provided only to prevent the floating of the differential signal S / S ′.

Further, since the leakage current is usually derived from the reverse bias leakage of the parasitic diode, the PMOS transistors P1 and P2 also have the configuration shown in FIG.
As shown in the figure, the resistors R1 and R2 (10 ¹⁰ to 10 ¹¹
Ω), it is possible to provide a supply current larger than the leakage current and prevent data loss of the differential signal S / S ′. In this case, the resistors R1 and R2
Can be formed on NMOS transistors to occupy the same chip area as 4T memory cells.
Furthermore, the resistors R1 and R2 in FIG.
(D) As shown in (prior art), by replacing the thin film transistors TFT1 and TFT2, the noise margin can be increased and the standby current can be reduced. In this case, the thin film transistors TFT1 and TFT2
Can also be formed on NMOS transistors to occupy the same chip area as 4T memory cells.

As described above, a pseudo SRAM using 4T memory cells is manufactured by a standard CMOS process.
The two PMOS transistors reduce the chip area and can operate as a standard SRAM. However, in addition to the normal read / write operation, a rewrite operation (that is, turning on all the word lines for a short time) is also required, which results in a waste of power.

FIG. 8A (Prior Art) shows a pseudo SRAM.
FIG. 3 is a circuit diagram showing a conventional driving device of FIG. This FIG.
As shown in FIG. 1, the driving device of the memory array 10 includes a row address decoder 11, a column address decoder 12, a multiplexer 13, a rewriting counter 14, and a control device 1.
5 is included. The multiplexer 13 under the control of the control device 15 selectively transfers the row address RA or the counting result of the rewrite counter 14 to the row address decoder 11, thereby driving the corresponding word line drive signal of the memory array 10. generate. The column address decoder 12 generates a drive signal for a corresponding bit line of the memory array 10 by receiving the column address CA. Therefore, the drive signal generated by the row address decoder 11 and the column address decoder 12 allows the memory array 10 to be accessed and rewritten.

As shown in FIG. 8B (prior art), the rewrite counter 14 in FIG. 8A can be replaced with a shift register 16. In this case, the shift register 16 serves as a drive signal for a corresponding word line of the memory array 10 by sequentially outputting pulses. Meanwhile, the row address decoder 11 also generates a drive signal for the corresponding word line by receiving the row address RA. Then, the multiplexer 13 drives the corresponding word line by selectively transferring the drive signal of the row address decoder 11 or the shift register 16. Column address decoder 12
Generates a drive signal for a corresponding bit line of the memory array 10 by receiving the column address CA. Thereby, the access and the rewrite operation of the memory array 10 are performed by the drive signal generated by the column address decoder 12 while being selected by the multiplexer 13.

FIG. 8C (prior art) is a circuit diagram showing the shift register 16 of FIG. 8B. This FIG.
As shown in (c), the shift register 16 is connected in a ring shape and is constituted by a D-type flip-flop controlled by a system clock CLK. The pulse, when input to shift register 16, travels along the D flip-flop on the rising or falling edge of the system clock. Therefore, when the number of D-type flip-flops is designed to be the same as the number of word lines of the memory array 10, the output of the shift register 16 is directly used as a drive signal for the word lines of the memory array 10.

In the pseudo SRAM using the 4T memory cell, when the accessed transistors N3 and N4 are off (for example, the word line WL is "0"), the logic "1".
The transistor N1 (or N2) storing the signal can be rewritten not only by changing the voltage level of the bit line BL / BL ', but also by turning on the word line WL. Further, the accessed transistor N3
And when N4 is on (eg, word line WL is "1"), a large read current flows into transistor N2 (or N1) which stores a logic "0" signal, thereby simultaneously connecting two or more word lines. Causes data confusion when turned on. Therefore, the pseudo SRAM is
A rewrite must be performed with the extra power consuming columns.

[0015]

Thus, there is a general need in the art for an improved and optimized SRAM for use in a computer. In particular, there is a need to provide a hidden rewrite 2P2N pseudo-SRAM that prevents confusion of data when simultaneously turning on a plurality of word lines and reduces power consumption.

The present invention provides a hidden rewrite 2P2N pseudo SRAM having a small chip area and a small power consumption.
And a rewrite method in which the operation of the SRAM is simple and the read time is reduced.

[0017]

SUMMARY OF THE INVENTION The present invention provides a hidden rewrite 2P2N pseudo SRAM for use in a computer having an array of memory cells. Each memory cell is
Includes a cross pair latch and two PMOS access transistors. A cross-pair latch includes two NMOS transistors that cross and connect to each other. Two PMOS access transistors are controlled by the word lines and are provided for accessing the two NMOS transistors and the pair of bit lines, respectively, of the crossed pair latch.

Hidden rewrite 2P2N according to the present invention
In the pseudo SRAM, two NMOS transistors of the cross pair latch include a first NMOS transistor and a second NM
An OS transistor, wherein the first NMOS transistor has a gate, a drain, and a source connected to a negative power supply voltage, and the second NMOS transistor has a first NMOS transistor.
A gate connected to the drain of the NMOS transistor,
A drain connected to the gate of the first NMOS transistor and a source connected to the negative power supply voltage;

Further, in the hidden rewrite 2P2N pseudo SRAM according to the present invention, two PMOS access transistors are a first PMOS transistor and a second PM transistor.
An OS transistor, wherein the first PMOS transistor has a gate connected to the word line, a source connected to the pair of bit lines, and a drain connected to the drain of the first NMOS transistor.
The transistor has a gate connected to the word line, a source connected to another pair of bit lines, and a drain connected to the drain of the second NMOS transistor.

In addition, the present invention also provides a hidden-type rewriting method for a hidden-type rewrite 2P2N pseudo SRAM, as described above. According to a preferred embodiment of the method of the present invention, the rewrite operation is performed by driving the pair of bit lines to a voltage difference higher than the positive power supply voltage of the 2P2N pseudo SRAM when the word line is at the positive power supply voltage, and thereby performing PMOS access. Completed by turning on the transistor slightly and having a small rewrite current.

According to a specific example of the concealed rewriting method according to the present invention, the rewriting operation for the pseudo SRAM is performed when the sense amplifier connected to the pair of bit lines is operating. The read time does not increase. Furthermore, the voltage difference is the two PM
It is smaller than the threshold voltage of the OS access transistor.
By supplying enough current to the cross-pair latch,
A time period is provided to ensure that the logic "1" signal stored therein is regained.

[0022]

BRIEF DESCRIPTION OF THE DRAWINGS In order to further clarify the above and other objects, features and advantages of the present invention, preferred embodiments are described below with reference to the drawings. FIG. 1A is a circuit diagram showing a memory cell of a hidden rewrite 2P2N pseudo SRAM according to the present invention. As shown in FIG. 1A, the memory cell includes two NMOS transistors N5 and N6.
And two PMOS transistors P5 and P6.

The NMOS transistors N5 and N6
Represents a source connected to the negative power supply voltage and data (signal S
/ S '), each having a drain and a gate joined together to form a cross-paired latch for preservation.

The PMOS transistors P5 and P6
Is a gate connected to the word line WL and a bit line BL /
The signal S is connected to BL 'and the drains of the NMOS transistors N1 and N2 of the cross pair latch, respectively.
/ S ′ to access the source / drain.

The diode reverse bias voltage I (LEAK
AGE) and the sub-threshold current I (SUB) of the transistor (for example, the transistor used in the present invention) are represented by the following equations. I (LEAKAGE) = A ・ Is (e ^{V / VT} -1) I (SUB) ∝ (W / L) ・ e ^{(Vgs-Vt) / nVT} [1-e- ^{Vds / VT} ]

In these equations, A is the area of the diode, W / L is the width / length ratio of the transistor, Vgs is the bias between the gate and source of the transistor, and Vt is , The threshold voltage of the transistor.

Therefore, the leakage current ID3 + IN6 and the supply current ID2 + IP6 can be effectively controlled by changing the process parameters or layout of the SRAM.
When the PMOS transistors P5 and P6 are off (closed) (the word line is "1"), for example, the node (nod)
e) The logic "1" signal stored in S 'is in a floating state. At this time, as shown in FIG. 1B, two parasitic diodes D2 (located at the source / drain junction of the NMOS transistor N6) and D3 (located at the source / drain junction of the PMOS transistor P6) are connected. , And two reverse bias currents ID2 and ID3, respectively. Further, although the NMOS transistor N6 and the PMOS transistor P6 are off,
Two sub-threshold currents IN6 and IP6 are applied to node S '. Next, the node S 'is provided with a leakage current ID3 + IN6 for decreasing the voltage level at the node S' and a supply current ID2 + IP6 for increasing the voltage level at the node S '. Therefore, as long as the supply current is controlled to be larger than the leakage current (eg, ID2 + IP6> ID3 + IN6), data loss in the SRAM can be prevented.

Further, in order to secure a sufficient supply current, a rewriting method by boosting the bit line is provided as a specific example of the present invention, which will be described in detail below. When the PMOS transistors P5 and P6 are off (the word line WL is "1"), the pair of bit lines BL / B
L ′ is driven up to VDD + V. VDD
Is a positive power supply voltage, V is a voltage difference smaller than the threshold voltage | VTP | of the PMOS transistor, and a small rewrite current is generated by turning on the PMOS transistors P5 and P6 slightly. Provided to provide a 1 "signal. As long as the rewrite time is long enough, the logic "1" signal can be raised to VDD + V. Further, this embodiment of the method of the present invention rewrites a column of memory cells that are connected to bit lines BL / BL 'substantially simultaneously. For conventional 4T memory cells, the method according to the present invention does not cause the bit line voltage to drop rapidly by causing a large current in the logic "0" signal (since V <VT). Thus, the method according to the invention allows the column of memory cells to be rewritten almost simultaneously and does not cause data confusion between different memory cells.

As described above, the method of the present invention does not require sequentially opening the corresponding word lines, and the bit lines BL / BL '.
Is driven up to VDD + V, so that one column of memory cells can be rewritten in a single cycle. Therefore, the method according to the present invention is simple in operation, and as a result, the power consumption in the SRAM can be reduced.

In a further embodiment of the present invention, one or a predetermined number of columns of memory cells are implemented using a multiplexer to reduce power supply loading and increase noise margin when rewriting multiple columns of memory cells. Rewritten within a single cycle. The multiplexer is controlled by a counter or a shift register.

FIG. 2 is a timing chart showing a rewrite operation of the 2P2N pseudo SRAM of the present invention. In FIG.
The timer signal is determined by the detection of the leakage current to drive the counter to generate an address representing the execution time of the rewrite operation. Then, the rewrite pulses REF1, REF2,
REFk is generated by decoding the address generated by the counter with an address decoder. The counter is reset after generating a predetermined number of pulses, and is restarted until the next timer signal, thereby preventing a very large number of columns of memory cells from being rewritten substantially simultaneously.

Specific examples of the read operation and the write operation of the rewriting method according to the present invention will be described in detail below. A. Read operation In the read operation, the write enable signal WE '
Is a logic “1”, and the chip selection signal CS ′ is
Logic "0". Precharge enable signal PRE
Is activated by the rising edge of the system clock CLK and has a pulse width determined by the delay element. Then, the word line enable signal WL is
It is activated from the falling edge of the precharge enable signal PRE and has a pulse width determined by the delay element. After the word line WL is turned on for a short time and a voltage difference (eg, 0.1 to 0.3 V) appears between the bit lines BL / BL ', the sense amplifier enable signal SA
The logic "1" amplifies the voltage difference.
This not only accelerates the read operation, but also
Reduce the power consumption of M. Word line WL is also
The sense amplifier SA is turned off after the swing and power consumption of the signal on the bit lines BL / BL 'can be reduced. Thereafter, the rewrite enable signal REF is activated from the falling edge of the word line enable signal and has a pulse width determined by the delay element. Since the rewrite enable signal REF is activated when the sense amplifier SA is available and the word line WL is off, the rewrite method according to the present invention does not increase the read time of the SRAM.

B. Write Operation In a write operation, the chip select signal CS 'is at logic "0" and the write enable signal WE' is at logic "0". At this time, the corresponding timing of all the signals is almost the same as the read operation except that the sense amplifier enable signal SA is not required and the write enable signal WE 'is used for controlling the data input. Further, when the chip select signal CS 'is logic "1" and the write enable signal WE' is optional, no read or write operation is performed. At this time, the hidden type rewriting is performed only by generating the rewriting enable signal REF and the counter address.

As described above, the hidden rewrite 2P2N pseudo SRAM according to the present invention has a smaller chip area than the conventional 6TSRAM. The hidden rewriting method according to the present invention is easy to operate and consequently reduces power consumption in the SRAM. Further, the hidden rewrite operation according to the present invention is performed when the sense amplifier is operable, so that the read time of the SRAM is reduced.

The present invention also relates to a method as shown in FIG.
It can be applied to T (six element) memory cells. Referring to FIG. 3, the access transistors are NMOS transistors, and the PMOS load transistors each have a gate connected to a positive power supply voltage. In normal operation, the PMOS load transistors, like conventional 4T memory cells, each have a source connected to the positive power supply voltage VDD. However, in a rewrite operation according to the present invention, the PMOS load transistor will be at VDD + | VTP |
Each has a source connected to it.

Although the present invention discloses preferred embodiments as described above, they are not intended to limit the invention in any way, and any person skilled in the art does not depart from the spirit and scope of the invention. Various changes and changes can be made within the scope, and accordingly, the protection scope of the present invention is based on the contents specified in the claims.

[0037]

The rewrite pseudo SRAM according to the present invention
Is a hidden rewrite 2P having a plurality of memory cells.
Each memory cell is a 2N pseudo SRAM, and each memory cell is controlled by a word line and a cross pair latch composed of two NMOS transistors crossing each other, and accesses the NMOS transistor and a pair of bit lines of the cross pair latch, respectively. , A hidden rewrite 2P2N pseudo SR that prevents data confusion when turning on a plurality of word lines simultaneously and reduces power consumption.
AM can be provided. Also, the SR according to the present invention
AM can have a smaller chip area than a conventional SRAM.

A method of rewriting a pseudo SRAM according to the present invention is characterized in that a plurality of memory cells each having a crossed pair latch composed of two NMOS transistors crossed and connected to each other are controlled by a word line. A step of previously providing a hidden type 2P2N pseudo SRAM including an NMOS transistor and two PMOS access transistors respectively accessing a pair of bit lines; and, when the word line is at a positive power supply voltage, the hidden type 2
Driving the pair of bit lines up to a first voltage higher than the positive power supply voltage of the P2N pseudo SRAM by the first voltage, so that the operation is simple and the power consumption in the SRAM can be reduced as a result. Further, according to the present invention, since the operation is performed when the sense amplifier is operable, the read time of the SRAM is reduced.

Since the voltage difference is made smaller than the threshold voltage of the PMOS access transistor, as long as the supply current is controlled to be larger than the leakage current, S
Data loss in the RAM can be prevented.

Since a time limit is given in the driving step, it is possible to supply a sufficient current to the crossed pair latch and to recover the stored data.

The method further includes the steps of starting the precharge enable signal by the rising and falling edges of the system clock in the SRAM, turning on the word line, and expressing a voltage difference between the bit lines. In addition, the read operation can be accelerated, and the power consumption of the SRAM can be reduced.

Since the method further includes the step of amplifying the voltage difference using the sense amplifier enable signal, the read operation can be accelerated and the power consumption of the SRAM can be reduced.

The method further includes the steps of enabling the sense amplifier to amplify the voltage difference, turning off the word line after the sense amplifier has amplified the voltage difference, and reducing the fluctuation of the signal on the bit line. Therefore, the power consumption of the SRAM can be reduced.

According to the present invention, 1T1C memory cells, 3
It can be used for any of the group consisting of T memory cells, 4T memory cells, and 6T memory cells.

The method further includes the steps of resetting the counter after a predetermined number of rewrite pulses have been generated, and activating the counter with the next timer signal.
Reset after generating a predetermined number of pulses,
By starting again until the next timer signal, it is possible to prevent the memory cells in an extremely large number of columns from being rewritten almost simultaneously.

[Brief description of the drawings]

FIGS. 1A and 1B show an embodiment of a hidden rewrite 2P2N pseudo SRAM according to the present invention, in which FIG. 1A is an electric circuit diagram, and FIG. 1B is a cross-sectional diagram formed on a semiconductor substrate.

FIG. 2 is a timing diagram illustrating an exemplary rewrite operation of an SRAM according to the present invention.

FIG. 3 is an electric circuit diagram showing another application example of the SRAM according to the present invention.

4A and 4B show a conventional DRAM, in which FIG.
FIG. 2B is an electric circuit diagram showing the 1C memory cell, and FIG. 2B is a cross-sectional view of the 1T1C memory cell shown in FIG. 1A formed on a semiconductor substrate.

FIG. 5 is an electric circuit diagram showing another conventional 3T memory cell.

FIG. 6 is an electric circuit diagram showing another conventional 4T memory cell.

FIG. 7 shows still another conventional memory cell;
(A) is an electric circuit diagram showing a 6T memory cell, (b)
Is an electric circuit diagram showing a 6T memory cell different from (a),
(C) is an electric circuit diagram showing a 4T memory cell using a poly load, and (d) is an electric circuit diagram showing a 6T memory cell using a TFT load.

FIG. 8 shows a conventional pseudo SRAM driving circuit,
(A) is a block diagram of a first example, (b) is a block diagram of a second example, and (c) is a block diagram showing a shift register in (b).

[Explanation of symbols]

10: memory array, 11: row address decoder, 12
... column address decoder, 13 ... multiplexer, 14 ...
Rewrite counter, 15 control device, 16 shift register, BL, BL 'bit line, CA column address,
CLK: system clock, CS: storage capacitor, D
1, D2, D3: parasitic diode, ID2 + IP6: supply current, ID3 + IN6: leakage current, L: load, N1
N6: NMOS transistor, P1 to P6: PMOS transistor, R1, R2: resistor, RA: row address, R
BL: read bit line, RWL: read word line,
S, S '... signal, T1 ... access transistor, T2 ...
Read transistor, T3 ... Storage transistor, T4
... Write transistors, TFT1, TFT2, thin film transistors, WBL, word bit lines, WL, word lines, WWL, write word lines.

Claims (17)

[Claims] 1. A hidden rewrite 2P2N pseudo SRAM having a plurality of memory cells, wherein each memory cell comprises:
A cross-pair latch consisting of two NMOS transistors intersecting each other, and two PMOS access transistors controlled by a word line and respectively accessing the NMOS transistor and the pair of bit lines of the cross-pair latch. A rewrite pseudo SRAM characterized by the features. 2. The NMOS transistor of the cross pair latch includes a first NMOS transistor and a second NMOS transistor, wherein the first NMOS transistor has a gate, a drain, and a source connected to a negative power supply voltage, and the second NMOS transistor The transistor includes the first N
2. The rewrite pseudo-SRAM according to claim 1, comprising a gate connected to the drain of a MOS transistor, a drain connected to the gate of the first NMOS transistor, and a source connected to the negative power supply voltage. 3. The PMOS transistor is a first PMOS transistor.
And a second PMOS transistor, wherein the first PMOS transistor has a gate connected to a word line, a source connected to one of bit lines, and a first PMOS transistor.
The second PMOS transistor is connected to a gate connected to a word line, a source connected to the other of the bit lines, and connected to the drain of the second NMOS transistor. 3. The rewrite pseudo SRAM according to claim 2, comprising a drain. 4. Two NMOSs crossing and connected to each other
A concealed 2P2N pseudo memory comprising a plurality of memory cells each having a cross-pair latch composed of transistors, and two PMOS access transistors controlled by a word line and respectively accessing the NMOS transistor and the pair of bit lines of the cross-pair latch. It is characterized by comprising a step of providing an SRAM in advance and a step of driving a pair of bit lines to a voltage higher than the positive power supply voltage of the hidden 2P2N pseudo SRAM by a voltage difference when the word line is at the positive power supply voltage. Rewriting method of pseudo SRAM. 5. The NMOS transistor of the cross pair latch comprises a first NMOS transistor and a second NMOS transistor, wherein the first NMOS transistor comprises a gate, a drain, and a source connected to a negative power supply voltage, and the second NMOS transistor comprises: The transistor is the first transistor.
The pseudo transistor according to claim 4, further comprising a gate connected to the drain of the NMOS transistor, a drain connected to the gate of the first NMOS transistor, and a source connected to the negative power supply voltage. S
How to rewrite RAM. 6. The first PMOS transistor is a first PMOS transistor.
A transistor and a second PMOS transistor,
The first PMOS transistor includes a gate connected to a word line, a source connected to one of bit lines, and a drain connected to a drain of a first NMOS transistor, and the second PMOS transistor is connected to a word line. 5. The method according to claim 4, further comprising a gate connected to the bit line, a source connected to the other of the bit lines, and a drain connected to a drain of the second NMOS transistor. 7. The pseudo SRAM is rewritten when a sense amplifier connected to a bit line is operating to prevent an increase in the read time of the pseudo SRAM. Pseudo SRA according to 4
How to rewrite M. 8. The method according to claim 4, wherein the voltage difference is smaller than a threshold voltage of the PMOS access transistor. 9. The pseudo-SRAM of claim 4, wherein a time limit is provided in the driving step to supply sufficient current to the crossed pair latches to ensure that stored data is recovered. Rewriting method. 10. A method performed in a read operation of an SRAM, the method comprising: activating a precharge enable signal by rising and falling edges of a system clock in the SRAM; turning on a word line; And restoring the pseudo SRAM between the bit lines. 11. A method performed in a read operation of an SRAM, in which the read operation is accelerated.
5. The pseudo SRAM of claim 4, further comprising amplifying a voltage difference using a sense amplifier enable signal for reducing power consumption of the SRAM.
Rewriting method. 12. A method performed in a read operation of an SRAM, wherein a step of allowing a sense amplifier to amplify a voltage difference, and a step of turning off a word line after the sense amplifier is able to amplify the voltage difference. 5. The method according to claim 4, further comprising the step of reducing the fluctuation of the signal of the bit line, so as to reduce the power consumption of the SRAM. 13. A method performed in a read operation of an SRAM, further comprising the step of amplifying a voltage difference and activating a rewrite enable signal when a word line is off as in the case of reducing the read time in the SRAM. The method of claim 4, wherein the method includes rewriting the pseudo SRAM. 14. A method performed in a write operation of an SRAM, further comprising: providing a write enable signal for controlling data input to the SRAM; and generating a rewrite enable signal. The method for rewriting a pseudo SRAM according to claim 4. 15. The pseudo-SRAM rewrite of claim 4, including a method used for any of the group consisting of 1T1C memory cells, 3T memory cells, 4T memory cells, and 6T memory cells. Method. 16. A step of detecting a leakage current, a step of driving a counter by judging a timer signal to generate an address representing a rewrite execution time for each memory cell in the SRAM, The method of claim 4, further comprising: decoding the address; and generating a rewrite pulse corresponding to each address of the memory cell. 17. The method of claim 16, further comprising: resetting the counter after a predetermined number of rewrite pulses have occurred; and activating the counter with a next timer signal. Rewriting method of pseudo SRAM.