CN116266469A - Data latch circuit and semiconductor memory device - Google Patents

Abstract

Embodiments provide a data latch circuit and a semiconductor memory device capable of miniaturization. In general, according to one embodiment, the data latch circuit includes a first transistor of the first conductivity type, a second transistor of the first conductivity type, a third transistor of the second conductivity type, and a fourth transistor of the second conductivity type. The third transistor and the fourth transistor are controlled to perform a first control action to store data in the data latch circuit, and to perform a second control action to read the stored data.

Description

Data latch circuit and semiconductor memory device

Cross References to Related Applications

This application is based on Japanese Patent Application No. 2021-204613 filed on December 16, 2021 and U.S. Patent Application No. 17/898868 filed on August 30, 2022 and claims priority from these applications, and is hereby incorporated by reference The entire contents of these applications are incorporated herein.

technical field

In summary, the embodiments described herein relate to data latch circuits and semiconductor memory devices.

Background technique

The bit density of flash memory continues to increase through the use of multi-level cells (MLC) and three-dimensional stacking. As its bit density increases, the area of peripheral circuits also increases. Among peripheral circuits, a data latch circuit (also called a page buffer: pagebuffer) occupies the largest area. When the data latch circuit cannot be made small, it is difficult to reduce the size of the flash memory chip.

Contents of the invention

Embodiments provide a data latch circuit and a semiconductor memory device capable of miniaturization.

In general, according to one embodiment, the data latch circuit includes a first transistor of the first conductivity type, a second transistor of the first conductivity type, a third transistor of the second conductivity type, and a fourth transistor of the second conductivity type. The third transistor and the fourth transistor are controlled to perform a first control action to store data in the data latch circuit, and to perform a second control action to read the stored data.

Description of drawings

1 is a block diagram showing a schematic configuration of a semiconductor memory device including a data latch circuit according to a first embodiment.

FIG. 2 is a circuit diagram of a data latch circuit according to a comparative example.

FIG. 3A is a diagram showing features of a data latch circuit according to the first embodiment.

FIG. 3B is a circuit diagram of a data latch circuit according to the first embodiment.

FIG. 4A is a diagram showing the operation of the data latch circuit according to the first embodiment.

FIG. 4B is a graph showing voltages of word lines and bit lines when the data latch circuit in FIG. 4A reads data, writes data, and stores data.

FIG. 5 is a graph showing memory characteristics of the semiconductor memory device according to the first embodiment.

FIG. 6 is a layout diagram of a data latch circuit according to the first embodiment.

FIG. 7 is a cross-sectional view showing a stacked position of each layer in FIG. 6 .

FIG. 8 is a layout view in which a plurality of data latch circuits having the layout arrangement in FIG. 6 are located in a two-dimensional direction.

9A is a layout diagram of a first modified example of the data latch circuit according to the first embodiment.

FIG. 9B is a diagram showing a configuration in which the layout arrangement in FIG. 9A is shifted left or right by half a period.

FIG. 10A is a layout diagram in which a plurality of data latch circuits having the layout arrangement in FIG. 9A are arranged in each of a first direction and a second direction.

FIG. 10B is a layout diagram in which a plurality of data latch circuits having the layout arrangement in FIG. 9B are arranged in each of a first direction and a second direction.

FIG. 11A is a diagram showing features of a data latch circuit according to the second embodiment.

FIG. 11B is a circuit diagram of a data latch circuit according to the second embodiment.

FIG. 11C is a graph showing voltages of word lines and bit lines when the data latch circuit in FIG. 11B reads data, writes data, and stores data.

FIG. 12 is a layout diagram of a data latch circuit according to the second embodiment.

FIG. 13 is a layout view in which a plurality of data latch circuits having the layout arrangement in FIG. 12 are located in a two-dimensional direction.

14A is a layout diagram of a first modification example of the data latch circuit according to the second embodiment.

Fig. 14B is a layout diagram of a second modification.

FIG. 15A is a layout diagram in which a plurality of data latch circuits having the layout arrangement in FIG. 14A are arranged in each of a first direction and a second direction.

FIG. 15B is a layout diagram in which a plurality of data latch circuits having the layout arrangement in FIG. 14B are arranged in each of the first direction and the second direction.

FIG. 16A is a diagram showing features of a data latch circuit according to the third embodiment.

FIG. 16B is a circuit diagram of a data latch circuit according to the third embodiment.

FIG. 16C is a graph showing voltages of word lines, bit lines, and control signals when the data latch circuit in FIG. 16B reads data, writes data, and stores data.

FIG. 17 is a layout diagram of a data latch circuit according to the third embodiment.

FIG. 18 is a layout view in which a plurality of data latch circuits having the layout arrangement in FIG. 17 are located in a two-dimensional direction.

FIG. 19A is a diagram showing features of a data latch circuit according to the fourth embodiment.

FIG. 19B is a circuit diagram of a data latch circuit according to the fourth embodiment.

FIG. 19C is a graph showing voltages of word lines, bit lines, and control signals when the data latch circuit in FIG. 16B reads data, writes data, and stores data.

FIG. 20 is a layout diagram of a data latch circuit according to a fourth embodiment.

FIG. 21 is a layout view in which a plurality of data latch circuits having the layout arrangement in FIG. 20 are located in a two-dimensional direction.

Detailed ways

Hereinafter, embodiments of a data latch circuit and a semiconductor memory device will be described in detail with reference to the accompanying drawings. In the following description, the main components of the data latch circuit and the semiconductor memory device will be mainly described. The data latch circuit and the semiconductor memory device may have components and functions not shown in the drawings or described in this specification. The following description does not exclude components or functions not shown in the drawings or described in this specification.

first embodiment

1 is a block diagram showing a schematic configuration of a semiconductor memory device 1 including a data latch circuit 10 according to the first embodiment. A semiconductor memory device 1 in FIG. 1 shows a schematic configuration of a flash memory. The semiconductor memory device 1 according to the present embodiment can be applied to various types of semiconductor memories other than flash memory. Specifically, the semiconductor memory device 1 according to the present embodiment can be applied to nonvolatile memories such as MRAM (Magnetoresistive Random Access Memory), and can also be applied to nonvolatile memories such as DRAM (Dynamic Random Access Memory) and Volatile memory such as SRAM (Static Random Access Memory). Furthermore, the flash memory may be a NAND flash memory or a NOR flash memory, and the semiconductor memory device 1 according to the present embodiment is applicable to both the NAND flash memory and the NOR flash memory. In the following description, an example in which the semiconductor memory device 1 according to the present embodiment is applied to a flash memory will be mainly described.

A semiconductor memory device 1 in FIG. 1 includes a plurality of memory modules 2, a serial conversion section 3, an I/O signal processing section 4, a high voltage generation circuit 5, a low voltage generation circuit 6, a synchronization control section 7, and a row control section 8. and Column Control 9.

Each of the memory modules 2 includes a memory cell array 11 , a row decoder 12 , a sense amplifier & data latch section 13 , a transfer data latch section 14 and a column decoder 15 .

The memory cell array 11 has a configuration in which a plurality of strings having a plurality of NAND flash memory cells provided therein in a cascode connection are arranged in a two-dimensional configuration. Row decoder 12 decodes row address signals and drives corresponding word lines.

The sense amplifier & data latch unit 13 writes data into the memory cell array 11 and reads data from the memory cell array 11 through the bit line BL. According to the present embodiment, the sense amplifier & data latch section 13 includes a data latch circuit (DL) 10 configured to store data to be written into the memory cell array 11 and to store data read from the memory cell array 11 .

The transfer data latch section 14 temporarily stores data to be written into the memory cell array 11 or data to be read from the memory cell array 11 . The transmission data latch section 14 also includes the data latch circuit 10 according to the present embodiment.

The column decoder 15 performs prescribed arithmetic processing including decoding processing of data to be written into the memory cell array 11 or data to be read from the memory cell array 11 .

The serial conversion section 3 converts the data read from the memory cell array 11 into serial data, and supplies the converted data to the I/O signal processing section 4 . Also, the serial conversion section 3 converts the serial data to be written and sent from the I/O signal processing section 4 into parallel data, and sends it to the column decoder 15 .

The I/O signal processing unit 4 performs high-speed serial communication with the controller 16 . The high voltage generation circuit 5 boosts a power supply voltage VDD supplied from the outside, thereby generating high voltages VPGM, VERA, VPASS, etc., for use when writing data to or erasing data from memory cells.

The low voltage generation circuit 6 generates reference voltages, clock signals, low power supply voltages, and the like to be used in the semiconductor memory device 1 .

The synchronization control section 7 performs timing control, sequence control, and parameter control for each block in the semiconductor memory device 1 .

The row control section 8 controls the timing of driving the word lines in each memory cell array 11 . The column control unit 9 controls the timing of driving the bit lines of each memory cell array 11 .

As described above, the data latch circuit 10 according to the present embodiment is provided in the sense amplifier & data latch section 13 and the transfer data latch section 14 in the semiconductor memory device 1 in FIG. 1 . The data latch circuit 10 according to this embodiment may be provided in a position other than the sense amplifier & data latch section 13 and the transfer data latch section 14 .

Flash memory with the block configuration shown in Figure 1 is currently the lowest cost non-volatile memory and is commonly used as mass storage in a variety of applications. In the block configuration shown in FIG. 1, components other than the memory cell array 11 may be referred to as peripheral circuits. The data latch circuit 10 occupies most of the area of peripheral circuits. The data latch circuit 10 serving as a temporary storage place is configured to temporarily store data to be written into the memory cell array 11 and data read from the memory cell array 11 .

In a flash memory configured to change from a planar structure to a three-dimensional structure, its bit density is increased by increasing the number of bits per cell, implementing a multi-level cell (MLC), and increasing the number of stacked word lines. Here, as its bit density increases, the area of peripheral circuits increases.

When the ratio of the area of the peripheral circuit to the total area of the flash memory chip becomes larger, the number of bits per wafer decreases and the bit cost increases. As a solution to reduce the area of the flash memory chip, a CUA (CMOS under array: CMOS under the array) structure and a CBA (CMOS bonded array: array bonded CMOS) structure in which the peripheral circuit is arranged under the memory cell array 11 have been proposed. In the structure, the wafer provided with the memory cell array and the wafer provided with peripheral circuits are bonded together. In the CUA structure and the CBA structure, when the area of the peripheral circuit is larger than the area of the memory cell array 11, the area of the flash memory chip will also increase.

Therefore, the semiconductor memory device 1 according to the present embodiment is characterized in that the area of the data latch circuit 10 in the peripheral circuit is reduced. Hereinafter, first, a circuit configuration of a general-purpose data latch circuit 100 according to a comparative example will be described.

FIG. 2 is a circuit diagram of a data latch circuit 100 according to a comparative example. The data latch circuit 100 in FIG. 2 includes eight transistors Q1 to Q8. Among the eight transistors Q1 to Q8, four transistors are NMOS transistors Q1 to Q4, and the remaining four transistors are PMOS transistors Q5 to Q8.

The drain of transistor Q1 is connected to the gate of transistor Q2, the drain of transistor Q3, the drain of transistor Q7 and the gate of transistor Q8. The drain of transistor Q2 is connected to the gate of transistor Q1, the drain of transistor Q4, the gate of transistor Q7, and the drain of transistor Q8. The sources of transistors Q1 and Q2 are connected to a reference voltage node VSS (eg, a ground node).

Word line WL1 is connected to the gate of transistor Q3, and word line WL2 is connected to the gate of transistor Q4. Only one of the word lines WL1 and WL2 becomes high level. The sources of transistors Q3 and Q4 are connected to bit line BL.

In this way, the data latch circuit 100 in FIG. 2 includes two word lines WL1 and WL2 and one bit line BL.

The source of the transistor Q5 is connected to the power supply voltage node VDD, the drain of the transistor Q5 is connected to the source of the transistor Q7, and the control signal Vctl is input to the gate of the transistor Q5. The source of the transistor Q6 is connected to the power supply voltage node VDD, the drain of the transistor Q6 is connected to the source of the transistor Q8, and the control signal Vctl is input to the gate of the transistor Q7. When the control signal Vctl is at low level, both transistors Q5 and Q6 are turned on. In this case, when the word line WL1 or WL2 goes high, the nodes n1 and n2 store data on the bit line BL.

As shown in FIG. 2, the data latch circuit 100 according to the comparative example is formed of eight transistors Q1 to Q8. Therefore, as the number of data latch circuits 100 increases, the number of transistors increases by a factor of 8, which results in an increase in the area of the semiconductor memory device 1 .

FIG. 3A is a diagram showing features of the data latch circuit 10 according to the first embodiment, and FIG. 3B is a circuit diagram of the data latch circuit 10 according to the first embodiment.

As shown in FIG. 3A , the data latch circuit 10 according to the first embodiment has a configuration in which the first transistors including transistors Q5 and Q6 are omitted from the data latch circuit 100 according to the comparative example of FIG. 2 Group 21, a second transistor group 22 including transistors Q7 and Q8, and VDD. Furthermore, the data latch circuit 10 according to the first embodiment includes PMOS transistors Q3 a and Q4 a instead of the NMOS transistors Q3 and Q4 in FIG. 2 .

As described above, the data latch circuit 10 according to the first embodiment includes two NMOS transistors Q1 and Q2 and two PMOS transistors Q3a and Q4a.

As shown in FIG. 3B, the drain of transistor Q1 is connected to the gate of transistor Q2 and the source of transistor Q3a. This connected node is referred to as node n1. The drain of transistor Q2 is connected to the gate of transistor Q1 and the source of transistor Q4a. This connected node is referred to as node n2.

The sources of transistors Q1 and Q2 are connected to the ground node. The gate of transistor Q3a is connected to word line WL1, and the gate of transistor Q4a is connected to word line WL2. The drains of transistors Q3a and Q4a are connected to the bit line.

FIG. 4A is a diagram showing the operation of the data latch circuit 10 according to the first embodiment. The data latch circuit 10 according to the first embodiment performs a data write operation, a data storage operation, and a data read operation. The two word lines WL1 and WL2 do not become low at the same time. When one of the word lines WL1 and WL2 becomes high level, a data writing operation is performed. For example, when word line WL1 is at low level and word line WL2 is at high level, transistor Q3a is turned on and transistor Q4a is turned off. Therefore, the voltage of the bit line BL is transferred to the node n1 via the transistor Q3a. For example, when the bit line BL has a low voltage, the node n1 also becomes a low voltage, and when the bit line BL has a high voltage, the node n1 also becomes a high voltage. Node n2 becomes the inverse logic voltage of node n1. Transistors Q1 and Q2 perform an operation of storing potentials of nodes n1 and n2.

In the data storage operation, both word lines WL1 and WL2 are set to a voltage level slightly lower than the power supply voltage VDD. Set bit line BL to VDD. The voltage level slightly lower than the power supply voltage VDD is, for example, a voltage level 5% to 30% lower than the power supply voltage VDD. Specifically, during data storage at nodes n1 and n2, the voltage levels at the gates of transistors Q3a and Q4a are lowered by the following percentages: Any percentage within the range of 5% to 30% of the voltage level on the higher side of the level. The reason for setting word lines WL1 and WL2 to a voltage level slightly lower than power supply voltage VDD during data storage is to allow leakage current to flow through transistors Q3a and Q4a whose gates are connected to word lines WL1 and WL2, respectively.

For example, when the node n1 has a low voltage, the transistor Q1 is turned on, and the voltage of the node n1 is stored in the low voltage from the ground voltage node VSS via the transistor Q1, as shown by the dotted arrow line y1 in FIG. 4A . On the other hand, the transistor Q2 is turned off, and the leakage current flowing from the bit line BL through the transistor Q4a stores the voltage of the node n2 at a high voltage, as indicated by the dotted arrow line y2 in FIG. 4A.

In this way, the word lines WL1 and WL2 are set to a voltage level slightly lower than the power supply voltage VDD, and the bit line BL is set to VDD. Here, when the node n1 has a high voltage, the leakage current flowing from the bit line BL through the transistor Q3a maintains the voltage level of the node n1. In addition, when the node n2 has a high voltage, the leakage current flowing from the bit line BL through the transistor Q4a maintains the voltage level of the node n2.

FIG. 4B is a graph showing voltages of the word lines WL1 and WL2 and the bit line BL when the data latch circuit 10 in FIG. 4A reads data, writes data, and stores data. FIG. 4B shows an example of accessing word line WL1. Here, when the word line WL2 is accessed, the voltage relationship between the word lines WL1 and WL2 in FIG. 4B is reversed.

When the data latch circuit 10 reads the data stored in the nodes n1 and n2 via the transistor Q3a, the word line WL1 is set to the ground voltage VSS (for example, 0V), and the word line WL2 is set to be slightly lower than the power supply voltage VDD voltage (for example, VDD×0.95-0.7V). In addition, the bit line BL is precharged to the power supply voltage VDD. Therefore, the data stored in the nodes n1 and n2 are read in the bit line BL via the transistor Q3a.

When the data latch circuit 10 writes data into the nodes n1 and n2 via the transistor Q3a, the word line WL1 is set to the ground voltage VSS (for example, 0V), and the word line WL2 is set to the power supply voltage VDD. When the data to be written is 0, the bit line BL is set to the ground voltage VSS (for example, 0V). Therefore, data of "0" is stored in the nodes n1 and n2 through the transistor Q3a. Meanwhile, when the data to be written is 1, the bit line BL is set to the power supply voltage VDD.

When the data latch circuit 10 stores data in the nodes n1 and n2, the word lines WL1 and WL2 are set to a voltage slightly lower than the power supply voltage VDD (for example, VDD×0.95-0.7V), and the bit line BL is set to is the supply voltage VDD.

FIG. 5 is a graph showing memory characteristics of the semiconductor memory device 1 according to the first embodiment. The horizontal axis in FIG. 5 is the voltage level of the node n2, and the vertical axis in FIG. 5 is the voltage level of the node n1. The curve w1 in FIG. 5 shows the change of the voltage level of the node n1 relative to the voltage of the node n2, and the curve w2 shows the change of the voltage level of the node n2 relative to the voltage of the node n1. As shown in FIG. 5, it can be seen that nodes n1 and n2 are stable at two points p1 and p2, and have good storage properties. At point p1, the voltage level of node n1 is the power supply voltage VDD. At point p2, the voltage level of node n2 is the power supply voltage VDD.

FIG. 6 is a layout view of the data latch circuit 10 according to the first embodiment, and FIG. 7 is a cross-sectional view showing a stacked position of each layer in FIG. 6 . As shown in FIG. 7 , the data latch circuit 10 according to the first embodiment is formed by stacking a plurality of layers having different layer heights, and includes a plurality of contacts CT0 and CT1 configured to electrically connect the respective layers. Figure 6 shows the planar structure of multiple layers with different layer heights viewed in the lamination direction. The layout and cross-sectional views of the data latch circuit 10 according to the first embodiment are not necessarily limited to those shown in FIGS. 6 and 7 . The black and gray circles in Figure 6 represent contacts.

In the examples of FIGS. 6 and 7 , the first diffusion region D1 and the second diffusion region D2 are located in the lowermost layer. The first diffusion area D1 and the second diffusion area D2 may be referred to as active areas. The first diffusion area D1 and the second diffusion area D2 are separated from each other in the first direction X. Source and drain regions of the transistors Q1 and Q2 are formed in the first diffusion region D1. Source and drain regions of the transistors Q3a and Q4a are formed in the second diffusion region D2. The first diffusion region D1 and the second diffusion region D2 are formed by implanting impurity ions such as boron (B), phosphorus (P), and arsenic (As) into a semiconductor substrate and thermally diffusing therein.

A first gate layer G1 connected to the gate of the transistor Q3a and a second gate layer G2 connected to the gate of the transistor Q4a are located on the second diffusion region D2 via an insulating layer. A third gate layer G3 connected to the gate of the transistor Q1 and a fourth gate layer G4 connected to the gate of the transistor Q2 are located on the first diffusion region D1 through an insulating layer.

The first to fourth gate layers G1 to G4 are located at the same layer height. Specifically, each of the first to fourth gate layers G1 to G4 extends in the second direction Y. Referring to FIG. In addition, the first to fourth gate layers G1 to G4 are separated from each other in the first direction X. Referring to FIG.

The first metal layer M1 is located on the first to fourth gate layers G1 to G4 via an insulating layer. The first metal layer M1 is made of tungsten (W), copper (Cu), aluminum (A1), or the like. The first metal layer M1 includes a first wiring layer WR1 , a second wiring layer WR2 , a third wiring layer WR3 , and a fourth wiring layer WR4 each extending in the first direction X. Here, the first to fourth wiring layers WR1 to WR4 are separated from each other in the second direction Y. Referring to FIG.

The first wiring layer WR1 is the bit line BL connected to the drain of the transistor Q3a and the drain of the transistor Q4a. The second wiring layer WR2 is connected to the drain of the transistor Q1, the fourth gate layer G4, and the source of the transistor Q3a. The third wiring layer WR3 is connected to the drain of the transistor Q2, the third gate layer G3, and the source of the transistor Q4a.

The fourth wiring layer WR4 is connected to source regions of the transistors Q1 and Q2 in the first diffusion region D1.

The second metal layer M2 is located on the first metal layer M1 via an insulating layer. The second metal layer M2 is made of tungsten (W), copper (Cu), aluminum (Al) or the like.

The second metal layer M2 has a fifth wiring layer WR5. The fifth wiring layer WR5 is set to the ground voltage VSS (first reference voltage). The fifth wiring layer WR5 is located over the first diffusion region D1 and extends in the second direction Y. The fifth wiring layer WR5 is connected to the fourth wiring layer WR4. Therefore, the fourth wiring layer WR4 is set to the ground voltage VSS. In addition, since the fourth wiring layer WR4 is connected to the source regions of the transistors Q1 and Q2 in the first diffusion region D1, these source regions are also set to the ground voltage VSS.

The first diffusion region D1, the second diffusion region D2, the first gate layer G1 to the fourth gate layer G4, and the first wiring layer WR1 to the second wiring layer WR4 in FIG. 6 are line-symmetrically arranged.

FIG. 8 is a layout diagram of a plurality of data latch circuits 10 having the layout arrangement in FIG. 6 in a two-dimensional direction. In FIG. 8, data latch circuits 10 having the layout arrangement in FIG. 6 are arranged in plural in each of the first direction X and the second direction Y. As shown in FIG. A plurality of data latch circuits located in the second direction Y share the word lines WL1 and WL2. A plurality of data latch circuits 10 located in the first direction X share the bit line BL.

The layout arrangements shown in FIGS. 6 and 8 are merely examples, and various modifications thereof are conceivable. For example, a point-symmetrical layout configuration may be adopted.

FIG. 9A is a layout diagram of a first modification example of the data latch circuit 10 according to the first embodiment, and FIG. 9B is a layout diagram of a second modification example thereof. Both FIGS. 9A and 9B have a point-symmetrical layout arrangement with respect to the center position of the layout area. In the configuration of FIG. 9B, the layout arrangement in FIG. 9A is shifted to the left or right by half a period. In the following description, details of the layout arrangement in FIG. 9A will be described, and description of the layout arrangement in FIG. 9B will be omitted. The hierarchical relationship among the layers shown in FIGS. 9A and 9B is the same as that in FIG. 7 .

In the layout arrangement in FIG. 9A , the first diffusion region D1 , the second diffusion region D2 , the third diffusion region D3 and the fourth diffusion region D4 are separated from each other in the second direction Y in the lowest layer. Each of the first to fourth diffusion regions D1 to D4 extends in the first direction X. Referring to FIG. The first gate layer G1, the second gate layer G2, the third gate layer G3, and the fourth gate layer G4 are separated from each other along the second direction Y above the first to second diffusion regions D1 to D4.

The first gate layer G1 overlaps the second diffusion region D2 in the stacking direction. The second gate layer G2 overlaps the third diffusion region D3 in the lamination direction. The third gate layer G3 overlaps the first diffusion region D1 in the stacking direction. The fourth gate layer G4 overlaps the fourth diffusion region D4 in the lamination direction.

The first metal layer M1 is located above the first gate layer G1 to the fourth gate layer G4. In the first metal layer M1, the second to ninth wiring layers WR2 to WR9 are separated from each other in the first direction X. Referring to FIG. Each of the second to fifth wiring layers WR2 to WR5 extends in the second direction Y.

The second wiring layer WR2 is a word line WL1 connected to the first gate layer G1. The third wiring layer WR3 is a word line WL2 connected to the second gate layer G2. The fourth wiring layer WR4 is connected to the drain region of the transistor Q1 in the first diffusion region D1, the source region of the transistor Q3a in the second diffusion region D2, and the fourth gate layer G4. The fifth wiring layer WR5 is connected to the third gate layer G3, the source region of the transistor Q4a in the third diffusion region D3, and the drain region of the transistor Q2 in the fourth diffusion region D4. The sixth wiring layer WR6 is connected to the source region of the transistor Q1 in the first diffusion region D1. The seventh wiring layer WR7 is connected to the drain region of the transistor Q3a in the second diffusion region D2. The eighth wiring layer WR8 is connected to the drain region of the transistor Q2 in the fourth diffusion region D4. The ninth wiring layer WR9 is connected to the drain region of the transistor Q4a in the third diffusion region D3.

The second metal layer M2 is located over the first metal layer M1 including the second to fifth wiring layers WR2 to WR5 . The second metal layer M2 includes a first wiring layer WR1, a tenth wiring layer WR10, and an eleventh wiring layer WR11. The first wiring layer WR1 is the bit line BL, and the tenth wiring layer WR10 and the eleventh wiring layer WR11 are wiring layers set to the ground voltage VSS.

The first wiring layer WR1 is located between the second diffusion region D2 and the third diffusion region D3. The tenth wiring layer WR10 is located near the first diffusion region D1. The eleventh wiring layer WR11 is located near the fourth diffusion region D4.

The first wiring layer WR1 is connected to the seventh wiring layer WR7, and is also connected to the ninth wiring layer WR9. The tenth wiring layer WR10 is connected to the sixth wiring layer WR6. The eleventh wiring layer WR11 is connected to the eighth wiring layer WR8.

FIG. 10A is a layout diagram of a plurality of data latch circuits 10 in a first direction X and a second direction Y having the layout arrangement in FIG. 9A . FIG. 10B is a layout diagram in which a plurality of data latch circuits 10 having the layout in FIG. 9B are respectively arranged in the first direction X and the second direction Y.

10A and 10B both have a point-symmetrical layout arrangement of the cells of FIGS. 9A and 9B , and have a symmetrical layout arrangement with respect to an axis extending in the second direction Y.

As described above, the data latch circuit 10 according to the first embodiment is formed of four transistors Q1, Q2, Q3a, and Q4a, thereby significantly reducing the circuit area. Data is stored in nodes n1 and n2, and during data storage, a voltage slightly lower than the power supply voltage VDD is applied to word lines WL1 and WL2, so data can be stably stored in nodes using leakage current from bit line BL n1 and n2. The data latch circuit 10 according to the first embodiment may be located in a line-symmetrical layout as shown in FIG. 6 , or may adopt a point-symmetrical layout as shown in FIG. 9A or 9B .

second embodiment

Although the data latch circuit 10 according to the first embodiment includes two word lines WL1 and WL2 and one bit line BL, each of which is connected to its corresponding part, the data latch circuit 10 may also have a BL and configuration of two bit lines BL and bBL, each connected to a corresponding component.

FIG. 11A is a diagram showing features of a data latch circuit 10a according to the second embodiment, and FIG. 11B is a circuit diagram of the data latch circuit 10a according to the second embodiment.

In the data latch circuit 10a according to the second embodiment, one word line WL and two bit lines BL and bBL are provided, each of which is connected to a corresponding part of the data latch circuit 10a. A common word line WL is connected to the gates of transistors Q3a and Q4a. Bit line BL is connected to the drain of transistor Q3a, and bit line bBL is connected to the drain of transistor Q4a. Bit lines BL and bBL have opposite logic levels with respect to each other. The connection relationship among other transistors Q1 to Q4a is the same as that of FIGS. 3A and 3B.

FIG. 11C is a graph showing the voltages of the word line WL, the bit lines BL and bBL when the data latch circuit 10 a in FIG. 11B reads data, writes data, and stores data.

When the data latch circuit 10a reads the data stored in the nodes n1 and n2, the word line WL is set to the ground voltage VSS (for example, 0V). The bit lines BL and bBL are precharged to the power supply voltage VDD. Therefore, the data stored in the nodes n1 and n2 are read into the bit lines BL and bBL via the transistors Q3a and Q4a in reverse logic.

When data is written to the nodes n1 and n2, the word line WL is set to the ground voltage VSS (for example, 0V). When the data to be written is 0, the bit line BL is set to the ground voltage VSS (for example, 0V), and the bit line bBL is set to the power supply voltage VDD. Therefore, transistors Q1 and Q2 perform an action of storing "0" data. Meanwhile, when the data to be written is 1, the voltage levels of the bit lines BL and bBL are opposite to those in FIG. 11C.

When storing data in the nodes n1 and n2, the word line WL is set to a voltage slightly lower than the power supply voltage VDD (for example, VDD×0.95-0.7V), and the bit lines BL and bBL are set to the power supply voltage VDB.

FIG. 12 is a layout diagram of a data latch circuit 10a according to the second embodiment. The hierarchical relationship among the layers shown in FIG. 12 is the same as that in FIG. 7 .

In the layout arrangement of FIG. 12 , the first diffusion region D1 , the second diffusion region D2 and the third diffusion region D3 are located at the lowest layer. The first diffusion area D1 and the second diffusion area D2 are separated from each other in the second direction Y. The third diffusion area D3 is separated from the first diffusion area D1 and the second diffusion area D2 in the first direction X.

The first gate layer G1, the second gate layer G2 and the third gate layer G3 are located on the first to third diffusion regions D1 to D3. The first gate layer G1 to the third gate layer G3 are located at the same layer height. The first gate layer G1 is a word line. The first gate layer G1 overlaps the first diffusion region D1 and the second diffusion region D2 in the stacking direction. The first gate layer G1 is a layer connected to the gates of the transistors Q3a and Q4a.

The second gate layer G2 and the third gate layer G3 overlap the third diffusion region D3 in the lamination direction. The second gate layer G2 is a layer connected to the gate of the transistor Q1. The third gate layer G3 is a layer connected to the gate of the transistor Q2.

The first metal layer M1 is located on the first gate layer G1 to the third gate layer G3. The first metal layer M1 includes a first wiring layer WR1, a second wiring layer WR2, a third wiring layer WR3, a fourth wiring layer WR4, and a fifth wiring layer WR5. Here, the first to fifth wiring layers WR1 to WR5 extend in the first direction X, respectively, and are separated from each other in the second direction Y.

The first wiring layer WR1 is a bit line BL, and the second wiring layer WR2 is a bit line bBL. The first wiring layer WR1 overlaps the first diffusion region D1 and the third diffusion region D3 in the stacking direction. The first wiring layer WR1 is connected to the drain region of the transistor Q3a in the first diffusion region D1. The second wiring layer WR2 overlaps the second diffusion region D2 and the third diffusion region D3 in the stacking direction. The second wiring layer WR2 is connected to the drain region of the transistor Q4a in the second diffusion region D2.

The third wiring layer WR3 overlaps the first diffusion region D1 and the third diffusion region D3 in the stacking direction. The third wiring layer WR3 is connected to the source region of the transistor Q3a in the first diffusion region D1, the drain region of the transistor Q1 in the third diffusion region D3, and the third gate layer G3.

The fourth wiring layer WR4 overlaps the second diffusion region D2 and the third diffusion region D3 in the stacking direction. The fourth wiring layer WR4 is connected to the source region of the transistor Q4a in the second diffusion region D2, the second gate layer G2 in the third diffusion region D3, and the drain region of the transistor Q2 in the third diffusion region D3.

The fifth wiring layer WR5 overlaps the third diffusion region D3 in the stacking direction. The fifth wiring layer WR5 is connected to the source regions of the transistors Q1 and Q2 in the third diffusion region D3.

The second metal layer M2 is located on the first to fifth wiring layers WR1 to WR5. The second metal layer M2 includes a sixth wiring layer WR6. The sixth wiring layer WR6 is set to the ground voltage VSS. The sixth wiring layer WR6 is connected to the fifth wiring layer WR5.

FIG. 13 is a layout diagram in which a plurality of data latch circuits 10a having the layout arrangement in FIG. 12 are in a two-dimensional direction. In FIG. 13, a plurality of data latch circuits 10a are line-symmetrically arranged with respect to axes ax1 and ax2 extending in the second direction Y. Referring to FIG.

The layout arrangement shown in FIG. 12 is just an example, and various modifications thereof are conceivable. For example, a point-symmetrical layout arrangement may be adopted.

14A is a layout diagram of a first modification example of the data latch circuit 10 a according to the second embodiment, and FIG. 14B is a layout diagram of a second modification example thereof. 14A and 14B have a point-symmetrical layout arrangement with respect to the central position of the layout area. Hereinafter, details of the layout arrangement in FIG. 14A will be described, and description of the layout arrangement in FIG. 14B will be omitted. The hierarchical relationship among the layers shown in FIGS. 14A and 14B is the same as that in FIG. 7 .

In the layout arrangement of FIG. 14A, the first diffusion region D1, the second diffusion region D2, the third diffusion region D3, and the fourth diffusion region D4 are separated from each other in the second direction Y in the lowest layer. Each of the first to fourth diffusion regions D1 to D4 extends in the first direction X. Referring to FIG. The first gate layer G1, the second gate layer G2, the third gate layer G3, and the fourth gate layer G4 are separated from each other along the second direction Y on the first to second diffusion regions D1 to D4.

The first gate layer G1 overlaps the second diffusion region D2 in the stacking direction. The second gate layer G2 overlaps the third diffusion region D3 in the lamination direction. The third gate layer G3 overlaps the first diffusion region D1 in the stacking direction. The fourth gate layer G4 overlaps the fourth diffusion region D4 in the lamination direction.

The first metal layer M1 is located on the first gate layer G1 to the fourth gate layer G4. In the first metal layer M2, the third to ninth wiring layers WR3 to WR9 are separated from each other in the first direction X. As shown in FIG. Each of the third to ninth wiring layers WR3 to WR9 extends in the second direction Y.

The third wiring layer WR3 is connected to the first gate layer G1 and the second gate layer G2. The fourth wiring layer WR4 is connected to the first diffusion region D1, the second diffusion region D2, and the fourth diffusion region D4. The fifth wiring layer WR5 is connected to the first diffusion region D1, the third diffusion region D3 and the fourth diffusion region D4. The sixth wiring layer WR6 is connected to the first diffusion region D1. The seventh wiring layer WR7 is connected to the second diffusion region D2. The eighth wiring layer WR8 is connected to the fourth diffusion region D4. The ninth wiring layer WR9 is connected to the third diffusion region D3.

The second metal layer M2 is located on the first metal layer M1 including the third to ninth wiring layers WR3 to WR9 . In the second metal layer M2, the first wiring layer WR1, the second wiring layer WR2, the tenth wiring layer WR10, and the eleventh wiring layer WR11 are separated from each other in the second direction Y. The first wiring layer WR1 is a bit line BL, and the second wiring layer WR2 is a bit line bBL. The tenth wiring layer WR10 and the eleventh wiring layer WR11 are layers set to the ground voltage VSS.

The tenth wiring layer WR10 is connected to the sixth wiring layer WR6. The first wiring layer WR1 is connected to the seventh wiring layer WR7. The eleventh wiring layer WR11 is connected to the eighth wiring layer WR8. The second wiring layer WR2 is connected to the ninth wiring layer WR9.

FIG. 15A is a layout diagram in which a plurality of data latch circuits 10a having the layout arrangement in FIG. 14A are located in a first direction X and a second direction Y. Referring to FIG. FIG. 15B is a layout diagram in which a plurality of data latch circuits 10a having the layout arrangement in FIG. 14B are arranged in each of the first direction X and the second direction Y.

Both Figures 15A and 15B have a point-symmetrical layout arrangement in the cells of Figures 14A and 14B, and also have a line-symmetrical layout arrangement about an axis extending in the second direction Y.

As described above, in the same manner as the first embodiment, the data latch circuit 10a according to the second embodiment is formed of four transistors Q1 to Q4a, thereby being different from the data latch circuit 100 according to the comparative example shown in FIG. Compared with that, the circuit area is significantly reduced. The data latch circuit 10 a according to the second embodiment may have a point-symmetrical layout arrangement as shown in FIG. 12 , and may also have a line-symmetrical layout arrangement as shown in FIG. 14A or 14B .

third embodiment

In the first and second embodiments described above, the data latch circuit 10 including four transistors Q1 to Q4a was described. Here, a data latch circuit 10b including six transistors may also be provided. Two additional transistors judge whether to supply the power supply voltage VDD to the data latch circuit 10b. That is, two additional transistors make it possible to judge whether the data latch circuit 10b performs a data storage action or a data read action.

FIG. 16A is a diagram showing features of a data latch circuit 10b according to the third embodiment, and FIG. 16B is a circuit diagram of the data latch circuit 10a according to the third embodiment. The data latch circuit 10b according to the third embodiment has a configuration in which the second transistor group 22 including the transistors Q7 and Q8 is omitted from the data latch circuit 100 according to the comparative example in FIG. 2 . Transistors Q1 to Q4 are NMOS transistors, and transistors Q5 and Q6 are PMOS transistors.

As shown in FIG. 16B, the source of transistor Q5 is connected to power supply voltage node VDD. The drain of transistor Q5 is connected to the drain of transistor Q1, the gate of transistor Q2 and the drain of transistor Q3. The source of transistor Q6 is connected to the supply voltage node VDD, and the drain of transistor Q6 is connected to the drain of transistor Q2, the gate of transistor Q1, and the drain of transistor Q4.

A common control signal Vct1 is input to the gates of transistors Q5 and Q6. In the data storage operation, Vct1 is set to a voltage level slightly lower than the power supply voltage VDD. For example, a voltage level slightly lower than the power supply voltage VDD is a voltage level that is 5% to 30% lower than the power supply voltage VDA. The reason for setting the gate voltage Vctl of the transistors Q5 and Q6 to a voltage level slightly lower than the power supply voltage VDD during data storage is to allow leakage current to flow through the transistors Q5 and Q6.

From the data storage state, one of the word lines WL1 and WL2 is set high and the other is set low, so that one of the transistors Q3 and Q4 can be turned on and node n1 can be read in the bit line or the state of node n2.

When a high-level control signal is input to the gates of the transistors Q5 and Q6, the transistors Q5 and Q6 are turned off. In this state, setting one of the word lines WL1, WL2 to a high level and the other to a low level turns on one of the transistors Q3 and Q4 and writes the data from the bit line to node n1 and node n2.

When a low-level control signal is input to the gates of the transistors Q5 and Q6, the transistors Q5 and Q6 are turned on, and the drains of the transistors Q1 and Q2 become the power supply voltage VDD. This action can also be used as a function to initialize the state of node n1 and node n2.

FIG. 16C is a graph showing voltages of word lines WL1 and WL2, bit line BL, and control signal Vct1 when data latch circuit 10b in FIG. 16B reads data, writes data, and stores data. FIG. 16C shows an example of accessing word line WL1. When word line WL2 is accessed, the voltage relationship between word lines WL1 and WL2 in FIG. 16C is reversed.

When the data latch circuit 10b reads data stored in the nodes n1 and n2 via the transistor Q3, the word line WL1 is set to the power supply voltage VDD, and the word line WL2 is set to the ground voltage VSS. In addition, the bit line BL is precharged to the power supply voltage VDD. In addition, the control signal Vct1 is set to a voltage slightly lower than the power supply voltage VDD (for example, VDD×0.95-0.7). Therefore, the data stored in the nodes n1 and n2 are read to the bit line BL via the transistor Q3.

When the data latch circuit 10b writes data into the nodes n1 and n2 via the transistor Q3, the word line WL1 is set to the power supply voltage VDD, and the word line WL2 is set to the ground voltage VSS (for example, 0V). When the data to be written is 0, the bit line BL is set to the ground voltage VSS (for example, 0V). Also, the control signal Vct1 is set to the power supply voltage VDD. Therefore, data of "0" is stored in the nodes n1 and n2 through the transistor Q3. Meanwhile, when the data to be written is 1, the bit line BL is set to the power supply voltage VDD.

When the data latch circuit 10b stores data in the nodes n1 and n2, the word lines WL1 and WL2 are set to a voltage slightly lower than the power supply voltage VDD (for example, VDD×0.95-0.7V), and the bit line BL is set to is the supply voltage VDD. In addition, the control signal Vctl is set to a voltage slightly lower than the power supply voltage VDD (for example, VDD×0.95-0.7V).

FIG. 17 is a layout diagram of a data latch circuit 10b according to the third embodiment. The third embodiment has a configuration in which a plurality of layers having different layer heights are stacked on each other, and a plurality of contacts configured to electrically connect the respective layers are provided. The hierarchical relationship between the respective layers forming the data latch circuit 10b in FIG. 17 is the same as that in FIG. 7 .

In the layout arrangement of FIG. 17 , the first diffusion region D1 , the second diffusion region D2 and the third diffusion region D3 are located at the lowest layer. The first diffusion area D1 and the second diffusion area D2 are separated from each other in the second direction Y. The third diffusion area D3 is separated from the first diffusion area D1 and the second diffusion area D2 in the first direction X.

The first gate layer G1, the second gate layer G2, the third gate layer G3, the fourth gate layer G4, and the fifth gate layer G5 are located on the first to third diffusion regions D1 to D3. The first to fifth gate layers G1 to G5 extend in the second direction Y, are separated from each other in the first direction X, and are located at the same layer height.

The first gate layer G1 is a word line WL1, and is connected to the gate of the transistor Q3. The first gate layer G1 overlaps the third diffusion region D3 in the stacking direction. The second gate layer G2 is a word line WL2, and is connected to the gate of the transistor Q4. The second gate layer G2 overlaps the third diffusion region D3 in the lamination direction.

The third gate layer G3 is connected to the gate of the transistor Q1. The fourth gate layer G4 is connected to the gate of the transistor Q2. The fifth gate layer G5 is connected to the gates of the transistors Q5 and Q6.

The second to eleventh wiring layers WR2 to WR11 are located on the first to fifth gate layers G1 to G5. The second wiring layer WR2 to the eleventh wiring layer WR11 extend in the second direction Y, and are separated from each other in the first direction X.

The second wiring layer WR2 is a layer set to a power supply voltage (second reference voltage) VDD. The third wiring layer WR3 is connected to the drain region of the transistor Q5 in the first diffusion region D1. The fourth wiring layer WR4 is connected to the drain of the transistor Q6 in the second diffusion region D2. The third wiring layer WR3 and the fourth wiring layer WR4 are separated from each other in the second direction Y.

The fifth wiring layer WR5 is a layer set to the ground voltage VSS. The sixth wiring layer WR6 is connected to the gate of the transistor Q1. The seventh wiring layer WR7 is connected to the source region of the transistor Q3 in the third diffusion region D3. The eighth wiring layer WR8 is connected to the first wiring layer WR1. The ninth wiring layer WR9 is connected to the drain region of the second transistor in the third diffusion region D3. The tenth wiring layer WR10 is connected to the twelfth wiring layer WR12 . The eleventh wiring layer WR11 is a layer set to the ground voltage VSS.

The first wiring layer WR1 , the twelfth wiring layer WR12 , and the thirteenth wiring layer WR13 are located on the second wiring layer WR2 to the eleventh wiring layer WR11 . The first wiring layer WR1 , the twelfth wiring layer WR12 , and the thirteenth wiring layer WR13 extend in the first direction X and are separated from each other in the second direction Y.

The first wiring layer WR1 is a bit line BL, and is connected to the eighth wiring layer WR8. The twelfth wiring layer WR12 is connected to the third wiring layer WR3 , the seventh wiring layer WR7 , and the tenth wiring layer WR10 . The thirteenth wiring layer WR13 is connected to the fourth wiring layer WR4 , the sixth wiring layer WR6 , and the ninth wiring layer WR9 .

FIG. 18 is a layout diagram in which a plurality of data latch circuits 10b having the layout arrangement in FIG. 17 are located in a two-dimensional direction. In FIG. 18, a plurality of data latch circuits 10b are arranged line-symmetrically with respect to an axis extending in the second direction Y.

The layout arrangement shown in FIG. 17 is only an example, and various modifications are conceivable. For example, a point-symmetrical layout arrangement may also be adopted.

As described above, the data latch circuit 10b according to the third embodiment is formed of six transistors Q1 to Q6, so that the circuit area can be reduced compared with the data latch circuit 100 according to the comparative example shown in FIG. Furthermore, unlike the first and second embodiments, during data storage, it is not necessary to set the voltage of the word line to a voltage slightly lower than the power supply voltage VDD, and therefore, the control of the word line becomes easy.

Fourth Embodiment

Although the data latch circuit 10b according to the third embodiment includes two word lines WL1 and WL2 and one bit line BL, each of which is connected to its corresponding part, the data latch circuit 10b may also have a A configuration of line BL and two bit lines BL-bBL, each connected to its corresponding component.

FIG. 19A is a diagram showing features of a data latch circuit 10c according to the fourth embodiment, and FIG. 19B is a circuit diagram of the data latch circuit 10c according to the fourth embodiment.

The data latch circuit 10c according to the fourth embodiment includes one word line WL and two bit lines BL and bBL, each of which is connected to its corresponding part. A common word line WL is connected to the gates of transistors Q3 and Q4. Bit line BL is connected to the drain of transistor Q3, and bit line bBL is connected to the drain of transistor Q4. The bit lines BL and bBL are logic opposite to each other. The connection relationship among other transistors Q1 to Q4 is the same as that of FIGS. 3A and 3B.

FIG. 19C is a graph showing the voltages of the word line WL, the bit lines BL and bBL, and the control signal Vct1 when the data latch circuit 10c in FIG. 19B reads data, writes data, and stores data.

When the data latch circuit 10c reads the data stored in the nodes n1 and n2, the word line WL is set to the power supply voltage VDD. The bit lines BL and bBL are precharged to the power supply voltage VDD. In addition, the control signal Vctl is set to a voltage slightly lower than the power supply voltage VDD (for example, VDD×0.95-0.7V). Therefore, the data stored in the nodes n1 and n2 are read to the bit lines BL and bBL via the transistors Q3 and Q4 in reverse logic.

When the data latch circuit 10c writes data into the nodes n1 and n2, the word line WL is set to the power supply voltage VDD. When the data to be written is 0, the bit line BL is set to the ground voltage VSS (for example, 0V), and the bit line bBL is set to the power supply voltage VDD. The control signal Vct1 is set to the power supply voltage VDD. Therefore, transistors Q1 and Q2 perform an action of storing "0" data. Meanwhile, when the data to be written is 1, the voltage levels of the bit lines BL and bBL are opposite to those in FIG. 19C.

When the data latch circuit 10c stores data in the nodes n1 and n2, the word line WL is set to the ground voltage VSS (for example, 0V), and the bit lines BL and bBL are set to the power supply voltage VDD. In addition, the control signal Vct1 is set to a voltage slightly lower than the power supply voltage VDD (for example, VDD×0.95-0.7V).

FIG. 20 is a layout diagram of a data latch circuit 10c according to the fourth embodiment. The hierarchical relationship among the layers shown in FIG. 20 is the same as that in FIG. 7 .

In the layout arrangement of FIG. 20 , the first diffusion region D1 , the second diffusion region D2 and the third diffusion region D3 are located at the lowest layer. The first diffusion area D1 and the second diffusion area D2 are separated from each other in the second direction Y. The third diffusion area D3 is separated from the first diffusion area D1 and the second diffusion area D2 in the first direction X.

The first gate layer G1, the second gate layer G2, the third gate layer G3, the fourth gate layer G4, and the fifth gate layer G5 are located on the first to third diffusion regions D1 to D3. The first to fifth gate layers G1 to G5 extend in the second direction Y and are separated from each other in the first direction X at the same layer height.

The first gate layer G1 is a word line WL, and is connected to the gate of the transistor Q3. The first gate layer G1 overlaps the third diffusion region D3 in the stacking direction. The second gate layer G2 is also the word line WL, and is connected to the gate of the transistor Q4. The second gate layer G2 is a word line WL, and overlaps the third diffusion region D3 in the stacking direction. Since the first gate layer G1 and the second gate layer G2 have the same word line WL, the first gate layer G1 and the second gate layer G2 can be integrated into one gate layer.

The third gate layer G3 is connected to the gate of the transistor Q1. The fourth gate layer G4 is connected to the gate of the transistor Q2. The fifth gate layer G5 is connected to the gates of the transistors Q5 and Q6.

The third to twelfth wiring layers WR3 to WR12 are located on the first to fifth gate layers G1 to G5. The third to twelfth wiring layers WR3 to WR12 extend in the second direction Y and are separated from each other in the first direction X.

The third wiring layer WR3 is a layer set to the power supply voltage VDD. The fourth wiring layer WR4 is connected to the drain region of the transistor Q5 in the first diffusion region D1. The fifth wiring layer WR5 is connected to the drain of the transistor Q6 in the second diffusion region D2. The fourth wiring layer WR4 and the fifth wiring layer WR5 are separated from each other in the second direction Y.

The sixth wiring layer WR6 is connected to the source region of the transistor Q3 in the third diffusion region D3. The seventh wiring layer WR7 is connected to the drain region of the transistor Q3 in the third diffusion region D3. The eighth wiring layer WR8 is connected to the gate of the transistor Q1. The ninth wiring layer WR9 is a layer set to the ground voltage VSS. The tenth wiring layer WR10 is connected to the gate of the transistor Q2. The eleventh wiring layer WR11 is connected to the drain region of the transistor Q4 in the third diffusion region D3. The twelfth wiring layer WR12 is connected to the source region of the transistor Q4 in the third diffusion region D3.

The first wiring layer WR1 , the second wiring layer WR2 , the thirteenth wiring layer WR13 , and the fourteenth wiring layer WR14 are located on the third to twelfth wiring layers WR3 to WR12 . The first wiring layer WR1 , the second wiring layer WR2 , the thirteenth wiring layer WR13 , and the fourteenth wiring layer WR14 extend in the first direction X and are separated from each other in the second direction Y.

The first wiring layer WR1 is a bit line BL and is connected to the sixth wiring layer WR6. The second wiring layer WR2 is the bit line bBL, and is connected to the twelfth wiring layer WR12. The thirteenth wiring layer WR13 is connected to the fourth wiring layer WR4 , the seventh wiring layer WR7 , and the tenth wiring layer WR10 . The fourteenth wiring layer WR14 is connected to the fifth wiring layer WR5 , the eighth wiring layer WR8 , and the eleventh wiring layer WR11 .

FIG. 21 is a layout diagram in which a plurality of data latch circuits 10c having the layout arrangement in FIG. 20 are located in two-dimensional directions. The plurality of data latch circuits 10c shown in FIG. 21 are arranged line-symmetrically with respect to an axis extending in the second direction Y.

The layout arrangement shown in FIG. 21 is just an example, and various modifications are conceivable. For example, a point-symmetrical layout arrangement may be adopted.

As described above, since the data latch circuit 10c according to the fourth embodiment is formed of six transistors Q1 to Q6, the same effects as those of the third embodiment can be obtained.

In addition, each of the above-described embodiments can be applied and used even in an environment where the temperature is 50° C. or lower, room temperature, or lower than the temperature by using immersion or the like. Each of these embodiments can also be applied and used in an extremely low temperature environment of -40°C or lower down to liquid nitrogen temperature of -196°C.

While certain implementations have been described, these implementations have been presented by way of example only, and are not intended to limit the scope of the disclosure. Indeed, the novel embodiments described herein may be embodied in various other forms; moreover, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the disclosure. The appended claims and their equivalents are intended to cover such forms or modifications as fall within the scope and spirit of the disclosure.

Label description

1: Semiconductor memory device

2: Memory module

3: Serial conversion unit

4: I/O signal processing unit

5: High voltage generating circuit

6: Low voltage generating circuit

7: Synchronous control department

8: row control department

9: column control section

10, 10a, 10b, 10c: data latch circuit

11: memory cell array

12: row decoder

13: Sense amplifier & data latch section

14: Transmission data latch unit

15: column decoder

16: Controller

21: First transistor group

22: Second transistor group

100: data latch circuit

Claims (20)

1. A data latch circuit, comprising: a first transistor of the first conductivity type and a second transistor of the first conductivity type; and A third transistor of the second conductivity type and a fourth transistor of the second conductivity type, wherein The third transistor and the fourth transistor are controlled to perform a first control action to store data in the data latch circuit, and to perform a second control action to read the stored data. 2. The data latch circuit according to claim 1, wherein, the gate of the first transistor is connected to the drain of the second transistor, the gate of the second transistor is connected to the drain of the first transistor, the source of the first transistor and the source of the second transistor are connected to a specified first reference voltage node, the source of the third transistor is connected to the drain of the first transistor and the gate of the second transistor, The source of the fourth transistor is connected to the drain of the second transistor and the gate of the first transistor. 3. The data latch circuit according to claim 2, comprising: a first gate layer connected to the gate of the third transistor; a second gate layer connected to the gate of the fourth transistor; and The first wiring layer is connected to the drain of the third transistor and the drain of the fourth transistor, and transmits the data. 4. The data latch circuit according to claim 3, wherein, The third transistor or the fourth transistor is turned on and off through the first gate layer and the second gate layer, thereby storing the data in the data latch circuit. on the first wiring layer, or read the stored data onto the first wiring layer. 5. The data latch circuit according to claim 4, wherein, During the period of holding the data, the voltage levels of the first gate layer and the second gate layer are lowered to the following voltage level, that is, the first gate layer and the second gate layer are stored when the data is stored. A voltage level of any percentage within the range of 5% to 30% of the highest voltage level in the second gate layer. 6. The data latch circuit according to claim 5, further comprising: a first diffusion region and a second diffusion region separated from each other along a first direction on the semiconductor substrate; a third gate layer connected to the gate of the first transistor; and a fourth gate layer connected to the gate of the second transistor, a source and a drain of each of the first transistor and the second transistor are located on the first diffusion region, a source and a drain of each of the third transistor and the fourth transistor are located on the second diffusion region, the first gate layer and the second gate layer extend in a second direction crossing the first direction to overlap the second diffusion region in a lamination direction, the first wiring layer extends in the first direction to overlap the first diffusion region and the second diffusion region in the lamination direction, The third gate layer and the fourth gate layer respectively extend in the second direction to overlap the first diffusion region in the lamination direction, and are separated from each other in the first direction . 7. The data latch circuit according to claim 5, further comprising: the first diffusion region, the second diffusion region, the third diffusion region and the fourth diffusion region are separated from each other in a second direction crossing the first direction on the semiconductor substrate; a third gate layer connected to the gate of the first transistor; and a fourth gate layer connected to the gate of the second transistor, The first gate layer, the second gate layer, the third gate layer and the fourth gate layer respectively extend in the first direction and mutually extend in the second direction separate, The first wiring layer is located between the second diffusion region and the third diffusion region and extends along the first direction. 8. The data latch circuit according to claim 1, comprising: a first gate layer connected to the gate of the third transistor and the gate of the fourth transistor; a first wiring layer connected to the drain of the third transistor; and A second wiring layer connected to the drain of the fourth transistor. 9. The data latch circuit according to claim 8, wherein, During holding of the data in the data latch circuit, the voltage level of the first gate layer is lowered by any percentage in the range of 5% to 30% of the power supply voltage level. 10. The data latch circuit according to claim 9, further comprising: a first diffusion region and a second diffusion region separated from each other in a second direction crossing the first direction on the semiconductor substrate; a third diffusion area separated from the first diffusion area and the second diffusion area in the first direction; a second gate layer connected to the gate of the first transistor; and a third gate layer connected to the gate of the second transistor, the source and the drain of the first transistor are located on the first diffusion region, the source and the drain of the second transistor are located on the second diffusion region, a source and a drain of each of the third transistor and the fourth transistor are located on the third diffusion region, the first gate layer extends in the second direction so as to overlap the first diffusion region and the second diffusion region in a stacking direction, the second gate layer and the third gate layer respectively extend in the second direction to overlap the third diffusion region in the stacking direction and are separated from each other in the first direction, the first wiring layer extends in the first direction to overlap the first diffusion region and the third diffusion region in a lamination direction, The second wiring layer extends in the first direction to overlap the second diffusion region and the third diffusion region in a lamination direction. 11. The data latch circuit according to claim 9, further comprising: the first diffusion region, the second diffusion region, the third diffusion region and the fourth diffusion region are separated from each other in a second direction crossing the first direction on the semiconductor substrate; a first gate layer connected to the gate of the third transistor; a second gate layer connected to the gate of the fourth transistor; a third gate layer connected to the gate of the first transistor; and a fourth gate layer connected to the gate of the second transistor, the source and the drain of the first transistor are located on the first diffusion region, the source and the drain of the second transistor are located on the fourth diffusion region, the source and the drain of the third transistor are located on the second diffusion region, The source and the drain of the fourth transistor are located on the third diffusion region, the first wiring layer extends in the first direction to overlap the second diffusion region in a lamination direction, The second wiring layer extends in the first direction to overlap the third diffusion region in a lamination direction. 12. A data latch circuit comprising: a first transistor of the first conductivity type and a second transistor of the first conductivity type; The third transistor of the first conductivity type and the fourth transistor of the first conductivity type, wherein the third transistor and the fourth transistor are controlled to perform a first control action to store data in the in the data latch unit, and execute a second control action to read the stored data; and A fifth transistor of a second conductivity type and a sixth transistor of the second conductivity type, wherein the fifth transistor and the sixth transistor are controlled to initialize data stored in the data latch circuit. 13. The data latch circuit according to claim 12, wherein, the gate of the first transistor is connected to the drain of the second transistor and the drain of the fourth transistor, the gate of the second transistor is connected to the drain of the first transistor and the drain of the third transistor, the source of the first transistor and the source of the second transistor are connected to a specified first reference voltage node, the source of the fifth transistor and the source of the sixth transistor are connected to a specified second reference voltage node, the drain of the fifth transistor is connected to the drain of the first transistor, the drain of the sixth transistor is connected to the drain of the second transistor, A common control signal is input to the gate of the fifth transistor and the gate of the sixth transistor. 14. The data latch circuit according to claim 13, further comprising: a first gate layer connected to the gate of the third transistor; a second gate layer connected to the gate of the fourth transistor; and The first wiring layer is connected to the source of the third transistor and the source of the fourth transistor, and transmits the data. 15. The data latch circuit according to claim 14, further comprising: the first diffusion region and the second diffusion region are separated from each other in a second direction crossing the first direction on the semiconductor substrate; and a third diffusion area separated from the first diffusion area and the second diffusion area in the first direction, a source and a drain of each of the first to fourth transistors are located on the third diffusion region, the source and the drain of the fifth transistor are located on the first diffusion region, The source and the drain of the sixth transistor are located on the second diffusion region, the first gate layer and the second gate layer respectively extend in the second direction to overlap the third diffusion region in the lamination direction and are separated from each other in the first direction, The first wiring layer extends in the first direction to overlap the third diffusion region in a stacking direction, and is located between the first diffusion region and the second diffusion region. 16. The data latch circuit according to claim 12, further comprising: a first gate layer connected to the gate of the third transistor and the gate of the fourth transistor; a first wiring layer connected to the source of the third transistor and transferring the data; and The second wiring layer is connected to the source of the fourth transistor and has a logic level opposite to that of the first wiring layer. 17. The data latch circuit according to claim 16, further comprising: the first diffusion region and the second diffusion region are separated from each other in a second direction crossing the first direction on the semiconductor substrate; and a third diffusion area separated from the first diffusion area and the second diffusion area in the first direction, a source and a drain of each of the first to fourth transistors are located on the third diffusion region, the source and the drain of the fifth transistor are located on the first diffusion region, The source and the drain of the sixth transistor are located on the second diffusion region, the first gate layer extends in the second direction to overlap the third diffusion region in a stacking direction, the first wiring layer extends in the first direction to overlap the first diffusion region and the third diffusion region in a lamination direction, The second wiring layer extends in the first direction to overlap the second diffusion region and the third diffusion region in a lamination direction. 18. The data latch circuit according to claim 12, wherein, During the period when the data is held in the data latch circuit, a voltage lowered by any percentage within the range of 5% to 30% of the power supply voltage level is applied to the gates of the fifth transistor and the sixth transistor. pole. 19. A semiconductor memory device comprising: an array of memory cells; and a data latch circuit configured to temporarily store data to be written into the memory cell array and data read from the memory cell array, The data latch unit includes: a data storage circuit comprising at least two but no more than four transistors of a first conductivity type, and Two transistors of the second conductivity type, wherein the two transistors of the second conductivity type are controlled to perform a first control action to write data into the data storage circuit, and to perform a second control action to read from The stored data is read from the data storage circuit. 20. The semiconductor memory device according to claim 19, wherein, The data storage circuit includes four transistors of the first conductivity type.

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