JP2005530347A - Improved structure and method for local embedded interconnects - Google Patents

Abstract

A structure and method for forming embedded interconnects of integrated circuits in a single crystal semiconductor layer of a substrate.
The buried interconnect includes one or more vertical sidewalls formed from deposited conductors and in contact with a single crystal region of an electronic device formed in the single crystal semiconductor layer.

Description

  The present invention relates to semiconductor processing pre-process (FEOL), and more particularly to local buried interconnects formed at the transistor level.

  There is a continuing need in the microelectronics industry for high density, high speed but nevertheless miniaturized microcircuits, especially for memory cells and support circuits. Various solutions have been implemented to achieve maximum density, speed, and desired dimensions.

  Previously embodied techniques in semiconductor processing, such as silicon on insulator (SOI), are more widely used to help meet the demand for high speed integrated circuits. In SOI techniques, a relatively thin layer of semiconductor material, usually silicon (Si), is placed on a layer of insulating material, commonly referred to as buried oxide (BOX). This relatively thin layer of semiconductor material is generally the region where active elements are formed in SOI devices.

  Integrated circuits are manufactured with a number of electronic semiconductor devices such as resistors, transistors, diodes, capacitors, etc. that are fabricated on a semiconductor substrate in a combined process. A substrate refers to one or more semiconductor layers or structures that comprise an active or active portion of a semiconductor device. One important aspect of integrated circuit fabrication is the electrical interconnection of active devices through interconnect structures therein.

  This interconnect structure generally includes regions of conductive material formed between semiconductor devices that are in electrical contact. This interconnect serves as a path for supplying current between the semiconductor devices. Special types of interconnect structures are known to those skilled in the art and include M0, M1 interconnect level local interconnects, buried contacts, vias, studs, surface straps, and buried straps, to name a few Can be. Often diodes can also serve as interconnects between semiconductor devices. The diode can be formed in the semiconductor substrate by bonding different carrier type active regions.

  One type that is frequently used as an interconnect structure is a buried contact. This buried contact may be a region of polysilicon that makes direct contact between the interconnect structure and the active region, thereby eliminating the need for metal links. In forming the buried contact, a window is opened in the thin gate oxide over the active region of the counterpart to which the interconnect structure is to be electrically connected. Polysilicon is then deposited in this opening in direct contact with the active region, but separated from the underlying silicon by field oxide in the gate oxide and other portions of the semiconductor substrate. As the dopant present in the polysilicon diffuses into the active region, an ohmic contact is formed at the interface between the polysilicon and the active region. The diffusion of dopant within the active region effectively fuses the polysilicon with the active region. A layer of insulating coating is then deposited to cover the buried contact. A buried contact is so named because the metal layer passes over the active region, thereby forming a buried contact without making an electrical connection to the buried contact.

  In some cases, multiple layers of metal interconnects are stacked together to allow for increased density of the circuits involved. In general, the element density of each successive metal layer decreases one after another. This is because such a density hierarchy accumulates mask overlay errors for each additional interconnect layer. For example, if a contact is required between the active area (AA) and the second metal layer (M2), a via is created between AA and the first metal layer (M1), and then a second via is created to create M1 And M2 must be interconnected. The total overlay tolerance for AA-M2 contacts is the sum of the overlay tolerances for AA-M1 and M1-M2 contacts. Thus, the ability to increase circuit density by adding interconnect layers is limited.

  In many cases, providing sufficient manufacturing tolerances while meeting size, speed, and density requirements is a challenging task. What is needed is a new structure that allows circuit density to be increased while maintaining manufacturing tolerances at a workable level.

  In accordance with one aspect of the present invention, a structure and method are provided for forming embedded interconnects of integrated circuits in a single crystal semiconductor layer of a substrate. The buried interconnect comprises two or more vertical sidewalls formed of deposited conductors and in contact with a single crystal region of an electronic device formed in a single crystal semiconductor layer.

  According to another aspect of the present invention, a step of forming a trench isolation region in the substrate, and a bottom surface is separated from the single crystal region and a sidewall is formed in the trench isolation region in the single crystal region of the substrate in contact with the isolation region. Forming an abutting trench, then depositing a conductor in contact with the single crystal region on at least one sidewall of the trench, and forming a contact on the deposited conductor. A method of forming a buried interconnect is provided.

  FIG. 1 illustrates a buried interconnect according to a silicon-on-insulator (SOI) embodiment of the present invention. As shown in FIG. 1, a buried interconnect 10 is formed in a single crystal semiconductor layer (SOI layer 12) of an SOI substrate including a buried oxide layer (BOX 14) covering a support substrate 16. The buried interconnect 10 generally includes a vertically oriented (hereinafter referred to as “vertical”) sidewall 18 that may be, for example, a transistor, diode, capacitor, or resistor formed in the SOI layer 12. In contact with the single crystal region 12 of the electronic device 20, which may be

  If the electronic device 20 is an insulated gate field effect transistor (IGFET), the vertical sidewalls 18 of the buried interconnect 10 are the body or diffusion regions (ie, source / drain diffusions) of the electronic device formed in the SOI layer 12. Area) directly. When the electronic device 20 is a diode or depletion capacitor, the vertical sidewall 18 of the buried interconnect 10 can contact the diffusion region of such a device.

  The buried interconnect 10 is generally constructed to extend in a direction parallel to the substrate 16 (extend perpendicular to the plane of FIG. 1). In this way, the buried interconnect 10 moves to the next single crystal region 12 of the substrate, where the interconnect is connected to other electrons by vertical sidewalls 18 or other sidewalls that are not themselves isolated. One or more single crystal regions 12 of the device can be contacted. Other electronic devices except where isolation regions 28 (e.g., trench isolations) extending in a direction perpendicular to the paper plane by at least a portion of the length of the buried interconnect 10 would like to make contact with the buried interconnect 10 along the sidewall 30 Separate from. Where it is desired to make contact with another electronic device, contact can be made along the portion of the side wall 30 where there is no isolation region 28.

The buried interconnect 10 may be polysilicon, metal silicide (eg, WSi _x , CoSi _x , TiSi _x ), polysilicon deposited, followed by metal deposition and self-aligned silicide, and preferably tungsten. (W), or other refractory metals such as titanium (Ti), niobium (Nb), zirconium (Zr), tantalum (Ta), molybdenum (Mo), or deposited metals that may be layers thereof Formed of a conductive conductor. The buried interconnect can be lined with a liner 32 comprising a deposited conductor metal nitride or similar metal nitride, ie tungsten nitride or titanium nitride or tantalum silicon nitride (TaSiN). Alternatively, particularly when the deposited conductor is polysilicon, a very thin (eg, 7 cm or less) layer of silicon nitride can be used, as described more fully below.

  The buried interconnect 10 is preferably conductively coupled to a conductor 22 formed on the substrate. This conductor 22 is, for example, a polysilicon conductor that can form the gate conductor or “poly conductor” of a MOS device 24 (ie, “MOS” or insulated gate, field effect transistor, or MOS capacitor). This lead 22 covers the gate dielectric 26 formed on the SOI layer 12. As a gate conductor, a poly conductor 22 is shown in FIG. 1 connecting a MOS device, such as a MOSFET 24, to a source / drain region 20 of another electronic device, such as another MOSFET. The MOSFETs can be linked in such a way that multiple latches, flip-flops, drivers, and even cross-coupled CMOSFET pairs are used, as in static random access memory (SRAM).

  Alternatively, poly conductor 22 can be patterned and extend only over STI 28 and oxide 46 as an interface to buried interconnect 10. As another alternative, the poly conductor 22 may extend over the gate dielectric of the MOSFET device 20, with the buried interconnect 10 in conductive contact by the sidewall 18 in its body. In such a case, the body of MOSFET 20 should be coupled to the same voltage as gate conductor 22. Such a gate-body interconnection allows MOSFET 20 to act as a variable threshold voltage device where the threshold voltage decreases as the gate conductor voltage increases.

  FIG. 2 is a top view illustrating an exemplary semiconductor device layer arrangement with buried interconnects formed in accordance with the present invention. In such an arrangement, areas 110 and 210 represent buried interconnects and areas 120 and 220 represent the active areas of the substrate. In the illustrated example, it is preferable to form an n-channel IGFET (NFET) in the active area 120 and a p-channel IGFET (PFET) in the active area 220. Poly conductors 122, 222, and 322 are shown intersecting portions of active areas 120 and 220 as gate conductors for the NFET and PFET therein. The first buried interconnect 110 comprises one or more sidewalls 118, 119 that are in contact with the source / drain regions of the NFET in the single crystal region (active area 120). The buried interconnect 110 also includes sidewalls 218, 219 that are in contact with the source / drain regions of another device, PFET, in the single crystal region (active area 220). Thus, it will be understood that a single buried interconnect comprises one or more sidewalls in contact with one or more single crystal regions of a plurality of electronic devices (eg, NFET or PFET). Let's go. A buried contact 148 is formed between the poly conductor 222 and the buried interconnect 110 to establish a conductive interconnect for the poly conductor 222.

  Similarly, the second buried interconnect 210 comprises one or more sidewalls 318, 319 in contact with the electronic device in the single crystal region (active area 120), the source / drain region of the NFET. The buried interconnect 210 also includes one or more sidewalls 418, 419 that are in contact with the source / drain regions of another electronic device PFET in the single crystal region (active area 220). A buried contact 248 is formed between the poly conductor 122 and the buried interconnect 210 to establish a conductive interconnect for the poly conductor 122.

  FIGS. 3-8 illustrate the steps of fabricating the embedded interconnect 10 in the SOI method embodiment as shown in FIG. As shown in FIG. 3, a shallow trench isolation region (STI 28) is formed in the SOI layer 12 of the substrate including the buried oxide layer (BOX 14) covering the support substrate 16. The STI 28 extends to the BOX layer 14 to isolate the electronic devices formed in the SOI layer 12 on each side. The SOI layer 12 other than the STI 28 is covered with a pad nitride 34.

  Next, as shown in FIG. 4, a photoresist is deposited and patterned to form a mask 36, preferably on at least one side using directional reactive ion etching (RIE). An opening 35 that contacts the STI 28 and contacts the SOI layer 12 on at least the other side is formed by etching. This etching can be time controlled or preferably stopped when the support substrate 16 is reached. Next, the mask 36 is removed. The exposed sidewall 13 of the SOI layer 12 can be passivated at this point to remove surface damage to the single crystal SOI layer, as is the case with time-controlled sidewall oxidation and immediate oxide removal. Good.

  Then, as shown in FIG. 5, an oxide is deposited, preferably by high density plasma deposition, to form an isolation layer 38 at the bottom of the trench and an oxide 40 on the surface. Oxide deposited on the sidewall 13 of the opening 35 is removed at this point (eg, by isotropic etching), including any oxide resulting from the optional passivation process described above. Then, as shown in FIG. 6, the openings are first lined, preferably by depositing a liner 32, and then conductors 44 are deposited to fill the openings 35. Various of metals including polysilicon, tungsten (W), niobium (Nb), zirconium (Zr), tantalum (Ta), molybdenum (Mo), and silicides and nitrides of these metals, or combinations thereof A new material can be deposited as the conductor 44. When forming the conductor 44 by depositing a refractory metal such as tungsten, it is preferable to form the liner 32 by depositing a material that promotes adhesion, such as tungsten nitride or titanium nitride.

  When depositing polysilicon to form conductors 44, it is preferable to dope heavily during deposition, but alternatively, in situ doping can be performed following deposition. When the conductor 44 is formed of polysilicon, the liner 32 may not be required for adhesion. However, for another reason, it may still be preferable to line the opening 35 with a barrier of either a conductive material or even a very thin silicon nitride layer. A very thin silicon nitride layer, e.g., 7 cm or less, is known to be conductive due to quantum tunneling through this very thin layer. Such a barrier layer delays the diffusion of dopants from the polysilicon into the adjacent SOI area 12 and / or prevents polysilicon from recrystallizing at the interface between the conductor 44 and the SOI area 12. Should work. Recrystallization should be avoided. This is because it can potentially cause crystal defects in the SOI area 12, which ultimately degrades the performance of the electronic device formed therein.

  After the conductor 44 is deposited, the substrate is planarized to the height of the pad nitride 34 by a method such as chemical mechanical polishing (CMP) selective to nitride to provide a conductor deposited from the top surface of the substrate. And removing the deposited oxide, resulting in the structure shown in FIG. The conductor 44 and liner 32 are then recessed, preferably by directional etching, such as reactive ion etching selective to oxides and nitrides, resulting in the structure shown in FIG.

  Next, as shown in FIG. 8, a top oxide layer 46 is formed on the conductor 44. This includes an oxide deposition step by a high density plasma method, then planarizing the oxide 46 to the level of the pad nitride 34 (such as by CMP selective to nitride), and then the SOI area. Preferably, it is formed by removing the remaining pad nitride 34 from 12.

  Next, referring again to the completed structure shown in FIG. 1, further processing is performed to form buried contacts 48 from polyconductor 22. The poly conductor 22 may be, but need not be, the gate conductor of one or more electronic devices within the SOI area 12. This process is preferably performed after any necessary ion implantation is performed on device 24 and optionally device 20 to form gate dielectric 26 by oxidation or deposition. A window is then defined for etching to form a contact opening in the top oxide 46 deposited by patterning the photoresist. The photoresist is then stripped and heavily doped polysilicon is deposited and patterned to form the illustrated polyconductor 22 and buried contact 48.

  9 and 10 show the stages of an alternative process for completing the embedded interconnect 10. FIG. 10 shows the completed structure resulting from an alternative process of making the buried contact 50 from the second conductor 52 in contact with the polyconductor 22 to the buried interconnect 10. The structure shown in FIG. 10 differs from the structure of FIG. 1 in that the embedded interconnect 10 includes a side wall 18 that contacts the body of the electronic device 20A formed in the SOI layer 12. This is because the SOI layer 12 is below the gate dielectric 26 and poly conductor 22 where it is in contact, where it is used as the gate conductor. Contacting the body of the electronic device 20A by the embedded interconnect 10 is just one possible embodiment, with this alternative process focused on using the second conductor 52 in contact with the polyconductor 22. Note that this is not necessarily required. The second conductor 52 can be formed of any suitable material such as heavily doped polysilicon, metal silicide, or the metal itself.

  In such an alternative process, processing proceeds by forming a gate dielectric in the same manner as described above with reference to FIGS. Next, as shown in FIG. 9, a poly conductor layer 22 is deposited. This is the one described above with respect to FIG. 1 in that the poly conductor layer 22 is deposited on the gate dielectric 26 before etching the opening through the oxide layer 46 to form the buried contact 48. Is different. Such a process sequence may be desirable to avoid possible interactions between the gate dielectric 26 and the photoresist used to pattern the contact openings.

  Referring again to FIG. 10, a photoresist is then applied and patterned to define locations in the polysilicon layer 22 where contact openings are to be formed by etching. A second conductor layer 52 is then deposited on the polysilicon layer 22 including the contact openings to form the buried contact 50. Photoresist may then be applied and patterned, and the second conductor layer 52 and polysilicon layer 22 may be etched together in one combined etch, such as by directional reactive ion etching.

  FIG. 11 shows a buried interconnect structure 10 formed and completed in accordance with another embodiment of the present invention, which is formed in a bulk semiconductor substrate, unlike an SOI substrate. Except as described below, the process proceeds in the same manner as described above with reference to the embodiment of FIGS. 2-7 or FIGS. 3-10. Referring to FIG. 5, since the bulk substrate embodiment does not have a buried oxide layer, the buried interconnect 10 is connected to the bulk substrate to avoid undesirable leakage current from the source / drain diffusion region 20B to the bulk substrate 17. Oxide 38 may need to be deposited higher in opening 35 to contact device layer 20B, such as the source / drain diffusion region of the electronic device rather than 17.

  Although the present invention has been described in terms of several preferred embodiments thereof, those skilled in the art will depart from the true scope and spirit of the present invention which is limited only by the following claims. It will be appreciated that many modifications and improvements can be made.

  The present invention is applicable to an integrated electronic circuit and a manufacturing method thereof.

FIG. 3 illustrates a buried interconnect according to an embodiment of the present invention. FIG. 3 illustrates a buried interconnect according to an embodiment of the present invention. FIG. 6 illustrates one manufacturing stage of a buried interconnect structure according to an embodiment of the present invention. FIG. 6 illustrates one manufacturing stage of a buried interconnect structure according to an embodiment of the present invention. FIG. 6 illustrates one manufacturing stage of a buried interconnect structure according to an embodiment of the present invention. FIG. 6 illustrates one manufacturing stage of a buried interconnect structure according to an embodiment of the present invention. FIG. 6 illustrates one manufacturing stage of a buried interconnect structure according to an embodiment of the present invention. FIG. 6 illustrates one manufacturing stage of a buried interconnect structure according to an embodiment of the present invention. FIG. 6 illustrates one manufacturing stage of a buried interconnect structure according to an embodiment of the present invention. FIG. 5 illustrates a buried interconnect according to an alternative embodiment of the present invention. FIG. 5 illustrates a buried interconnect according to an alternative embodiment of the present invention.

Claims (21)

  A buried interconnect formed in a single crystal semiconductor layer of a substrate, wherein the buried interconnect is formed from a deposited conductor, and the single crystal region of an electronic device formed in the single crystal semiconductor layer An integrated circuit comprising interconnects having one or more vertical sidewalls in contact with the.   The integrated circuit of claim 1, wherein a plurality of electronic devices are connected by the buried interconnect through the one or more vertical sidewalls in a single crystal region.   The integrated circuit of claim 1, wherein the buried interconnect comprises at least one sidewall that contacts an isolation region on a side other than the vertical sidewall that contacts the single crystal region.   The integrated circuit of claim 1, wherein the single crystal regions connected by the buried interconnect comprise at least one diffusion region of at least one of the electronic devices.   The integrated circuit of claim 4, wherein source / drain regions of the electronic device are formed in the diffusion region.   The integrated circuit of claim 1, wherein the single crystal regions connected by the buried interconnect comprise at least one body of the electronic device.   The integrated circuit of claim 1, wherein at least one conductor formed on the substrate is conductively coupled to the buried interconnect.   The integrated circuit of claim 7, wherein the at least one lead is operatively coupled to the buried interconnect.   The integrated circuit of claim 8, wherein the conductor contacts the top surface of the buried interconnect.   The integrated circuit of claim 1, wherein the buried interconnect comprises a sidewall that abuts a trench isolation region.   The integrated circuit of claim 1, wherein the deposited conductor comprises doped polysilicon.   The integrated circuit of claim 1, wherein the deposited conductor comprises a metal.   The integrated circuit of claim 1, wherein the deposited conductor comprises a metal silicide.   14. An integrated circuit as claimed in any one of claims 11, 12 or 13, further comprising a liner formed in the trench before the deposited conductor.   The integrated circuit of claim 1, wherein the single crystal region is separated from the substrate by a buried oxide layer. Forming a trench isolation region in the substrate;
Forming a trench having a bottom separated from the single crystal region and a side wall in contact with the trench isolation region in the single crystal region of the substrate that contacts the isolation region;
Depositing a conductor in contact with the single crystal region on at least one sidewall of the trench;
Forming a buried interconnect according to any one of the preceding claims, comprising forming a contact from above to the deposited conductor.   The method of claim 16, wherein the contact to the deposited conductor is made through an opening etched in a separation layer deposited on the deposited conductor.   The method of claim 16, further comprising depositing a first conductor on the substrate, wherein the contact to the deposited conductor operatively couples the conductor to the deposited conductor.   Depositing a second conductor in contact with the first conductor, wherein the contact to the deposited conductor operatively couples the first conductor and the second conductor to the deposited conductor; The method of claim 18.   The method of claim 16, wherein the bottom of the trench is separated by a deposited oxide.   The method of claim 16, further comprising depositing a liner in the trench prior to depositing the conductor.

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