CN104867864B - A method of realizing local interlinkage - Google Patents
A method of realizing local interlinkage Download PDFInfo
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- CN104867864B CN104867864B CN201510142147.9A CN201510142147A CN104867864B CN 104867864 B CN104867864 B CN 104867864B CN 201510142147 A CN201510142147 A CN 201510142147A CN 104867864 B CN104867864 B CN 104867864B
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- 238000000034 method Methods 0.000 title claims abstract description 64
- 238000005530 etching Methods 0.000 claims abstract description 34
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims abstract description 22
- 239000000463 material Substances 0.000 claims abstract description 19
- 229920002120 photoresistant polymer Polymers 0.000 claims description 27
- 238000005516 engineering process Methods 0.000 claims description 23
- 239000000758 substrate Substances 0.000 claims description 19
- 230000008859 change Effects 0.000 claims description 11
- 239000004020 conductor Substances 0.000 claims description 10
- 230000003647 oxidation Effects 0.000 claims description 9
- 238000007254 oxidation reaction Methods 0.000 claims description 9
- 230000015572 biosynthetic process Effects 0.000 claims description 8
- 238000000992 sputter etching Methods 0.000 claims description 7
- 238000004528 spin coating Methods 0.000 claims description 6
- 238000000231 atomic layer deposition Methods 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 238000006243 chemical reaction Methods 0.000 claims description 3
- 238000009413 insulation Methods 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 21
- 229920005591 polysilicon Polymers 0.000 abstract description 21
- 238000004519 manufacturing process Methods 0.000 abstract description 11
- 238000003860 storage Methods 0.000 abstract description 9
- 230000007704 transition Effects 0.000 abstract description 9
- 239000004065 semiconductor Substances 0.000 abstract description 7
- 238000002955 isolation Methods 0.000 description 22
- 239000012071 phase Substances 0.000 description 14
- 230000008569 process Effects 0.000 description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 229910052581 Si3N4 Inorganic materials 0.000 description 7
- 238000001259 photo etching Methods 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 229910000618 GeSbTe Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000007630 basic procedure Methods 0.000 description 1
- 210000003323 beak Anatomy 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 239000007792 gaseous phase Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
Abstract
The present invention relates to semiconductor structure and its preparing technical field more particularly to a kind of methods for realizing local interlinkage.The present invention is by using existing etching technics or increases special etching technics, it forms contact hole and is used as local interlinkage line to pick out the polysilicon in deep trench, the area used in device interconnection is reduced in this way, to reduce the area of device, the structure and manufacturing process of phase transition storage are also utilized simultaneously, titanium nitride and Ge-Sb-Te material are used as local interlinkage line, so as to produce the more accurate resistance of bigger.
Description
Technical field
The present invention relates to semiconductor structure and its preparing technical field more particularly to a kind of use deep trench isolation technique are real
Existing local interlinkage and the technology that accurate big resistance is made on the area of very little.
Background technology
Modern electronic circuit is that the device by detaching one by one is connected by specific electric path, therefore
It allows for semiconductor devices to keep apart in IC manufacturing, these devices then are also wanted to interconnect with needed for formation
The specific circuit structure wanted.In the manufacturing process of integrated circuit, often there are multiple semiconductors on same substrate
Device, it would be desirable to ensure the electric isolation between each device, and be isolated it is bad can cause electric leakage, breakdown potential force down, latch
The problems such as effect.Therefore isolation technology is a key technology in IC manufacturing, the isolation between semiconductor devices at present
Technology has following several：
1, junction isolation, mainly utilizes backgate diode to realize, this technology is mainly used between bipolar transistor
Isolation, under current CMOS technology, the isolation of PMOS and NMOS can be realized by N traps, and N traps and p-type epitaxial layer are constituted
PN junction plays the role of isolation, and the area that this isolation technology occupies is larger；
2, (LOCOS) is isolated in localized oxidation of silicon, and the field oxygen isolation between the MOS process devices of 0.5um or more is general to be used
The structure of LOCOS, this technology are to utilize silicon nitride (such as Si3N4) film oxidation masking layer the characteristics of, first in the active of device
Area covers a floor silicon nitride, then grows one layer of thicker oxide layer by wet-oxygen oxidation in exposed isolated area place, finally
Silicon nitride layer is removed, active area, the making devices in active area are formed.This structure fabrication is simple, but can be in isolated area shape
At beak effect, the length of active area is reduced；
3, shallow trench isolation technology (STI), shallow trench isolation is main isolation technology to be applied under current CMOS technology, shallow
The basic procedure of trench isolation techniques is first deposit silicon nitride, then corrodes in isolated area and the groove of certain depth, then carries out
Side wall aoxidizes, and silica is deposited in the trench with chemical vapor deposition (CVD), flat finally by chemically mechanical polishing (CMP)
Smoothization forms channel separating zone and active area.Shallow trench isolation technology has more effective device isolation, can make the surface of device
Product reduce, have superpower latch protection ability, raceway groove is not corroded, it is mutually compatible with CMP process the advantages that,
But a disadvantage is that process costs are more expensive, it is more complicated.
4, deep trench isolation technology (DTI), deep trench isolation technology can be applied in the manufacturing process of semiconductor devices.
Currently, how by realizing local interlinkage in the device architecture with deep trench, it is mutual used in device to reduce
Even level, and reduce the area of device, while can be using the structure and process characteristic of phase transition storage under smaller area
Making more accurate big resistance becomes the direction that those skilled in the art are dedicated to research.
Invention content
In view of the above problems, the present invention discloses a kind of method for realizing local interlinkage, includes the following steps：
One substrate with conduction type is provided；
Deep trench is formed in the substrate, and after the first insulating layer is formed on the bottom of the deep trench and its side wall,
It prepares conductive material and is full of the deep trench；
Etching removal part first insulating layer and the part conductive material layer, with the top shape in the deep trench
After a shallow trench, prepares second insulating layer and be full of the shallow trench；
Second insulating layer described in partial etching forms contact hole, is drawn the conductive material with reality by the contact hole
Existing local interlinkage.
The method of above-mentioned realization local interlinkage, wherein the conduction type is p-type or N-type.
The method of above-mentioned realization local interlinkage, wherein using the method for deep reaction ion etching in the substrate shape
At deep trench.
The method of above-mentioned realization local interlinkage, wherein the conductive material is the polysilicon of doping.
The method of above-mentioned realization local interlinkage, wherein first insulating layer and the second insulating layer are oxidation
Layer.
The method of above-mentioned realization local interlinkage, wherein form the first insulation in the bottom of the deep trench and its side wall
Layer the step of include：
Oxidation technology is carried out, oxide layer is formed in the bottom of the deep trench and its side wall.
The method of above-mentioned realization local interlinkage, wherein when the thickness of the second insulating layer is less than setting value, part
Etching the step of second insulating layer forms contact hole includes：
In the second insulating layer upper surface spin coating photoresist, and the photoresist is exposed, is developed to have
The photoresist of graphical window；
Using the photoresist with graphical window as mask, second absolutely described in the method partial etching using ion etching
Edge layer, to form the contact hole.
The method of above-mentioned realization local interlinkage, wherein when the thickness of the second insulating layer is greater than or equal to described set
When definite value, the step of second insulating layer formation contact hole described in partial etching, includes：
In the second insulating layer upper surface spin coating photoresist, and the photoresist is exposed, is developed to have
The photoresist of graphical window；
Using the photoresist with graphical window as mask, using second insulating layer described in etching technics partial etching,
To form the contact hole.
The invention also discloses a kind of methods for realizing local interlinkage, include the following steps：
A phase change memory structure is provided, the phase change memory structure includes first successively according to sequence from bottom to up
Oxide layer, Ge-Sb-Te material layer and titanium nitride layer and the second oxide layer；
Second oxide layer described in partial etching forms contact hole, by the contact hole by the titanium nitride layer and the germanium
Antimony tellurium material layer is drawn to realize local interlinkage.
The method of above-mentioned realization local interlinkage, wherein the titanium nitride layer is formed by way of atomic layer deposition.
The invention discloses the methods for realizing local interlinkage, specific by increasing the characteristics of using deep trench isolation technology
Technique, the insulating layer in shallow trench can be performed etching to form contact hole, will be more in deep trench by contact hole
Crystal silicon, which picks out, is used as local interconnection line, can reduce the level used in device by the interconnection line of these parts, to subtract
The area of gadget, the present invention also utilize the structure and process characteristic of phase transition storage, titanium nitride and Ge-Sb-Te material are used as
Local interlinkage line, so as to make more accurate big resistance under smaller area.
Description of the drawings
Upon reading the detailed description of non-limiting embodiments with reference to the following drawings, the present invention and its feature, outer
Shape and advantage will become more apparent.Identical label indicates identical part in whole attached drawings.Not can according to than
Example draws attached drawing, it is preferred that emphasis is shows the purport of the present invention.
Fig. 1 a-1k are the flowage structure schematic diagrames for the method that local interlinkage is realized in the embodiment of the present invention one；
Fig. 2 is the flow chart for the method that local interlinkage is realized in the embodiment of the present invention one；
Fig. 3 a are the structural schematic diagrams for the phase transition storage that contact hole is formed in the embodiment of the present invention two；
Fig. 3 b are the structural schematic diagrams for doing big resistance in the embodiment of the present invention two using " L " shape titanium nitride；
Specific implementation mode
The present invention is further illustrated with specific embodiment below in conjunction with the accompanying drawings, but not as the limit of the present invention
It is fixed.
Embodiment one：
As shown in Fig. 2, present embodiments providing a kind of method for realizing local interlinkage, specifically comprise the following steps：
Step S1 provides a substrate 1 with conduction type, which can be p-type or N-type, which can be with
For silicon substrate or epitaxial layer, structure as shown in Figure 1a.
Step S2 forms one layer of etch mask 2 in the surface of substrate 1 and passes through chemical gaseous phase in an embodiment of the present invention
The method of deposition forms etch mask 2 in the surface of substrate 1, forms structure as shown in Figure 1 b.
Step S3, in etch mask 2 upper surface deposit a layer photoresist, through exposure and development after, formed have window figure
The photoresist of shape forms photoetching window, structure as illustrated in figure 1 c by mask of the photoresist in etch mask 2.
Step S4 continues with etch mask 2 to be that mask forms deep trench 3 in substrate 1, in an embodiment of the present invention,
Deep trench 3 is formed in substrate 1 using deep trench isolation technique, it is preferred that the side of deep reaction ion etching (DRIE) can be used
Method carries out substrate 1 deep plough groove etched, forms the deep trench 3, structure as shown in Figure 1 d.
Step S5, remove etch mask 2, remove the etch mask 2 technique may be used those skilled in the art institute it is ripe
The technology known, just it will not go into details herein, forms structure as shown in fig. le.
Step S6 continues to prepare conductive material and is full of after the bottom of deep trench 3 and its side wall form the first insulating layer 4
The deep trench 3, structure as shown in figure 1h.
In a preferred embodiment of the invention, above-mentioned steps S6 specifically comprises the following steps：
First, oxidation technology is carried out to substrate 1, to form the in the bottom on 1 surface of substrate and deep trench 3 and its side wall
One insulating layer 4, it follows that the material of first insulating layer 4 is silica；Structure as shown in Figure 1 f.
Secondly, conductive material (such as polysilicon) is filled into deep trench 3, it is preferred that in deep trench 3 and substrate 1
Upper surface forms polysilicon layer 5, and carries out CMP process to the polysilicon layer 5, forms structure as shown in Figure 1 g.
Again, removal is positioned at the polysilicon layer 5 and the first insulating layer 4 on 1 surface of substrate, the remaining covering of first insulating layer 4
The bottom of deep trench 3 and its side wall, and remaining polysilicon layer 5 is full of the deep trench 3, structure as shown in figure 1h.
Preferably, which is the polysilicon with doping, to reduce its resistivity.
Step S7 continues etching removal the first insulating layer of part 4 and partial polysilicon layer 5, with the top shape in deep trench 3
At shallow trench 7, prepares second insulating layer 8 and be full of shallow trench 7；Structure as shown in fig. ij.
In a preferred embodiment of the invention, above-mentioned steps S7 is specifically, first in semiconductor as shown in figure 1h
The top of structure forms one layer of isolated mask 6, and carries out photoetching process to the isolated mask 6 and form etching window, then with this
Isolated mask 6 is that mask etching removes the first insulating layer of part 4 and partial polysilicon layer 5, to form shallow ridges above deep trench 3
Slot 7, structure as shown in figure 1i；Isolated mask 6 is removed later, and is prepared second insulating layer 8 and be full of shallow trench 7, and passing through
Learning mechanical polishing makes the surface planarisation of substrate 1, forms structure as shown in fig. ij.
Preferably, the material of isolated mask 6 is Si3N4。
Preferably, the material of second insulating layer 8 is SiO2。
Step S8, partial etching second insulating layer 8 form contact hole 9, are drawn polysilicon layer 5 with reality by contact hole 9
Existing local interlinkage.
When the thickness of second insulating layer 8 is less than setting value, (contact hole prepared in standard CMOS process can be with zanjon
Polysilicon connection in road, the thickness of second insulating layer 8 more than setting shallow trench 7 upper surface in 100nm~400nm or so,
Such as：100nm, 150nm, 200nm, 250nm or 400nm etc.) when (since second insulating layer 8 is just full of shallow trench 7,
I.e. the thickness of second insulating layer 8 is equal to the depth of shallow trench 7), it can etch to obtain contact hole 9 by existing etching technics, such as
Shown in Fig. 1 k (a).At this point, formed contact hole 9 the specific steps are：Photoetching is carried out first, forms the graphical window of photoetching (i.e.
In 8 upper surface spin coating photoresist of second insulating layer, and the photoresist is exposed, is developed, there is graphical window to be formed
Photoresist), then according to the graphical window being lithographically formed, with the method pair of ion etching second at second insulating layer 8
Insulating layer 8 performs etching, and forms contact hole (i.e. using the photoresist with graphical window as mask, using ion etching
Method partial etching second insulating layer 8, to form contact hole 9), metal or other conduction materials are filled in contact hole 9 later
Matter, preparing interconnection line 10 again in this way can connect out by the polysilicon in deep trench, for the interconnection of part, can use
Contact hole technique in standard CMOS process does not have to add new technique.
(since second insulating layer 8 is just full of shallow ridges when the thickness of second insulating layer 8 is greater than or equal to setting value
Slot 7, the i.e. thickness of second insulating layer 8 are equal to the depth of shallow trench 7), the depth etched with existing technique is inadequate, so if
Polysilicon in deep trench is picked out to come, it is necessary to it adds additional etching process and forms the contact hole 9, it cannot be with mark
Contact hole in quasi- technique is molded together, as shown in Fig. 1 k (b).At this point, formed contact hole 9 the specific steps are：It carries out first
Photoetching, the graphical window for forming photoetching (i.e. in 8 upper surface spin coating photoresist of second insulating layer, and expose the photoresist
Light, development, to form the photoresist with graphical window), then according to the graphical window being lithographically formed, in the second insulation
Second insulating layer 8 is performed etching with new etching technics at layer 8, forms contact hole (i.e. with the light with graphical window
Photoresist is mask, using new etching technics partial etching second insulating layer 8, to form contact hole 9), then polysilicon is connect
Out it is used for local interlinkage.
Preferably, in an embodiment of the present invention, no matter the thickness of second insulating layer 8 is how many (that is, no matter the
The thickness of two insulating layers 8, which is greater than or equal to, is also less than setting value), the making work of local interlinkage is made of the polysilicon in deep trench
Skill is required to carry out before the manufacture craft of polysilicon gate.
Embodiment two：
In addition to using deep trench isolation technology using the polysilicon in groove as interconnection line other than, we can also utilize phase transformation
Titanium nitride and Ge-Sb-Te material in memory construction do interconnection line.
Specifically, the present embodiment is related to a kind of method for realizing local interlinkage, include the following steps：
First, a phase change memory structure is provided, phase change memory structure includes the successively according to sequence from bottom to up
One oxide layer, Ge-Sb-Te material layer and titanium nitride layer and the second oxide layer, since the method for forming phase change memory structure is this
Known to field technology personnel, in order to reduce repetition, just it will not go into details herein.
Secondly, the second oxide layer of partial etching is to form contact hole, by the contact hole by titanium nitride layer and Ge-Sb-Te material
The bed of material is drawn to realize local interlinkage.
Attached drawing 3a is the structure chart of phase transition storage, and 103 be titanium nitride (TiN) in figure, can be by atomic deposition (ALD)
Method generates, and in the technique of phase transition storage, the titanium nitride shape of formation is " L " shape, and 102 be Ge-Sb-Te material (GST),
Because the resistivity of titanium nitride is very high, therefore can be used for doing interconnection line, 101 be silica or silicon nitride, and 104 be oxidation
Object.Therefore titanium nitride and Ge-Sb-Te material are drawn to be used as local interlinkage line, to reduce the face of device by contact hole 105
Product.The manufacture craft of local interlinkage is done after the manufacture craft of polysilicon gate with titanium nitride and Ge-Sb-Te material, in metal 106
Manufacture craft before.
In addition, no matter with polysilicon or diffusion region do resistance all under existing standard CMOS process and cannot be made it is big and
Accuracy is not high, even if resistance value is made big, but area is very big, that is to say, that big resistance is with area greatly cost.
In the technique of phase transition storage, the shape of the titanium nitride of formation is " L " shape, and the resistivity of titanium nitride is very high, therefore I
Can be more accurately big resistance, and further reducing with process, Wo Menke with the titanium nitride of formation
With the smaller for doing area.
As shown in Figure 3b, 103 be the titanium nitride that " L " shape is formed in phase transition storage technique in figure, we just with it come
Resistance is done, 108 be contact hole, and 107 be the local interlinkage line of two " L " shape resistance, can be interconnected with silicide diffusion region
Line can also be other materials, we can be connected multiple " L " shape resistance with local interlinkage in this way, make very big
Resistance, and area very little；Preferably, the titanium nitride for being somebody's turn to do " L " shape is formed using the technique of atomic layer deposition.
In conclusion the present invention utilizes deep trench isolation technology, it is special by using existing etching technics or increase
Etching technics forms contact hole and is used as local interlinkage line to pick out the polysilicon in deep trench, it is mutual to reduce device in this way
Even used area to reduce the area of device, while also utilizing the structure and manufacturing process of phase transition storage, will nitrogenize
Titanium and Ge-Sb-Te material are used as local interlinkage line, so as to produce the more accurate resistance of bigger.
It should be appreciated by those skilled in the art that those skilled in the art are combining the prior art and above-described embodiment can be with
Realize change case, this will not be repeated here.Such change case does not affect the essence of the present invention, and it will not be described here.
Presently preferred embodiments of the present invention is described above.It is to be appreciated that the invention is not limited in above-mentioned
Particular implementation, wherein the equipment and structure be not described in detail to the greatest extent are construed as giving reality with the common mode in this field
It applies；Any technical person familiar with the field, without departing from the scope of the technical proposal of the invention, all using the disclosure above
Methods and technical content many possible changes and modifications are made to technical solution of the present invention, or be revised as equivalent variations etc.
Embodiment is imitated, this is not affected the essence of the present invention.Therefore, every content without departing from technical solution of the present invention, foundation
The technical spirit any simple modifications, equivalents, and modifications made to the above embodiment of the present invention, still fall within the present invention
In the range of technical solution protection.
Claims (10)
1. a kind of method for realizing local interlinkage, which is characterized in that include the following steps：
One substrate with conduction type is provided；
Deep trench is formed in the substrate, and after the first insulating layer is formed on the bottom of the deep trench and its side wall, is prepared
Conductive material is full of the deep trench；
Etching removal part first insulating layer and the part conductive material layer, with the top formation one in the deep trench
After shallow trench, prepares second insulating layer and be full of the shallow trench；
Second insulating layer described in partial etching forms contact hole, is drawn the conductive material to realize office by the contact hole
Portion interconnects.
2. the method for realizing local interlinkage as described in claim 1, which is characterized in that the conduction type is p-type or N-type.
3. the method for realizing local interlinkage as described in claim 1, which is characterized in that the method for using deep reaction ion etching
Deep trench is formed in the substrate.
4. the method for realizing local interlinkage as described in claim 1, which is characterized in that the conductive material is the polycrystalline of doping
Silicon.
5. the method for realizing local interlinkage as described in claim 1, which is characterized in that first insulating layer and described second
Insulating layer is oxide layer.
6. the method for realizing local interlinkage as claimed in claim 5, which is characterized in that in the bottom and its side of the deep trench
Wall formed the first insulating layer the step of include：
Oxidation technology is carried out, oxide layer is formed in the bottom of the deep trench and its side wall.
7. the method for realizing local interlinkage as described in claim 1, which is characterized in that when the thickness of the second insulating layer is small
When setting value, the step of second insulating layer formation contact hole described in partial etching, includes：
In the second insulating layer upper surface spin coating photoresist, and the photoresist is exposed, is developed to figure
Change the photoresist of window；
Using the photoresist with graphical window as mask, the second insulation described in the method partial etching using ion etching
Layer, to form the contact hole.
8. the method for realizing local interlinkage as claimed in claim 7, which is characterized in that when the thickness of the second insulating layer is big
When the setting value, the step of second insulating layer formation contact hole described in partial etching, includes：
In the second insulating layer upper surface spin coating photoresist, and the photoresist is exposed, is developed to figure
Change the photoresist of window；
Using the photoresist with graphical window as mask, using second insulating layer described in etching technics partial etching, with shape
At the contact hole.
9. a kind of method for realizing local interlinkage, which is characterized in that include the following steps：
A phase change memory structure is provided, the phase change memory structure includes the first oxidation successively according to sequence from bottom to up
Layer, Ge-Sb-Te material layer and titanium nitride layer and the second oxide layer；
Second oxide layer described in partial etching forms contact hole, by the contact hole by the titanium nitride layer and the Ge-Sb-Te
Material layer is drawn to realize local interlinkage.
10. the method for realizing local interlinkage as claimed in claim 9, which is characterized in that the shape by way of atomic layer deposition
At the titanium nitride layer.
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| CN1628387A (en) * | 2002-06-14 | 2005-06-15 | 国际商业机器公司 | Enhanced structure and method for buried local interconnects |
| CN1702883A (en) * | 2004-05-27 | 2005-11-30 | 三星电子株式会社 | Semiconductor devices having phase change memory cells, electronic systems employing the same and methods of fabricating the same |
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| US8021941B2 (en) * | 2009-07-21 | 2011-09-20 | International Business Machines Corporation | Bias-controlled deep trench substrate noise isolation integrated circuit device structures |
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| CN1702883A (en) * | 2004-05-27 | 2005-11-30 | 三星电子株式会社 | Semiconductor devices having phase change memory cells, electronic systems employing the same and methods of fabricating the same |
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