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JP2005524995A - Integrated circuit having internal impedance matching circuit - Google Patents

Integrated circuit having internal impedance matching circuit Download PDF

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Publication number
JP2005524995A
JP2005524995A JP2004504309A JP2004504309A JP2005524995A JP 2005524995 A JP2005524995 A JP 2005524995A JP 2004504309 A JP2004504309 A JP 2004504309A JP 2004504309 A JP2004504309 A JP 2004504309A JP 2005524995 A JP2005524995 A JP 2005524995A
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JP
Japan
Prior art keywords
integrated circuit
transmission line
package
die
lead
Prior art date
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Pending
Application number
JP2004504309A
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Japanese (ja)
Inventor
シュミット、ノーバート、エー
ジアチーノ、リチャード、ジェイ
ストラブル、ウエーン、エム
Original Assignee
メイコム インコーポレイテッド
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Priority claimed from US10/142,250 external-priority patent/US6828658B2/en
Priority claimed from US10/427,330 external-priority patent/US6903447B2/en
Application filed by メイコム インコーポレイテッド filed Critical メイコム インコーポレイテッド
Publication of JP2005524995A publication Critical patent/JP2005524995A/en
Pending legal-status Critical Current

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    • H01L2924/181—Encapsulation
    • H01L2924/183—Connection portion, e.g. seal
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Abstract

【解決手段】集積回路パッケージ（１００）はダイとの接続部を収容し、内部整合部（１０６）を有する集積回路（１０４）を形成する。このパッケージは、少なくとも１本の伝送線からなるリードフレーム、ダイパドル、少なくとも１ほんの入力リード及び少なくとも１本の出力リード（１０２）を具備する。結合線は、少なくとも１本の伝送線に沿ってインピーダンス整合ネットワーク（１０６）により選択位置を接地接続する。また、このパッケージは、リードフレームを実質的に封入する一方、ダイパドル及び入力・出力リードを露出する。An integrated circuit package (100) accommodates a connection to a die and forms an integrated circuit (104) having an internal matching portion (106). The package comprises a lead frame consisting of at least one transmission line, a die paddle, at least one input lead and at least one output lead (102). The coupled line is grounded at a selected location by an impedance matching network (106) along at least one transmission line. The package substantially encapsulates the lead frame while exposing the die paddle and input / output leads.

Description

本発明は半導体デバイスの分野に関し、特に内部インピーダンス整合部を有する集積回路に関する。   The present invention relates to the field of semiconductor devices, and more particularly to an integrated circuit having an internal impedance matching section.

携帯電話において、無線周波数（ＲＦ）電力増幅器（ＰＡ）は、低出力インピーダンス（例えば２Ω未満）を有する半導体デバイス（例えばシリコン又はガリウム砒素）を使用して構築される。このインピーダンスは、無線の残余のフィルタ、スイッチ、ダイプレクサ及びアンテナに接続するために、より大きなインピーダンス値（例えば50Ω）に変換する必要がある。このインピーダンス変換ネットワークは「出力整合」と称されるのが代表的である。
米国特許第６０８４３００号明細書 米国特許第５５５７１４４号明細書 In mobile phones, radio frequency (RF) power amplifiers (PA) are built using semiconductor devices (eg, silicon or gallium arsenide) that have a low output impedance (eg, less than 2Ω). This impedance needs to be converted to a larger impedance value (eg 50Ω) in order to connect to the remaining wireless filters, switches, diplexers and antennas. This impedance transformation network is typically referred to as “output matching”.
US Patent No. 6084300 US Pat. No. 5,557,144

２Ωのインピーダンスを50Ωに変換することに加え、出力整合は、携帯電話の効率及びバッテリ寿命（例えば通話時間）を増大するように調波周波数に調整されるのが代表的である。これらの調波周波数は６GHzにまでわたる。これらの周波数において、キャパシタと出力整合部を構成するのに使用される他の受動部品との間の距離は重大であり、例えば0.025mmの距離も重要である。例えば、供給元は、キャパシタと出力整合ネットワークの他の受動部品との間を0.025mmの精度で1.57mm及び10.67mmの距離に特定することができる。   In addition to converting 2Ω impedance to 50Ω, the output matching is typically tuned to a harmonic frequency to increase cell phone efficiency and battery life (eg, talk time). These harmonic frequencies range up to 6 GHz. At these frequencies, the distance between the capacitor and other passive components used to construct the output matching section is critical, for example, a distance of 0.025 mm is also important. For example, the supplier can specify a distance of 1.57 mm and 10.67 mm with an accuracy of 0.025 mm between the capacitor and other passive components of the output matching network.

調波周波数は第２の問題を提起する。キャパシタは、調波周波数で重要になる寄生値を有する。寄生値は製造者毎に異なるので、同一の値を有する部品の供給元を変更することは異なる結果を生み出すことになる。   Harmonic frequencies pose a second problem. Capacitors have parasitic values that become important at harmonic frequencies. Since parasitic values vary from manufacturer to manufacturer, changing the source of parts having the same value will produce different results.

大量生産（例えば年間3000万個）する場合、これら寄生値は単一の供給元に依存し、0.025mmの許容差を管理することはコスト高になる。従って、インピーダンス整合ネットワークを提供する改良技法に対するニーズがある。   For mass production (eg 30 million pieces per year), these parasitic values depend on a single source, and managing a tolerance of 0.025 mm is costly. Accordingly, there is a need for improved techniques for providing an impedance matching network.

簡潔に言えば、本発明の一実施形態によれば、集積回路は、パッケージに電気的に接続され且つパッケージ内に収容されるダイを具備する。このパッケージは、伝送線、少なくとも１本の入力信号リード、及び伝送線に接続された少なくとも１本の出力信号リードを具備するリードフレームを有する。ダイは伝送線上に出力信号を与える。伝送線に沿った少なくとも１個の選択位置は、集積回路内のインピーダンス整合回路を介して第１電気ノードに接続される。   Briefly, according to one embodiment of the present invention, an integrated circuit comprises a die that is electrically connected to a package and contained within the package. The package includes a lead frame having a transmission line, at least one input signal lead, and at least one output signal lead connected to the transmission line. The die provides an output signal on the transmission line. At least one selected location along the transmission line is connected to the first electrical node via an impedance matching circuit in the integrated circuit.

本発明の別の実施形態によれば、集積回路パッケージは、少なくとも１本の伝送線、少なくとも１本の入力信号リード及び少なくとも１本の出力信号リードを具備するリードフレームを有する。伝送線に沿った少なくとも１個の選択位置は、集積回路パッケージ内のインピーダンス整合回路を介して第１電気ノードに接続され、インピーダンス整合回路は出力信号リードに関連する。   In accordance with another embodiment of the present invention, an integrated circuit package has a lead frame that includes at least one transmission line, at least one input signal lead, and at least one output signal lead. At least one selected location along the transmission line is connected to the first electrical node via an impedance matching circuit in the integrated circuit package, the impedance matching circuit being associated with the output signal lead.

インピーダンス整合回路は集積回路内に配置可能である。例えば一実施形態において、インピーダンス整合回路は、伝送線に沿った少なくとも１個の選択位置とリードフレームのピンとの間を接続してもよい。   The impedance matching circuit can be arranged in the integrated circuit. For example, in one embodiment, the impedance matching circuit may connect between at least one selected location along the transmission line and a lead frame pin.

一実施形態において、伝送線に沿った少なくとも１個の選択位置は、キャパシタにワイヤボンディングされる。キャパシタの容量値及び伝送線の寸法は、所望の整合回路（すなわち出力インピーダンス）を提供するよう選択される。   In one embodiment, at least one selected position along the transmission line is wire bonded to the capacitor. The capacitance value of the capacitor and the size of the transmission line are selected to provide the desired matching circuit (ie, output impedance).

伝送線をリードフレームに組み込むことは、整合ネットワークを集積回路の外に配置する必要性を回避する。例えば、リードフレームをエッチング及び／又は半エッチングして伝送線を提供し、インピーダンス変換整合回路の部品（例えばキャパシタ、インダクタ等）を集積回路上に配置し、伝送線上の選択位置と第１電気ノード（例えば接地）との間にこれら部品を接続することは、比較的安価である。   Incorporating the transmission line into the lead frame avoids the need to place the matching network outside the integrated circuit. For example, the lead frame is etched and / or semi-etched to provide a transmission line, impedance conversion matching circuit components (eg, capacitors, inductors, etc.) are arranged on the integrated circuit, and the selected position on the transmission line and the first electrical node It is relatively inexpensive to connect these components to (eg ground).

本発明のこれら及び他の目的、特徴及び利点は、添付図面に図示されるように、以下の好適実施形態の説明に照らせばより明白になるであろう。   These and other objects, features and advantages of the present invention will become more apparent in light of the following description of preferred embodiments, as illustrated in the accompanying drawings.

図１は、線１０２上に出力信号を与える典型的な従来技術の整合回路構造の機能的ブロック図である。一実施形態において、線１０２上の出力信号は、集積回路１０４内のＲＦ電力増幅器（ＰＡ）から来る。集積回路１０４は、線１０２上の出力信号をインピーダンス変換ネットワーク１０６（本明細書では「整合ネットワーク」とも称する）に提供する。整合ネットワークは、インピーダンス整合された出力信号を線１０８上に提供する。例えば、線１０８上のインピーダンス整合された出力信号は例えば50Ωの出力インピーダンスを有するが、他方、線１０２の信号インピーダンスは例えば２Ωである。インピーダンス整合ネットワーク１０６は、要求されるインピーダンス変換及び調波濾波を提供するよう精確に配置された複数のキャパシタＣ1１１０及びＣ2１１２を具備する。例えば、キャパシタＣ1１１０は集積回路１０４の縁１１４から精確に配置される（例えば0.025mmの許容差で）が、キャパシタＣ1１１０及びＣ2１１２間の距離も精確に制御される。上述したように、これらの配置制限は問題を含み、集積回路１０４の外部にある整合ネットワークを比較的コスト高にする。 FIG. 1 is a functional block diagram of a typical prior art matching circuit structure that provides an output signal on line 102. In one embodiment, the output signal on line 102 comes from an RF power amplifier (PA) in integrated circuit 104. Integrated circuit 104 provides the output signal on line 102 to impedance transformation network 106 (also referred to herein as a “matching network”). The matching network provides an impedance matched output signal on line 108. For example, the impedance-matched output signal on line 108 has an output impedance of, for example, 50Ω, while the signal impedance of line 102 is, for example, 2Ω. The impedance matching network 106 includes a plurality of capacitors C 1 110 and C 2 112 that are precisely arranged to provide the required impedance transformation and harmonic filtering. For example, capacitor C 1 110 is accurately positioned from edge 114 of integrated circuit 104 (eg, with a tolerance of 0.025 mm), but the distance between capacitors C 1 110 and C 2 112 is also accurately controlled. As mentioned above, these placement restrictions are problematic and make the matching network external to the integrated circuit 104 relatively expensive.

図２は、プラスチックパッケージ内に第１ダイ２０２と第２ダイ２０４とを具備する第１の集積回路２００の上部を切り取った平面図である。第１ダイ２０２は、結合ワイヤ（bond wire）２０６，２０８を介してリードフレーム（例えばエッチングされた銅）上に配置された第１伝送線２１０に出力信号を提供する。第２ダイ２０４は、結合ワイヤ２１２，２１４を介してリードフレーム上に配置された第２伝送線２１６に出力信号を提供する。また、リードフレームは複数の入力／出力（Ｉ／Ｏ）リード（例えば２１８〜２２２）を有する。結合ワイヤはダイ上のパッド及びＩ／Ｏリードを相互接続する。本発明の一側面によれば、リードフレームも、集積回路内の回路部品と協働して集積回路に内部整合部を提供する少なくとも１本の伝送線（例えば、非露出領域で厚さ0.1mm、露出領域で厚さ0.2mm）を具備する。具体的には、本実施形態において、第１ダイ２０２に配置されたキャパシタ及びインダクタ（図示せず）の一方又は両方等の整合回路部品は、第１伝送線２１０に接続される。例えば、第１ダイ２０２に配置された第１キャパシタは、結合ワイヤ２３０，２３１により伝送線２１０上の第２選択位置に接続される。本実施形態では、電流を扱うために２本の結合ワイヤが示される。しかし、当業者であれば、要求される電流の取扱いに依ってダイ上の整合回路部品を伝送線に接続するために２本より多いか少ない結合ワイヤを使用可能であることをもちろん認識するであろう。さらに、第２キャパシタをダイ２０２上に配置し、結合ワイヤ（図示せず）により伝送線２１０上の第２位置（例えば位置２４０）に接続して、図１に示される回路１０６と機能的に類似する整合回路を提供してもよい。しかし、図２の実施形態において、整合ネットワークは集積回路内に配置されている。すなわち、図２の集積回路は内部整合部を具備する。   FIG. 2 is a top plan view of the first integrated circuit 200 having the first die 202 and the second die 204 in a plastic package. The first die 202 provides an output signal to a first transmission line 210 disposed on a lead frame (eg, etched copper) via bond wires 206 and 208. The second die 204 provides an output signal to the second transmission line 216 disposed on the lead frame via the bonding wires 212 and 214. The lead frame also has a plurality of input / output (I / O) leads (eg, 218-222). Bond wires interconnect the pads and I / O leads on the die. According to one aspect of the invention, the lead frame also cooperates with circuit components in the integrated circuit to provide at least one transmission line (e.g., 0.1 mm thick in the unexposed area) that provides an internal alignment for the integrated circuit. The thickness of the exposed area is 0.2 mm). Specifically, in the present embodiment, matching circuit components such as one or both of a capacitor and an inductor (not shown) arranged on the first die 202 are connected to the first transmission line 210. For example, the first capacitor disposed on the first die 202 is connected to the second selected position on the transmission line 210 by the coupling wires 230 and 231. In this embodiment, two bond wires are shown to handle current. However, those skilled in the art will, of course, recognize that more or fewer coupling wires can be used to connect the matching circuit components on the die to the transmission line depending on the required current handling. I will. In addition, a second capacitor is placed on the die 202 and connected to a second location (eg, location 240) on the transmission line 210 by a bond wire (not shown) to provide functionality with the circuit 106 shown in FIG. A similar matching circuit may be provided. However, in the embodiment of FIG. 2, the matching network is located within the integrated circuit. That is, the integrated circuit of FIG. 2 includes an internal matching unit.

また、第２ダイ２０４も、第２ダイ２０４内の整合回路部品を例えば結合ワイヤ２４２，２４４を介して伝送線２１６に接続することにより構築される内部整合ネットワークを具備してもよい。   The second die 204 may also include an internal matching network constructed by connecting matching circuit components in the second die 204 to the transmission line 216 via, for example, coupling wires 242 and 244.

図３は、図２に示される第１ダイ２０２に関連した内部整合ネットワークの機能的ブロック図である。例えば、ダイ２０２上に配置された出力増幅器２４６は、伝送線２１０により導通される出力信号をＩ／Ｏリード２４８に提供する。ダイ２０２上に配置されたキャパシタ２５２の第１リードは、結合ワイヤ２３０，２３１を介して伝送線２１０上の第１選択位置２５４に接続される。キャパシタ２５２の第２リードは第１電位、例えば接地に接続される。注目に値するのは、これが、集積回路２００内に配置されたインピーダンス整合回路２５８を提供することである。   FIG. 3 is a functional block diagram of an internal matching network associated with the first die 202 shown in FIG. For example, output amplifier 246 located on die 202 provides an output signal conducted on transmission line 210 to I / O lead 248. A first lead of a capacitor 252 disposed on the die 202 is connected to a first selected position 254 on the transmission line 210 via coupling wires 230 and 231. The second lead of capacitor 252 is connected to a first potential, for example ground. It is worth noting that this provides an impedance matching circuit 258 located within the integrated circuit 200.

図４は、複数のＩ／Ｏリード（例えば３０８〜３１４）を含むリードフレーム３０６（例えばエッチングされた銅）のダイパドル３０２上に配置された、ダイ（図示せず）を有する第２の集積回路３００の上部を切り取った平面図である。ダイ上に配置された相互接続ボンディングパッドは、例えば結合ワイヤを介してＩ／Ｏリードに接続される。また、リードフレーム３０６は、ハッチングで示された第１伝送線３２０を有する。本実施形態において、パッケージも、パッケージの外部に露出していない第２伝送線３２２を有する。第１伝送線３２０はパッケージからの第１出力信号に関連するが、第２伝送線はパッケージからの第２出力信号に関連する。ダイ上に配置され第１出力信号に関連したキャパシタ、インダクタ（図示せず）等の整合回路部品は、第１電位（例えば接地）と第１伝送線３２０上の少なくとも１個の選択位置との間に接続される。   FIG. 4 illustrates a second integrated circuit having a die (not shown) disposed on a die paddle 302 of a lead frame 306 (eg, etched copper) that includes a plurality of I / O leads (eg, 308-314). It is the top view which cut off the upper part of 300. FIG. Interconnect bond pads located on the die are connected to I / O leads, for example, via bond wires. The lead frame 306 includes a first transmission line 320 indicated by hatching. In the present embodiment, the package also has a second transmission line 322 that is not exposed to the outside of the package. The first transmission line 320 is associated with a first output signal from the package, while the second transmission line is associated with a second output signal from the package. Matching circuit components, such as capacitors, inductors (not shown), etc., disposed on the die and associated with the first output signal are connected between the first potential (eg, ground) and at least one selected location on the first transmission line 320. Connected between.

図５は、図４のＡ−Ａ線に沿った断面図である。ダイ４０２はパドル３０２上に配置され、少なくとも１本の結合ワイヤ４０４は、リード３１３とダイ４０２上の結合パッド（図示せず）とを接続する。図６は、第２集積回路の底面図である。図示されるように、リードフレームは、パドル３０２及び複数のＩ／Ｏリード、例えば３０８〜３１４を具備する。図５及び図６を参照すると、パッケージも、整合回路部品が接続可能である伝送線に沿った選択位置を代表する複数の露出したワイヤボンド支持構造５１０〜５１７を有する。例えば、一実施形態において、これら支持構造（例えばエッチングされた銅）は、ダイ上の整合部品と、パッケージのリードフレーム内の伝送線との間の結合ワイヤ用の接続点である。例えば、接続ワイヤ４３０（図５参照）は、ダイ４０２上の整合部品（例えばキャパシタ）と支持構造５１１（すなわち伝送線３２０上の選択位置）との間をつなぐ。   FIG. 5 is a cross-sectional view taken along line AA in FIG. The die 402 is disposed on the paddle 302 and at least one bond wire 404 connects the lead 313 and a bond pad (not shown) on the die 402. FIG. 6 is a bottom view of the second integrated circuit. As shown, the lead frame includes a paddle 302 and a plurality of I / O leads, eg, 308-314. Referring to FIGS. 5 and 6, the package also has a plurality of exposed wire bond support structures 510-517 that are representative of selected locations along the transmission line to which matching circuit components can be connected. For example, in one embodiment, these support structures (eg, etched copper) are connection points for bonding wires between the matching components on the die and the transmission lines in the package leadframe. For example, the connecting wire 430 (see FIG. 5) connects between the matching component (eg, a capacitor) on the die 402 and the support structure 511 (ie, a selected location on the transmission line 320).

図７は図５のパッケージの側面図である。   FIG. 7 is a side view of the package of FIG.

図８は、ダイ８０２と、第３のプラスチックパッケージのリードフレーム８０４とを具備する第３の集積回路８００の上部を切り取った平面図である。図９は、図８のリードフレーム８０４をクロスハッチングで示した平面図である。リードフレーム８０４は、ダイパドル８０６と、複数のＩ／Ｏリード８０８〜８２３とを具備する。また、リードフレームは、ダイ８０２上の出力部８２８を選択されたＩ／Ｏリード８０８〜８２３に接続する伝送線８２６を具備する。本実施形態において、ダイ出力８２８は、複数の結合ワイヤ８３１により伝送線８２６に接続される。ダイ８０２は、インピーダンス整合／変換ネットワークの少なくとも一部品（例えばキャパシタ、インダクタ等）を具備する。ダイ内のネットワーク整合部品は、伝送線８２６に沿って第１選択位置８３０に接続される。結果として、図３に示されるような回路構成が提供される。インピーダンス整合及び濾波の要求事項に依って、ダイ８０２内の整合回路部品は、選択位置８３０よりも伝送線に沿った複数の選択位置８３２〜８３６の一つで伝送線８２６に接続してもよい。図８の実施形態において、集積回路８００は４mmｘ４mmである（すなわちＬ８５０が４mmに等しい）。図８に示されるように、伝送線８２６の経路長は、整合回路部品が接続される伝送線に沿った選択位置（例えば８３０）によって変わる。   FIG. 8 is a top plan view of a third integrated circuit 800 having a die 802 and a third plastic package lead frame 804 cut away. FIG. 9 is a plan view showing the lead frame 804 of FIG. 8 by cross-hatching. The lead frame 804 includes a die paddle 806 and a plurality of I / O leads 808 to 823. The lead frame also includes a transmission line 826 that connects the output 828 on the die 802 to the selected I / O leads 808-823. In the present embodiment, the die output 828 is connected to the transmission line 826 by a plurality of coupling wires 831. The die 802 includes at least one component (eg, capacitor, inductor, etc.) of an impedance matching / conversion network. The network matching components in the die are connected to the first selected location 830 along the transmission line 826. As a result, a circuit configuration as shown in FIG. 3 is provided. Depending on impedance matching and filtering requirements, the matching circuit components in die 802 may connect to transmission line 826 at one of a plurality of selection positions 832-836 along the transmission line rather than selection position 830. . In the embodiment of FIG. 8, the integrated circuit 800 is 4 mm × 4 mm (ie, L850 is equal to 4 mm). As shown in FIG. 8, the path length of the transmission line 826 varies depending on the selected position (for example, 830) along the transmission line to which the matching circuit component is connected.

図１０は、図８のリードフレームをクロスハッチングで示した底面図である。本図において、伝送線８２６に沿った選択位置８３０，８３６に関連する支持構造は、集積回路８００の下面に露出する。   FIG. 10 is a bottom view of the lead frame of FIG. 8 shown by cross hatching. In this figure, the support structure associated with selected locations 830, 836 along the transmission line 826 is exposed on the underside of the integrated circuit 800.

図１１は、ダイ１１０２と、第４のプラスチックパッケージのリードフレーム１１０４とを具備する第４の集積回路１１００の上部を切り取った平面図である。本実施形態は、内部整合ネットワーク部品１１０６（例えばキャパシタ）がダイパドル１１０８と伝送線８２６上の第１選択位置１１１０との間に配置される点を除き、図８ないし図１０に示された実施形態と実質的に同じである。すなわち、内部整合回路部品はダイ上に配置されていない。しかし、内部整合回路は依然として集積回路内にあり、内部整合部を提供している。   FIG. 11 is a plan view of the top of a fourth integrated circuit 1100 that includes a die 1102 and a fourth plastic package lead frame 1104. This embodiment is the embodiment shown in FIGS. 8-10 except that an internal matching network component 1106 (eg, a capacitor) is placed between the die paddle 1108 and the first selected location 1110 on the transmission line 826. Is substantially the same. That is, the internal matching circuit components are not arranged on the die. However, the internal matching circuit is still in the integrated circuit and provides an internal matching section.

図１２は、ダイ１２０２と、第５のプラスチックパッケージのリードフレーム１２０４とを具備する第５の集積回路１２００の上部を切り取った平面図である。本実施形態は、第１内部整合ネットワーク部品１２０６（例えばキャパシタ）がダイパドル１２０８と伝送線８２６上の第１選択位置１２１０との間に配置される点、及び第２内部整合ネットワーク部品（図示せず）がダイ１２０２内に配置され且つ伝送線上の第２選択位置に結合されている点を除き、図８ないし図１０及び図１１に示された実施形態と実質的に同じである。   FIG. 12 is a top plan view of a fifth integrated circuit 1200 that includes a die 1202 and a fifth plastic package lead frame 1204. In this embodiment, a first internal matching network component 1206 (for example, a capacitor) is disposed between the die paddle 1208 and a first selected position 1210 on the transmission line 826, and a second internal matching network component (not shown). Is substantially the same as the embodiment shown in FIGS. 8-10 and 11 except that is disposed in the die 1202 and is coupled to a second selected position on the transmission line.

図１３は、図１２の集積回路に関連した内部整合ネットワークの機能的ブロック図である。例えば、ダイ１２０２上に配置された出力増幅器１３０２は、伝送線８２６により導通される出力信号をＩ／Ｏリード８０８に提供する。ダイ１２０２上に配置されたキャパシタ１３０６の第１リードは、結合ワイヤ１３１４を介して伝送線８２６上の第２選択位置１２１２に接続される。ダイ上のキャパシタ１３０６の第２リードは第１電位、例えば接地に接続される。キャパシタ１３０６の第１リードは伝送線８２６上の第１選択位置１２１０に接続され、他方、キャパシタ１３０６の第２リードはダイパドル（すなわち接地）に接続される。   FIG. 13 is a functional block diagram of an internal matching network associated with the integrated circuit of FIG. For example, output amplifier 1302 disposed on die 1202 provides an output signal conducted by transmission line 826 to I / O lead 808. A first lead of a capacitor 1306 disposed on the die 1202 is connected to a second selected location 1212 on the transmission line 826 via a bond wire 1314. The second lead of capacitor 1306 on the die is connected to a first potential, eg, ground. The first lead of capacitor 1306 is connected to a first selected position 1210 on transmission line 826, while the second lead of capacitor 1306 is connected to a die paddle (ie, ground).

図１４は、ダイ１４０２と、第６のパッケージのリードフレーム１４０４とを具備する第６の集積回路１４００の上部を切り取った平面図である。本実施形態は、内部整合ネットワーク部品１４０６が接地ピン１４０８からなる第１電位と伝送線１４２６上の選択位置１４１０との間に配置される点を除き、図８ないし図１０、図１１及び図１２に示された実施形態と実質的に同じである。図１４において、内部整合ネットワーク部品はキャパシタとして図示されているが、他の任意の適当な部品、例えばインダクタ等も同様に使用可能であることを理解されたい。前の実施形態に連結して上述したことに類似するが、本実施形態のパッケージは、例えばプラスチック、すなわちプラスチック成形複合物等の従来の熱可塑性又は熱硬化性材料等の任意の所望の材料を使用するオーバモールド法により、集積回路を実質的に封入（又は閉じ込め）してもよい。例えば、本発明の別の実施形態と同様に、リードフレーム等の本実施形態における集積回路の或る部分は実質的に封入可能であるのに対し、ダイパドル及び入力／出力リード等の他の部分は露出したままである。   FIG. 14 is a top plan view of the sixth integrated circuit 1400 having the die 1402 and the lead frame 1404 of the sixth package. In the present embodiment, except that the internal matching network component 1406 is disposed between the first potential consisting of the ground pin 1408 and the selected position 1410 on the transmission line 1426, FIGS. 8 to 10, FIG. 11 and FIG. Is substantially the same as the embodiment shown in FIG. In FIG. 14, the internal matching network component is illustrated as a capacitor, but it should be understood that any other suitable component, such as an inductor, can be used as well. Similar to that described above in connection with the previous embodiment, the package of this embodiment can be made of any desired material, such as a conventional thermoplastic or thermoset material such as plastic, ie a plastic molded composite. Depending on the overmolding method used, the integrated circuit may be substantially encapsulated (or confined). For example, as with other embodiments of the present invention, some parts of the integrated circuit in this embodiment, such as lead frames, can be substantially encapsulated, while other parts, such as die paddles and input / output leads. Remains exposed.

また、図１４に示される内部整合ネットワーク部品１４０６は、他の実施形態では望ましいであろういかなる位置１４１０以外の位置で伝送線１４２６に接続してもよい。同様に、他の実施形態において、内部整合ネットワーク部品１４０６は、接地ピン１４０８以外の部分に接続してもよい。さらに、他の実施形態において、複数の整合ネットワーク部品は、例えば図８ないし図１０及び図１２に示された実施形態で図示されたように、所望の場所で使用してもよい。   Also, the internal matching network component 1406 shown in FIG. 14 may connect to the transmission line 1426 at a location other than any location 1410 that may be desirable in other embodiments. Similarly, in other embodiments, the internal matching network component 1406 may be connected to portions other than the ground pin 1408. Furthermore, in other embodiments, a plurality of matching network components may be used at a desired location, for example, as illustrated in the embodiments shown in FIGS.

有利なことに、本発明の実施形態は、内部インピーダンス整合のために、そして例えば、電話ハンドセット製造者がインピーダンス変換整合回路のために基板に空間を設ける必要が無いようにするために、集積回路及びパッケージを提供できる。さらに、本発明の実施形態は、集積回路を実質的に封入する部材を区画するパッケージを提供できるので、水分の侵入又は他の不要物を防止できるバリアを提供する。さらに、本発明の実施形態は、集積回路の全体設計にエッチング又は半エッチングの特徴を使用することができる。例えば、図５に図示されているように、部品３１３，３１４は半エッチング特徴の例であり、特定部品のインタロックが望まれるところで使用可能である。   Advantageously, embodiments of the present invention provide integrated circuits for internal impedance matching and, for example, so that telephone handset manufacturers do not have to provide space in the substrate for impedance transformation matching circuits. And can provide package. Furthermore, embodiments of the present invention can provide a package that partitions a member that substantially encapsulates an integrated circuit, thus providing a barrier that can prevent moisture ingress or other unwanted material. Furthermore, embodiments of the present invention can use etched or semi-etched features in the overall design of an integrated circuit. For example, as shown in FIG. 5, parts 313, 314 are examples of semi-etched features and can be used where interlocking of specific parts is desired.

無線電話ハンドセット用の電力増幅器用パッケージとの関連で本発明を説明したが、他の多くの用途では、従来、回路基板上で実行された又は要素部品の集合体としてインピーダンス整合を要する用途を、集積回路内に含まれる整合回路で置換することが望ましいことが考えられる。有利なことに、整合回路の部品を精確に配置する必要に関連する製造容易性の多くの問題を未然に防ぐ。さらに、整合ネットワーク部品は伝送線及び接地間を接続したが、第１電位を接地する必要は必ずしもない。   Although the invention has been described in the context of a power amplifier package for a radiotelephone handset, many other applications have traditionally been implemented on circuit boards or require impedance matching as a collection of component parts. It may be desirable to replace with a matching circuit included in the integrated circuit. Advantageously, it obviates many of the manufacturability issues associated with the need to accurately place the components of the matching circuit. Further, although the matching network component connects the transmission line and the ground, it is not always necessary to ground the first potential.

いくつかの好適な実施形態に関して本発明を示し説明したが、本発明の真髄から逸脱することなく、その形態及び詳細に対して種々の変更、省略及び付加が可能である。   Although the invention has been shown and described with respect to several preferred embodiments, various changes, omissions and additions can be made to the form and details without departing from the essence of the invention.

従来技術のＲＦ出力信号用整合回路構成の機能的ブロック図である。It is a functional block diagram of the matching circuit structure for RF output signals of a prior art. 第１のプラスチックパッケージ内に第１ダイと第２ダイとを具備する第１集積回路の上部を切り取った平面図である。It is the top view which cut off the upper part of the 1st integrated circuit which comprises the 1st die and the 2nd die in the 1st plastic package. 図２に示される第１ダイに関連した内部整合ネットワークの機能的ブロック図である。FIG. 3 is a functional block diagram of an internal matching network associated with the first die shown in FIG. 2. 少なくとも一つの出力信号を提供する第２集積回路のリードフレームの上部を切り取った平面図である。FIG. 6 is a plan view of a top portion of a lead frame of a second integrated circuit that provides at least one output signal. 図４のＡ−Ａ線に沿った断面図である。It is sectional drawing along the AA line of FIG. 第２集積回路の底面図である。It is a bottom view of the second integrated circuit. 図５のパッケージの側面図である。FIG. 6 is a side view of the package of FIG. 5. ダイ内に配置される内部整合回路を具備する第３の集積回路のリードフレームを示す、上部を切り取った平面図である。FIG. 5 is a top plan view of a third integrated circuit leadframe with an internal matching circuit disposed within the die, with the top cut away. 図８のリードフレームをクロスハッチングで示した平面図である。It is the top view which showed the lead frame of FIG. 8 by cross hatching. 図８のリードフレームの露出部分をクロスハッチングで示した底面図である。FIG. 9 is a bottom view showing an exposed portion of the lead frame in FIG. 8 by cross-hatching. ダイパドルと伝送線上の第１選択位置との間に配置された内部整合ネットワークを具備する第４の集積回路のリードフレームを示す、上部を切り取った平面図である。FIG. 10 is a top plan view, with a top cut away, showing a lead frame of a fourth integrated circuit with an internal matching network disposed between the die paddle and a first selected position on the transmission line. ダイ及び伝送線の第１選択位置間に配置された第１内部整合ネットワーク部品と、ダイパドル及び伝送線の第２選択位置間に配置された第２内部整合ネットワーク部品とを具備する第５の集積回路のリードフレームを示す、上部を切り取った平面図である。A fifth integration comprising a first internal matching network component disposed between a first selected location of the die and the transmission line and a second internal matching network component disposed between a second selected location of the die paddle and the transmission line. It is the top view which cut out the upper part which shows the lead frame of a circuit. 図１２の集積回路に関連した内部整合ネットワークの機能的ブロック図である。FIG. 13 is a functional block diagram of an internal matching network associated with the integrated circuit of FIG. 伝送線の第１選択位置及び接地ピン間に配置された内部整合ネットワークを具備する第６の集積回路のリードフレームを示す、上部を切り取った平面図である。FIG. 9 is a top plan view of the sixth integrated circuit leadframe with an internal matching network disposed between the first selected location of the transmission line and the ground pin;

符号の説明Explanation of symbols

２００，３００，８００，１１００，１２００，１４００ 集積回路
２０６，２０８，２１２，２１４，２３０，２３１，２４２，２４４，４０４，８３１，１３１４ 結合ワイヤ
２１０，２１６，３２０，３２２，８２６，１４２６ 伝送線
２５２ キャパシタ
２５４，８３０，８３６，１１１０，１２１０，１２１２，１４１０ 選択位置
２５８ インピーダンス整合回路
３０６，８０４，１１０４，１２０４，１４０４ リードフレーム
１４０８ 接地ピン 200, 300, 800, 1100, 1200, 1400 Integrated circuit 206, 208, 212, 214, 230, 231, 242, 244, 404, 831, 1314 Coupling wire 210, 216, 320, 322, 826, 1426 Transmission line 252 Capacitors 254, 830, 836, 1110, 1210, 1212, 1410 Selection position 258 Impedance matching circuit 306, 804, 1104, 1204, 1404 Lead frame 1408 Ground pin

Claims (37)

少なくとも１本の入力信号リード、少なくとも１本の出力信号リード、及び前記少なくとも１本の出力信号リードに接続された少なくとも１本の伝送線を具備するリードフレームを有するパッケージと、
該パッケージに電気的に接続されると共に該パッケージ内に収容され、前記少なくとも１本の伝送線に信号を提供するダイとを具備し、
前記少なくとも１本の伝送線に沿った選択位置は、集積回路上に配置されたインピーダンス整合回路を介して第１電位に電気的に接続されていることを特徴とする内部整合集積回路。 A package having a lead frame comprising at least one input signal lead, at least one output signal lead, and at least one transmission line connected to the at least one output signal lead;
A die electrically connected to the package and housed in the package for providing a signal to the at least one transmission line;
The internal matching integrated circuit, wherein the selected position along the at least one transmission line is electrically connected to the first potential via an impedance matching circuit disposed on the integrated circuit. 前記伝送線に沿った前記選択位置及び前記インピーダンス整合回路は、少なくとも１本の接合ワイヤを介して接続されていることを特徴とする請求項１記載の内部整合集積回路。   2. The internal matching integrated circuit according to claim 1, wherein the selected position along the transmission line and the impedance matching circuit are connected via at least one bonding wire. 前記インピーダンス整合回路はキャパシタであることを特徴とする請求項２記載の内部整合集積回路。   3. The internal matching integrated circuit according to claim 2, wherein the impedance matching circuit is a capacitor. 前記インピーダンス整合回路はインダクタであることを特徴とする請求項２記載の内部整合集積回路。   3. The internal matching integrated circuit according to claim 2, wherein the impedance matching circuit is an inductor. 前記ダイはガリウム砒素デバイスからなることを特徴とする請求項２記載の内部整合集積回路。   3. The internal matching integrated circuit according to claim 2, wherein the die comprises a gallium arsenide device. 前記ダイはシリコンダイからなることを特徴とする請求項２記載の内部整合集積回路。   3. The internal matching integrated circuit according to claim 2, wherein the die is a silicon die. 前記第１電位は接地ピンからなることを特徴とする請求項１記載の内部整合集積回路。   2. The internal matching integrated circuit according to claim 1, wherein the first potential is a ground pin. 前記パッケージは前記リードフレームを実質的に閉じ込めることを特徴とする請求項１記載の内部整合集積回路。   The internal matching integrated circuit of claim 1, wherein the package substantially encloses the lead frame. 前記パッケージはプラスチックであることを特徴とする請求項１記載の内部整合集積回路。   2. The internal matching integrated circuit according to claim 1, wherein the package is made of plastic. 前記ダイは、前記少なくとも１本の伝送線上に入力信号又は出力信号のうち少なくとも一方を提供することを特徴とする請求項１記載の内部整合集積回路。   2. The internal matching integrated circuit of claim 1, wherein the die provides at least one of an input signal or an output signal on the at least one transmission line. 前記インピーダンス整合回路は前記ダイ上に配置されていることを特徴とする請求項１記載の内部整合集積回路。   2. The internal matching integrated circuit according to claim 1, wherein the impedance matching circuit is disposed on the die. 少なくとも１本の伝送線、ダイパドル、少なくとも１本の入力信号リード、及び前記少なくとも１本の伝送線に接続された少なくとも１本の出力信号リードを具備するリードフレームを有するパッケージと、
該パッケージに電気的に接続されると共に該パッケージ内に収容され、前記少なくとも１本の伝送線上に信号を提供するダイとを具備し、
前記少なくとも１本の伝送線上の少なくとも一つの選択位置は、インピーダンス整合回路を介して第１電位に電気的に接続されていることを特徴とする内部整合集積回路。 A package having a lead frame comprising at least one transmission line, a die paddle, at least one input signal lead, and at least one output signal lead connected to the at least one transmission line;
A die electrically connected to the package and housed in the package for providing a signal on the at least one transmission line;
An internal matching integrated circuit, wherein at least one selected position on the at least one transmission line is electrically connected to a first potential via an impedance matching circuit. 前記インピーダンス整合回路は、前記伝送線に沿って前記選択位置に接続された第１リードと、前記第１電位に接続された第２リードとを有するキャパシタを具備することを特徴とする請求項１２記載の内部整合集積回路。   13. The impedance matching circuit includes a capacitor having a first lead connected to the selected position along the transmission line and a second lead connected to the first potential. An internal matching integrated circuit as described. 前記インピーダンス整合回路は、前記伝送線に沿って前記選択位置に接続された第１リードと、前記第１電位に接続された第２リードとを有するインダクタを具備することを特徴とする請求項１２記載の内部整合集積回路。   13. The impedance matching circuit includes an inductor having a first lead connected to the selected position along the transmission line and a second lead connected to the first potential. An internal matching integrated circuit as described. 前記インピーダンス整合回路は、前記伝送線に沿って前記選択位置に接続された第１リードと、前記第１電位に接続された第２リードとを具備することを特徴とする請求項１２記載の内部整合集積回路。   13. The internal of claim 12, wherein the impedance matching circuit includes a first lead connected to the selected position along the transmission line and a second lead connected to the first potential. Matching integrated circuit. 前記伝送線は少なくとも１mmの長さを有することを特徴とする請求項１２記載の内部整合集積回路。   13. The internal matching integrated circuit according to claim 12, wherein the transmission line has a length of at least 1 mm. 前記第１電位は接地ピンからなることを特徴とする請求項１２記載の内部整合集積回路。   13. The internal matching integrated circuit according to claim 12, wherein the first potential is a ground pin. 前記第１電位は前記ダイパドルからなることを特徴とする請求項１２記載の内部整合集積回路。   13. The internal matching integrated circuit according to claim 12, wherein the first potential is formed by the die paddle. 前記パッケージは前記リードフレームを実質的に閉じ込めることを特徴とする請求項１２記載の内部整合集積回路。   13. The internal matching integrated circuit of claim 12, wherein the package substantially encloses the lead frame. 前記パッケージはプラスチックであることを特徴とする請求項１２記載の内部整合集積回路。   13. The internal matching integrated circuit according to claim 12, wherein the package is plastic. 前記ダイは、前記少なくとも１本の伝送線上に入力信号又は出力信号のうち少なくとも一方を提供することを特徴とする請求項１２記載の内部整合集積回路。   13. The internal matching integrated circuit of claim 12, wherein the die provides at least one of an input signal or an output signal on the at least one transmission line. 前記ダイは、ガリウム砒素又はシリコンのうち少なくとも一方からなることを特徴とする請求項１２記載の内部整合集積回路。   13. The internal matching integrated circuit according to claim 12, wherein the die is made of at least one of gallium arsenide and silicon. ダイを収容すると共に該ダイに電気的に接続して内部整合部と集積回路を形成する集積回路パッケージであって、
伝送線、ダイパドル、複数本の入力リード、及び少なくとも１本が前記伝送線に接続された複数本の出力リードを具備するリードフレームと、
該リードフレームを実質的に閉じ込める一方、前記ダイパドル、前記入力リード及び前記出力リードを露出する部材とを具備し、
前記伝送線に沿った少なくとも１個の選択位置が、前記パッケージ内に含まれるインピーダンス整合回路を介して第１電気ノードに電気的に接続され、前記伝送線に接続された前記出力リードの少なくとも１本に関連したインピーダンス整合ネットワークを提供することを特徴とする集積回路パッケージ。 An integrated circuit package containing a die and electrically connected to the die to form an internal matching portion and an integrated circuit,
A lead frame comprising a transmission line, a die paddle, a plurality of input leads, and a plurality of output leads, at least one of which is connected to the transmission line;
A member that substantially encloses the lead frame while exposing the die paddle, the input lead, and the output lead;
At least one selected position along the transmission line is electrically connected to the first electrical node via an impedance matching circuit included in the package, and at least one of the output leads connected to the transmission line. An integrated circuit package, characterized by providing an impedance matching network associated with the book. 前記伝送線は、エッチングされた銅又は半エッチングされた銅の少なくとも一方からなることを特徴とする請求項２３記載の集積回路パッケージ。   24. The integrated circuit package of claim 23, wherein the transmission line comprises at least one of etched copper or semi-etched copper. 前記インピーダンス整合回路はキャパシタを具備することを特徴とする請求項２３記載の集積回路パッケージ。   24. The integrated circuit package of claim 23, wherein the impedance matching circuit comprises a capacitor. 前記インピーダンス整合回路はインダクタを具備することを特徴とする請求項２３記載の集積回路パッケージ。   24. The integrated circuit package of claim 23, wherein the impedance matching circuit comprises an inductor. 前記インピーダンス整合回路は前記集積回路上に配置されていることを特徴とする請求項２３記載の集積回路パッケージ。   24. The integrated circuit package of claim 23, wherein the impedance matching circuit is disposed on the integrated circuit. 前記第１電気ノードはピンを具備し、
前記インピーダンス整合回路は、前記ピンに接続された第１リードと、前記伝送線上に配置された前記選択位置に接続された第２リードとを有するキャパシタを具備することを特徴とする請求項２３記載の集積回路パッケージ。 The first electrical node comprises a pin;
24. The impedance matching circuit includes a capacitor having a first lead connected to the pin and a second lead connected to the selected position disposed on the transmission line. Integrated circuit package. 前記インピーダンス整合回路は前記ダイパドル上に実装されたダイ内に配置されていることを特徴とする請求項２３記載の集積回路パッケージ。   24. The integrated circuit package of claim 23, wherein the impedance matching circuit is disposed in a die mounted on the die paddle. 前記第１電気ノードは前記ダイパドル上に配置され、
前記インピーダンス整合回路は、前記ダイパドルに接続された第１リードと、前記伝送線上に配置された前記選択位置に接続された第２リードとを有するキャパシタを具備することを特徴とする請求項２３記載の集積回路パッケージ。 The first electrical node is disposed on the die paddle;
24. The capacitor according to claim 23, wherein the impedance matching circuit comprises a capacitor having a first lead connected to the die paddle and a second lead connected to the selected position disposed on the transmission line. Integrated circuit package. 複数の入力リード、複数の出力リード、及び該出力リードの少なくとも１本に接続された少なくとも１本の伝送線を具備するリードフレームを有するパッケージと、
該パッケージに電気的に接続されると共に該パッケージ内に収容され、前記少なくとも１本の伝送線上に信号を提供するダイとを具備し、
前記少なくとも１本の伝送線に沿った選択位置は、集積回路内に配置されたインピーダンス整合回路を介して第１電位に電気的に接続されていることを特徴とする内部整合集積回路。 A package having a lead frame comprising a plurality of input leads, a plurality of output leads, and at least one transmission line connected to at least one of the output leads;
A die electrically connected to the package and housed in the package for providing a signal on the at least one transmission line;
The internal matching integrated circuit characterized in that the selected position along the at least one transmission line is electrically connected to the first potential via an impedance matching circuit disposed in the integrated circuit. 前記パッケージは前記リードフレームを実質的に閉じ込めることを特徴とする請求項３１記載の内部整合集積回路。   32. The internal matching integrated circuit of claim 31, wherein the package substantially encloses the lead frame. 前記パッケージはプラスチックであることを特徴とする請求項３１記載の内部整合集積回路。   32. The internal matching integrated circuit of claim 31, wherein the package is plastic. 前記ダイは、前記少なくとも１本の伝送線上に入力信号又は出力信号のうち少なくとも一方を提供することを特徴とする請求項３１記載の内部整合集積回路。   32. The internal matching integrated circuit of claim 31, wherein the die provides at least one of an input signal or an output signal on the at least one transmission line. 前記ダイはガリウム砒素であることを特徴とする請求項３１記載の内部整合集積回路。   32. The internal matching integrated circuit of claim 31, wherein the die is gallium arsenide. 前記伝送線は、エッチングされた銅又は半エッチングされた銅の少なくとも一方からなることを特徴とする請求項３１記載の内部整合集積回路。   32. The internal matching integrated circuit according to claim 31, wherein the transmission line is made of at least one of etched copper and semi-etched copper. 前記第１電位は接地ピンからなることを特徴とする請求項３１記載の内部整合集積回路。   32. The internal matching integrated circuit according to claim 31, wherein the first potential is a ground pin.
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