JP2005332979A - Semiconductor integrated circuit device, and designing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device which can reduce effectively the operational faultiness caused by its voltage drop. <P>SOLUTION: An LSI 10 is so partitioned into a plurality of segments 20 as to set in each segment 20 each region 40 for each decoupling capacitor to be disposed therein. In each segment 20, operational currents fed to each segment 20 by each main or auxiliary power-supply trunk line 16, 18 flow from each power-supply feeding position toward the periphery of each segment 20. Each decoupling capacitor is so disposed in the periphery as to deal with the IR drops generated at the terminals of the currents caused by each operational power supply. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor integrated circuit device and a design method thereof, and more particularly to prevention of malfunction due to dynamic voltage fluctuation (dynamic IR drop) accompanying operation.

  In recent years, with the increase in scale and integration of semiconductor integrated circuit devices (LSIs), miniaturization and multilayering of design rules for designing internal elements and wiring have been promoted. A power supply wiring formed in a mesh shape is used in order to suitably supply power to the logic circuit unit composed of such internal elements (see, for example, Patent Document 1).

Further, a decoupling capacitor is mounted on the LSI. This capacitor reduces the voltage drop (IR drop) of the power supply voltage generated during the operation of the internal element, and stabilizes the operation of the internal element. This capacitor is effective in removing EMI generated by the LSI itself. In other words, a decoupling capacitor is mounted on the LSI as an EMI countermeasure and a dynamic IR drop countermeasure of the LSI.
Japanese Patent No. 31399783

  However, the insertion position and capacity of the decoupling capacitor must be adjusted appropriately. For this reason, it is necessary to verify and optimize the insertion position and capacity simultaneously for the entire LSI area by IR drop analysis and EMI simulation. However, this method has a very heavy calculation processing load, and causes a prolonged design period.

  In the method of empirically determining the insertion position of the decoupling capacitor, there are cases where the IR drop is not effectively eliminated because the function circuit may be inserted into a region where a circuit with a low operation frequency is mounted. .

  The present invention has been made in view of such circumstances, and an object of the present invention is to provide a semiconductor integrated circuit device and a design method thereof that can effectively reduce malfunctions due to a voltage drop.

  In the following, means for achieving the above object and its effects are described.

  The invention according to claim 1 is provided with a power supply trunk line that supplies the operating power of the element to at least a part of the region where the element is formed, from the power supply position where the operating power is supplied to the periphery of the region. In the semiconductor integrated circuit device in which the power supply wiring is formed so that a current flows, a decoupling element for the operation power supply is disposed around at least one of the periphery of the region and the power supply trunk line.

  In the above configuration, with respect to the current flow by the operating power supply supplied to the elements in the region, the periphery of the region where the element is formed is the end point of the flow, and the decoupling element is arranged at the end point. Therefore, the influence of the dynamic IR drop of the operating power supply is efficiently improved by the decoupling element. And since a decoupling element should just be arrange | positioned around the area | region, design is easy and design time is shortened. The decoupling element arranged in the power supply main line reduces noise propagating from the outside to the inside or from the inside to the outside through the power supply main line.

  The invention according to claim 2 is the semiconductor integrated circuit device according to claim 1, wherein the power supply wiring is formed in a lattice shape.

  In the above configuration, a current flows from the power supply position toward the side of the region by the power supply wiring formed in a lattice shape.

  The invention according to claim 3 is the semiconductor integrated circuit device according to claim 1 or 2, wherein a plurality of the regions are provided.

  In the configuration described above, the semiconductor integrated circuit device is divided into a plurality of regions, and the position of the decoupling element is determined for each region, so that the design is made as compared with the case where the decoupling device is arranged for the entire semiconductor integrated circuit device. It is easy and can be processed in a short time. Further, by arranging the decoupling element around each region, noise mixed from adjacent regions can be reduced.

  In addition, it is desirable to further arrange a decoupling element at or near the power supply position. In addition, it is desirable to further dispose decoupling elements at or near the starting point of the power supply trunk line. Then, since the power supply to the region is by the power supply trunk line, it is possible to easily specify the position where the noise is generated by the power supply, and the noise is efficiently generated by arranging the decoupling element according to the position. Can be reduced.

  According to a fourth aspect of the present invention, in the semiconductor integrated circuit device according to any one of the first to third aspects, the power supply position is set substantially at the center of the region, and the decoupling element is The gist is that it is arranged in a region around the region.

  In the above configuration, the current from the operation power source supplied from substantially the center is the end point of the flow in the entire periphery of the region, and the IR drop is the largest at the end point. Therefore, the region in which the decoupling capacitor is arranged in the entire periphery of the region By setting as above, it is possible to easily and effectively take measures against IR drop. Further, by arranging the decoupling element around each region, noise mixed from adjacent regions can be reduced.

  According to a fifth aspect of the present invention, in the semiconductor integrated circuit device according to any one of the first to third aspects, the power supply position is set to a part of one side of the region, and the decoupling The gist of the ring element is that it is arranged on the other side except the one side.

  In the above configuration, the current supplied from the power supply position set to a part of one side flows toward the side excluding the one side. Therefore, those sides are the end points of the current, and the IR drop is the largest at the end point. Therefore, by setting the region where the decoupling capacitor is arranged around the entire region, measures against IR drop can be easily and efficiently performed. Can be done. In addition, by not setting a region in which the decoupling element is arranged on the side where the power supply position is set, it is possible to appropriately increase the number of elements by suppressing the increase in the number of elements.

  According to a sixth aspect of the present invention, in the semiconductor integrated circuit device according to any one of the first to third aspects, the power supply position extends along one first side of the region. And the decoupling element includes a second side facing the first side, and a third side and a fourth side sandwiched between the first side and the second side. The gist is that it is arranged in the portion on the side of 2.

In the above configuration, the current supplied from the power supply position set along the first side flows toward the second side opposite to the first side. Therefore, these sides are the end points of the current, and the IR drop is the largest at the end point. Therefore, by setting the region where the decoupling capacitor is arranged around the entire region, measures against IR drop can be easily and efficiently performed. Can be done. For the third and fourth sides sandwiched between the first and second sides, a region where the decoupling capacitor is arranged in a portion close to the second side, in other words, a portion away from the first side. By setting, it is possible to appropriately increase the number of elements by arranging the elements according to the effect.

  According to a seventh aspect of the present invention, there is provided a step of disposing a power supply trunk line that supplies operating power of the element to at least a part of a region where the element is formed, and a power supply position to which the operating power is supplied. A step of arranging power supply wiring so that a current flows toward the periphery, a step of setting a placement region around the region, and a decoupling element for the operating power supply in at least one of the placement region and the power supply trunk line And a step of performing the above.

  In the above configuration, with respect to the current flow by the operating power supply supplied to the elements in the region, the periphery of the region where the element is formed is the end point of the flow, and the decoupling element is arranged at the end point. Therefore, the influence of the dynamic IR drop of the operating power supply is efficiently improved by the decoupling element. And since a decoupling element should just be arrange | positioned around the area | region, design is easy and design time is shortened.

  Hereinafter, a first embodiment of the present invention will be described with reference to FIGS.

  FIG. 1 is a schematic configuration diagram of a semiconductor integrated circuit device (LSI).

  As shown in FIG. 1A, the LSI 10 includes a substrate 12 formed in a square shape, and cells as a plurality of elements are formed on the substrate 12. On the substrate 12, a plurality of power supply pads 14 for supplying operation power to the LSI 10 (cell) are formed around the substrate 12. The substrate 12 has a plurality of pads formed along the periphery, some of which are used as the power supply pads 14. Other pads are omitted in order to prevent the figure from becoming complicated.

  The LSI 10 includes a main power supply trunk line 16 and a sub power supply trunk line 18 that are connected to the power supply pad 14 and extend from the power supply pad 14 toward the inside of the LSI 10. The main power supply trunk line 16 and the sub power supply trunk line 18 are wired corresponding to the segment 20.

  In the segment 20, reinforcing power supply wirings 22 for supplying current from the main power supply trunk line 16 to the cells included in the segment 20 are formed. The reinforcing power supply wiring 22 is formed in a mesh shape.

  The segment 20 defines an area in which a plurality of cells constituting the LSI 10 are formed, and is set according to the power consumption of the LSI 10 when the LSI 10 is designed. The LSI 10 does not partition internal circuits. However, it can be determined by the arrangement positions of the main power supply trunk line 16 and the sub power supply trunk line 18 and the reinforcing power supply wiring 22.

  The main power supply trunk line 16 is formed to reach the inside of the corresponding segment 20 from the power supply pad 14, and the sub power supply trunk line 18 is formed to reach the inside of the corresponding segment 20 from the power supply pad 14. The main power supply trunk line 16 and the sub power supply trunk line 18 are arranged at positions corresponding to the peaks of the IR drop in each segment 20. The wiring widths of the main power supply trunk line 16 and the sub power supply trunk line 18 are determined based on the provisional IR drop value at the IR drop peak position.

  The peak position of the IR drop and the provisional IR drop value are based on the power supply analysis executed in the semiconductor design and the IR drop map created thereby. The segment 20 is set so that the voltage drop of the power supplied from the main power supply trunk line 16 is within a predetermined value. The position where the power supply current is supplied from the main power supply trunk line 16 and the sub power supply trunk line 18 to the internal circuit (the tip position in FIG. 1A) is called a power supply position (power supply point). As shown in FIG. 1B, the supplied current flows radially from the point B, which is the power supply position, to the periphery of the segment 20 via the reinforcing power supply wiring 22, and is supplied to each cell.

  Therefore, the power supply trunk lines 16 and 18 and the reinforcement power supply wiring 22 are configured so that the main power supply trunk line 16 or the sub power supply trunk line 18 is wired to each segment 20 and the reinforcement power supply wiring 22 is constructed in each segment 20 in the design of the LSI 10. In other words, the mesh-like reinforcing power supply wiring 22 is wired separately for each segment 20, thereby forming the segments 20 separated from each other in the LSI 10.

  As shown in FIG. 1C, the segment 20 includes an S point that is a start point of the main power supply trunk line 16 (which is a voltage supply source for the LSI 10 and in the vicinity of the power supply pad 14) and an end point thereof. A decoupling capacitor is arranged between point B (power supply position).

  The decoupling capacitor arranged in the power supply main line 16 (between the S point and the B point) has the following functions.

  (A) Noise as a dynamic power supply fluctuation propagating from the outside of the segment 20 toward the inside through the power supply wiring is reduced. Specifically, the noise propagated by a noise filter constituted by a decoupling capacitor is reduced, thereby improving the noise resistance (immunity) of the segment 20 against external noise.

  (B) Reduce static (stationary) IR drops.

  (C) Noise that propagates to the outside of the segment 20 through the power supply wiring due to dynamic power supply fluctuation in the segment 20 is reduced. Specifically, noise propagated by a noise filter constituted by a decoupling capacitor is reduced, and the influence of the noise on others (electromagnetic interference (EMI)) is reduced.

  In each segment 20, a decoupling capacitor is arranged in a surrounding arrangement region 40 (E region) (for example, point E). The reinforcing power supply wiring 22 is composed of a high potential side power supply wiring and a low potential side power supply wiring, and the decoupling capacitor is connected between the high potential side power supply wiring and the low potential side power supply wiring. A decoupling capacitor located in the E region effectively reduces dynamic IR drop. That is, the current supplied through the power supply trunk line 16 flows from the point B as the power supply position toward the periphery of the segment 20 as shown in FIG. Therefore, the periphery is the end point of the current flowing in the segment 20, and the IR drop is the largest at the end point. For this reason, by taking the periphery of the segment 20 as a region (E region) where a decoupling capacitor is disposed, measures against IR drop can be easily and efficiently performed.

  In each of the other segments 20, as in the segment 20 shown in FIGS. 1B and 1C, a decoupling capacitor is disposed between the S point and the B point and in each of the E regions. As described above, the position where the decoupling capacitor is disposed is not limited to the E region between the S point and the B point, and may be in the vicinity thereof, as long as it is effective in improving the IR drop and reducing the noise. . Therefore, between the S point and the B point, the E region includes the vicinity thereof.

  The high potential side power supply wiring and the low potential side power supply wiring are formed in parallel in different wiring layers or the same layer. Therefore, the current supplied from the power supply position is supplied toward the periphery of the segment 20 through the high potential side power supply wiring, and flows from the periphery to the power supply position via the low potential side power supply wiring. Accordingly, the direction of the current flowing from the power supply position toward the periphery of the segment is substantially opposite to the direction of the current flowing from the periphery of the segment toward the power supply position.

  FIG. 2 is an equivalent circuit diagram showing an outline of the segment 20.

  Each power supply trunk line 16, 18 includes a high potential side power supply line 30 and a low potential side power supply line 32, and the high potential side power supply line 30 is supplied with a high potential side voltage VDD, and the low potential side power supply line 32 is low. The potential side voltage VSS is supplied. Each cell 34 is connected between the high potential side power supply wiring 30 and the low potential side power supply wiring 32. Each cell 34 is equivalently represented as a current source through which current flows when it operates. The high-potential-side power supply wiring 30 and the low-potential-side power supply wiring 32 are equivalently represented as resistors R having resistance values between the connection points. Each resistor R has a resistance value determined by a length between connection points, a wiring width, and the like. A potential difference ΔV (i) (i = 0 to n) between both terminals of each resistor R is a voltage drop value due to IR drop.

  Between the high-potential-side power supply wiring 30 and the low-potential-side power supply wiring 32, there is an E region (an arrangement region 40 (see FIG. 1C) set around the segment 20, for example, the E point) at the IR region. A decoupling capacitor C0 as a countermeasure against dropping is connected. In addition, between the high potential side power supply wiring 30 and the low potential side power supply wiring 32, between the point S (the source of voltage supply to the LSI 10 and in the vicinity of the power supply pad 14) and the point B (power supply position). Are connected to decoupling capacitors C1 and C2 for EMI countermeasures.

  FIG. 2 is an equivalent representation of elements (power supply trunk line 16, power supply wiring 22, cell 32, decoupling capacitor) included in one segment, and does not limit the number or connection positions. Absent. For example, FIG. 2 illustrates one decoupling capacitor C0 to C2 respectively, but actually one or a plurality of decoupling capacitors are provided as necessary. The capacitors C0 to C2 are provided on a path for supplying operating power, and are displayed at various points for illustration. For example, the capacitors C1 and C2 are equivalent to those connected to the power supply trunk line 16, that is, one or more capacitors connected to the power supply wirings 30 and 32 from the point S to the point B in FIG. Is. Further, in FIG. 2, decoupling capacitors may be connected between the power supply wirings 30 and 32 from the point B to the E region, but these are common and are not shown. .

  By adopting the structure of the power supply wiring shown in FIG. 1, noise propagation due to EMI can be integrated in the power supply wiring between the S point and the B point within the segment range. Further, since the return path can be limited to a small amount with respect to the power supply current, the effective point between the S point and the B point can be automatically specified, and the decoupling capacitors C1, C2 can be specified at the specified point. EMI countermeasures can be efficiently implemented by inserting.

  Furthermore, as described above, the LSI 10 has a plurality of segments 20 that are separated from each other in power source. And in each segment 20, the decoupling capacitor is arrange | positioned in E area | region (E point) between S point and B point according to the supplied electric current. For this reason, noise reduction and improvement of IR drop are efficiently performed in each segment 20. In addition, a decoupling capacitor is arranged for each segment 20 having a small area, and a decoupling capacitor is arranged in the E region around each segment 20 as compared with the case where the arrangement of the decoupling capacitors is studied collectively for the entire LSI 10. By doing so, the capacity and arrangement of the decoupling capacitor can be easily determined with a short processing time.

  Next, a configuration example of the power supply wiring for the segment and setting of the corresponding arrangement area will be described.

  In the configuration example shown in FIG. 3A, the end point of the main power supply trunk line 16a is arranged at a substantially central portion of the segment 20a. This configuration example is configured in the same manner as the segment 20 shown in FIG. 1B, and as shown in FIG. 3B, from the power supply position (point B), which is the end point, toward the periphery. A current flows radially. Therefore, in this segment 20a, arrangement areas 40a are set along the four periphery of the segment 20a, and the decoupling capacitor C0 is arranged in the arrangement area 40a.

  In the configuration example shown in FIG. 4A, the end point of the main power supply trunk line 16b is arranged at a part (for example, substantially the center) of one side of the segment 20b. In this configuration example, the current supply position (point B) is moved to the periphery of the segment 20b as compared with the segment 20 shown in FIG. 3B. That is, as shown in FIG. A current flows in a fan shape from the supply position toward the other periphery. Therefore, for the side where the main power supply trunk line 16b is provided and a part of two adjacent sides, decoupling capacitors added to the main power supply trunk line 16b (decoupling provided at the S point and the B point). Dynamic IR drop is eliminated by the capacitors C1 and C2. For this reason, in this segment 20b, the arrangement area 40b is set along the three peripheries of the segment 20b at a predetermined distance from the power supply position, and the decoupling capacitor C0 is arranged in the arrangement area 40b. The predetermined distance corresponds to a distance at which the effect of improving dynamic IR drop by the decoupling capacitors C1 and C2 disposed between the S point and the B point cannot be obtained.

  In the configuration example shown in FIG. 5A, the end point of the main power supply trunk line 16c is arranged along one side of the segment 20c. In this configuration example, the current supply position (point B) extends along one side of the segment 20c as compared to the segment 20 shown in FIG. Therefore, the side where the main power supply trunk line 16c is provided and the portion (approximately half in FIG. 5A) at a predetermined distance from the main power supply trunk line 16c among the two adjacent sides are in relation to the main power supply trunk line 16c. The dynamic IR drop is eliminated by the decoupling capacitors (decoupling capacitors provided at the points S and B) C1 and C2. For this reason, in this segment 20c, the arrangement area 40c is set along the three peripheries of the segment 20c at a predetermined distance from the power supply position, and the decoupling capacitor C0 is arranged in the arrangement area 40c. The predetermined distance corresponds to a distance at which the effect of improving dynamic IR drop by the decoupling capacitors C1 and C2 arranged at the S point and the B point cannot be obtained.

  3 to 6, the regions 40 a to 40 c are illustrated outside the segments 20 a to 20 c in order to clarify the respective ranges with respect to the periphery of the segments 20 a to 20 c.

  Next, the design process of the semiconductor integrated circuit device will be described.

  FIG. 6 is a flowchart of the above design process. This design process is executed by the information processing apparatus 50 shown as an example in FIG.

  The information processing apparatus 50 is configured by connecting an input device 52, a display device 53, and storage devices 54, 55, 56 to a computer 51.

  The input device 52 includes a keyboard and a mouse device (not shown), and is used for a request or instruction from a user, input of parameters, and the like. The display device 53 includes a VDT, a monitor, and a printer, and is used for displaying a parameter input screen, a processing result, and the like.

The storage devices 54 to 56 usually include a magnetic disk device, an optical disk device, and a magneto-optical disk device, and these are used as appropriate according to the type and state of data stored in each of the storage devices 54 to 56. 7 shows the storage devices 54 to 56 functionally divided. The storage devices 54 to 56 may be stored in a state in which they are not divided or in a plurality of storage devices.

  The first storage device 54 stores program data for design processing. The program data may include other functions such as various display functions and data list display functions, and may include a plurality of program data. Further, the data necessary for executing the program may be specified via the input device 52 during the execution of the program.

  Program data is provided by a recording medium. As the recording medium, any computer-readable recording medium such as a memory card, a flexible disk, an optical disk (CD-ROM, DVD-ROM,...), A magneto-optical disk (MO, MD,...) Can be used. . Further, the program data may be loaded on the recording medium via the communication medium. The computer 51 drives a drive device (not shown), loads program data recorded on a recording medium into the storage device 54, and executes it. The program data recorded on the recording medium may be directly executed.

  The second storage device 55 stores an input file. The input file includes LSI 10 circuit data and specification data (such as the size of the board 12), library data necessary for design processing, and the like. The computer 51 executes the program (the flowchart shown in FIG. 6) in the storage device 54 in response to an instruction from the input device 52 and generates layout data for the LSI 10 based on the circuit data and the like. Then, the output file including the generated layout data is stored in the third storage device 56.

  First, the computer 51 sets the upper limit of the allowable IR drop value and the allowable current density of the wiring satisfying the EM constraint, and calculates the total amount of current flowing through the logic circuit unit by power analysis (step 61).

  Next, the computer 51 temporarily arranges each cell constituting the logic circuit unit, and constructs a virtual power mesh on the logic circuit unit (step 62). In this state, static IR drop analysis is performed to create an IR drop map (step 63). Note that the amount of current flowing through each cell varies with time depending on the operating state of the LSI, and the analysis result differs depending on the current amount at which time is used as a reference. For example, an average value is used.

  Next, when an IR drop exceeding the upper limit of the IR drop has occurred, the computer 51 grasps an area where the IR drop exceeds the upper limit, and determines the peak position of the IR drop, that is, the coordinates of the IR drop peak. Remember. Then, the segment is set so that the total value (total power consumption) of the power consumption of each minimum block near the IR drop peak stored in step 63 becomes a predetermined value (step 64).

  Next, the computer 51 performs IR drop analysis on each segment 20 described above, creates an IR drop map for each segment 20, and based on the IR drop map, the main power trunk 16 and the sub power trunk corresponding to each segment 20 18 and the reinforcing power supply wiring 22 are arranged (step 65).

  Next, the computer 51 sets an area 40 in which a decoupling capacitor is arranged for each segment based on the power supply trunk line (step 66), and decoupling elements (decoupling capacitors C0) are arranged at appropriate intervals in the area. Arrange (step 67).

  As described above, according to the present embodiment, the following effects can be obtained.

  (1) The LSI 10 is partitioned into a plurality of segments 20, and a region 40 in which a decoupling capacitor C 0 is disposed is set for each segment 20. In the segment 20, the operating power supplied to the segment 20 by the main power supply trunk line 16 or the sub power supply trunk line 18 flows from the power supply position toward the periphery of the segment 20. Therefore, by disposing the decoupling capacitor C0 in the vicinity thereof, it is possible to efficiently improve the IR drop by taking measures against the IR drop at the end point of the current from the operating power supply.

  (2) The decoupling capacitor C0 is arranged in the region 40 along the periphery of the segment 20. Therefore, noise propagated from the segment 20 where the decoupling capacitor C0 is disposed to the other segment 20 is reduced by the decoupling capacitor C0 inserted in the region 40. Further, noise mixed from the adjacent segment 20 is reduced by the decoupling capacitor C0 provided in the peripheral region 40. Therefore, noise propagating between the segments 20 can be efficiently reduced.

  (3) The LSI 10 is partitioned into a plurality of segments 20, and a region 40 in which the decoupling capacitor C0 is disposed is set for each segment 20. The segment 20 is supplied with operation power from the main power supply trunk line 16 or the sub power supply trunk line 18, and the operation power supply is not supplied to the cells of the other segments 20. That is, each segment 20 does not share power supply wiring. Further, it can be said that the cells of each segment 20 are separated from the cells of the other segments 20 in terms of power. For this reason, it is only necessary to model a noise source in a circuit unit constituted by cells included in each segment 20. Since the number of elements is small, the noise source can be easily modeled, and the time required for design is shortened. be able to.

  It should be noted that the time required to model the noise source for the cells of the entire LSI 10 is much longer than the total time required to model the noise sources individually for all the segments 20. Therefore, the method of the present embodiment, in which the noise source is modeled for each segment 20 of the entire LSI 10, can be processed in a very short time compared to the method of modeling the noise source in which all the cells are symmetric. It greatly contributes to shortening of time.

  Each of the above embodiments may be modified as follows.

  In the above embodiment, the decoupling capacitor C0 is disposed as the decoupling element. However, a noise filter may be inserted, and this can also reduce the influence applied to the element by IR drop or EMI.

In the above embodiment, the LSI 10 and the segments 20 (20a to 20c) constituting the LSI 10 are examples, and are not limited to the above configuration. Also,
In the above-described embodiment, the case where the decoupling capacitor C0 is arranged for the LSI 10 partitioned into a plurality of segments 20 has been described. However, the above technique may be applied to an LSI that is not partitioned into segments.

(A)-(c) is a schematic block diagram of a semiconductor integrated circuit device. Equivalent circuit diagram of power supply wiring. (A) and (b) are explanatory views showing a positional relationship between a configuration example of power supply wiring and a decoupling element. (A) and (b) are explanatory views showing a positional relationship between a configuration example of power supply wiring and a decoupling element. (A) and (b) are explanatory views showing a positional relationship between a configuration example of power supply wiring and a decoupling element. The flowchart of a design process. The schematic block diagram of a design processing apparatus.

Explanation of symbols

  16, 18 ... Power supply trunk line, 20 ... Segment as region, 22 ... Reinforced power supply wire as power supply wire, 40, 40a-40c ... Arrangement region, C0-C2 ... Decoupling capacitor.

Claims (7)

A power supply trunk line that supplies operating power to the element is provided in at least a part of a region where the element is formed, and power supply wiring is provided so that current flows from a power supply position to which the operating power is supplied toward the periphery of the region. In the formed semiconductor integrated circuit device,
A semiconductor integrated circuit device, wherein a decoupling element for the operation power supply is disposed in the periphery of the region and at least one of the power supply trunk line.   The semiconductor integrated circuit device according to claim 1, wherein the power supply wiring is formed in a lattice shape.   The semiconductor integrated circuit device according to claim 1, wherein a plurality of the regions are provided. The power supply position is set at approximately the center of the area,
The semiconductor integrated circuit device according to claim 1, wherein the decoupling element is disposed in a region around the region. The power supply position is set to a part of one side of the region,
The semiconductor integrated circuit device according to claim 1, wherein the decoupling element is disposed on another side excluding the one side. The power supply position is set to extend along one first side of the region;
The decoupling element includes a second side facing the first side, and the second side of the third side and the fourth side sandwiched between the first side and the second side. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is disposed in a portion on the side. Disposing a power supply trunk for supplying an operating power of the element to at least a part of a region where the element is formed;
Arranging power wiring so that current flows from the power supply position to which the operating power is supplied toward the periphery of the region;
Setting an arrangement area around the area;
Arranging a decoupling element for the operation power supply in at least one of the arrangement region and the power supply trunk line;
A method for designing a semiconductor integrated circuit device, comprising:

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