JP5456093B2 - Semiconductor integrated circuit and design method of semiconductor integrated circuit - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit and a design method thereof. In particular, the present invention relates to a power supply wiring structure of a semiconductor integrated circuit and a design method thereof.

  The power supply wiring of a semiconductor integrated circuit usually has a mesh-like wiring structure. The electric power supplied to the power supply pad is distributed to the mesh-like power supply wiring network through the I / O cells arranged on the outer periphery of the semiconductor chip. The cells in the semiconductor integrated circuit receive and consume current from the power supply wiring network. Since current is consumed at each point in the semiconductor integrated circuit, the potential drop (IR drop) in the power supply wiring network increases toward the center of the chip as shown in FIG. That is, the potential is high at the peripheral edge of the semiconductor integrated circuit, and the potential decreases toward the center of the chip.

  When the potential drop amount exceeds the allowable amount, the cell arranged at that point cannot exhibit its original performance. In particular, since the potential near the center of the chip is lowered, there is a possibility that a malfunction such as a decrease in operation speed may occur in a cell arranged near the center. A technique that can avoid such a malfunction due to potential drop is desired. Particularly in recent years, with the miniaturization of semiconductor integrated circuits, the power supply potential has become smaller, and the effect of potential drop has become prominent. Measures against potential drop are one of the most important issues.

  A semiconductor integrated circuit described in Patent Document 1 includes a first mesh power supply wiring that supplies a predetermined power to a first area, and a power supply that is the same as the predetermined power supply in a second area different from the first area. Second mesh power supply wiring for supplying The first mesh power supply wiring and the second mesh power supply wiring are separated at the boundary between the first region and the second region. The first region is located on the outer periphery of the chip, and power is directly supplied from the chip ring to the first mesh power supply wiring. On the other hand, the second region is located at the center of the chip, and power is supplied from the chip ring to the second mesh power supply wiring via the power supply wiring.

JP 2004-273844 A

  As described above, the potential drop may exceed the allowable amount depending on the region in the semiconductor integrated circuit. This leads to cell malfunction. Moreover, according to the technique described in Patent Document 1, a special wiring for supplying power to the second mesh power supply wiring is provided. Since it is necessary to allocate a wiring area to the special wiring, the wiring property is poor and the versatility is not provided.

  [Means for Solving the Problems] will be described below using the numbers and symbols used in [Mode for Carrying Out the Invention]. These numbers and symbols are added with parentheses in order to clarify the correspondence between the description of [Claims] and [Mode for Carrying Out the Invention]. However, these numbers and symbols should not be used for the interpretation of the technical scope of the invention described in [Claims].

  In a first aspect of the present invention, a method for designing a semiconductor integrated circuit is provided. The design method includes (A) a step of arranging the functional blocks (21, 22), (B) a step of determining the position of the power supply pad (2a), (C) a power supply pad (2a) and a functional block (21 , 22) and the step of arranging the power supply wiring structure (10). The step (C) includes (a) arranging a plurality of first power supply wirings (11) in the first wiring layer (M1), and (b) a plurality of first power supply wirings (11) and a plurality of intersections. Disposing a plurality of second power supply wirings (12) overlapping in (IS1, IS2) in a second wiring layer (M2) above the first wiring layer (M1); and (c) a plurality of first power wirings (12). Disposing vias (13) connecting the power supply wiring (11) and the plurality of second power supply wirings (12) at all of the plurality of intersections (IS1, IS2); and (d) functional blocks (21, 22). Analyzing the potential drop with respect to, and (e) deleting a portion of the via (13) on the current path (CP1) to the functional block (21) if the potential drop exceeds an allowable amount; including.

  Thus, according to the present invention, when the potential drop exceeds the allowable amount at a certain point, a part of the via on the current path to that point is deleted. As a result, the potential drop amount at that point is reduced. By sequentially removing vias from a region having a sufficient potential drop amount, the potential drop at that point can be kept within an allowable range. Therefore, the malfunction of the cell is eliminated. Further, according to the present invention, it is not necessary to provide a special wiring in order to alleviate the potential drop, and it is only necessary to delete some vias. Accordingly, the deterioration of the wiring property is prevented and the versatility is improved.

  In a second aspect of the present invention, a semiconductor integrated circuit is provided. The semiconductor integrated circuit includes a power supply pad (2a) disposed on the chip (1) and a circuit group (21, 22) connected to the power supply pad (2a) via the power supply wiring structure (10). . The power supply wiring structure (10) includes a plurality of first power supply wirings (11) and a plurality of second power supply wirings (12) which are formed in different wiring layers and overlap at a plurality of intersections (IS1, IS2). The first power supply wiring (11) and the via (13) connecting the plurality of second power supply wirings (12). The circuit group includes a functional block (21) arranged in the first region (R1). The via (13) is not disposed at a part of the plurality of intersections (IS2) in the second region (R2) between the first region (R1) and the power supply pad (2a).

  According to the present invention, it is possible to prevent cell malfunction caused by potential drop. Moreover, deterioration of wiring property is prevented. Furthermore, the present invention can be applied universally to any chip.

FIG. 1 is a diagram showing a potential drop distribution in a semiconductor chip. FIG. 2 is a schematic diagram showing a semiconductor chip according to an embodiment of the present invention. FIG. 3 is a schematic diagram showing a power supply wiring structure according to the embodiment of the present invention. FIG. 4 is a flowchart showing a design method according to the embodiment of the present invention. FIG. 5 is a plan view for explaining the design method according to the embodiment of the present invention. FIG. 6 is a cross-sectional view showing the structure of the semiconductor integrated circuit according to the embodiment of the present invention. FIG. 7 is a schematic diagram for explaining the effect of the present invention. FIG. 8 is a schematic diagram showing an example of a semiconductor chip to which the present invention is applied. FIG. 9 is a schematic view showing another example of a semiconductor chip to which the present invention is applied. FIG. 10 is a block diagram showing the configuration of the design system according to the embodiment of the present invention.

  A semiconductor integrated circuit and a design method thereof according to embodiments of the present invention will be described with reference to the accompanying drawings.

1. Design Object First, a schematic structure of a semiconductor integrated circuit that is a design object in the present embodiment will be described. FIG. 2 shows an overview of the semiconductor chip 1 according to the present embodiment. A plurality of pads 2 are arranged on the peripheral edge (outer peripheral part) of the semiconductor chip 1. The plurality of pads 2 include an input / output pad, a power supply pad, and a ground pad. The arrangement pattern of the plurality of pads 2 is not limited to that shown in FIG.

  A power supply wiring structure 10 as shown in FIG. 3 is formed in the semiconductor chip 1. The power supply wiring structure 10 connects a power supply pad and an internal circuit group, and is composed of the following wiring. In the first wiring layer, a plurality of first power supply wirings 11 are formed substantially in parallel along the Y direction. In the second wiring layer, which is an upper layer of the first wiring layer, a plurality of second power supply wirings 12 are formed substantially in parallel along the X direction. The X direction and the Y direction are orthogonal to each other. That is, the plurality of first power supply wires 11 and the plurality of second power supply wires 12 overlap each other at a plurality of intersections. In other words, the plurality of first power supply wires 11 and the plurality of second power supply wires 12 are arranged in a “mesh shape”. A via 13 is arranged at a part of the plurality of intersections so as to connect the plurality of first power supply lines 11 and the plurality of second power supply lines 12. A mesh wiring 14 is formed by the first power supply wiring 11 and the second power supply wirings 12 and 13.

  Further, a ring wiring 15 having a ring shape is provided on the peripheral edge (outer peripheral part) of the semiconductor chip. The ring wiring 15 is a main power supply wiring for supplying power to the mesh wiring 14 and is provided so as to surround the mesh wiring 14. Of the plurality of pads 2 described above, the power supply pad (2a) is connected to the ring wiring 15 via an I / O cell including a buffer. The power supplied to the power supply pad (2a) is supplied to the ring wiring 15 through the I / O cell. The electric power supplied to the ring wiring 15 is distributed to the circuit group (cell group) of the semiconductor integrated circuit through the mesh mesh wiring 14.

  The power supply wiring structure 10 is not limited to the structure shown in FIG. 3, and may be composed of three or more wiring layers. In the multilayer wiring layer structure, generally, the resistance of the lower layer power supply wiring (local wiring) is larger than the resistance of the upper layer power supply wiring (global wiring). In FIG. 3, the resistance of the first power supply wiring 11 formed in the first wiring layer is larger than the resistance of the second power supply wiring 12 formed in the second wiring layer. For example, the width of the second power supply wiring 12 is designed to be larger than the width of the first power supply wiring 11. For example, the film thickness of the second power supply wiring 12 is larger than the film thickness of the first power supply wiring 11.

2. Design Method Next, a method for designing a semiconductor integrated circuit according to the present embodiment will be described with reference to the flowchart shown in FIG.

  First, functional blocks are arranged at predetermined locations in the layout area corresponding to the semiconductor chip 1 (step S10). Next, the position of the power pad (power supply point) is determined (step S20). For example, as shown in FIG. 2, the position of the power supply pad is set at the periphery of the semiconductor chip 1. Here, the balance of the power supply pads is determined according to the distribution of power consumption in the chip. Next, the power supply wiring structure 10 for connecting the power supply pad and the functional block is disposed (step S30). The power supply wiring structure 10 has a structure as shown in FIG. Hereinafter, this step S30 will be described in more detail with reference to the plan view shown in FIG. 5 and the cross-sectional view shown in FIG.

  First, a plurality of first power supply wires 11 are arranged in the Y direction in the first wiring layer M1. In addition, a plurality of second power supply wires 12 are arranged along the X direction in the second wiring layer M2 above the first wiring layer M1 (step S31). As a result, the plurality of first power supply wires 11 and the plurality of second power supply wires 12 overlap each other at a plurality of intersections IS. As will be described later, the plurality of intersections IS are classified into a first intersection IS1 where the via 13 is provided and a second intersection IS2 where the via 13 is not provided.

  Next, vias 13 are arranged for connecting the plurality of first power supply lines 11 and the plurality of second power supply lines 12 to each other. At this stage, the vias 13 are arranged at all the above-mentioned intersections IS (IS1, IS2) (step S32). In this way, the preliminary power supply wiring structure 10 is temporarily formed.

  Next, the potential drop (IR drop) is analyzed for the preliminary power supply wiring structure 10 (step S33). That is, potential drop analysis is performed on each of the arranged functional blocks. Through this analysis, a region (functional block) in which the potential drop exceeds a predetermined allowable amount is searched.

  For example, with reference to FIGS. 5 and 6, it is assumed that the first functional block 21 is arranged in the first region R <b> 1 in the semiconductor chip 1. In addition, it is assumed that the second functional block 22 is arranged in the second region R2. The second region R2 is located between the power supply pad 2a (chip peripheral portion) and the first region R1. That is, the second region R2 is closer to the power supply pad 2a than the first region R1, and the potential drop in the second region R2 is smaller than the potential drop in the first region R1.

  As a result of the potential drop analysis, it is assumed that the potential drop in the second region R2 satisfies the potential drop allowable amount related to the second functional block 22. On the other hand, it is assumed that the potential drop in the first region R1 exceeds the potential drop allowable amount related to the first function block 21 (step S34; No). In this case, analysis of the current path to the first functional block 21 is performed.

  Referring to FIGS. 5 and 6, of the four sides of the semiconductor chip 1, the side closest to the first region R1 is the side Sa. Therefore, the power supply to the first functional block 21 is mainly performed via the first current path CP1 from the power supply pad 2a on the side Sa side. According to the present embodiment, a part of the vias 13 is deleted from a region having a margin for potential drop at least on the first current path CP1 (step S36). For example, the second region R2 described above is located between the power supply pad 2a and the first region R1, and the current path CP1 to the first functional block 21 passes through the second region R2. In addition, the potential drop in the second region R2 satisfies an allowable amount. Therefore, the via 13 is preferably deleted from a part of the intersection in the second region R2. In this case, the intersection IS2 where the via 13 is not disposed is provided in the second region R2, and the current path CP2 to the second functional block 22 is partially blocked.

  The effect of omitting the via 13 will be described with reference to FIG. FIG. 7 schematically shows the first power supply wiring 11 and the second power supply wiring 12 in a certain section. As the first power supply wiring 11 and the second power supply wiring 12 intersect, intersections P1 to P4 appear. In FIG. 7, the mesh wiring 14 in a part of the region is cut out and shown, and the first power supply wiring 11 in FIG. 7 is also connected to the second power supply wiring 12 outside the region, The second power supply wiring 12 in FIG. 7 is also connected to the first power supply wiring 11 outside the region. Here, only the shortest current path from the current supply point is considered.

  In FIG. 7, it is assumed that the power consumption is uniform across all regions. The intervals of the intersections P1 to P4 are equal, and the resistance of the second power supply wiring 12 at each interval (current supply points to P1, P1 to P2, P2 to P3, P3 to P4) is given by “R”. And Further, when the via 13 is not deleted, it is assumed that an equal current “I” flows into the via 13 provided at each of the intersections P1 to P4.

  When the via 13 is not deleted, the current gradually decreases from the intersection P1 toward P4. The potential drop amount at the intersection P4 is given by “(4I + 3I + 2I + I) × R = 10 × IR”.

  On the other hand, when some of the vias 13 are deleted, for example, when the vias 13 are deleted from the intersections P2 and P3, the current is concentrated at the intersections P1 and P4. For example, it is assumed that a current 2.5I flows into the via 13 at the intersection P1, and a current 1.5I flows into the via 13 at the intersection P4. In this case, the potential drop amount at the intersection P4 is “4I + 1.5I + 1.5I + 1.5I) × R = 8.5 × IR”, which is smaller than the case where the via 13 is not deleted.

  In this way, by partially omitting the via 13, it is possible to reduce the potential drop amount ahead. In other words, it is possible to increase the potential at a location far from the current supply source. As described above, the upper second power supply wiring 12 has a smaller resistance than the lower first power supply wiring 11. By deleting the via 13 on the current path CP1, the low-resistance second power supply wiring 12 can be used as a main wiring path to the first functional block 21. Thereby, the potential drop related to the first functional block 21 can be alleviated. In order to effectively suppress the potential drop, as shown in FIG. 5, a part of the current path CP1 between the first region R1 and the side Sa closest to the first region R1 It is preferred that the via 13 is omitted.

  As described above, the via 13 is partially deleted from the second region R2 in step S36. Thereafter, the potential drop analysis is executed again (step S33). As a result of the analysis, if the potential drop still exceeds the allowable amount (step S34; No), the via 13 is further deleted from the second region R2 (step S36). Thus, steps S33 to S36 are repeatedly performed. For each step S36, the vias 13 may be deleted one by one or may be deleted for each group. The via 13 is deleted so that the current path CP2 to the second functional block 22 does not disappear.

  The iterative process may be performed until the potential drop satisfies an allowable amount. Alternatively, after the repetition process is performed a predetermined number of times, when the potential drop still exceeds the allowable amount (step S35; Yes), the design process may return to step S20. In this case, the position of the power pad (power supply point) is changed. Subsequently, step S31 is skipped, and the vias 13 are disposed again at all intersections (step S32). Thereafter, similarly, steps S33 to S36 are repeatedly performed. If the potential drop satisfies the allowable amount over the entire semiconductor chip 1 (step S34; Yes), the process ends.

  As described above, according to the present embodiment, the potential drop in the first region R1 can be kept within the allowable range by sequentially deleting the vias 13 from the region having a sufficient potential drop amount. It becomes possible. Therefore, malfunction of the first functional block 21 is prevented. Furthermore, according to the present embodiment, it is not necessary to provide a special wiring in order to alleviate the potential drop, and it is only necessary to delete some vias 13. Since it is not necessary to allocate a part of the wiring area to the special wiring, deterioration of the wiring property is prevented. Further, since no special wiring is required, the present invention can be applied to any chip for general purposes.

3. Application example 3-1. First Application Example FIG. 8 schematically shows a semiconductor chip 1 in a first application example. In FIG. 8, the first functional block 21 is arranged at the center of the semiconductor chip 1. That is, the first region R <b> 1 in which the first functional block 21 is disposed includes the central portion of the semiconductor chip 1. The power supply pad is provided on the outer peripheral portion of the semiconductor chip 1, that is, power is supplied to the internal circuit from the peripheral portion of the semiconductor chip 1. Therefore, the amount of potential drop increases toward the center of the semiconductor chip 1. If the present invention is not applied, it is assumed that the potential drop in the first region R1 exceeds the allowable amount PE.

  Therefore, some vias 13 are omitted from the second region R2 located between the first region R1 (center portion) and the peripheral portion of the semiconductor chip 1. For example, as shown in FIG. 8, the second region R2 includes four strip regions Ra to Rd surrounding the first region R1, and some vias 13 are omitted from each of the strip regions Ra to Rd. It is burned. The strip regions Ra and Rc are regions extending from the end of the first region R1 toward the sides Sa and Sc along the X direction. On the other hand, the strip regions Rb and Rd are regions extending from the end of the first region R1 toward the sides Sb and Sd along the Y direction. That is, the strip regions Ra to Rd are arranged in a cross shape. A part of the intersection IS included in the belt-like regions Ra to Rd becomes an intersection IS2 where the via 13 is not arranged. The arrangement of the intersection IS2 can be determined as appropriate in each of the strip regions Ra to Rd. For example, in each strip region, the intersection IS2 is arranged for each predetermined number of power supply lines.

  As a result, as shown in FIG. 8, the potential drop amount increases in a region (second region R2) with a margin for potential drop, and instead, the potential drop amount in the first region R1 decreases. By appropriately providing the intersection IS2, the potential drop satisfies the allowable amount PE over the entire semiconductor chip 1. As a result, the performance of all the internal circuits including the first functional block 21 is prevented from being deteriorated.

3-2. Second Application Example The worst point of potential drop is not limited to the central portion of the semiconductor chip 1. For example, a functional block that performs high-speed operation has a high power density, and a potential drop tends to increase in a region where the functional block is arranged. If the potential drop exceeds the allowable amount, the operation speed of the functional block that should perform high-speed operation decreases. In other words, the potential drop increases in the region where the speed is desired to be increased, and conversely, it is easily affected by the speed deterioration.

  The second application example is a case where a functional block that performs such a high-speed operation is relieved. FIG. 9 schematically shows the semiconductor chip 1 in the second application example. In FIG. 9, a first functional block 21 that performs high-speed operation is arranged in a first region R <b> 1 in the semiconductor chip 1. For example, the first functional block 21 is a CPU core. If the present invention is not applied, it is assumed that the potential drop in the first region R1 exceeds the allowable amount PE.

  Therefore, some vias 13 are omitted from the second region R2 located between the first region R1 and the power supply pad 2a. The second function block 22 is arranged in the second region R2 (see FIG. 6), and there is a margin in the potential drop related to the second function block 22. That is, the power density of the first functional block 21 is higher than the power density of the second functional block 22. In other words, the power consumption per unit area of the first functional block 21 is larger than that of the second functional block 22. In other words, the operation speed of the first function block 21 is higher than the operation speed of the second function block.

  Similar to the first application example, the second region R2 may include four belt-like regions Ra to Rd surrounding the first region R1. Some of the vias 13 are omitted from each of the belt-like regions Ra to Rd, and an intersection IS2 where no vias 13 are arranged is provided. As a result, as shown in FIG. 9, the potential drop amount increases in a region (second region R2) with a margin for potential drop, and instead, the potential drop amount in the first region R1 decreases. By appropriately providing the intersection IS2, the potential drop satisfies the allowable amount PE over the entire semiconductor chip 1. As a result, the performance of all the internal circuits including the first functional block 21 is prevented from being deteriorated.

4). Design system (CAD system)
FIG. 10 is a block diagram showing an example of a design system 100 for realizing the design technique (layout technique) according to the present invention. The design system 100 is constructed by a computer such as a workstation, and includes an arithmetic processing device 110, a storage device 120, an input device 140, and a display device 150.

  Examples of the storage device 120 include a RAM and a hard disk. The storage device 120 stores a net list 121, IP macro data 122, layout data 123, and the like. The netlist 121 describes circuit connection relationships and is used for layout processing. The IP macro data 122 provides the functional blocks described above. The layout data 123 indicates a circuit layout and is generated by layout processing.

  Examples of the input device 140 include a keyboard and a mouse. The designer can input various data and commands using the input device 140 while referring to the information displayed on the display device 150.

  The arithmetic processing unit 110 executes the design program 130. The design program 130 is recorded on a computer-readable recording medium, for example. The design program 130 provides a design function (layout function) according to the present invention in cooperation with the arithmetic processing unit 110. In the layout process, the net list 121 and the IP macro data 122 are used. As a result of the layout process, layout data 123 including the pattern of the power supply wiring structure 10 described above is created. Based on the layout data 123, the semiconductor integrated circuit according to the present embodiment is manufactured.

DESCRIPTION OF SYMBOLS 1 Chip 2 Pad 2a Power supply pad 10 Power supply wiring structure 11 1st power supply wiring 12 2nd power supply wiring 13 Via 14 Mesh wiring 15 Ring wiring 21 1st functional block 22 2nd functional block 100 Design system 110 Arithmetic processing device 120 Storage device 121 Netlist 122 IP macro data 123 Layout data 130 Design program 140 Input device 150 Display device CP1 First current path CP2 Second current path IS1 First intersection IS2 Second intersection

Claims (6)

A power pad disposed on the periphery of the chip;
Power wiring structure,
And a circuit connected group to said power supply pads through the power wiring structure,
The circuit group includes a plurality of functional blocks arranged in a plurality of areas including a first functional block arranged in the first area and a second functional block arranged in the second area,
The second region is located between the first region and the side of the chip closest to the first region;
The power supply wiring structure is
A plurality of first power supply lines formed in the first wiring layer above the circuit group so as to extend in the first direction;
A plurality of second power supply wirings formed in the second wiring layer above the first wiring layer so as to extend in a second direction orthogonal to the first direction , wherein the plurality of first power supply wirings; The plurality of second power supply wires intersect at a plurality of intersections in a top view,
Of the plurality of intersections, each of the connection intersections other than the selected intersection has a via provided to connect the associated first power supply wiring and the second power supply wiring ;
As a result of the analysis of the potential drop from the power supply pad in each unit of the plurality of regions, the potential drop in the first region exceeds a predetermined allowable value, and the potential drop in the second region is A semiconductor integrated circuit in which the via is removed at the selected intersection in the second region so that the potential drop in the first region satisfies the predetermined tolerance when the predetermined tolerance is satisfied. . The semiconductor integrated circuit according to claim 1,
The second region is a semiconductor integrated circuit is a band-like region extending toward the side of the chip along the first direction or the second direction from an end portion of the first region. The semiconductor integrated circuit according to claim 1, wherein
The first region includes a central portion of the chip. The semiconductor integrated circuit according to claim 1, wherein
The power consumption per unit area of the first functional block is larger than that of the second functional block. Semiconductor integrated circuit. The semiconductor integrated circuit according to claim 1, wherein
The operation speed of the first functional block is higher than that of the second functional block. Semiconductor integrated circuit. A semiconductor integrated circuit according to any one of claims 1 to 5,
A resistance of each of the plurality of second power supply wirings is smaller than a resistance of each of the plurality of first power supply wirings.

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