JP2005312235A - Power converter - Google Patents

Abstract

An object of the present invention is to provide a power converter capable of accurately detecting an abnormality when the abnormality occurs in the power converter.
A control unit that outputs a gate command for turning on or off a semiconductor element;
A first gate drive that controls a semiconductor element based on a gate command and outputs a gate feedback signal, a second gate drive that controls the semiconductor element based on a gate command and outputs a gate feedback signal, and outputs to the gate drive Failure detection mismatch detection unit that takes the logic of the gate command and the gate feedback signal output from the gate drive, and failure detection short-circuit detection unit that takes the logic of the gate feedback signals, and which semiconductor element and gate drive fail The power converter characterized by guessing whether it was done.
[Selection] Figure 1

Description

The present invention relates to failure detection of a power converter.

As a conventional failure detection method for a power conversion device, as described in Japanese Patent Application Laid-Open No. 07-95761, the logic between gate commands given from a control unit to a plurality of gate drives and the operation state of a semiconductor element are represented. There has been known a method of determining a failure when both semiconductor elements are turned on from the logic of the gate feedback signals.
JP 07-95761 A

As a cause of the failure of the railway vehicle power converter, there are more abnormalities in the semiconductor element than the failure of the control unit. However, in the conventional power conversion device, when a semiconductor element abnormality occurs, it can be determined whether the gate signal side or the feedback signal side is abnormal,
It was not possible to determine which semiconductor element was abnormal.

Therefore, the failure records before and after the semiconductor element abnormality are examined, and it is inferred which semiconductor element is abnormal,
Since the inspection was started after that, it was one of the causes of the long working time.

Then, the objective of this invention is providing the power converter device which can detect abnormality correctly when abnormality generate | occur | produces in a power converter device.

In the two-level inverter mounted on the railway vehicle, the above-described problem is a control unit that outputs a gate command for turning on or off the semiconductor element, and controls the semiconductor element based on the gate command output from the control unit. A first gate drive for outputting a feedback signal; a second gate drive for controlling a semiconductor element based on a gate command output from the control unit; and outputting a gate feedback signal; and the first from the control unit. A first failure determination mismatch detection unit that takes the logic of a gate command output to the gate drive and a gate feedback signal output from the first gate drive, and output from the control unit to the second gate drive Gate command and gate output from the second gate drive A second failure determination mismatch detection unit that takes the logic of the feedback signal; and a failure determination short-circuit detection unit that takes the logic of the gate feedback signal output from the first gate drive and the second gate drive. Can be achieved.

In the three-level inverter mounted on the railway vehicle, the above-described problem is a control unit that outputs a gate command for turning on or off the semiconductor device, and controls the semiconductor device based on the gate command output from the control unit, A first gate drive for outputting a feedback signal; a second gate drive for controlling a semiconductor element based on a gate command output from the control unit; and outputting a gate feedback signal; and a gate output from the control unit A third gate drive for controlling the semiconductor element based on the command and outputting a gate feedback signal; and a fourth gate drive for controlling the semiconductor element based on the gate command output from the control unit and outputting a gate feedback signal. And from the control unit to the first game A first failure determination mismatch detection unit that takes a logic of a gate command output to the drive and a gate feedback signal output from the first gate drive; and a gate output from the control unit to the first gate drive Command and the first
A second failure determination / mismatch detection unit that takes the logic of the gate feedback signal output from the gate drive, and a gate command output from the control unit to the first gate drive and the first gate drive. A third failure determination mismatch detection unit that takes the logic of the gate feedback signal, a gate command output from the control unit to the second gate drive, and a logic of the gate feedback signal output from the second gate drive And a logic of gate feedback signals output from the first gate drive, the second gate drive, the third gate drive, and the fourth gate drive. This can be achieved by providing a failure determination short-circuit detection unit.

In the power conversion apparatus mounted on a railway vehicle, the above-described problem is a control unit that outputs a gate command for turning on or off the semiconductor element, and controls the semiconductor element based on the gate command output from the control unit, A gate drive that outputs a feedback signal, a gate command output from the control unit, a failure determination mismatch detection unit that takes a logic of a gate feedback signal corresponding to the gate command, and a gate feedback signal output from the gate drive This can be achieved by providing a failure determination short-circuit detection unit that takes logic.

In the power conversion apparatus mounted on a railway vehicle, the above-described problem is a control unit that outputs a gate command for turning on or off the semiconductor element, and controls the semiconductor element based on the gate command output from the control unit, This can be achieved by including a gate drive that outputs a feedback signal, a gate command output from the control unit, and a failure determination mismatch detection unit that takes the logic of the gate feedback signal corresponding to the gate command.

According to the present invention, it is possible to provide a power conversion device capable of accurately detecting an abnormality when an abnormality occurs in the power conversion device.

(First embodiment)
A power converter according to a first embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of a power conversion device according to a first embodiment of the present invention. FIG.
It is a block diagram of the failure discrimination | determination mismatch detection part of 1st Embodiment based on this invention. FIG. 3 is a configuration diagram of the short-circuit detection unit according to the first embodiment based on the present invention.

In the power conversion device according to the first embodiment of the present invention, the control unit 1 sends a gate command for turning on / off the semiconductor element to the gate drive 2 via the first transmission line 5 to detect failure discrimination mismatch. Transmit to unit 4. The gate drive 2 controls the semiconductor element 3 based on the gate command transmitted from the control unit 1, and sends a gate feedback signal representing the state of the semiconductor element 3 through the second transmission path 6 to the failure determination short circuit. Input to the detection unit 7 and the failure determination mismatch detection unit 4.

In the power conversion device configured as described above, in order to detect a failure, the failure determination mismatch detection unit 4A, which is the first failure determination mismatch detection unit, transmits the gate transmitted from the control unit 1 to the first gate drive 2A. The command and the gate feedback signal from the gate drive 2A are compared, and if the signals do not match, a failure is determined. The failure determination mismatch detection unit 4B which is the second failure determination mismatch detection unit is similar to the failure determination mismatch detection 4A in the control unit 1.
The gate command 5B transmitted to the second gate drive 2B is compared with the gate feedback signal 6B, and the same determination is made. The failure determination short-circuit detection 7 determines that a failure has occurred when both the gate feedback signal from the gate drive 2A and the gate feedback signal from the gate drive 2B are ON. When the failure determination mismatch detection 4a detects a failure, 1 is set as a failure flag. If the failure determination mismatch detection 4b detects a failure,
Set failure flag 2. The display method of the failure flag is not particularly limited.

In the power conversion device configured as described above, the failure determination mismatch detection unit 4 includes an XOR unit 8 that ORs the input gate command and the gate feedback signal, as shown in FIG.
The ONTD unit 9 is configured to output a mismatch detection signal when an abnormal signal output from the XOR unit 9 continues for a predetermined time or longer.

In the power conversion device configured as described above, the short-circuit detection unit 7 has an AND unit 10 that takes an AND between input gate feedback signals, and an abnormal signal output from the AND unit 10 continues for a certain period of time. It consists of ONTD8 part which outputs a short circuit detection signal.

In the power conversion device configured as described above, when the failure determination mismatch detection 4a detects an abnormality and only the failure flag 1 is set, the semiconductor element 3a and the gate drive 2a are expected to fail. You can start work such as measurement. Failure discrimination mismatch detection 4
When b detects an abnormality and only the failure flag 2 is set, a failure of the semiconductor element 3b and the gate drive 2b is expected. Further, when both the failure flag 1 and the failure flag 2 are set, the possibility of failure of the control unit 1 is high.

The power conversion device configured as described above can estimate a portion having a high possibility of failure depending on how the failure flag is set, and therefore can efficiently work at the time of failure. Also,
Since the logic of the gate command and the gate feedback is taken and the logic of the gate feedback is also taken, it is possible to provide a power conversion device capable of accurately detecting an abnormality.

(Second Embodiment)
A power converter according to a second embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 4 is a block diagram of a power conversion apparatus according to the second embodiment of the present invention. In addition, FIG.
Throughout, the same structural elements as those shown in FIG.

The power conversion device according to the second embodiment of the present invention is characterized in that the present invention is applied to a three-level inverter. Therefore, the first to fourth failure discrimination mismatch detection units 4 are (4
a, 4b, 4c, 4d).

In the power conversion device configured as described above, when the failure determination mismatch detection unit 4a detects an abnormality, 1 is set as the failure flag. In the case of the failure discrimination mismatch detection unit 4b, 2
In the case of the failure discrimination mismatch detection unit 4c, 3 is set, and in the case of the failure discrimination mismatch detection unit 4d, a failure flag of 4 is set. From this failure flag, it is possible to estimate the failure site.

The power conversion device configured as described above can estimate a portion having a high possibility of failure depending on how the failure flag is set, and therefore can efficiently work at the time of failure. Moreover, since the logic of gate command and gate feedback is taken and the logic of gate feedback is also taken, the power converter device which can detect abnormality correctly can be provided.

(Third embodiment)
A power converter according to a third embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 5 is a block diagram of a power conversion device according to a third embodiment of the present invention. In addition, FIG.
Throughout, the same structural elements as those described in FIG.

A power conversion device according to a third embodiment of the present invention includes a control unit 1 that outputs a gate command for turning on or off a semiconductor element, and a semiconductor device 3 based on the gate command output from the control unit 1. Gate drive 2 that controls and outputs a gate feedback signal
And a failure determination / mismatch detection unit 4 that takes a logic of a gate command output from the control unit and a gate feedback signal corresponding to the gate command, and detects a failure of the semiconductor element 3.

The power conversion device configured as described above determines that the semiconductor element 3a has failed when the failure determination mismatch detection unit 4a detects a failure, and the failure determination mismatch detection unit 4b detects a failure. Determines that the semiconductor element 3b has failed.

Since the power conversion device configured as described above can detect which semiconductor element has failed, an efficient operation can be performed at the time of the failure.

The power conversion device configured as described above can be made smaller than the power conversion devices of the first and second embodiments.

It is a block diagram of the power converter device of a 1st embodiment based on the present invention. It is a block diagram of the failure discrimination | determination mismatch detection part of 1st Embodiment based on this invention. It is a block diagram of the short circuit detection part of 1st Embodiment based on this invention. It is a block diagram of the power converter device of 2nd Embodiment based on this invention. It is a block diagram of the power converter device of 3rd Embodiment based on this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Control unit 2 Gate drive 3 Semiconductor element 4 Failure determination mismatch detection part 5 1st transmission path 6 2nd transmission path 7 Failure determination short circuit detection part 8 XOR part 9 ONTD part 10 AND part

Claims (4)

In a two-level inverter mounted on a railway vehicle,
A control unit for outputting a gate command for turning on or off the semiconductor element;
A first gate drive that controls a semiconductor element based on a gate command output from the control unit and outputs a gate feedback signal;
A second gate drive that controls the semiconductor element based on the gate command output from the control unit and outputs a gate feedback signal;
A first failure determination mismatch detection unit that takes a logic of a gate command output from the control unit to the first gate drive and a gate feedback signal output from the first gate drive;
A second failure determination mismatch detection unit that takes the logic of a gate command output from the control unit to the second gate drive and a gate feedback signal output from the second gate drive;
A power converter comprising a failure determination short-circuit detection unit that takes a logic of a gate feedback signal output from the first gate drive and the second gate drive. In a three-level inverter mounted on a railway vehicle,
A control unit that outputs a gate command for turning on or off the semiconductor element; and
A first gate drive that controls a semiconductor element based on a gate command output from the control unit and outputs a gate feedback signal;
A second gate drive that controls a semiconductor element based on a gate command output from the control unit and outputs a gate feedback signal;
A third gate drive that controls a semiconductor element based on a gate command output from the control unit and outputs a gate feedback signal;
A fourth gate drive that controls the semiconductor element based on the gate command output from the control unit and outputs a gate feedback signal;
A first failure determination mismatch detection unit that takes a logic of a gate command output from the control unit to the first gate drive and a gate feedback signal output from the first gate drive;
A second failure determination mismatch detection unit that takes a logic of a gate command output from the control unit to the first gate drive and a gate feedback signal output from the first gate drive;
A third failure determination mismatch detection unit that takes a logic of a gate command output from the control unit to the first gate drive and a gate feedback signal output from the first gate drive;
A fourth failure determination mismatch detection unit that takes the logic of a gate command output from the control unit to the second gate drive and a gate feedback signal output from the second gate drive;
A failure determination short-circuit detection unit that takes a logic of a gate feedback signal output from the first gate drive, the second gate drive, the third gate drive, and the fourth gate drive is provided. Power conversion device. In power converters mounted on railway vehicles,
A control unit for outputting a gate command for turning on or off the semiconductor element;
A gate drive that controls a semiconductor element based on a gate command output from the control unit and outputs a gate feedback signal;
A failure determination mismatch detection unit that takes a logic of a gate command output from the control unit and a gate feedback signal corresponding to the gate command;
A power conversion device comprising a failure determination short-circuit detection unit that takes a logic of a gate feedback signal output from the gate drive. In power converters mounted on railway vehicles,
A control unit for outputting a gate command for turning on or off the semiconductor element;
A gate drive that controls a semiconductor element based on a gate command output from the control unit and outputs a gate feedback signal;
A power conversion device comprising: a gate command output from the control unit; and a failure determination mismatch detection unit that takes a logic of a gate feedback signal corresponding to the gate command.

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