JP2005310303A - Semiconductor memory device and its test method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device and its test method capable of simplifying the stress test. <P>SOLUTION: The flash memory 10 has a memory cell MC which includes a 1st MOS transistor MT having a charge storage layer and a control gate, bit lines to which an end of the current path of the 1st MOS transistors MT is electrically connected, write circuits 101 provided corresponding to the bit lines and holding the data to write, an inhibit voltage supply circuit 140 to generate a writing inhibit voltage Vinhibit when writing and to generate a stress voltage Vstress at the time of stress test, and control circuits 80, 150 to control the inhibit voltage supply circuit 140 to apply a writing inhibit voltage Vinhibit to the bit lines with all the connected memory cells not selected to write at the time of writing, and to control to apply a stress voltage Vstress to the bit lines at the time of the stress test. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor memory device and a test method thereof. For example, the present invention relates to a nonvolatile semiconductor memory device including a MOS transistor having a floating gate and a control gate.

  Conventionally, NOR flash memories and NAND flash memories are known and widely used as nonvolatile semiconductor memories.

  In recent years, there has been proposed a flash memory that combines the advantages of both a NOR flash memory and a NAND flash memory (see, for example, Non-Patent Document 1). This flash memory includes a memory cell including two MOS transistors (hereinafter referred to as a 2Tr flash memory). In such a memory cell, one MOS transistor functioning as a nonvolatile memory portion has a structure including a control gate and a floating gate, and is connected to a bit line. The other MOS transistor is connected to the source line and is used for selecting a memory cell.

  Further, in the flash memory, the memory cell is subjected to some stress not only when the target memory cell is operated but also when not operating. Therefore, it is necessary to conduct a resistance test against this stress. In this case, a method of performing a stress test on a plurality of memory cells at once has been proposed (see, for example, Patent Document 1).

However, the method described in Patent Document 1 has a problem that many circuits are required for the test and the circuit area increases. Furthermore, it is difficult to apply the method described in Patent Document 1 to a 2Tr flash memory as it is, and the 2Tr flash memory has a problem that it takes time for a stress test.
Wei-Hua Liu, “A 2-Transistor Source-select (2TS) Flash EEPROM for 1.8V-Only Application”, Non-Volatile Semiconductor Memory Workshop 4.1, 1997 JP-A-3-272100

  An object of the present invention is to provide a semiconductor memory device and a test method thereof that can simplify a stress test.

  A semiconductor memory device according to a first aspect of the present invention includes a plurality of memories including a first MOS transistor including a charge storage layer and a control gate, and writing data by transferring electrons to the charge storage layer by FN tunneling. A cell, a plurality of bit lines each connected to one end of a current path of each of the plurality of first MOS transistors, and a write that is provided corresponding to the bit line and holds write data to the memory cell A circuit, a forbidden voltage supply circuit that generates a write inhibit voltage during a write operation and generates a stress voltage during a stress test of the memory cell, and all the connected memory cells are not programmed during the write operation. The inhibit voltage supply is applied so that the write inhibit voltage is applied to the selected bit line. Control circuitry, said in times of stress tests, and a control circuit for controlling the inhibit voltage supply circuit so as to apply the stress voltage to the plurality of the bit lines.

  According to a second aspect of the present invention, there is provided a semiconductor memory device including a first MOS transistor having a charge storage layer and a control gate, and writing data by transferring electrons to the charge storage layer by FN tunneling. Memory cells, a plurality of bit lines electrically connected to one ends of the current paths of the plurality of first MOS transistors, and corresponding to the bit lines, and are connected to the memory cells during a write operation. A write circuit that holds write data and applies a stress voltage to the plurality of bit lines during a stress test of the memory cell, a inhibit voltage supply circuit that generates a write inhibit voltage during a write operation, and a write operation , All the connected memory cells are previously connected to the bit line which is not selected for writing. A control circuit that controls the prohibit voltage supply circuit so as to apply a write prohibit voltage, and controls the prohibit voltage supply circuit so as to be electrically disconnected from the plurality of bit lines during the stress test; It comprises.

  Furthermore, a test method for a semiconductor memory device according to an aspect of the present invention includes a first MOS transistor including a charge storage layer and a control gate, and writes data by transferring electrons to the charge storage layer by FN tunneling. A test method for a semiconductor memory device including a plurality of memory cells, wherein a bit line that commonly connects one ends of current paths of the plurality of first MOS transistors, a write circuit that holds write data, and a write inhibit voltage are supplied. Connecting one of the forbidden voltage supply circuit, the step of disconnecting the other of the bit line, the write circuit and the forbidden voltage supply circuit, and the write circuit and the forbidden. A stress voltage is applied to the bit line from any one of the voltage supply circuits connected to the bit line. And a step of.

  According to the present invention, it is possible to provide a semiconductor memory device and a test method thereof that can simplify the stress test.

  Embodiments of the present invention will be described below with reference to the drawings. In the description, common parts are denoted by common reference symbols throughout the drawings.

  A nonvolatile semiconductor memory device according to a first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a block diagram of a 2Tr flash memory according to this embodiment.

  A nonvolatile semiconductor memory device and a test method thereof according to a first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a block diagram of a flash memory according to the present embodiment.

  As shown, the flash memory 10 includes a memory cell array 20, a write selector 30, a write inhibit selector 40, a read selector 50, a write decoder 60, a select gate decoder 70, a selector control circuit 80, a column decoder 90, a write A circuit 100, a sense amplifier 110, a source line driver 120, an address buffer 130, a write inhibit voltage supply circuit 140, a control circuit 150, and booster circuits 160 and 170 are provided.

  The memory cell array 20, the write selector 30, the write inhibit selector 40, the read selector 50, and the write circuit 100 will be described with reference to FIG.

  The memory cell array 20 has ((m + 1) × (n + 1), where m and n are natural numbers) memory cells MC. The memory cell MC has a memory cell transistor MT and a select transistor ST whose current paths are connected in series with each other. Memory cell transistor MT has a stacked gate structure having a floating gate formed on a semiconductor substrate with a gate insulating film interposed therebetween, and a control gate formed on the floating gate with an inter-gate insulating film interposed therebetween. Yes. The source of the memory cell transistor MT is connected to the drain of the selection transistor ST. The drain regions of the memory cell transistors MT in the four memory cell columns are connected to the four local bit lines LBL0 to LBL3, respectively. The memory cell array 20 includes a plurality of memory cell columns arranged in four columns and local bit lines LBL0 to LBL3 connected to the respective memory cell columns. One end of each of the local bit lines LBL0 to LBL3 is connected to the write selector 30 and the read selector 50, and the other end is connected to the write inhibit selector 40. Further, in the memory cell array 20, the control gates of the memory cell transistors MT in the same row are commonly connected to any one of the word lines WL0 to WLm. The gates of the select transistors ST in the same row are commonly connected to any one of select gate lines SG0 to SGm. The word lines WL0 to WLm are connected to the write decoder 60, and the select gate lines SG0 to SGm are connected to the select gate decoder 70. The source region of the selection transistor ST is commonly connected to the source line SL and is connected to the source line driver 120.

  The write selector 30 includes a plurality of MOS transistors 31 to 34 provided for the individual local bit lines LBL0 to LBL3. One ends of the current paths of the MOS transistors 31 to 34 are connected to local bit lines LBL0 to LBL3, respectively. The other ends of the current paths of the MOS transistors 31 and 32 and the other ends of the current paths of the MOS transistors 33 and 34 are connected to the write global bit lines WGBL0 to WGBL (((n + 1) / 2) -1). It is connected. Further, the gates of the MOS transistors 31 and 33 and the gates of the MOS transistors 32 and 34 are commonly connected to the write column selection lines WCSL0 and WCSL1, respectively.

  That is, in the write selector 30, four MOS transistors 31 to 34 are provided for a set of four local bit lines LBL0 to LBL3. The local bit lines LBL0 and LBL1 are connected to the same write global bit line via MOS transistors 31 and 32, respectively. The local bit lines LBL2 and LBL3 are separated from each other via MOS transistors 33 and 34, respectively. Are connected to the same write global bit line. Further, of the MOS transistors 31 to 34, the MOS transistors 31 and 33 connected to different global bit lines and the MOS transistors 32 and 34 have gates connected to a common write column selection line.

  The read selector 50 includes a plurality of MOS transistors 51 to 54 provided for the individual local bit lines LBL0 to LBL3. One ends of the current paths of the MOS transistors 51 to 54 are connected to local bit lines LBL0 to LBL3, respectively. The other ends of the current paths of the MOS transistors 51 to 54 are connected to the read global bit lines RGBL0 to RGBL (((n + 1) / 4) -1). Further, the gates of the MOS transistors 51 to 54 are connected to read column selection lines RCSL0 to RCSL3, respectively.

  That is, in the read selector 50, four MOS transistors 51 to 54 are provided for a set of four local bit lines LBL0 to LBL3. The local bit lines LBL0 to LBL3 are connected to the same read global bit line via MOS transistors 51 to 54, respectively. Further, the gates of the MOS transistors 51 to 54 connected to the same read global bit line are connected to different read column selection lines.

  The write inhibit selector 40 includes a plurality of MOS transistors 41 to 44 provided for the individual local bit lines LBL0 to LBL3. One ends of the current paths of the MOS transistors 41 to 44 are connected to local bit lines LBL0 to LBL3, respectively. The other ends of the current paths of the MOS transistors 41 to 44 are connected in common and connected to the write inhibit voltage supply circuit 140. The gates of the MOS transistors 41 and 43 and the gates of the MOS transistors 42 and 44 are connected in common to the write inhibit column selection lines ICSL0 and ICSL1, respectively.

  That is, in the write inhibit selector 40, four MOS transistors 41 to 44 are provided for a set of four local bit lines LBL0 to LBL3. The local bit lines LBL0 to LBL3 are connected to the write inhibit voltage supply circuit 140 via MOS transistors 41 to 44, respectively. Further, of the MOS transistors 41 to 44, the MOS transistors 41 and 43 and the MOS transistors 42 and 44, which are electrically connected to different global bit lines, have their gates connected to a common write inhibit column selection line. ing.

  As described above, one write global bit line is provided for every two local bit lines, and one read global bit line is provided for every four local bit lines.

  The write circuit 100 includes a latch circuit 101 provided for each of the write global bit line lines WGBL0 to WGBL (((n + 1) / 2) -1). Each of the latch circuits holds data to be written in the memory cells connected to the write global bit line lines WGBL0 to WGBL (((n + 1) / 2) -1) at the time of writing. As shown in the figure, each latch circuit 101 includes two inverters 102 and 103. The input terminal of the inverter 102 is connected to the output terminal of the inverter 103, and the output terminal of the inverter 102 is connected to the input terminal of the inverter 103. A connection node between the input terminal of the inverter 102 and the output terminal of the inverter 103 is connected to the write global bit line.

  FIG. 3 is a circuit diagram illustrating a configuration example of the latch circuit 101. As shown in the figure, each of the inverters 102 and 103 includes an n-channel MOS transistor 104 and a p-channel MOS transistor 105 whose current paths are connected in series. The source of the n-channel MOS transistor 104 is connected to a negative potential VBB1 (for example, −6V), and the source of the p-channel MOS transistor 105 is connected to GND. That is, the inverters 102 and 103 operate using VBB1 and GND as power supply voltages. The gate of n channel MOS transistor 104 and the gate of p channel MOS transistor 105 are connected in common. The connection node between the drain of p-channel MOS transistor 105 and the drain of n-channel MOS transistor 104 in inverter 103 is connected to the connection node between the gate of p-channel MOS transistor 105 and the gate of n-channel MOS transistor 104 in inverter 102. Furthermore, it is connected to a write global bit line. The connection node between the drain of p-channel MOS transistor 105 and the drain of n-channel MOS transistor 104 in inverter 102 is connected to the connection node between the gate of p-channel MOS transistor 105 and the gate of n-channel MOS transistor 104 in inverter 103. Then, write data is input to this connection node. Note that the high voltage side of the power supply voltage of the inverter may be switchable between Vcc2 (for example, 3V) and GND.

Next, returning to FIG.
The write decoder 60 selects one of the word lines WL0 to WLm at the time of writing, and supplies a voltage to the selected word line. At the time of writing, a negative voltage is applied to all select gate lines SG0 to SGm. A voltage is applied to the well region where the memory cell array 20 is formed.

  The select gate decoder 70 selects one of the select gate lines SG0 to SGm at the time of reading, and supplies a voltage to the selected select gate line.

  The selector control circuit 80 controls the write selector 30 and the write inhibit selector 40. That is, at the time of writing and during a stress test, one of the write column selection lines WCSL0 and WCSL1 and the write prohibition column selection lines ICSL0 and ICSL1 is selected, and a voltage is applied to the selected column selection line.

  The column decoder 90 controls the read selector. That is, at the time of reading, one of the read column selection lines RCSL0 to RCSL3 is selected, and a voltage is applied to the selected column selection line.

  The sense amplifier 110 amplifies data read from the memory cell array 20.

  The source line driver 120 supplies a voltage to the source line.

  The address buffer 130 holds an address signal. Then, the column address signal CA is supplied to the column decoder 90, and the row address signal RA is supplied to the write decoder 60 and the select gate decoder 70.

  The write inhibit voltage supply circuit 140 supplies the write inhibit voltage Vinhibit to unselected local bit lines at the time of writing, and applies the stress voltage Vstress to all the local bit lines at the time of a stress test.

  The control circuit 150 controls the operations of the selector control circuit 80 and the write inhibit voltage supply circuit 140.

  The booster circuit 160 generates a positive potential. That is, the voltage Vcc1 (1.25 to 1.65V) input from the outside is boosted to the internal voltage Vcc2 (2.5 to 3.6V). The internal voltage Vcc2 is supplied to the select gate decoder 70, the column decoder 90, and the write inhibit voltage supply circuit 140. Further, the booster circuit 160 boosts Vcc1 to the internal voltage VPP (for example, 10V). Then, the internal voltage VPP is supplied to the write decoder 60.

  The booster circuit 170 generates a negative potential. That is, the internal voltage VBB1 is generated based on the externally input voltage Vcc1. The internal voltage VBB1 is -6V, for example. Then, the internal voltage VBB 1 is supplied to the write decoder 60 and the write circuit 100.

  Next, a planar pattern of the memory cell array included in the flash memory shown in FIG. 2 will be described. FIG. 4 is a plan view of a region including memory cells connected to write global bit line WGBL0 and word lines WL0 to WL3 in FIG.

  As shown in the figure, a plurality of stripe-shaped element regions AA along the first direction are formed in the semiconductor substrate 200 in the second direction orthogonal to the first direction. Striped word lines WL0 to WL3 and select gate lines SG0 to SG3 are formed along the second direction so as to straddle the plurality of element regions AA. A memory cell transistor MT (not shown) is formed in a region where the word lines WL0 to WL3 and the element region AA intersect. In a region where the select gate lines SG0 to SG3 and the element region AA intersect, A selection transistor ST (not shown) is formed. A floating gate (not shown) isolated for each memory cell transistor MT is formed in a region where the word lines WL0 to WL3 and the element region AA intersect.

  A stripe-shaped source line SL along the second direction is formed on the two adjacent select gate lines SG0, SG1, SG2, and SG3. The source line SL and the source region of the selection transistor ST are electrically connected by a contact plug CP1. In addition, stripe-shaped local bit lines LBL0 and LBL1 are formed along the first direction so as to substantially overlap the element region AA. One end of each of the local bit lines LBL0 and LBL1 is connected to the write selector 30, and the other end is connected to the write inhibit selector 40. The drain region of each memory cell transistor MT is connected via a contact plug CP2. In addition, a stripe-shaped metal wiring layer 210 is formed in the region directly above the select gate lines SG0 to SG3 along the second direction. The metal wiring layer 210 functions as a shunt wiring for the select gate lines SG0 to SG3, and is connected to the select gate lines SG0 to SG3 by contact plugs in a region not shown. Further, a stripe-shaped metal wiring layer is formed along the first direction at a level above the wiring. This metal wiring layer functions as a write global bit line WGBL0.

  Next, a cross-sectional structure of the memory cell array will be described with reference to FIGS. 5 is a cross-sectional view along the line X1-X1 'in FIG. 4, and FIG. 6 is a cross-sectional view along the line Y1-Y1' in FIG.

  As shown in the figure, a p-type well region 220 is formed in the surface region of the semiconductor substrate 200. An element isolation region STI is formed in the p-type well region 220. A region surrounded by the element isolation region STI is an element region AA. A gate insulating film 240 is formed on the element region AA of the semiconductor substrate 200, and gate electrodes of the memory cell transistor MT and the select transistor ST are formed on the gate insulating film 240. The gate electrodes of the memory cell transistor MT and the select transistor ST are a polycrystalline silicon layer 250 formed on the gate insulating film 240, an inter-gate insulating film 260 formed on the polycrystalline silicon layer 250, and an inter-gate insulating film 260. A polycrystalline silicon layer 270 is formed thereon. The inter-gate insulating film 260 is formed of, for example, a silicon oxide film, or an ON film, a NO film, or an ONO film that has a stacked structure of a silicon oxide film and a silicon nitride film. As shown in FIG. 5, in the memory cell transistor MT, the polycrystalline silicon layers 250 are separated from each other between adjacent element regions AA and function as floating gates. The polycrystalline silicon layer 270 functions as a control gate and is connected to the word line WL. And it is commonly connected between adjacent element regions AA. In the select transistor ST, the polycrystalline silicon layer 250 is commonly connected between adjacent element regions AA. A part of the inter-gate insulating film 260 is removed, and the polycrystalline silicon layers 250 and 270 are electrically connected. Polycrystalline silicon layers 250 and 270 are connected to select gate line SG. Also in the select transistor ST, the polycrystalline silicon layer 270 is commonly connected between adjacent element regions AA. An impurity diffusion layer 280 is formed in the surface of the semiconductor substrate 200 located between adjacent gate electrodes. The impurity diffusion layer 280 is shared by adjacent transistors.

  Note that the memory cell MC including the memory cell transistor MT and the select transistor ST is formed to have the following relationship. That is, in the adjacent memory cells MC and MC, the select transistors ST or the memory cell transistors MT are adjacent to each other. Adjacent ones share an impurity diffusion layer. Accordingly, when the two select transistors ST are adjacent to each other, the two adjacent memory cells MC and MC are arranged symmetrically around the impurity diffusion layer 280 shared by the two select transistors ST and ST. On the contrary, when the memory cell transistors MT are adjacent to each other, they are arranged symmetrically with the impurity diffusion layer 280 shared by the two memory cell transistors MT and MT as the center.

  An interlayer insulating film 290 is formed on the semiconductor substrate 200 so as to cover the memory cell transistor MT and the select transistor ST. In the interlayer insulating film 290, a contact plug CP1 reaching the impurity diffusion layer (source region) 280 shared by the two selection transistors ST and ST is formed. On the interlayer insulating film 290, a metal wiring layer 300 connected to the contact plug CP1 is formed. The metal wiring layer 300 functions as the source line SL.

  An interlayer insulating film 310 is formed on the interlayer insulating film 290 so as to cover the metal wiring layer 300. A contact plug CP2 is formed so as to penetrate the interlayer insulating film 290 from the surface of the interlayer insulating film 310 and reach the impurity diffusion layer (drain region) 280 of the memory cell transistor MT. On the interlayer insulating film 310, a metal wiring layer 320 connected in common to the plurality of contact plugs CP2 is formed. The metal wiring layer 320 functions as local bit lines LBL0 and LBL1.

  An interlayer insulating film 330 is formed on the interlayer insulating film 310 so as to cover the metal wiring layer 320. A metal wiring layer 210 is formed on the interlayer insulating film 330. The metal wiring layer 210 functions as a shunt wiring for the gate of the selection transistor ST. Therefore, a contact plug reaching the gate electrode 270 of the select transistor ST from the surface of the interlayer insulating film 330 is formed in a region not shown. The gate electrode 270 of the selection transistor ST and the metal wiring layer 210 are electrically connected through this contact plug.

  An interlayer insulating film 340 is formed on the interlayer insulating film 330 so as to cover the metal wiring layer 210. A metal wiring layer 350 is formed on the interlayer insulating film 340. The metal wiring layer 350 functions as the write global bit line WGBL0. An interlayer insulating film 360 is formed on the interlayer insulating film 340 so as to cover the metal wiring layer 350.

Next, the operation of the flash memory configured as described above will be described.
<Write operation>
Data writing is performed collectively for a plurality of memory cells connected to one of the word lines. Then, “0” data and “1” data are written depending on whether electrons are injected into the floating gate of the memory cell transistor MT. The injection of electrons into the floating gate is performed by Fowler-Nordheim (FN) tunneling. More specifically, among the memory cells connected to one of the word lines, the memory cell connected to one of the local bit lines LBL0 and LBL1, and one of the local bit lines LBL2 and LBL3. Data is simultaneously written into the memory cell.

  Hereinafter, a case where data is written to the memory cells MC connected to the word line WL0 and the local bit lines LBL0 and LBL2 will be described as an example. FIG. 7 is a flowchart of the write operation, and FIG. 8 is a circuit diagram showing the state of the memory cell array 20 at the time of write.

  First, in FIG. 1, the control circuit 150 instructs the selector control circuit 80 and the write inhibit voltage supply circuit 140 to enter the write mode (step S10).

  Next, write data (“1”, “0”) is input from an I / O terminal not shown in FIG. 1, and the write data is input to each of the write circuit 100 latch circuit 101 (step S11). When “1” data is stored in the latch circuit 101, the output of the latch circuit 101 becomes the high voltage side, that is, 0V. Conversely, when “0” data is stored, the output of the latch circuit 101 becomes the low voltage side, that is, VBB1 (−6V). These voltages are applied to the corresponding write global bit line WGBL.

  Further, the write inhibit voltage supply circuit 140 outputs the write inhibit voltage Vinhibit (0 V) based on the instruction from the control circuit 150 (step S12). Therefore, 0 V is applied to the sources of the MOS transistors 41 to 44 in the write inhibit selector 40.

  Next, the selector control circuit 80 turns on the MOS transistor connected to the local bit line to be unselected in the write inhibit selector 40 (step S13). That is, the selector control circuit 80 selects the write inhibit column selection line ICSL1 and deselects the write inhibit column selection line ICSL0. Therefore, the “L” level (0 V) is applied to the write inhibit column selection line ICSL0, and the “H” level (Vcc2 = 3 V) is applied to the write inhibit column selection line ICSL1. As a result, the MOS transistors 42 and 44 are turned on, and the MOS transistors 41 and 43 are turned off. Therefore, the write inhibit voltage Vinhibit supplied from the write inhibit voltage supply circuit 140 is applied to the local bit lines LBL1 and LBL3 that should not be selected.

  The selector control circuit 80 turns on the MOS transistor connected to the local bit line to be selected in the write selector 30 (step S14). That is, the selector control circuit 80 selects the write column selection line WCSL0 and deselects the write column selection line WCSL1. Therefore, the “H” level (Vcc2 = 3V) is applied to the write column selection line WCSL0, and the “L” level (0V) is applied to the write column selection line WCSL1. As a result, the MOS transistors 31 and 33 are turned on, and the MOS transistors 32 and 34 are turned off. Therefore, a voltage (0 V or VBB1) corresponding to the write data is applied from the latch circuit 101 to the local bit lines LBL0 and LBL1 to be selected.

  Then, the write decoder 60 selects one of the word lines WL0 to WLm based on the row address signal input from the address buffer 130 (step S15). In the example of FIG. 8, the word line WL0 is selected. The write decoder 60 applies VPP (for example, 10 V) to the selected word line WL0. The write decoder 60 deselects all the select gate lines SG0 to SGm (step S16). That is, the write decoder 60 applies the negative voltage VBB1 to all the select gate lines SG0 to SGm. Accordingly, all the select transistors ST are turned off. At this time, the select gate lines SG0 to SGm are electrically separated from the select gate decoder 70.

  Further, the write decoder 60 applies the negative potential VBB1 to the p-type well region 220 in which the memory cell array 20 is formed (step S17).

  As a result, “1” data or “0” data is transferred from the write global bit line to the local bit lines LBL 0 and LBL 2 to which the selected memory cell is connected via the MOS transistors 31 and 33 in the write selector 30. A potential corresponding to is applied. This potential is applied to the drain region of the memory cell transistor MT via the contact plug CP2. Then, Vpp (10 V) is applied to the selected word line WL, 0 V is applied to the drain region of the memory cell MC to which “1” data is to be written, and the drain region of the memory cell MC to which “0” data is to be written. VBB1 (−6V) is applied to VBB1. Accordingly, since the potential difference (10 V) between the gate and the drain is not sufficient in the memory cell MC to which “1” data is to be written, electrons are not injected into the floating gate, and the memory cell MC maintains a negative threshold value. On the other hand, in the memory cell MC to which “0” data is to be written, the potential difference (16 V) between the gate and the drain is large, so that electrons are injected into the floating gate by FN tunneling. As a result, the threshold value of the memory cell changes positively.

  Further, the write inhibit voltage Vinhibit is supplied from the write inhibit voltage supply circuit 140 to the local bit lines LBL1 and LBL3 to which the selected memory cell is not connected via the MOS transistors 42 and 44 of the write inhibit selector 40. Accordingly, erroneous writing is suppressed for the memory cells connected to the local bit lines LBL1 and LBL3.

  As described above, the write operation to the memory cell is performed.

  At the time of writing, the read column select lines RCSL0 to RCSL3 are not selected, and all the MOS transistors 51 to 54 in the read selector 50 are turned off. Therefore, the local bit lines LBL0 to LBL3 are electrically separated from the read global bit line RGBL.

<Erase operation>
Data is erased collectively for all memory cells sharing the well region. Therefore, in the example of FIG. 2, all the memory cells included in the memory cell array 20 are erased simultaneously. FIG. 9 is a circuit diagram of the memory cell array 20 during the erase operation.

  In the erase operation, the MOS transistors 31 to 34 in the write selector 30, the write inhibit selectors 41 to 44, and the MOS transistors 51 to 54 in the read selector 60 are turned off. Accordingly, all the local bit lines LBL0 to LBL3 in the memory cell array 20 are set in a floating state.

  Then, the write decoder 60 sets the potentials of all the word lines WL0 to WLm to VBB1. The potential of the well region 220 is set to VPP. As a result, electrons are extracted from the floating gate of the memory cell transistor of the memory cell MC to the well region 220 by FN tunneling. As a result, the threshold voltage of all the memory cells MC becomes negative and data is erased.

  Note that the select gate lines SG0 to SGm are floated, or VPP is applied from the write decoder. When floating, the potential rises to near VPP by coupling with the well region.

<Read operation>
In data reading, data can be read from a plurality of memory cells connected to any one of the word lines at a time. More specifically, data can be simultaneously read from memory cells connected to any of the local bit lines LBL0 to LBL3 among the memory cells connected to any of the word lines.

  Hereinafter, a case where data is read from the memory cell MC connected to the word line WL0 and the local bit line LBL0 will be described as an example. FIG. 10 is a circuit diagram showing a state of the memory cell array at the time of reading.

  First, the selector control circuit 80 deselects the write inhibit column select lines ICSL0 and ICSL1 and the write column select lines WCSL0 and WCSL1. That is, the “L” level (0 V) is applied to the write inhibit column select lines ICSL0 and ICSL1 and the write column select lines WCSL0 and WCSL1. Accordingly, all of the MOS transistors 41 to 44 in the write inhibit selector 40 and the MOS transistors 31 to 34 in the write selector 30 are turned off. As a result, the local bit lines LBL0 to LBL3 are electrically isolated from the write inhibit voltage supply circuit 140 and the write global bit lines WGBL0 to WGBL (((n + 1) / 2) -1).

  The column decoder 90 selects any one of the read column selection lines RCSL0 to RCSL3 based on the column address signal input from the address buffer 130. In the example of FIG. 10, the read column selection line RCSL0 is selected. That is, the column decoder 90 applies the “H” level (Vcc2) to the read column selection line RCSL0, and applies the “L” level (0 V) to the read column selection lines RCSL1 to RCSL3. Accordingly, the MOS transistor 51 in the read selector 50 is turned on. As a result, the local bit line LBL0 is connected to the read global bit lines RGBL0 to RGBL (((n + 1) / 4) -1). On the other hand, the local bit lines LBL1 to LBL3 are electrically isolated from the read global bit lines RGBL0 to RGBL (((n + 1) / 4) -1).

  The write decoder 60 applies 0V to all the word lines WL0 to WLm, and the source line driver 120 sets the source line potential to 0V. The select gate decoder 70 selects any one of the select gate lines SG0 to SGm. In the example of FIG. 10, the select gate decoder 70 selects the select gate line SG0 and applies Vcc2 to the select gate line SG0. The other select gate lines SG1 to SGm are supplied with 0V. Accordingly, the select transistor ST connected to the selected select gate line SG0 is turned on, and the select transistor ST connected to the unselected select gate line is turned off. At this time, the select gate lines SG0 to SGm are electrically separated from the write decoder 60.

  As a result, the local bit line LBL0 is connected to the sense amplifier 110 via the MOS transistor 51 in the read selector 50 and the read global bit lines RGBL0 to RGBL (((n + 1) / 4) -1). .

  Then, for example, about 1 to 3 V is applied to the read global bit lines RGBL0 to RGBL (((n + 1) / 4) -1). Then, the memory cell transistor MT of the memory cell MC in which “1” data is written is turned on because the threshold voltage is negative. Therefore, in the memory cell MC connected to the selected select gate line SG0, the local bit line LBL0, the memory cell transistor MT, and the selection from the read global bit lines RGBL0 to RGBL (((n + 1) / 4) -1) are selected. A current flows toward the source line SL through the transistor ST. On the other hand, the memory cell transistor MT of the memory cell MC in which “0” data is written is in the off state because the threshold voltage is positive. Therefore, no current flows through the read global bit lines RGBL0 to RGBL (((n + 1) / 4) -1).

  As described above, the potential of the read global bit lines RGBL0 to RGBL (((n + 1) / 4) -1) changes, and the read operation is performed by the sense amplifier 110 amplifying the change amount.

  Although the sense amplifier 110 is shown as one block in the drawing, it includes a sense amplifier provided for each read global bit line, and amplifies read data for each read global bit line. To do.

<Stress test operation>
The stress test is performed collectively for all the memory cells MC included in the memory cell array 20. The stress test operation will be described with reference to FIGS. FIG. 11 is a flowchart of the stress test operation, and FIG. 12 is a circuit diagram showing the state of the memory cell array 20 during the stress test.

  First, the control circuit 150 instructs the selector control circuit 80 and the write inhibit voltage supply circuit to enter the stress test mode (step S20).

  Further, the write inhibit voltage supply circuit 140 outputs a stress voltage Vstress (= Vcc2 = 2 to 3 V) based on an instruction from the control circuit 150 (step S21). Accordingly, Vcc2 is applied to the sources of the MOS transistors 41 to 44 in the write inhibit selector 40.

  Next, the selector control circuit 80 turns on all the MOS transistors 41 to 44 in the write inhibit selector 40 (step S22). That is, the selector control circuit 80 selects the write inhibit column selection lines ICSL0 and ICSL1, and applies the “H” level (Vcc2) to both. Therefore, the stress voltage Vstress supplied from the write inhibit voltage supply circuit 140 is applied to the local bit lines LBL1 to LBL4.

  The selector control circuit 80 also turns off all the MOS transistors 31 to 34 in the write selector 30 (step S23). That is, the selector control circuit 80 deselects the write column selection lines WCSL0 and WCSL1, and applies the “L” level (0 V) to both. Accordingly, the local bit lines LBL0 to LBL3 are electrically isolated from the write global bit lines WGBL0 to WGBL (((n + 1) / 2) -1).

  The column decoder 90 deselects the read column selection lines RCSL0 to RCSL3 and turns off all the MOS transistors 51 to 54 in the read selector 50. Therefore, the local bit lines LBL0 to LBL3 are electrically separated from the read global bit line RGBL (((n + 1) / 4) -1).

  Further, the write decoder 60 and the select gate decoder 70 deselect all the word lines WL0 to WLm and the select gate lines SG0 to SGm (step S24).

  As a result, the stress voltage Vstress is applied to the drains of all the memory cell transistors MT in the memory cell array 20 via the MOS transistors 41 to 44 in the write inhibit selector 40 and the local bit lines LBL0 to LBL3.

  Note that the order of steps S21 to S24 can be changed as appropriate.

  As described above, the flash memory according to the first embodiment of the present invention provides the following effects.

(1) The stress test can be simplified (part 1).
In the configuration according to this embodiment, the selector control circuit 80 and the write inhibit voltage supply circuit 140 have a stress test operation mode in addition to the write operation mode. In the stress test operation mode, the selector control circuit disconnects all the local bit lines from the write global bit line and connects all the local bit lines to the write inhibit voltage supply circuit. Further, the write inhibit voltage supply circuit 140 generates a stress voltage Vstress instead of the write inhibit voltage Vinhibit in the stress test operation mode. Therefore, a stress voltage is applied to all the memory cell transistors in the memory cell array 20 at once. That is, it is not necessary to perform a stress test for each individual memory cell by inputting an address signal as in the prior art, and a stress test can be performed on all the memory cells simultaneously. Therefore, the stress test method can be simplified, the test time can be shortened, and the manufacturing cost of the flash memory can be reduced.

(2) The reliability of the write operation can be improved.
In the flash memory according to the present embodiment, the write inhibit voltage Vinhibt supplied by the write inhibit voltage supply circuit 140 during the write operation is a local bit line to which the selected memory cell is not connected, that is, a connected memory cell. Are all applied to local bit lines which are not selected for writing. Therefore, erroneous writing to the unselected memory cell can be effectively suppressed.

  The bit lines are hierarchized into local bit lines and global bit lines, and a plurality of local bit lines are connected to one write global bit line. At the time of writing, only one local bit line including the selected memory cell is electrically connected to the write global bit line, and the other local bit lines are electrically isolated from the write global bit line. . Therefore, a voltage corresponding to the write data from the latch circuit is not applied to the local bit line to which the selected memory cell is not connected. Therefore, it is possible to effectively prevent erroneous writing to the memory cells connected to these local bit lines. As a result, the reliability of the write operation can be improved.

  In the above-described embodiment, the case where the stress voltage Vstress is Vcc2 (= 2 to 3 V) has been described. That is, the stress test is performed by applying stress to the memory cell during the read operation. However, if the write inhibit voltage supply circuit 140 is configured to supply the negative voltage generated by the booster circuit 170 during the stress test, the stress test can be performed by applying the stress during the write operation to the memory cell. .

  Next explained is a nonvolatile semiconductor memory device and a test method therefor according to the second embodiment of the invention. In this embodiment, the stress voltage is applied from the write circuit 100 instead of the write inhibit voltage supply circuit 140 in the first embodiment. Accordingly, since the basic configuration of the flash memory is the same as that shown in FIGS. 1 to 6, only the differences from the first embodiment will be described below. FIG. 13 is a circuit diagram of the booster circuit 170 and the latch circuit 101 included in the write circuit 100 included in the flash memory according to the present embodiment.

  As shown in the figure, the booster circuit 170 generates two types of negative voltages. One is VBB1 (= −6V) used during writing, and the other is VBB2 (= −7 to −8V <VBB1) used during stress testing. The low-voltage power supply voltage nodes of the inverters 102 and 103 in the latch circuit 101 are connected to the VBB1 output node and the VBB2 output node in the booster circuit 170 by the switch element 180.

  The switch element 180 is controlled by the control circuit 150. In the normal operation mode, the power supply potential nodes of inverters 102 and 103 are connected to the VBB1 node, and in the stress test, the power supply potential nodes of inverters 102 and 103 are connected to the VBB2 node.

  Next, the operation of the flash memory configured as described above will be described. Since the write operation, the erase operation, and the read operation are the same as those in the first embodiment, the description thereof will be omitted, and the stress test will be described below. FIG. 14 is a flowchart of the stress test operation, and FIG. 15 is a circuit diagram showing the state of the memory cell array 20 during the stress test. In this embodiment, the stress voltage Vstress is supplied not by the write inhibit voltage supply circuit 140 but by the write circuit 110. Therefore, during the stress test, the local bit lines LBL0 to LBL3 are connected to the write global bit lines WGBL0 to WGBL (((n + 1) / 2) -1) and disconnected from the write inhibit voltage supply circuit 140. . This will be described in detail below.

  First, the control circuit 150 instructs the selector control circuit 80 and the write inhibit voltage supply circuit to enter the stress test mode (step S20).

  Further, the write circuit 110 outputs a stress voltage Vstress (= VBB2 = −7 to −8V) (step S21). That is, in the configuration shown in FIG. 13, based on the command of the control circuit 150 in step S20, the switch element 180 switches the power supply voltage on the low voltage side of the inverters 102 and 103 from VBB1 to VBB2. As a result, the output of the latch circuit 101 is switched to VBB2. Accordingly, the stress voltage Vstress (= VBB2) is applied to the write global bit lines WGBL0 to WGBL3.

  Next, the selector control circuit 80 turns off all the MOS transistors 41 to 44 in the write inhibit selector 40 (step S26). That is, the selector control circuit 80 deselects the write inhibit column selection lines ICSL0 and ICSL1, and applies the “L” level (0 V) to both. Therefore, the local bit lines LBL 1 to LBL 4 are electrically isolated from the write inhibit voltage supply circuit 140.

  The selector control circuit 80 turns on all the MOS transistors 31 to 34 in the write selector 30 (step S27). That is, the selector control circuit 80 selects the write column selection lines WCSL0 and WCSL1, and applies the “H” level (Vcc2) to both. Therefore, the local bit lines LBL0 to LBL3 are electrically connected to the write global bit lines WGBL0 to WGBL (((n + 1) / 2) -1).

  The column decoder 90 deselects the read column selection lines RCSL0 to RCSL3 and turns off all the MOS transistors 51 to 54 in the read selector 50. Therefore, the local bit lines LBL0 to LBL3 are electrically separated from the read global bit line RGBL (((n + 1) / 4) -1).

  Further, the write decoder 60 and the select gate decoder 70 deselect all the word lines WL0 to WLm and the select gate lines SG0 to SGm (step S24).

  As a result, the stress voltage Vstress is applied from the write circuit 100 to the drains of all the memory cell transistors MT in the memory cell array 20 via the MOS transistors 31 to 34 and the local bit lines LBL0 to LBL3 in the write selector 30. Applied. Note that the order of steps S21 to S24 can be changed as appropriate.

  As described above, even with the configuration and method according to the present embodiment, a stress test can be performed. In addition to the effect (2) described in the first embodiment, the following effect (3) is obtained. can get.

(3) The stress test can be simplified (part 2).
In the configuration according to this embodiment, the selector control circuit 80 has a stress test operation mode in addition to the write operation mode. In the stress test operation mode, the selector control circuit connects all the local bit lines to the write global bit line and electrically isolates all the local bit lines from the write inhibit voltage supply circuit. Further, the latch circuit 101 generates a stress voltage Vstress instead of a voltage corresponding to write data during a stress test. Therefore, a stress voltage is applied to all the memory cell transistors in the memory cell array 20 at once. That is, it is not necessary to perform a stress test for each individual memory cell by inputting an address signal as in the prior art, and a stress test can be performed on all the memory cells simultaneously. Therefore, the stress test method can be simplified, the test time can be shortened, and the manufacturing cost of the flash memory can be reduced.

  In the above-described embodiment, the case where the stress voltage Vstress is VBB2 (= −7 V to −8 V) has been described. That is, the stress test is performed by applying stress to the memory cell during the write operation. However, if the write circuit 100 is configured to supply the positive voltage Vcc2 generated by the booster circuit 160 during a stress test, the stress test can be performed by applying a stress during reading to the memory cell.

  Next explained is a non-volatile semiconductor memory device and its test method according to a third embodiment of the invention. In the present embodiment, the stress voltage Vstress is applied not from the booster circuit 170 but from the outside in the first embodiment. FIG. 16 is a block diagram of an LSI including a flash memory according to the present embodiment.

  As shown in the figure, the LSI according to the present embodiment has a stress voltage from the outside of the LSI via a pin 190 to the write inhibit voltage supply circuit 140 in the configuration shown in FIG. 1 described in the first embodiment. Vstress is given.

  The operation of the flash memory according to the present embodiment is the same as that of the first embodiment. However, during the stress test, the write inhibit voltage supply circuit 140 applies a voltage input from the outside of the LSI to the local bit line as the stress voltage Vstress.

  In addition to the effects (1) and (2) described in the first embodiment, the following effects can be obtained with the configuration according to the present embodiment.

(4) The degree of freedom of stress test is improved.
With the configuration according to the present embodiment, the stress voltage Vstress can be arbitrarily applied from the outside. Therefore, the voltage value of the stress voltage Vstress can be arbitrarily given from a negative voltage to a positive voltage without depending on the capability of the booster circuit incorporated in the LSI. That is, the stress test can be performed with various voltages, and the degree of freedom of the stress test can be improved.

  Next explained is a non-volatile semiconductor memory device and its test method according to a fourth embodiment of the invention. In the present embodiment, the stress voltage Vstress is applied not from the booster circuit 170 but from the outside in the second embodiment. FIG. 17 is a block diagram of an LSI including a flash memory according to the present embodiment.

  As shown in the drawing, the LSI according to the present embodiment applies a stress voltage Vstress to the write circuit 100 from the outside of the LSI via a pin 190 in the configuration described in the second embodiment.

  18 is a circuit diagram of the booster circuit 170 included in the flash memory according to the present embodiment and the latch circuit 101 included in the write circuit 100.

  As shown in the figure, in the configuration of FIG. 13 described in the second embodiment, the switch element 180 connects the power supply potential node of the inverters 102 and 103 to the VBB1 node of the booster circuit 170 in the normal operation mode. In the stress test, the power supply potential nodes of the inverters 102 and 103 are connected to the external terminal 190. A stress voltage Vstress is applied from the external terminal.

  The operation of the flash memory according to the present embodiment is the same as that of the second embodiment. However, during the stress test, the write circuit 100 applies a voltage input from the outside of the LSI to the local bit line as the stress voltage Vstress.

  With the configuration according to the present embodiment, in addition to the effects (2) and (3) described in the second embodiment, the effect (4) described in the third embodiment is also obtained. .

  Next, a nonvolatile semiconductor memory device according to a fifth embodiment of the invention is described with reference to FIG. The present embodiment relates to a system LSI including the flash memory according to the first to fourth embodiments. FIG. 19 is a block diagram of a system LSI according to this embodiment.

  As illustrated, the system LSI 400 includes a NAND flash memory 500, a 3Tr-NAND flash memory 600, a 2Tr flash memory 10, an MCU 700, and an I / O circuit 800 formed on the same semiconductor substrate.

  The NAND flash memory 500 is used as a storage memory for storing image data and video data.

  The 3Tr-NAND flash memory 600 holds an ID code and a security code for accessing the LSI 400.

  The 2Tr flash memory 10 holds program data for the MCU 700 to operate.

  The MCU 700 performs processing based on a program read from the 2Tr flash memory 10 in response to various commands input from the outside. At this time, the MCU 700 directly accesses the 2Tr flash memory 10 without going through an SRAM (Static Random Access Memory) or the like. Examples of processing performed by the MCU 700 include compression and decompression of data input to the NAND flash memory 500 or control of an external device. Further, the MCU 700 reads predetermined data from the 3Tr-NAND flash memory 600 when the data held in the NAND flash memory 500 is accessed from the outside. The MCU 700 collates the read data with an ID code or security code input from the outside, and permits access to the NAND flash memory 500 if they match. When access to the NAND flash memory 500 is permitted, data in the NAND flash memory 500 is accessed from the outside (host). That is, the MCU 700 triggers the NAND flash memory 500 in response to a command received from the outside, and reads (writes) data.

  The I / O circuit 800 controls transmission / reception of signals between the LSI 1 and the outside.

  Next, the configuration of the two semiconductor memories 500 and 600 included in the LSI 400 will be described in detail below. The 2Tr flash memory 10 is as described in the first to fourth embodiments.

<NAND flash memory>
First, the configuration of the NAND flash memory 500 will be described with reference to FIG. FIG. 20 is a block diagram of a NAND flash memory.

  As illustrated, the NAND flash memory 500 includes a memory cell array 510, a column decoder 520, a row decoder 530, a sense amplifier 540, a write circuit 550, and a source line driver 560.

  The memory cell array 510 has a plurality of NAND cells arranged in a matrix. Each NAND cell includes eight memory cell transistors MT and select transistors ST1 and ST2. Memory cell transistor MT has a stacked gate structure having a floating gate formed on a semiconductor substrate with a gate insulating film interposed therebetween, and a control gate formed on the floating gate with an inter-gate insulating film interposed therebetween. Yes. The number of memory cell transistors MT is not limited to eight, and may be 16 or 32, and the number is not limited. Adjacent ones of the memory cell transistors MT share a source and a drain. And it arrange | positions so that the current path may be connected in series between selection transistor ST1, ST2. The drain region on one end side of the memory cell transistors MT connected in series is connected to the source region of the selection transistor ST1, and the source region on the other end side is connected to the drain region of the selection transistor ST2.

  The control gates of the memory cell transistors MT in the same row are commonly connected to any of the word lines WL0 to WLm, and the gates of the select transistors ST1 and ST2 of the memory cells in the same row are connected to the select gate lines SGD and SGS, respectively. It is connected. The drains of the select transistors ST1 in the same column are commonly connected to any of the bit lines BL0 to BLn. The sources of the select transistors ST2 are commonly connected to the source line SL and connected to the source line driver 15. Note that both the selection transistors ST1 and ST2 are not necessarily required. As long as a NAND cell can be selected, only one of them may be provided.

  The column decoder 520 decodes the column address signal to obtain a column address decode signal. Then, one of the bit lines BL0 to BLn is selected based on the column address decode signal.

  The row decoder 530 decodes the row address signal to obtain a row address decode signal. The row decoder 530 selects one of the word lines WL0 to WL8 and the select gate lines SGD and SGS.

  The sense amplifier 540 amplifies data read from the memory cell MC selected by the row decoder 530 and the column decoder 520.

  The write circuit 550 latches write data.

  The source line driver 560 supplies a voltage to the source line SL.

<3Tr-NAND flash memory>
Next, the configuration of the 3Tr-NAND flash memory 600 will be described with reference to FIG. FIG. 21 is a block diagram of the 3Tr-NAND flash memory 600.

  As illustrated, the 3Tr-NAND flash memory 600 includes a memory cell array 610, a column decoder 620, a row decoder 630, a sense amplifier 640, a write circuit 650, and a source line driver 660.

  The memory cell array 610 includes a plurality ((m + 1) × (n + 1), where m and n are natural numbers) memory cells MC arranged in a matrix. Each of the memory cells MC has a memory cell transistor MT and select transistors ST1, ST2 whose current paths are connected in series. The current path of the memory cell transistor MT is connected between the current paths of the select transistors ST1 and ST2. That is, the NAND cell included in the NAND flash memory 500 is equivalent to a single memory cell transistor MT. Memory cell transistor MT has a stacked gate structure having a floating gate formed on a semiconductor substrate with a gate insulating film interposed therebetween, and a control gate formed on the floating gate with an inter-gate insulating film interposed therebetween. Yes. The source region of the select transistor ST1 is connected to the drain region of the memory cell transistor MT, and the source region of the memory cell transistor MT is connected to the drain region of the select transistor ST2. Further, the memory cells MC adjacent in the column direction share the drain region of the selection transistor ST1 or the source region of the selection transistor ST2.

  The control gates of the memory cell transistors MT of the memory cells MC in the same row are commonly connected to any of the word lines WL0 to WLm, and the gates of the select transistors ST1 of the memory cells in the same row are select gate lines SGD0 to SGDm. And the gate of the select transistor ST2 is connected to one of the select gate lines SGS0 to SGSm. The drain region of the select transistor ST1 of the memory cells MC in the same column is commonly connected to one of the bit lines BL0 to BLn. The source region of the select transistor ST2 of the memory cell MC is commonly connected to the source line SL and connected to the source line driver 260.

  The column decoder 620 decodes the column address signal to obtain a column address decode signal. Then, one of the bit lines BL0 to BLn is selected based on the column address decode signal.

  The row decoder 630 decodes the row address signal to obtain a row address decode signal. Then, the row decoder 230 selects one of the word lines WL0 to WLm and the select gate lines SG0 to SGm.

  The sense amplifier 640 amplifies data read from the memory cell MC selected by the row decoder 630 and the column decoder 620.

  The write circuit 650 latches write data.

  The source line driver 660 supplies a voltage to the source line SL.

According to the LSI of the present embodiment, the following effects can be obtained in addition to the effects (1) to (4).
(5) A plurality of types of flash memories can be mounted on the same chip while reducing manufacturing costs.

  The memory cell transistors MT and select transistors ST1, ST2, and ST included in the NAND flash memory 500, 3Tr-NAND flash memory 600, and 2Tr flash memory 10 can be formed in the same process. That is, each MOS transistor is formed by the same oxidation process, film formation process, impurity implantation process, and photolithography / etching process. As a result, the gate insulating film 240, the inter-gate insulating film 260, the floating gate 250 and the control gate 270 of the memory cell transistor MT, and the select gates 250 and 270 of the selection transistor are the same among the three flash memories 10, 500, and 600. It becomes. With such a manufacturing method, a memory cell array of three flash memories can be formed by the number of steps necessary to form one flash memory. Therefore, it is possible to reduce the manufacturing cost of a system LSI equipped with three types of semiconductor memories.

(6) The system LSI can be improved in performance.

  The system LSI according to this embodiment includes a NAND flash memory 500 and a 3Tr-NAND flash memory 600 in addition to the 2Tr flash memory 10 described in the first to fourth embodiments.

  Unlike the NAND flash memory 500 and the 3Tr-NAND flash memory 600, the 2Tr flash memory 10 uses a positive voltage (10V) and a negative voltage (-6V) during writing and erasing. A potential difference of 16 V is applied between the control gate and the channel. Accordingly, the write inhibit voltage can be set to 0 V near the middle between 10 V and −6 V, and it becomes easy to apply the write inhibit voltage from the bit line. Further, by using the positive voltage and the negative voltage, the potential difference applied to the gate insulating film of the MOS transistor used in the decoders 60 and 70 is 10V or -6V. Accordingly, the MOS transistors used in the row decoders 60 and 70 included in the 2Tr flash memory 10 are gated more than the MOS transistors used in the row decoders 530 and 630 included in the NAND flash memory 500 and the 3Tr-NAND flash memory 600. A thin insulating film can be used. Therefore, the decoders 60 and 70 can be downsized, and the operation speed of the decoders 60 and 70 can be increased as compared with the row decoders 530 and 630. Therefore, the operation speed of the 2Tr flash memory can be improved, and random access can be speeded up.

  In the present embodiment, program data for operating the MCU 700 is stored in the 2Tr flash memory 10. Then, as described above, the 2Tr flash memory can operate at high speed. Therefore, the MCU 700 can directly read data from the 2Tr flash memory 10 without using a RAM or the like. As a result, a RAM or the like is unnecessary, and the configuration of the system LSI can be simplified and the operation speed can be improved.

  The 3Tr-NAND flash memory 600 holds an ID code and a security code. These code data are not so large in data amount itself, but are often changed / updated frequently. Therefore, a memory that holds these code data is required to have a certain high speed operation. In this regard, the 3Tr-NAND flash memory 600 is not as large as the erase unit in the NAND flash memory 100, and data can be rewritten in units of pages. Therefore, it can be said that the 3Tr-NAND flash memory 600 is an optimal semiconductor memory for holding the code data.

  Conventionally, in the case of an LSI having a NAND flash memory, the following controller is required to prevent rewriting from being concentrated on a specific block. That is, it is a controller that converts an address input in wear leveling or logic into a physical address or performs control so that the block is not used as a defective block when the block is defective. However, in this embodiment, such a controller is not necessary. This is because the firmware program for controlling the blocks in the NAND flash memory 500 may be held in the 2Tr flash memory 10 and the above control may be performed by the MCU 700. The MCU 700 may perform the above-described control using the time during the work that is originally performed (control of an external device, calculation processing of data input to the NAND flash memory 500, etc.). Of course, the capacity of the MCU 700 and the size of the processing amount that the MCU 700 originally needs to process are determined. If the processing amount is large, a hardware sequencer or the like may be provided to control the NAND flash memory 500. .

  Next, a nonvolatile semiconductor memory device according to a sixth embodiment of the invention is described with reference to FIG. In the present embodiment, in the flash memory 10 described in the first to fifth embodiments, the write global bit line is grounded at the time of reading. FIG. 22 is a circuit diagram of a partial region of the flash memory 10 according to the present embodiment, and shows a state during a read operation.

  As shown in the figure, the flash memory 10 according to the present embodiment further includes a voltage generation circuit 900 in the configuration of FIG. 2 described in the first embodiment. The voltage generation circuit 900 is connected to the write global bit lines WGBL0 to WGBL (((n + 1) / 2-1) via the switch element 910. The switch element 910 is connected to the write global bit line during the read operation. The bit lines WGBL0 to WGBL (((n + 1) / 2-1) and the voltage generation circuit 900 are connected to each other and disconnected during other periods. Is applied to write global bit lines WGBL0 to WGBL (((n + 1) / 2-1).

  According to the structure which concerns on this embodiment, in addition to the effect of said (1) thru | or (6), the effect of following (7) can be acquired collectively.

(7) Read operation reliability can be improved.
In the configuration according to the present embodiment, the potential of the write global bit line is set to the ground potential at the time of reading. This is a noise countermeasure for the read global bit line, and the read operation can be further stabilized. Therefore, the read operation reliability of the flash memory can be improved.

  As described above, according to the nonvolatile semiconductor memory device according to the first to sixth embodiments of the present invention, during the stress test, all the local bit lines included in the memory cell array are connected to the write inhibit voltage supply circuit or Connected to writing circuit. The write inhibit voltage supply circuit or the write circuit generates a stress voltage and applies the stress voltage to the drain of the memory cell transistor via the local bit line. Therefore, it is possible to apply stress to a plurality of (all) memory cells included in the memory cell array at once. Therefore, the stress test time can be greatly shortened.

  In the above embodiment, the case where the stress voltage is generated from the write inhibit voltage supply circuit and the write circuit has been described as separate configurations. However, one flash memory may be configured to apply a stress voltage from both circuits. FIG. 23 is a block diagram of such a flash memory 10 and corresponds to a configuration combining the first and second embodiments.

  As shown in the drawing, the write prohibition voltage supply circuit 140 is supplied with a positive voltage Vcc2 as the stress voltage Vstress from the booster circuit 160, and the write circuit 100 is supplied with the negative voltage VBB2 as the stress voltage Vstress.

  FIG. 24 is a flowchart at the time of a stress test of the flash memory having the configuration shown in FIG. That is, after the stress test mode is selected (step S20), when a read test is performed (step S28), the write inhibit voltage supply circuit 140 outputs the stress voltage Vstress = Vcc2 (step S29). The stress voltage Vstress is applied to the local bit line via the write prohibition selector, and a stress test is performed by the method described in the first embodiment. On the other hand, when the write test is performed (step S28), the latch circuit 101 outputs the stress voltage Vstress = VBB2 (step S30). The stress voltage Vstress is applied to the local bit line via the write global bit line and the write selector, and the stress test is performed by the method described in the second embodiment. Of course, the order of steps S29, S22, and S23 can be changed as appropriate. In addition, the order of steps S30, S26, and S27 can be changed.

  In the configuration according to the first embodiment, the write inhibit voltage supply circuit 140 may apply a stress voltage used for reading and writing tests. FIG. 25 is a block diagram of the flash memory in such a case.

  As shown in the figure, the write inhibit voltage supply circuit 140 is supplied with Vcc2 from the booster circuit 160 and VBB2 from the booster circuit 170 as the stress voltage Vstress. The operation is almost the same as that in FIG. 24, except that the write inhibit voltage supply circuit 140 supplies the stress voltage Vstress = VBB2 in step S30.

  Of course, in the configuration according to the second embodiment, the write circuit 100 may apply a stress voltage used for reading and writing tests. FIG. 26 is a block diagram of a flash memory in such a case.

  As shown in the drawing, the write circuit 100 is supplied with Vcc2 from the booster circuit 160 and VBB2 from the booster circuit 170 as the stress voltage Vstress. The operation is almost the same as that of FIG. 24, and is the same as the step S29 except that the write circuit 100 provides the stress voltage Vstress = Vcc2. FIG. 27 is a diagram illustrating a connection relationship between the latch circuit 101 included in the write circuit 100 illustrated in FIG. 26 and the booster circuits 160 and 170.

  As shown in the figure, the inverters 102 and 103 have their power supply voltage nodes on the high voltage side switched between GND and the booster circuit 160 by the switch element 181. The power supply voltage node on the low voltage side is switched between the VBB1 node and the VBB2 node by the switch element 180. In the read stress test, the power supply potential node on the high voltage side is connected to the booster circuit 160, and the output of the latch circuit 101 is Vcc2. In the write stress test, the power supply potential node on the low voltage side is connected to the VBB2 node. The output of the latch circuit 101 becomes VBB2.

  Further, in the above-described embodiment, it has been described that the stress test is collectively performed on all the memory cells included in the memory cell array 20. However, as shown in FIG. 28, the flash memory may include a plurality of memory cell arrays 20-1 and 20-2, and each may be controlled by a decoder circuit or the like provided corresponding to each. In such a case, it is possible to perform a stress test on all the memory cells included in the memory cell array 20-1 and not to perform a stress test on the memory cells included in the memory cell array 20-2.

  Furthermore, in the above-described embodiment, the values of the stress voltage Vstress have been described as VBB2 (−7 to −8 V) and Vcc2 (2 to 3 V). Can be changed arbitrarily. Further, when the write inhibit voltage supply circuit 140 applies the stress voltage Vstress, the stress voltage Vstress may be the same as or different from the write inhibit voltage Vinhibit. The same applies to the write circuit, and the stress voltage Vstress may be the same as or different from the voltage applied to the bit line during writing.

  Further, in the above embodiment, the case where the bit lines are hierarchized has been described. That is, one write global bit line is provided for every two local bit lines, and one read global bit line is provided for every four local bit lines. However, the number of local bit lines assigned to the write and read global bit lines is arbitrary and is not particularly limited. Furthermore, the present embodiment can be applied even when the bit lines are not hierarchized and the latch circuit 101 is provided for each bit line.

That is, the nonvolatile semiconductor memory devices according to the first to sixth embodiments of the present invention are:
1. A plurality of memory cells including a first MOS transistor including a charge storage layer and a control gate, and writing data by transferring electrons to the charge storage layer by FN tunneling;
A plurality of bit lines each having one end of a current path of the plurality of first MOS transistors electrically connected thereto;
A write circuit provided corresponding to the bit line and holding write data to the memory cell;
A prohibit voltage supply circuit that generates a write prohibit voltage during a write operation and generates a stress voltage during a stress test of the memory cell;
At the time of the write operation, the inhibit voltage supply circuit is controlled so as to apply the write inhibit voltage to the bit line where all the connected memory cells are not selected for writing, and at the time of the stress test, A control circuit that controls the prohibit voltage supply circuit so as to apply the stress voltage to the plurality of bit lines.

2. A plurality of memory cells including a first MOS transistor including a charge storage layer and a control gate, and writing data by transferring electrons to the charge storage layer by FN tunneling;
A plurality of bit lines each having one end of a current path of the plurality of first MOS transistors electrically connected thereto;
A write circuit provided corresponding to the bit line, holding write data to the memory cell during a write operation, and applying a stress voltage to the plurality of bit lines during a stress test of the memory cell;
A inhibit voltage supply circuit for generating a write inhibit voltage during a write operation;
In the write operation, the inhibit voltage supply circuit is controlled to apply the write inhibit voltage to the bit line in which all the connected memory cells are not selected for writing. And a control circuit for controlling the forbidden voltage supply circuit so as to be electrically disconnected from the bit line.

3. In the above 1 or 2, a memory cell array in which the memory cells are arranged in a matrix,
A plurality of word lines each commonly connecting the gates of the first MOS transistors of the memory cells located in the same row;
A row decoder for selecting any one of the word lines;
A column decoder for selecting any one of the bit lines, and in the stress test, the row decoder and the column decoder deselect all the word lines and the bit lines included in the memory cell array, The prohibit voltage supply circuit or the write circuit applies the stress voltage to all the bit lines included in the memory cell array.

4). In any one of 1 to 3, the prohibit voltage supply circuit or the write circuit can change the voltage value of the stress voltage to an arbitrary value, and the stress voltage includes the write inhibit voltage and the write circuit at the time of writing. Is different from the voltage applied to the bit line.

In addition, a test method for a nonvolatile semiconductor memory device according to the first to sixth embodiments of the present invention includes:
5). A test method for a semiconductor memory device including a first MOS transistor including a charge storage layer and a control gate, and including a plurality of memory cells for writing data by transferring electrons to the charge storage layer by FN tunneling,
Connecting a bit line that commonly connects one ends of current paths of the plurality of first MOS transistors, a write circuit that holds write data, and a inhibit voltage supply circuit that supplies a write inhibit voltage;
Disconnecting the bit line from the other of the write circuit and the forbidden voltage supply circuit;
Applying a stress voltage to the bit line from any one of the write circuit and the forbidden voltage supply circuit connected to the bit line.

6). In any one of 1 to 4, the stress voltage to be applied to the bit line by either the prohibit voltage supply circuit or the write circuit is external to either the prohibit voltage circuit or the write circuit. Can be applied.

7). In the above 1, the first switch element that connects the bit line and the write circuit;
A second switch element that connects the bit line and the forbidden voltage supply circuit; and the first switch element includes the bit line to which the selected memory cell is connected during the write operation and the write circuit. And connecting the plurality of bit lines and the write circuit during the stress test,
The second switch element connects the bit line to which the unselected memory cell is connected at the time of writing and the prohibit voltage supply circuit, and a plurality of the bit lines and the prohibit voltage supply circuit at the time of the stress test. Connect.

8). In the above item 2, the first switch element that connects the bit line and the write circuit;
A second switch element for connecting the bit line and the forbidden voltage supply circuit; and the first switch element connects the bit line to which the selected memory cell is connected during the writing and the write circuit. And connecting the plurality of bit lines and the write circuit during the stress test,
The second switch element connects the bit line to which the unselected memory cell is connected at the time of writing and the prohibit voltage supply circuit, and a plurality of the bit lines and the prohibit voltage supply circuit at the time of the stress test. Is disconnected.

9. In the above 1 or 2, a plurality of local bit lines each connected to one end of a current path of a first MOS transistor of a plurality of the memory cells;
A global bit line commonly connecting a plurality of the local bit lines;
A third switch element that connects the local bit line and the global bit line; and the write circuit is provided for each global bit line.

10. 9. In the above 9, the global bit line includes a write global bit line and a read global bit line,
The third switch element includes a fourth switch element that connects the write global bit line and the local bit line, and a fifth switch element that connects the read global bit line and the local bit line. ,
The write circuit is connected to the write global bit line;
A sense amplifier that is connected to the read global bit line and amplifies read data is further provided.

11. In the above 1 or 2, the memory cell further includes a second MOS transistor having one end of a current path connected to the other end of the current path of the first MOS transistor,
The bit line is connected to one end of the current path of the first MOS transistor;
The other ends of the current paths of the second MOS transistors are commonly connected to each other.

12 In 1 above, a negative voltage is applied to the bit line during the write operation, and a negative voltage is applied to the control gate of the first MOS transistor during the erase operation.

  Note that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention in the implementation stage. Furthermore, the above embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some constituent requirements are deleted from all the constituent requirements shown in the embodiment, the problem described in the column of the problem to be solved by the invention can be solved, and the effect described in the column of the effect of the invention Can be extracted as an invention.

1 is a block diagram of a flash memory according to a first embodiment of the present invention. 1 is a circuit diagram of a partial region of a flash memory according to a first embodiment of the present invention. 1 is a circuit diagram of a latch circuit included in a flash memory according to a first embodiment of the present invention. 1 is a plan view of a partial region of a memory cell array included in a flash memory according to a first embodiment of the present invention. FIG. 5 is a cross-sectional view taken along line X1-X1 ′ in FIG. 4. FIG. 5 is a cross-sectional view taken along line X1-X1 ′ in FIG. 4. 4 is a flowchart of the write operation of the flash memory according to the first embodiment of the present invention. FIG. 3 is a circuit diagram of a partial region of the flash memory according to the first embodiment of the present invention, showing a state during a write operation. FIG. 3 is a circuit diagram of a partial region of the flash memory according to the first embodiment of the present invention, showing a state during an erasing operation. FIG. 3 is a circuit diagram of a partial region of the flash memory according to the first embodiment of the present invention, showing a state during a read operation. 2 is a flowchart of a stress test operation of the flash memory according to the first embodiment of the present invention. FIG. 3 is a circuit diagram of a partial region of the flash memory according to the first embodiment of the present invention, showing a state during a stress test. FIG. 6 is a circuit diagram of a latch circuit and a booster circuit included in a flash memory according to a second embodiment of the present invention. 10 is a flowchart of a stress test operation of the flash memory according to the second embodiment of the present invention. FIG. 6 is a circuit diagram of a partial region of a flash memory according to a second embodiment of the present invention, showing a state during a stress test. The block diagram of the flash memory which concerns on 3rd Embodiment of this invention. The block diagram of the flash memory which concerns on 4th Embodiment of this invention. FIG. 10 is a circuit diagram of a latch circuit and a booster circuit included in a flash memory according to a fourth embodiment of the present invention. The block diagram of LSI provided with the flash memory which concerns on 5th Embodiment of this invention. 1 is a block diagram of a NAND flash memory. FIG. 3 is a block diagram of a 3Tr-NAND flash memory. It is a circuit diagram of the partial area | region of the flash memory based on 6th Embodiment of this invention, and shows the mode at the time of read-out operation | movement. The block diagram of the flash memory which concerns on the 1st modification of 1st thru | or 6th Embodiment of this invention. 10 is a flowchart of a stress test operation of the flash memory according to the first modification of the first to sixth embodiments of the present invention. The block diagram of the flash memory which concerns on the 2nd modification of 1st thru | or 6th Embodiment of this invention. The block diagram of the flash memory which concerns on the 3rd modification of 1st thru | or 6th Embodiment of this invention. FIG. 10 is a circuit diagram of a latch circuit and a booster circuit included in a flash memory according to a third modification of the first to sixth embodiments of the present invention. The block diagram of the flash memory which concerns on the 4th modification of 1st thru | or 6th Embodiment of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10, 500, 600 ... Flash memory, 20 ... Memory cell array, 30 ... Write selector, 31-34, 41-44, 51-54 ... MOS transistor, 40 ... Write prohibition selector, 50 ... Read selector, 60 ... Write decoder, 70 ... select gate decoder, 80 ... selector control circuit, 90 ... column decoder, 100 ... write circuit, 101 ... latch circuit, 102, 103 ... inverter, 110 ... sense amplifier, 120 ... source line driver, 130 ... Address buffer 140 ... Write inhibit voltage supply circuit 150 ... Control circuit 160, 170 ... Boost circuit 180, 181 ... Switch element 190 ... External input pin 700 ... MCU

Claims (5)

A plurality of memory cells including a first MOS transistor including a charge storage layer and a control gate, and writing data by transferring electrons to the charge storage layer by FN tunneling;
A plurality of bit lines each having one end of a current path of the plurality of first MOS transistors electrically connected thereto;
A write circuit provided corresponding to the bit line and holding write data to the memory cell;
A prohibit voltage supply circuit that generates a write inhibit voltage during a write operation and generates a stress voltage during a stress test of the memory cell;
At the time of the write operation, the inhibit voltage supply circuit is controlled so as to apply the write inhibit voltage to the bit line where all the connected memory cells are not selected for writing, and at the time of the stress test, And a control circuit that controls the forbidden voltage supply circuit to apply the stress voltage to a plurality of the bit lines. A plurality of memory cells including a first MOS transistor including a charge storage layer and a control gate, and writing data by transferring electrons to the charge storage layer by FN tunneling;
A plurality of bit lines each having one end of a current path of the plurality of first MOS transistors electrically connected thereto;
A write circuit provided corresponding to the bit line, holding write data to the memory cell during a write operation, and applying a stress voltage to the plurality of bit lines during a stress test of the memory cell;
A inhibit voltage supply circuit for generating a write inhibit voltage during a write operation;
In the write operation, the inhibit voltage supply circuit is controlled to apply the write inhibit voltage to the bit line in which all the connected memory cells are not selected for writing. And a control circuit for controlling the forbidden voltage supply circuit so as to be electrically disconnected from the bit line. A memory cell array in which the memory cells are arranged in a matrix;
A plurality of word lines each commonly connecting the gates of the first MOS transistors of the memory cells located in the same row;
A row decoder that selects any one of the word lines, and in the stress test, the row decoder deselects all the word lines included in the memory cell array, and The semiconductor memory device according to claim 1, wherein the write circuit applies the stress voltage to all the bit lines included in the memory cell array. The forbidden voltage supply circuit or the write circuit can change the voltage value of the stress voltage to an arbitrary value, and the stress voltage includes the write inhibit voltage and a voltage that the write circuit applies to the bit line at the time of writing. 4. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is a value different from A test method for a semiconductor memory device including a first MOS transistor including a charge storage layer and a control gate, and including a plurality of memory cells for writing data by transferring electrons to the charge storage layer by FN tunneling,
Connecting a bit line that commonly connects one ends of current paths of the plurality of first MOS transistors, a write circuit that holds write data, and a inhibit voltage supply circuit that supplies a write inhibit voltage;
Disconnecting the bit line from the other of the write circuit and the forbidden voltage supply circuit;
Applying a stress voltage to the bit line from any one of the write circuit and the forbidden voltage supply circuit connected to the bit line. A test method for a semiconductor memory device, comprising:

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