JP2005284088A - Flat panel display device and driving method for display - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To substantially eliminate luminance inclination resulting from wiring resistance of a scanning line. <P>SOLUTION: The flat panel display device is provided with a plurality of approximately parallel scanning lines Y, a plurality of signal lines X approximately perpendicular to the plurality of scanning line Y, a plurality of display pixels PX arranged near a cross position of the plurality of scanning lines Y and the plurality of signal lines X and each of which performs self-luminance in accordance with pixel voltage among each pair of scanning line Y and signal line X, a scanning line driving circuit 3 which sequentially drives the plurality of scanning line Y, and a signal line driving circuit 2 which drives the plurality of signal lines X during the driving of each of the plurality of scanning lines Y by the scanning line driving circuit 3. In particular, the scanning line driving circuit 3 is constituted so as to reverse distribution of voltage drop generated in wiring resistance of the plurality of scanning lines Y by emission current which emits the plurality of display pixels PX at least in one of units of the predetermined number of frames and the predetermined number of scanning lines. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a flat display device such as a field emission display (FED) in which a plurality of display pixels are configured using surface conduction electron-emitting devices, and a display driving method for the flat display device.

  The FED generally includes a display panel and a drive unit that drives the display panel. The display panel includes a plurality of scanning lines extending in the horizontal (horizontal) direction, a plurality of signal lines extending in the vertical (vertical) direction intersecting with the scanning lines, and a plurality of positions arranged at intersections of the scanning lines and the signal lines. Display pixels (see, for example, Patent Document 1). In a display panel for color display, for example, three display pixels adjacent in the horizontal direction are used as color display pixels. Each display pixel includes a surface conduction electron-emitting device and a red (R), green (G), or blue (B) phosphor that emits light by an electron beam emitted from the electron-emitting device.

  The driving unit includes a scanning line driving circuit connected to the plurality of scanning lines and a signal line driving circuit connected to the plurality of signal lines. Usually, the scanning line driving circuit sequentially drives a plurality of scanning lines using a scanning signal, and the signal line driving circuit uses a driving signal having a pulse width corresponding to the gradation level of the video signal while each scanning line is driven. A plurality of signal lines are driven. Each display pixel emits light with a luminance corresponding to the pixel voltage between the corresponding signal line and the corresponding scanning line.

By the way, each scanning line has a wiring resistance (that is, a distribution constant z), and generates a voltage drop that varies depending on the distance from the scanning line driving circuit. For this reason, for example, even if the display pixels of one horizontal line are driven corresponding to video signals of the same gradation level, these display pixels cannot emit light with a uniform luminance distribution. The effective value of the pixel voltage is higher as the display pixel is closer to the scanning line driving circuit and lower as the display pixel is farther from the scanning line driving circuit.
JP 2002-221933 A

  In recent years, a horizontally long display panel having an aspect ratio of horizontal: vertical = 16: 9 is becoming mainstream. In the case of such a screen size, since a large number of display pixels are connected to each scanning line, the influence of the wiring resistance of this scanning line cannot be ignored. For example, when the number of color display pixels is horizontal: vertical = 1280: 720, since 1280 × 3 (RGB) surface conduction electron-emitting devices are connected to each scanning line, a potential difference of at least 2 to 3 V is present. A voltage drop due to the wiring resistance occurs between both ends of the scanning line. This results in a luminance gradient in the display pixels arranged along the scanning line, and the display quality is remarkably lowered. For example, if the first and second scanning line drivers are respectively provided on the left end side and the right end side of a plurality of scanning lines, and both ends of each scanning line are simultaneously driven by these scanning line drivers, the center display farthest from these scanning line drivers is displayed. The distance to the pixel can be made almost half the length of the scanning line, so that the luminance gradient can be reduced. However, this brightness gradient cannot be eliminated.

  An object of the present invention is to provide a flat display device and a display driving method capable of substantially eliminating a luminance gradient due to wiring resistance of a scanning line.

  According to the present invention, a plurality of scanning lines that are substantially parallel to each other, a plurality of signal lines that are substantially orthogonal to the plurality of scanning lines, a plurality of scanning lines, and a plurality of signal lines that are disposed in the vicinity of the intersection positions, respectively. Each of the plurality of scanning lines is driven by the plurality of display pixels that emit light corresponding to the pixel voltage between the lines and the signal lines, the scanning line driving circuit that sequentially drives the plurality of scanning lines, and the scanning line driving circuit. A signal line driving circuit for driving a plurality of signal lines in between, and the scanning line driving circuit distributes a voltage drop distribution generated in the wiring resistance of the plurality of scanning lines by a light emission current that causes the plurality of display pixels to emit light in units of a predetermined number of frames. And a flat panel display configured to reverse at least one of the predetermined number of scanning lines.

  Further, according to the present invention, a plurality of substantially parallel scanning lines, a plurality of signal lines substantially orthogonal to the plurality of scanning lines, and a plurality of scanning lines and a plurality of signal lines are disposed in the vicinity of the intersection positions, and a pair of each. A display driving method for a flat panel display device including a plurality of display pixels including a surface conduction electron-emitting device that emits an electron beam corresponding to a pixel voltage between a scanning line and a signal line, A process of sequentially driving, and a process of driving a plurality of signal lines while each of the plurality of scanning lines is driven, and a plurality of processes for driving the plurality of scanning lines are performed by light emission currents that cause a plurality of display pixels to emit light. There is provided a display driving method which is performed so as to reverse the voltage drop distribution generated in the wiring resistance of the scanning lines at least one of the predetermined frame number unit and the predetermined scanning line number unit.

  In these flat display devices and display driving methods, the distribution of the voltage drop that occurs in the wiring resistance of the plurality of scanning lines due to the light emission current is reversed in at least one of the predetermined frame number unit and the predetermined scanning line number unit. The voltage drop distribution is reflected in the luminance distribution of the display pixels lined up along each scanning line, but the luminance difference of these display pixels is averaged by reversing the voltage drop distribution, and the observer can see the actual luminance. I can't feel the difference. Therefore, it is possible to substantially eliminate the luminance gradient due to the wiring resistance of the scanning line.

  Hereinafter, a flat display device according to a first embodiment of the present invention will be described with reference to the drawings. This flat display device is, for example, a field emission display (FED) device having the number of color display pixels of 1280 × 720.

  FIG. 1 schematically shows a circuit configuration of the flat display device. The flat display device includes a display panel 1, a signal line driving circuit 2, a scanning line driving circuit 3, and a video signal processing circuit 4. The display panel 1 has substantially parallel m (= 720) scanning lines Y (Y1 to Ym) extending in the horizontal (horizontal) direction, and n (extending in the vertical (vertical) direction substantially orthogonal to the scanning lines Y1 to Ym. = 1280 × 3) signal lines X (X1 to Xn), and m × n (= about 2.76 million) display pixels PX arranged at the intersections of the scanning lines Y1 to Ym and the signal lines X1 to Xn including. Each color display pixel is constituted by three display pixels PX adjacent in the horizontal direction. In this color display pixel, the three display pixels PX emit red light (R), green (G), and blue (B) emitted by the surface conduction electron-emitting devices 11 and the electron beams emitted from the electron-emitting devices 11, respectively. Of the phosphor 12. Each scanning line Y is used as a scanning electrode connected to the electron emitting element 11 of the display pixel PX on the corresponding horizontal line, and each signal line X is used as a signal electrode connected to the electron emitting element 11 of the display pixel PX on the corresponding column. Used.

  The signal line driving circuit 2, the scanning line driving circuit 3, and the video signal processing circuit 4 are arranged around the display panel 1 as a display driving unit, and are controlled by, for example, an external timing controller (not shown). The video signal processing circuit 4 processes an RGB video signal supplied from an external signal source in a digital format. The scanning line driving circuit 3 sequentially drives the scanning lines Y1 to Ym using the scanning signal, and the signal line driving circuit 2 is a video signal processing circuit while each of the scanning lines Y1 to Ym is driven by the scanning line driving circuit 3. 4 to drive the signal lines X1 to Xn. The scanning line driving circuit 3 includes first and second scanning line drivers 3A and 3B disposed on the left end side and the right end side of the scanning lines Y1 to Ym, for example. Each of the scanning line drivers 3A and 3B and the signal line driving circuit 2 is formed as a driver IC. The scanning line driver 3A is connected to the left end of the odd-numbered scanning lines Y1, Y3, Y5,..., Ym-1, and the second scanning line driver 3B is the right end of the even-numbered scanning lines Y2, Y4, Y6,. Connected to.

  The video signal processing circuit 4 detects the average level by summing up the levels of the RGB video signals for one frame in order to uniformly reduce the luminance of, for example, an image pattern having a large area of high luminance, and based on the average level. The RGB video signal is adjusted and supplied to the signal line driving circuit 2.

  In the signal line driving circuit 2, the video signal is sequentially sampled from the signal line X1 side in response to the data clock signal DCK supplied in synchronization with the video signal from the timing controller, and the pulse width corresponding to each sample result. Are converted into n PWM drive signals. These PWM drive signals are simultaneously supplied to the signal lines X1 to Xn in response to the load signal LD supplied in synchronization with the horizontal synchronization signal from the timing controller.

  In FIG. 1, z is a wiring resistance distributed in each of the scanning lines Y1 to Ym, i11 to imn are light emission currents that flow when m × n surface conduction electron-emitting devices 11 are discharged, and Vy is scanning. The output terminal voltages of the line drive circuit 3 are ΔV1 to ΔVm, which are voltage drops caused by the emission current flowing through the wiring resistances of the scanning lines Y1 to Ym when the n surface conduction electron-emitting devices 11 are discharged. It is the total value.

These ΔV1, ΔV2, ΔV3,... ΔVm have the following values.

ΔV1 = z × i11 + 2 × z × i12 + − − − − + n × z × i1n
ΔV2 = z × i21 + 2 × z × i22 + − − − − + n × z × i2n
ΔV3 = z × i31 + 2 × z × i32 + − − − − + n × z × i3n
ΔVm = z × im1 + 2 × z × im2 ++ − − − − + n × z × imn
When the display pixels PX of each horizontal line are driven via the signal lines X1 to Xn, light emission currents flow through the electron-emitting devices 11 of the display pixels PX except for those that display black among the display pixels PX, Further, all of these light emission currents flow to the scanning line driving circuit 3 through one scanning line Y. Specifically, assuming that the maximum current of each display pixel PX is 500 μA at maximum, the current becomes 1.92 A in total.

  The display pixels PX farther from the scanning line drivers 3A and 3B are affected by voltage drops ΔV1 to ΔVm depending on the wiring resistance and the light emission current. When the total wiring resistance of each scanning line Y is 4Ω and the voltage drop is simply obtained by current (1.92A) × wiring resistance (4Ω), this voltage drop is 7.68V. Actually, since the wiring resistance and current are dispersed, it becomes about 2V. If there is such a voltage drop, the pixel voltage applied to the surface conduction electron-emitting device 11 is lowered, and the original light emission ability cannot be exhibited.

  Here, each of the scanning line drivers 3A and 3B reverses the distribution of the voltage drop generated in the wiring resistance of the plurality of scanning lines Y by a light emission current that causes the plurality of display pixels PX to emit light in units of a predetermined number of scanning lines. Composed. Specifically, the scanning line driver 3A drives odd-numbered scanning lines Y1, Y3, Y5,... Ym-1 from the left end, and the scanning line driver 3B scans even-numbered scanning lines Y2, Y4, Y6,. Drive from the right end.

  In the conversion from the video signal to the PWM drive signal, as shown in FIG. 2, the pulse width of the drive signal is set to 0 for the 0th gray level where the video signal is the minimum gray level, And set to T times j times the j-th gradation. If the video signal is in 1024 stages from the 0th gray level to the 1023rd gray level, the pulse width of the PWM drive signal is 1 horizontal scanning period even when the video signal is the 102nd gray level, which is the maximum gray level. For example, a period equal to 1/1023 of the effective video period in one horizontal scanning period is set in advance.

  The scanning line drivers 3A and 3B are connected to m / 2 output terminals connected to the left ends of the scanning lines Y1, Y3, Y5,..., Ym-1, respectively, and to the right ends of Y2, Y4, Y6,. The output terminals are respectively selected, m / 2 output terminals are sequentially selected, and a scanning signal is output from the selected output terminals. Here, the start signal ST is supplied in synchronization with the vertical synchronization signal from the above-described timing controller to start scanning from the scanning line Y1 and scanning line Y2, respectively, and the enable signal EN is used to control whether output is possible. The clock signal CK is supplied from the timing controller and is supplied from the timing controller every two horizontal scanning periods in order to shift the scanning position to the next line.

  The scanning signal is a negative voltage Vyon supplied from the scanning voltage terminal, and is output only for one horizontal scanning period as shown in FIG. In each electron-emitting device 11, discharge occurs when the sum of the voltage Vx (= Vref + ΔV) of the signal electrode and the voltage Vy of the scanning electrode exceeds the threshold, and the electron beam emitted thereby causes the phosphor 12 to be discharged. Excited. Note that in order to sequentially drive the scanning lines Y1 to Ym by one horizontal scanning period, the start signal ST, the clock signal CK, and the enable signal EN are shifted from each other by one horizontal scanning period to the scanning line driver 3A and the scanning line driver 3B. Supplied.

In the flat display device of this embodiment, the distribution of the voltage drop generated in the wiring resistance z of the plurality of scanning lines Y by the light emission current is reversed in units of a predetermined number of scanning lines. That is, the voltage drop distribution shown in FIG. 3 occurs in the odd-numbered scanning lines Y1, Y3, Y5,..., Ym−1, and the voltage drop distribution shown in FIG. ..., occurs at Ym. The voltage drop distribution is reflected in the luminance distribution of the display pixels PX arranged along each scanning line Y. The luminance difference of these display pixels PX is averaged as shown in FIG. 5 by reversing the voltage drop distribution. The observer cannot perceive the actual brightness difference. Therefore, the luminance gradient due to the wiring resistance z of the scanning line can be substantially eliminated. In the above-described configuration, the scanning line driver 3A drives the odd-numbered scanning lines Y1, Y3, Y5,. Since Ym is driven, the number of output channels of the scanning line driver 3A and the scanning line driver 3B can be halved as compared with the case where each of the scanning lines Y1, Y2, Y3,. The circuit scale can be reduced and the cost can be reduced. Further, when the scanning line driver 3A and the scanning line driver 3B are configured by a plurality of driver ICs, the number of ICs used can be halved, so that the cost can be reduced.
In the first embodiment, the predetermined number of scanning lines is set to one, and the voltage drop distribution is divided into odd-numbered scanning lines Y1, Y3, Y5,... Ym-1 and even-numbered scanning lines Y2, Y4. Y6,..., Ym are mutually reversed, but if the total number of scanning lines Y is extremely large, the same effect can be obtained even if the predetermined number of scanning lines is set to two or more.

  Next, a flat display device according to a second embodiment of the present invention will be described with reference to the drawings.

FIG. 6 schematically shows a circuit configuration of the flat display device. This flat display device is configured in the same manner as in the first embodiment except for the configuration of the scanning line driving circuit 3. For this reason, in FIG. 6, the same part as 1st Embodiment is represented by the same referential mark, and the detailed description is abbreviate | omitted.

  Similarly to the first embodiment, the scanning line driving circuit 3 is added to the first and second scanning line drivers 3A and 3B and the scanning line drivers 3A and 3 disposed on the left end side and the right end side of the scanning lines Y1 to Ym, respectively. First and second switch circuits 3SA and 3SB. The scanning line drivers 3A and 3B cooperate with the switch circuits 3SA and 3SB to distribute a voltage drop distribution generated in the wiring resistances of the plurality of scanning lines Y by a light emission current that causes the plurality of display pixels PX to emit light. The reversing is performed in units of the number of scanning lines and the reversing is performed in units of a predetermined number of frames of one frame. The scanning line driver 3A and the switch circuit 3SA are driver units on the left end side of the scanning lines Y1 to Ym, and the scanning line driver 3B and the switch circuit 3SB are driver units on the right end side of Y1 to Ym.

  Each of the scanning line drivers 3A and 3B is a driver IC having m / 2 output terminals, and sequentially selects m / 2 output terminals and outputs a scanning signal from the selected output terminals. Here, the start signal ST is supplied in synchronization with the vertical synchronization signal from the above-described timing controller to start scanning from the scanning line Y1 and scanning line Y2, respectively, and the enable signal EN is used to control whether output is possible. The clock signal CK is supplied from the timing controller and is supplied from the timing controller every two horizontal scanning periods in order to shift the scanning position to the next line. The switch circuit 3SA connects the output end of the scanning line driver 3A to the left end of odd-numbered scanning lines Y1, Y3, Y5,..., Ym-1 or the left end of even-numbered scanning lines Y2, Y4, Y6,. The switch circuit 3SB includes an output terminal of the scanning line driver 3B at the right end of the odd-numbered scanning lines Y1, Y3, Y5,..., Ym-1 or the even-numbered scanning line Y2, M / 2 changeover switches 33 connected to the right ends of Y4, Y6,. The changeover switch 33 of the switch circuit 3SA is controlled by a changeover signal S supplied from the timing controller, and the changeover switch 33 of the switch circuit 3SB is controlled by a changeover signal S bar supplied from the timing controller and an inverted signal of the changeover signal S. The These switching signals S and S bar are inverted every frame period (vertical scanning period), and are supplied continuously for this one frame period.

  In one of the two adjacent frame periods, as shown in FIG. 7, the switch circuit 3SA assigns the scanning line driver 3A to the odd-numbered scanning lines Y1, Y3, Y5,. The driver 3B is assigned to even-numbered scanning lines Y2, Y4, Y6,. Thus, the scanning line driver 3A drives the odd-numbered scanning lines Y1, Y3, Y5,..., Ym-1 from the left end, and the scanning line driver 3B scans the even-numbered scanning lines Y2, Y4, Y6,. Drive from the right end. That is, the scanning lines Y1, Y2, Y3,..., Ym are sequentially driven by scanning signals supplied alternately from the scanning line drivers 3A and 3B.

  In the other of the two adjacent frame periods, as shown in FIG. 8, the switch circuit 3SA assigns the scanning line driver 3A to the even-numbered scanning lines Y2, Y4, Y6,..., Ym, and the switch circuit 3SB uses the scanning line driver 3B. Are assigned to odd-numbered scanning lines Y1, Y2, Y3, Y5,. Accordingly, the scanning line driver 3A drives even-numbered scanning lines Y2, Y4, Y6,..., Ym from the left end, and the scanning line driver 3B scans odd-numbered scanning lines Y1, Y3, Y5,. Drive from the right end. That is, the scanning lines Y1, Y2, Y3,..., Ym are sequentially driven by the scanning signals supplied alternately from the scanning line drivers 3B and 3A.

  The scanning signal is a negative voltage Vyon supplied from the scanning voltage terminal, and is output only for one horizontal scanning period as described in the first embodiment. In each electron-emitting device 11, discharge occurs when the sum of the voltage Vx (= Vref + ΔV) of the signal electrode and the voltage Vy of the scanning electrode exceeds the threshold, and the electron beam emitted thereby causes the phosphor 12 to be discharged. Excited. Note that in order to sequentially drive the scanning lines Y1 to Ym by one horizontal scanning period, the start signal ST, the clock signal CK, and the enable signal EN are shifted from each other by one horizontal scanning period to the scanning line driver 3A and the scanning line driver 3B. Supplied.

  In the flat display device of this embodiment, the distribution of the voltage drop generated in the wiring resistance z of the plurality of scanning lines Y due to the light emission current is reversed in units of a predetermined number of scanning lines of one, and further reversed in units of a predetermined number of frames of one frame. To do. That is, in one frame, a voltage drop distribution similar to that in FIG. 3 occurs in odd-numbered scanning lines Y1, Y3, Y5,..., Ym−1, and a voltage drop distribution similar to FIG. It occurs on the lines Y2, Y4, Y6,. Further, in the other frame, the same voltage drop distribution as in FIG. 3 is generated in the even-numbered scanning lines Y2, Y4, Y6,... Ym, and the voltage drop distribution similar to FIG. , Y3, Y5,..., Ym−1.

The voltage drop distribution is reflected in the luminance distribution of the display pixels PX arranged along each scanning line Y. The luminance difference between the display pixels PX is the same as that shown in FIG. Similarly averaged. In particular, when the predetermined scanning line number unit and the predetermined frame number unit are combined as described above, the observer cannot perceive an actual luminance difference at all. Accordingly, it is possible to substantially eliminate the luminance gradient caused by the wiring resistance z of the scanning line with higher accuracy than in the first embodiment. Also, since the output fraction of the scanning line driver 3A and the scanning line driver 3B is m / 2 with respect to all the scanning lines Y1, Y2, Y3,..., Ym, the circuit scale of the driver IC is the same as in the first embodiment. Can be reduced.

  In the second embodiment, the predetermined number of scanning lines is set to one, and the voltage drop distribution is divided into odd-numbered scanning lines Y1, Y3, Y5,..., Ym-1 and even-numbered scanning lines Y2, Y4. Y6,..., Ym are mutually reversed, but if the total number of scanning lines Y is extremely large, the same effect can be obtained even if the predetermined number of scanning lines is set to two or more. In addition, the predetermined number of frames is set to one frame, and the voltage drop distribution is reversed between two adjacent frames. However, if the frame frequency is extremely high, the same can be said even if the predetermined number of frames is set to two or more. The effect of can be obtained.

  The switch circuits 3SA and 3SB are added outside the scanning line driver 3A and the scanning line driver 3B, but may be provided in the scanning line driver 3A and the scanning line driver 3B.

  Next, a flat display device according to a third embodiment of the present invention will be described with reference to the drawings.

FIG. 9 schematically shows a circuit configuration of the flat display device. This flat display device is configured in the same manner as in the first embodiment except for the configuration of the scanning line driving circuit 3. For this reason, in FIG. 9, the same part as 1st Embodiment is represented by the same referential mark, and the detailed description is abbreviate | omitted.

  Similarly to the first embodiment, the scanning line driving circuit 3 includes first and second scanning line drivers 3A and 3B arranged on the left end side and the right end side of the scanning lines Y1 to Ym, respectively. These scanning line drivers 3A and 3B are each configured to reverse the distribution of the voltage drop generated in the wiring resistance of the plurality of scanning lines Y by a light emission current that causes the plurality of display pixels PX to emit light in units of a predetermined number of frames of one frame. . The first scanning line driver 3A is connected to the left end of all the scanning lines Y1, Y2, Y3, Y4, Y5,..., Ym-1, Ym, and these scanning lines Y1, Y2, Y3, Y4, Y5,. −1, Ym are driven from the left end. The second scanning line driver 3B is connected to the right end of all the scanning lines Y1, Y2, Y3, Y4, Y5,..., Ym-1, Ym, and these scanning lines Y1, Y2, Y3, Y4, Y5,. −1, Ym are driven from the right end.

  The scanning line drivers 3A and 3B have m output ends connected to the left ends of the scanning lines Y1, Y2, Y3, Y4, Y5..., Ym−1, Ym, respectively, and the scanning lines Y1, Y2, Y3, Y4, Y5. , Ym−1, and Ym, respectively, have output terminals connected to the right ends, respectively, and sequentially select m output ends, and output scanning signals from the selected output ends. Here, the start signal ST is supplied in synchronization with the vertical synchronization signal from the above-described timing controller to start scanning from the scanning line Y1 and scanning line Y2, respectively, and the enable signal EN is used to control whether output is possible. The clock signal CK is supplied from the timing controller and is supplied from the timing controller every horizontal scanning period in order to shift the scanning position to the next line.

  In one of the two adjacent frame periods, the start signal ST, the clock signal CK, and the enable signal EN are supplied from the timing controller to the scanning line driver 3A. Accordingly, the scanning line driver 3A is assigned to all the scanning lines Y1, Y2, Y3, Y4, Y5,..., Ym−1, Ym. FIG. 10 shows a state in which the scanning line driver 3A is assigned to all the scanning lines Y1, Y2, Y3, Y4, Y5,..., Ym−1, Ym in one of the two adjacent frame periods. The scanning lines Y1, Y2, Y3, Y4, Y5,..., Ym-1, Ym are sequentially driven by the scanning line driver 3A in this state.

  In the other of the two adjacent frame periods, the start signal ST, the clock signal CK, and the enable signal EN are supplied from the timing controller to the scanning line driver 3B. Accordingly, the scanning line driver 3B is assigned to all the scanning lines Y1, Y2, Y3, Y4, Y5,..., Ym−1, Ym. FIG. 11 shows a state in which the scanning line driver 3B is assigned to all the scanning lines Y1, Y2, Y3, Y4, Y5,..., Ym−1, Ym in the other of the two adjacent frame periods. The scanning lines Y1, Y2, Y3, Y4, Y5,..., Ym-1, Ym are sequentially driven by the scanning line driver 3B in this state.

  The scanning signal is a negative voltage Vyon supplied from the scanning voltage terminal, and is output only for one horizontal scanning period as described in the first embodiment. In each electron-emitting device 11, discharge occurs when the sum of the voltage Vx (= Vref + ΔV) of the signal electrode and the voltage Vy of the scanning electrode exceeds the threshold, and the electron beam emitted thereby causes the phosphor 12 to be discharged. Excited.

  In the flat display device of this embodiment, the distribution of the voltage drop generated in the wiring resistance z of the plurality of scanning lines Y by the light emission current is reversed in units of a predetermined number of frames of one frame. That is, in one frame, the same voltage drop distribution as in FIG. 3 occurs in all the scanning lines Y1, Y2, Y3, Y4, Y5,. Further, in the other frame, the same voltage drop distribution as in FIG. 4 occurs in all the scanning lines Y1, Y2, Y3, Y4, Y5,.

  The voltage drop distribution is reflected in the luminance distribution of the display pixels PX arranged along each scanning line Y. The luminance difference between the display pixels PX is the same as that shown in FIG. Similarly, it is averaged and the observer cannot perceive any actual brightness difference. Therefore, as in the first embodiment, the luminance gradient due to the wiring resistance z of the scanning line can be substantially eliminated.

  In the third embodiment, the predetermined number of frames is set to 1 frame, and the voltage drop distribution is reversed between two adjacent frames. However, when the frame frequency is extremely high, the predetermined number of frames is 2 frames or more. The same effect can be obtained even if set to.

  The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention.

  In each of the embodiments described above, the signal line X is driven by the pulse width modulation driving method using the driving signal having a variable pulse width. However, the signal line X is driven by the voltage amplitude driving method using the driving signal having a variable voltage amplitude. It may be driven. Further, a pulse width modulation driving method and a voltage amplitude driving method may be used in combination. In this case, a drive signal whose pulse width and voltage amplitude are variable is supplied to the signal line X.

  In each embodiment, the flat display device is a field emission display (FED) device having, for example, a horizontal display size of 1280 × vertical 720, but the present invention has a color display pixel count of, for example, horizontal 1920 ×. The present invention can also be applied to an FED apparatus having a vertical length of 1080.

1 is a diagram schematically showing a circuit configuration of a flat display device according to a first embodiment of the present invention. It is a figure which shows the PWM drive signal generate | occur | produced in the drive signal generation part shown in FIG. It is a figure which shows distribution of the voltage drop which arises in the wiring resistance of the odd-numbered scanning line shown in FIG. It is a figure which shows distribution of the voltage drop which arises in the wiring resistance of the even-numbered scanning line shown in FIG. FIG. 5 is a diagram illustrating a distribution of pixel luminances averaged by combining the voltage drop distributions illustrated in FIGS. 3 and 4. It is a figure which shows roughly the circuit structure of the flat display apparatus which concerns on 2nd Embodiment of this invention. FIG. 7 is a diagram illustrating a state in which the first and second scanning line drivers illustrated in FIG. 6 are assigned to odd-numbered scanning lines and even-numbered scanning lines, respectively. FIG. 7 is a diagram illustrating a state in which the first and second scanning line drivers illustrated in FIG. 6 are assigned to even-numbered scanning lines and odd-numbered scanning lines, respectively. It is a figure which shows roughly the circuit structure of the flat display apparatus which concerns on 3rd Embodiment of this invention. FIG. 10 is a diagram illustrating a state where the first scanning line driver illustrated in FIG. 9 is assigned to all scanning lines. FIG. 10 is a diagram illustrating a state in which the second scanning line driver illustrated in FIG. 9 is assigned to all scanning lines.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Display panel, 2 ... Signal line drive circuit, 3 ... Scan line drive circuit, 3A ... 1st scan line driver, 3B ... 2nd scan line driver, 3SA ... 1st switch circuit, 3SB ... 2nd switch circuit, 4 DESCRIPTION OF SYMBOLS ... Image signal processing circuit, 11 ... Surface conduction electron-emitting device, 12 ... Phosphor, 33 ... Changeover switch, X ... Signal line, Y ... Scanning line, PX ... Display pixel.

Claims (12)

A plurality of scanning lines that are substantially parallel, a plurality of signal lines that are substantially orthogonal to the plurality of scanning lines, and a pair of scanning lines and signals that are disposed in the vicinity of intersections of the plurality of scanning lines and the plurality of signal lines, respectively. Each of the plurality of scanning lines is driven by the plurality of display pixels that self-emit according to the pixel voltage between the lines, the scanning line driving circuit that sequentially drives the plurality of scanning lines, and the scanning line driving circuit. A signal line driving circuit for driving the plurality of signal lines in between, and the scanning line driving circuit has a distribution of voltage drops generated in wiring resistances of the plurality of scanning lines by a light emission current that causes the plurality of display pixels to emit light. A flat display device configured to reverse at least one of a predetermined frame number unit and a predetermined scanning line number unit. The scanning line driving circuit includes: a first driver unit that drives an odd-numbered scanning line of the plurality of scanning lines from one end side; and an even-numbered scanning line of the plurality of scanning lines from the other end side. The flat display device according to claim 1, further comprising a second driver unit to be driven. The scanning line driving circuit drives a plurality of scanning lines from one end side in one of the two adjacent frame periods, and drives the plurality of scanning lines from the other end in the other of the two adjacent frame periods. The flat display device according to claim 1, further comprising: a second driver unit that performs the following operation. The scanning line driving circuit drives an odd-numbered scanning line of the plurality of scanning lines from one end side in one of the two adjacent frame periods and an even number of the plurality of scanning lines in the other of the two adjacent frame periods. A first driver section for driving the second scanning line from the one end side, and the second adjacent frame period by driving an even-numbered scanning line of the plurality of scanning lines from the other end side in one of the two adjacent frame periods. 2. The flat display device according to claim 1, further comprising: a second driver unit that drives an odd-numbered scanning line of the plurality of scanning lines from the other end side. The flat display device according to claim 1, wherein at least one of the predetermined number of frames and the predetermined number of scanning lines is two or more. The flat display device according to claim 1, wherein the display pixel is a surface conduction electron-emitting device that emits an electron beam. A plurality of scanning lines that are substantially parallel, a plurality of signal lines that are substantially orthogonal to the plurality of scanning lines, and a pair of scanning lines and signals that are disposed in the vicinity of intersections of the plurality of scanning lines and the plurality of signal lines, respectively. A display driving method for a flat panel display device including a plurality of display pixels including a surface conduction electron-emitting device that emits an electron beam in response to a pixel voltage between lines, and sequentially driving the plurality of scanning lines And a process of driving the plurality of signal lines while each of the plurality of scanning lines is driven, and the process of driving the plurality of scanning lines is performed by a light emission current that causes the plurality of display pixels to emit light. The display driving method, wherein the distribution of the voltage drop generated in the wiring resistance of the plurality of scanning lines is reversed so as to reverse at least one of a predetermined frame number unit and a predetermined scanning line number unit. In the process of driving the plurality of scanning lines, the odd-numbered scanning lines of the plurality of scanning lines are driven from one end side, and the even-numbered scanning lines of the plurality of scanning lines are driven from the other end side. The display driving method according to claim 7, further comprising: In the process of driving the plurality of scanning lines, the plurality of scanning lines are driven from one end in one of the two adjacent frame periods, and the plurality of scanning lines are driven from the other end in the other of the two adjacent frame periods. The display driving method according to claim 7, further comprising a process. The process of driving the plurality of scanning lines drives an odd-numbered scanning line and an even-numbered scanning line of the plurality of scanning lines in one adjacent frame period from one end side and the other end side, respectively. 8. The method includes driving an odd-numbered scan line and an even-numbered scan line of the plurality of scan lines from the other end side and the one end side, respectively, in the other of two adjacent frame periods. The display driving method described in 1. The display driving method according to claim 7, wherein at least one of the predetermined number of frames and the predetermined number of scanning lines is two or more. The display driving method according to claim 7, wherein the display pixel is a surface conduction electron-emitting device that emits an electron beam.

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