JP2005268278A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device in which arriving time difference of clock can be suppressed between respective flip-flops, arriving time of a clock signal being inputted to the flip-flop can be shorted, and the flip-flop, other cell and normal signal line can be arranged efficiently on a semiconductor chip. <P>SOLUTION: The semiconductor device has a multilayer wiring layer consisting of clock wiring 3 and 6 for supplying a clock signal to a cell arranged on a semiconductor chip, and power supply wiring 1, 2, 4 and 5 for supplying a power supply voltage to the cells arranged on the opposite sides of the clock wiring 3 and 6 wherein the clock wiring 3 and 6 arranged, respectively, on the opposing wiring layers are connected at arbitrary intersecting position 13. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device.

  In the conventional semiconductor device, a cell and a flip-flop connected to the cell are arranged on a semiconductor chip in consideration of the function, and a clock wiring is arranged between the clock input terminal and the flip-flop. At this time, by arranging the clock wiring in a tree shape while making the resistance value and capacitance parasitic to the clock wiring uniform, a clock arrival time difference between the flip-flops does not occur in the clock signal input to each flip-flop. I have done so.

  FIG. 9 is a structural diagram of a conventional clock wiring disclosed in Japanese Patent Laid-Open No. 7-86416. 9, 10, and 11, 7 is a clock input terminal, 10 is a drive buffer, 17 is an H-type basic wiring for clock wiring, and 18 is an I-type basic wiring for clock wiring.

  The H-type basic wiring 17 having flip-flops connected to the four corners and the driving buffer 10 are combined and arranged at a desired location according to the cells arranged in consideration of the function, and the I-type basic wiring 18 is arranged in a plurality of H-types. The basic wiring 17 is arranged to be connected. In FIG. 9, the H-type basic wiring including the drive buffer is arranged in the area surrounded by the broken line B. Similarly, after the H-type basic wiring is arranged in the other three places, the driving buffer is included in the area surrounded by the broken line C. By arranging the I-type basic wiring 18, two H-type basic wirings 17 are connected. Two I-type basic wirings 18 connected to two H-type basic wirings 17 are further connected by another I-type basic wiring 18 to be connected to each H-type basic wiring 17 from the clock input terminal 7. The tree-like clock wiring to each flip-flop is realized.

  Even if the number of necessary flip-flops increases, the H-type basic wiring 17 and the I-type basic wiring 18 are increased, and the connection between the H-type basic wiring 17 and the I-type basic wiring 18 is repeated, so that A tree-like clock wiring connection to each flip-flop connected to the H-type basic wiring 17 can be realized.

  In the conventional semiconductor device, the lengths of the wirings constituting the H-type basic wiring 17 and the I-type basic wiring 18 are made constant, and the connection locations of the H-type basic wiring 17 and the I-type basic wiring 18 are defined as the basic wiring. It is characterized by making the length of the clock wiring from the clock input terminal to each flip-flop constant. By doing so, the resistance value parasitic to the clock wiring from the clock input terminal to each flip-flop becomes constant, and the clock arrival time difference between the flip-flops does not occur in the clock signal input to each flip-flop. I have done it.

JP-A-7-86416

  However, in the conventional method, since the clock wiring is arranged adjacent to the normal signal line, the capacitance parasitic to the clock wiring differs depending on the arrangement position of the clock wiring, and a clock arrival time difference occurs between each flip-flop. There is a problem of end up.

  Further, when the number of H-type basic wirings 17 and I-type basic wirings 18 increases as the circuit scale increases, the number of clock wirings increases. This causes wiring congestion, and cells, flip-flops, and normal signal lines cannot be efficiently arranged on the semiconductor chip.

  Further, when the number of flip-flops to which a clock signal is to be supplied increases and the number of H-type basic wirings 17 and I-type basic wirings 18 increases, the resistance value and the capacitance parasitic on the clock wiring increase. As the number of drive buffers increases, the number of drive buffers 10 required to supply a clock signal must be increased. As the resistance value and capacity increase, at the same time, the number of drive buffers through which the clock signal passes increases, so that the delay of the clock signal increases. Therefore, the flip-flop to which the clock signal should be supplied to the tree-like clock wiring When the number of the clocks increases, there is a problem that the clock arrival time from the clock input terminal to the flip-flop increases.

  When the clock arrival time is long, the operation characteristics of the semiconductor device are likely to vary, and the semiconductor device may not operate at a desired timing. The tree-like clock wiring in the conventional semiconductor device has a structure in which the clock arrival time increases as the chip size increases, and as a result, the semiconductor device is likely to malfunction.

  The present invention solves the above-described conventional problems, and an object thereof is to provide a semiconductor device that can suppress a clock arrival time difference between flip-flops.

  Another object of the present invention is to provide a semiconductor device capable of efficiently arranging flip-flops, other cells, and normal signal lines on a semiconductor chip without complicating clock wiring.

  It is another object of the present invention to provide a semiconductor device that can shorten the clock arrival time of a clock signal input to a flip-flop.

  The semiconductor device of the present invention includes a clock wiring for supplying a clock signal to a cell disposed on a semiconductor chip, and a power wiring for supplying a power supply voltage to the cell, disposed on both sides of the clock wiring.

  According to this configuration, the power supply wirings on both sides protect the clock wiring from capacitance fluctuations caused by the adjacent normal signal lines, so that the clock arrival time difference in each flip-flop can be suppressed.

  In addition, the semiconductor device of the present invention includes a wiring layer having a laminated structure including the clock wiring and the power supply wiring.

  According to this configuration, cells and normal signal lines can be efficiently arranged on the semiconductor chip without being restricted by the arrangement of the clock wiring and the power supply wiring.

  In the semiconductor device of the present invention, clock wirings arranged in each of the opposing wiring layers are connected at an arbitrary crossing position.

  According to this configuration, by shortening the distance from the clock input terminal to the flip-flop and reducing the resistance value, it is possible to shorten the clock arrival time until the clock signal arrives from the clock input terminal to the flip-flop. .

  In the semiconductor device of the present invention, the wiring layer is divided into a plurality of blocks.

  According to this configuration, clock signals can be input to the cells constituting the plurality of blocks on the semiconductor chip at different timings.

  In addition, the semiconductor device of the present invention includes a gate connected to each block.

  According to this configuration, by controlling the timing at which the gate outputs the clock signal, the clock signal can be input to the cells constituting the plurality of blocks on the semiconductor chip at different timings.

  The semiconductor device of the present invention can suppress a clock arrival time difference between flip-flops due to the influence of adjacent normal signal lines.

  In addition, the semiconductor device of the present invention can efficiently arrange cells and normal signal lines on a semiconductor chip.

  In addition, the semiconductor device of the present invention can suppress problems caused in the semiconductor device by reducing the clock arrival time of the clock signal input to the flip-flop.

Hereinafter, a first embodiment according to the present invention will be described.
FIG. 1 is a structural diagram of a clock wiring according to the first embodiment of the present invention. In FIG. 1, 1 is an even layer power wiring VSS, 2 is an even layer power wiring VDD, 3 is an even layer clock wiring, 4 is an odd layer power wiring VSS, 5 is an odd layer power wiring VDD, and 6 is an odd layer clock wiring. A power supply voltage or a clock signal is supplied to cells arranged on the semiconductor chip. The even layer and the odd layer are arranged so that the directions of the wirings arranged in the even layer and the odd layer are 90 degrees different from each other, and are laminated so as to form a mesh shape in which the wirings of the respective layers intersect. Has been. In addition, a layer in which an even layer and an odd layer composed of clock wiring and power supply wiring are stacked is an upper layer, and a layer composed of flip-flops, other cells, and normal signal lines is a lower layer.

  The even layer power line VSS1 and the even layer power line VDD2 are arranged on both sides of the even layer clock line 3 so as to sandwich the even layer clock line 3 therebetween. Further, the odd layer power wiring VSS4 and the odd layer power wiring VDD5 are arranged so as to sandwich the odd layer clock wiring 6 on both sides of the odd layer clock wiring 6. As a result, the clock wirings 3 and 6 prevent the increase in the capacity of the clock wirings 3 and 6 due to the normal signal lines adjacent to the power supply wirings VSS1 and 4 and the power supply wirings VDD2 and 5, so Therefore, the difference in clock arrival time between the flip-flops can be suppressed.

  FIG. 2 is an enlarged view of a region A surrounded by a broken line in the enlarged view of the structure of the clock wiring in FIG. In FIG. 2, reference numeral 11 denotes a connection portion between the even-numbered power supply wiring VSS1 and odd-numbered power supply wiring VSS4, 12 denotes a connection location between the even-numbered power supply wiring VDD2 and odd-numbered power supply wiring VDD5, and 13 denotes an even-numbered layer crossing. This is a connection point between the clock wiring 3 and the odd-numbered clock wiring 6.

  As described above, the clock wirings 3 and 6 and the power supply wirings VSS1 and 4 and VDD2 and 5 of the even-numbered layer and odd-numbered layer are connected at the intersecting points, so that the clock signal and power The voltage can be shared. Compared to the clock wiring arranged in a tree shape, the clock wiring stacked in this mesh shape has a shorter wiring path distance from the clock input terminal to the flip-flop. Can be small. Therefore, an increase in clock arrival time due to an increase in resistance value can be minimized, and at the same time, the number of drive buffers 10 required can be reduced by minimizing the resistance value. Can be suppressed.

  FIG. 3 is a structural diagram of the clock wiring of the first embodiment according to the present invention. In FIG. 3, reference numeral 14 in FIG. 3 denotes a flip-flop.

  As shown in FIG. 3, since the mesh-shaped clock wirings 3 and 6 are disposed on the entire surface of the semiconductor chip, the flip-flop 14 disposed on the semiconductor chip and the clock wirings 3 and 6 are connected to each other by the flip-flop 14. Wirings can be arranged where the distance between the arrangement location and the clock wirings 3 and 6 is the shortest. In the lower layer, the wiring region connecting the flip-flop 14 and the clock wirings 3 and 6 can be minimized without being congested. Therefore, cells and normal signals are placed on the semiconductor chip without being restricted by the arrangement of the clock wiring. Lines can be arranged efficiently.

  According to the first embodiment of the present invention, the clock arrival time difference between the flip-flops can be suppressed by making the capacitance parasitic to the clock wiring constant regardless of the arrangement position of the clock wiring. In addition, by suppressing the resistance value parasitic on the clock wiring to a minimum, an increase in clock arrival time can be suppressed to a minimum. In addition, cells and normal signal lines can be efficiently arranged on the semiconductor chip without being restricted by the arrangement of the clock wiring and the power supply wiring.

  In the first embodiment according to the present invention, even-numbered wiring lines 1, 2, and 3 are arranged in the depth direction of FIG. 1, and odd-numbered wiring lines 4, 5, and 6 are arranged in the left-right direction. Although the structure has been described, as shown in the structure diagram of the clock wiring of the first embodiment according to the present invention in FIG. The same effect can be obtained even if the clock wiring structures are arranged in the depth direction, respectively.

  Further, in the first embodiment according to the present invention, the even layer and the odd layer are laminated so as to form a mesh shape in which the directions of the wirings arranged in the even layer and the odd layer are different by 90 degrees. However, the layer is not limited to 90 degrees, and can be stacked to form various mesh shapes that suppress an increase in clock arrival time.

  Further, in the first embodiment according to the present invention, as shown in the structural diagram of the clock wiring of the first embodiment according to the present invention in FIG. When the drive capacity of the drive buffer 10 is insufficient with respect to the load due to the scale, the drive capacity can be increased and dealt with by adding the drive buffer 10 in parallel.

  FIG. 6 is a structural diagram showing the clock wiring when the clock wiring of the second embodiment according to the present invention branches into a plurality of parts inside the semiconductor device. In FIG. 6, 7 is a clock input terminal, and 15 is a cell arrangement block by function. In FIG. 6, only the clock wirings 3 and 6 are illustrated to facilitate understanding of the structure of the clock wiring, and the power supply wirings VSS1 and 4 and the power supply wirings VDD2 and 5 are not illustrated. The power supply lines VSS1, 4 and the power supply lines VDD2, 5 may be disposed on both sides of the clock lines 3, 6 as described in the first embodiment.

  As described in the first embodiment, the mesh-shaped clock wiring has a structure that can minimize a clock arrival time difference between clock signals input to cells on a semiconductor chip. In some cases, the clock signal must be input with a clock arrival time difference from other blocks. In the second embodiment, in such a case, even if the mesh-shaped clock wiring is suitable for inputting the clock signal to all cells at the same timing, the clock signal is sent to a specific block at different timings. The clock wiring that can be input will be described.

  Here, as shown in FIG. 6, the even-numbered clock wiring 3 and the odd-numbered clock wiring 6 are divided at the end face of the function-specific cell arrangement block 15 to provide a specific function-specific cell arrangement block that needs to have a clock arrival time difference. Only the tree-like clock wiring branched from the clock wiring connected to the clock input terminal is connected to 15.

  As described above, by using the conventional tree-shaped clock wiring having the disadvantage that the clock arrival time difference becomes large, the mesh-shaped clock wiring 3 suitable for inputting the clock signal to all the cells at the same timing, Even if the timing is 6, the timing of the clock signal input to the function-specific cell arrangement block 15 can be changed intentionally.

  In the second embodiment according to the present invention, the even-numbered clock wiring and odd-numbered clock wiring connected to the clock input terminal are divided at the end face of the cell placement block by function, and the clock wiring on which a desired branch is performed is functioned. By connecting to another cell arrangement block, clock wiring combining a mesh shape and a tree shape is realized. As a result, a clock signal having a timing different from that of other function-specific cell arrangement blocks can be input to the function-specific cell arrangement block.

  In the second embodiment according to the present invention, the branch from the clock wiring connected to the clock input terminal has been described. However, the present invention is not limited to this. For example, the clock wiring of one function-specific cell arrangement block has another function. It is also possible to branch to the clock wiring of another cell arrangement block.

  FIG. 7 is a structural diagram showing clock wiring when there are a plurality of clock input terminals according to the third embodiment of the present invention. In FIG. 7, 8 is a second clock input terminal, and 9 is a third clock input terminal. In FIG. 7, only the clock wirings 3 and 6 are illustrated in order to facilitate understanding of the structure of the clock wiring, and the power supply wirings VSS1 and 4 and the power supply wirings VDD2 and 5 are not illustrated. The power supply lines VSS1, 4 and the power supply lines VDD2, 5 may be disposed on both sides of the clock lines 3, 6 as described in the first embodiment.

  When it is necessary to input a clock signal having a timing different from the clock signal from the clock input terminal 7 to the function-specific cell arrangement block 15, the even-numbered clock wiring 3 and the odd-numbered clock wiring 6 are connected to the function-specific cell arrangement block 15. By dividing at the end face and connecting the clock wiring from the second clock input terminal 8 to the cell placement block 15 by function, a clock signal having a timing different from that of the clock signal input to the other cell placement block by function is obtained. Then, the data is input from the clock input terminal 8 to the cell placement block 15 by function.

  In the third embodiment according to the present invention, a clock signal is input to a specific block at a different timing even if the clock wiring has a mesh shape suitable for inputting the clock signal to all cells at the same timing. Therefore, the even-numbered clock wiring and the odd-numbered clock wiring are divided at the end face of the function-specific cell arrangement block, and one clock wiring from a plurality of clock input terminals is connected to the function-specific cell arrangement block. As a result, it is possible to input a clock signal having a timing different from that of the other function-specific cell arrangement block to the function-specific cell arrangement block.

  Similarly, a clock signal is input from the third clock input terminal 9 to another function-specific cell arrangement block, or the clock wiring connected to the clock input terminal 7 is branched as in the second embodiment. It is also possible to input a clock signal to the function-specific cell arrangement block.

  FIG. 8 is a structural diagram showing the clock wiring when the clock wiring of the fourth embodiment according to the present invention branches into a plurality of parts inside the semiconductor device and a gate is inserted into a part of the clock wiring. In FIG. 8, 16 is a gate for outputting an input clock signal at an arbitrary timing, and 10 is a drive buffer. In FIG. 8, only the clock wirings 3 and 6 are illustrated in order to make it easy to grasp the structure of the clock wiring, and the power supply wirings VSS1 and 4 and the power supply wirings VDD2 and 5 are not illustrated. The power supply lines VSS1, 4 and the power supply lines VDD2, 5 may be disposed on both sides of the clock lines 3, 6 as described in the first embodiment.

  When the function-specific cell arrangement block 15 requires different clock signal input timings from other function-specific cell arrangement blocks, the even-numbered clock wiring 3 and the odd-numbered clock wiring 6 are connected to the end faces of the function-specific cell arrangement block 15. The clock signal output from the gate 16 is input to the function-specific cell arrangement block 15 by being connected to the clock wirings 3 and 6 via the drive buffer 10 and the gate 16 arranged on the semiconductor chip.

  In the fourth embodiment of the present invention, a clock signal is input to a specific block at different timings even if the clock wiring has a mesh shape suitable for inputting the clock signal to all cells at the same timing. For this purpose, the even-numbered clock wiring and the odd-numbered clock wiring are divided at the end faces of the cell-by-function block, and connected to the clock wiring via the drive buffer and gate arranged on the semiconductor chip. Thus, by controlling the timing at which the gate outputs the clock signal, it becomes possible to input the clock signal to the function-specific cell arrangement block at a different timing from other function-specific cell arrangement blocks.

  In the fourth embodiment according to the present invention, the even-numbered clock wiring 3 and the odd-numbered clock wiring 6 have been described as being divided by the end face of the function-specific cell arrangement block 15, but the clock wiring is as shown in FIG. In the case of three or more layers, the clock wiring of the uppermost layer is left undivided, the clock wiring of layers other than the uppermost layer is divided, and the clock wiring of the uppermost layer and the layers below it are further divided. Similarly, the clock signal output from the gate 16 can be input to the functional cell placement block 15 by deleting the connection portion 13 (see FIG. 2) with the clock wiring.

  Even if the resistance value of the clock wiring connected to the functional cell placement block increases by inserting the gate by leaving the clock wiring of the uppermost layer without being divided in this way, other cell placement by function is possible. The resistance value of the clock wiring connected to the block can be suppressed.

  The semiconductor device of the present invention can suppress a clock arrival time difference between flip-flops due to the influence of adjacent normal signal lines.

  In the semiconductor device of the present invention, since the clock wiring is not complicated, cells and normal signal lines can be efficiently arranged on the semiconductor chip without being restricted by the arrangement of the clock wiring and the power supply wiring. .

  In addition, the semiconductor device of the present invention can prevent a malfunction of the semiconductor device by shortening the clock arrival time of the clock signal input to the flip-flop.

  Further, the semiconductor device of the present invention can input a clock signal to a specific block at different timings even if the clock wiring has a mesh shape suitable for inputting the clock signal to all cells at the same timing. .

  For this reason, a great effect is brought about in improving the reliability of the semiconductor device and preventing wiring congestion in the semiconductor device.

Structure of clock wiring of the first embodiment according to the present invention Enlarged view of region A surrounded by a broken line in the enlarged view of the structure of the clock wiring in FIG. Structure of clock wiring of the first embodiment according to the present invention Structure of clock wiring of the first embodiment according to the present invention Structure of clock wiring of the first embodiment according to the present invention FIG. 6 is a structural diagram showing clock wiring when the clock wiring of the second embodiment according to the present invention branches into a plurality of parts inside the semiconductor device; Structural diagram showing clock wiring when there are a plurality of clock input terminals according to the third embodiment of the present invention FIG. 6 is a structural diagram showing a clock wiring when the clock wiring of the fourth embodiment according to the present invention branches into a plurality of portions inside the semiconductor device and a gate is inserted into a part of the clock wiring. Structure of conventional clock wiring Structure of conventional clock wiring H-type basic wiring (enlarged view of B) Structure diagram of conventional clock wiring I type basic wiring (enlarged view of C)

Explanation of symbols

1 Even layer power supply wiring VSS
2 Even layer power supply wiring VDD
3 Even layer clock wiring 4 Odd layer power wiring VSS
5 Odd layer power supply wiring VDD
6 Odd layer clock wiring 7 First clock input terminal 8 Second clock input terminal 9 Third clock input terminal 10 Driving buffer 11 Even layer power supply line VSS 1 and odd layer power supply line VSS 4 connection point 12 Even layer power supply line VDD 2 And the odd-numbered power line VDD5 connection point 13 The even-numbered clock line 3 and odd-numbered clock line 6 connection point 14 Flip-flop 15 Cell placement block 16 by function Gate 17 inserted into the clock signal H-type basic wiring 18 I Type basic wiring 19 Tree-shaped wiring

Claims (5)

A clock wiring for supplying a clock signal to cells arranged on the semiconductor chip;
A power supply wiring disposed on both sides of the clock wiring for supplying a power supply voltage to the cell;
A semiconductor device comprising:   The semiconductor device according to claim 1, further comprising a wiring layer having a laminated structure including the clock wiring and the power supply wiring.   The semiconductor device according to claim 2, wherein clock wirings arranged in each of the opposing wiring layers are connected at an arbitrary intersection position.   The semiconductor device according to claim 3, wherein the wiring layer is divided into a plurality of blocks.   The semiconductor device according to claim 4, further comprising a gate connected to each block.

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