JP2005235244A - Semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device resistant to being influenced by an external magnetic field. <P>SOLUTION: In this MRAM, a tunnel magneto-resistance element 21 ia connected across a memory node N1 and the ground potential line GND; two tunnel magneto-resistance elements 22, 23 are connected in parallel across a memory node N2 and the ground potential line GND; and a data "1" or a data "0" is stored depending on whether or not the magnetic tunnel junction of the tunnel magneto-resistance element 21 is damaged. Therefore, the storage data are not damaged by the influence of the external magnetic field. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device including a plurality of magnetoresistive elements.

  In recent years, MRAM (Magnetic Random Access Memory) using a magnetoresistive element has attracted attention as a memory that can store nonvolatile data with low power consumption. FIG. 6 is a circuit block diagram showing a configuration of a memory cell 51 of a conventional MRAM.

  6, memory cell 51 is arranged at the intersection of word line WL and digit line DL, bit line pair BL, / BL, and write bit line pair WBL, / WBL, and P channel MOS transistors 52, 53. N channel MOS transistors 54 to 59 and tunnel magnetoresistive elements 60 and 61 are included.

  When signal EN is set to “H” level to make N channel MOS transistors 58 and 59 conductive and write bit lines WBL and / WBL are set to “L” level, memory cell 51 has the same configuration as that of the SRAM memory cell. . For example, data “1” is stored by holding “H” level and “L” level in storage nodes N51 and N52, respectively, and “L” level and “H” level are held in storage nodes N51 and N52, respectively. Thus, data “0” is stored. The signal write / read operation of storage nodes N51 and N52 is performed in the same manner as a normal SRAM (Static Random Access Memory).

  When the signals of the storage nodes N51 and 52 are written to the tunnel magnetoresistive elements 60 and 61, the signals of the storage nodes N51 and N52 are once read to the outside through the bit line pair BL and / BL, and then a dedicated write circuit. Is used to pass a predetermined current through the digit line DL and the write bit lines WBL, ZWBL to write signals to the tunnel magnetoresistive elements 60, 61. The resistance value of each of the tunnel magnetoresistive elements 60 and 61 becomes a value corresponding to the logic level of the written signal, and does not change even when the power supply voltage VDD is cut off.

When power supply voltage VDD is cut off and turned on again, signal EN is set to “H” level to set write bit lines WBL, / WBL to “L” level. As a result, a difference occurs in the current driving force that lowers the storage nodes N51 and N52 to the “L” level due to the difference in the resistance values of the tunnel magnetoresistive elements 60 and 61, and a signal of a logic level corresponding to this difference becomes a storage node N1. , N2. Therefore, this MRAM operates as a non-volatile memory (see, for example, US Pat. No. 6,304,477).
US Pat. No. 6,304,477

  However, since the conventional MRAM stores data by applying a magnetic field to the tunnel magnetoresistive element 60 or 61 and changing the resistance value of the tunnel magnetoresistive element 60 or 61, the stored data is affected by the influence of the external magnetic field. It was sometimes destroyed.

  Further, since the difference between the resistance values of the tunnel magnetoresistive elements 60 and 61 is only about 20%, the noise resistance at the time of data reading was weak.

  Further, since the resistance values of the tunnel magnetoresistive elements 60 and 61 are changed using a large current of about 10 mA flowing through the N channel MOS transistors 56 to 59, the size of the N channel MOS transistors 56 to 59 is increased, and the memory cell 51 The layout area of was large.

  In the initial state, the data stored in the memory cell 51 is indefinite, and cannot be used unless some initial data is written in the memory cell 51.

  SUMMARY OF THE INVENTION Therefore, a main object of the present invention is to provide a semiconductor memory device that is not easily affected by an external magnetic field, has high noise resistance, has a small layout area, and does not require separate writing of initial data.

  The semiconductor memory device according to the present invention includes a first magnetoresistive element connected between a first storage node and a reference potential line, and a parallel connection between a second storage node and the reference potential line. A plurality of connected second magnetoresistive elements, and when the magnetic tunnel junction of the first magnetoresistive element is broken, the first logic signal is stored, and the magnetic tunnel of the first magnetoresistive element is stored. If the junction is not broken, the storage portion for storing the second logic signal and the write potential is applied to the first storage node during the write operation to destroy the magnetic tunnel junction of the first magnetoresistive element And a write circuit that makes the resistance value of the first magnetoresistive element smaller than the resistance value of the parallel connection body of the plurality of second magnetoresistive elements, and the resistance value of the first magnetoresistive element during the read operation. The resistance value of the parallel connection of the plurality of second magnetoresistive elements And, those having a reading read circuit of the first or second logic signal stored in the storage unit based on the comparison result.

  In the semiconductor memory device according to the present invention, the first magnetoresistive element is connected between the first storage node and the reference potential line, and a plurality of the second storage node and the reference potential line are connected. By connecting the second magnetoresistive elements in parallel, destroying the magnetic tunnel junction of the first magnetoresistive element, storing the first logic signal, and not destroying the magnetic tunnel junction of the first magnetoresistive element A second logic signal is stored. Therefore, since data is stored depending on whether or not the magnetic tunnel junction of the first magnetoresistive element is broken, the data is not destroyed by the external magnetic field. Further, the breakdown of the magnetic tunnel coupling causes the resistance value of the first magnetoresistive element to be about 1/10, and the difference between the resistance value of the first magnetoresistive element and the resistance value of the second magnetoresistive element is twice or more. Therefore, the noise tolerance during the read operation is strong. Further, since the write current only needs to flow through the first magnetoresistive element, the number of transistors through which the write current flows can be reduced, and the layout area can be reduced. Further, in the initial state where the magnetic tunnel junction of the first magnetoresistive element is not destroyed, the resistance value of the first magnetoresistive element is always larger than the resistance value of the second magnetoresistive element. There is no need to write separately.

  FIG. 1 is a circuit diagram showing a main part of an MRAM according to an embodiment of the present invention. 1, this MRAM includes a pair of bit lines BL, / BL, an N channel MOS transistor 1 and a P channel MOS transistor 2. Transistors 1 and 2 constitute an equalizer. N channel MOS transistor 1 is connected between bit lines BL and / BL, and has a gate receiving bit line equalize signal EQ. P channel MOS transistor 2 is connected between bit lines BL and / BL, and has a gate receiving inverted signal / EQ of bit line equalize signal EQ.

  When bit line equalize signal EQ is at the “H” level of the activation level, transistors 1 and 2 are turned on, and bit lines BL and / BL are set to the same potential. When bit line equalize signal EQ is set to the “L” level of the inactivation level, transistors 1 and 2 are rendered non-conductive, and equalization of bit lines BL and / BL is stopped.

  The MRAM includes N channel MOS transistors 3 and 4 and NOR gates 5 and 6. N-channel MOS transistors 3 and 4 and NOR gates 5 and 6 constitute a write driver. The sources of N channel MOS transistors 3 and 4 both receive ground potential GND, and their drains are connected to bit lines / BL and BL, respectively. NOR gate 5 receives inverted signal / DI of write data signal DI and first write instruction signal / WE1, and its output signal is input to the gate of N channel MOS transistor 3. NOR gate 6 receives write data signal DI and first write instruction signal / WE 1, and its output signal is input to the gate of N channel MOS transistor 4.

  When write data signal DI is at "H" level, when signal / WE1 is set to activation level "L", the output signal of NOR gate 5 is raised to "H" level and N channel MOS Transistor 3 becomes conductive, and bit line / BL is set to ground potential GND. When write data signal DI is at "L" level, when signal / WE1 is set to activation level "L", the output signal of NOR gate 6 is raised to "H" level and N channel MOS Transistor 4 becomes conductive, and bit line / BL is set to ground potential GND.

  The MRAM includes P channel MOS transistors 7 and 8 and N channel MOS transistors 9 to 15. Transistors 7 to 11 constitute a sense amplifier. The sources of P channel MOS transistors 7 and 8 both receive power supply potential VDD (for example, 1.2 V), their sources are connected to bit lines / BL and BL, respectively, and their gates are connected to bit lines BL and / BL, respectively. Connected. N channel MOS transistors 9 and 10 have drains connected to bit lines / BL and BL, sources connected to node N11, and gates connected to bit lines BL and / BL, respectively. N channel MOS transistor 11 is connected between node N11 and a line of ground potential GND, and the gate thereof receives sense amplifier activation signal SE.

  When sense amplifier activation signal SE is set to the “H” level of the activation level, N channel MOS transistor 11 is rendered conductive and the sense amplifier is activated. When the potential of the bit line / BL is lower than that of the bit line BL, the resistance value of the transistors 8 and 9 is smaller than the resistance value of the transistors 7 and 10, the potential of the bit line / BL is pulled down to the ground potential GND, The potential of the bit line BL is raised to the power supply potential VDD. When the potential of the bit line / BL is higher than that of the bit line BL, the resistance value of the transistors 7 and 10 becomes smaller than the resistance value of the transistors 8 and 9, and the potential of the bit line / BL is raised to the power supply potential VDD. The potential of bit line BL is pulled down to ground potential GND.

  When sense amplifier activation signal SE is set to the “L” level of the inactivation level, N channel MOS transistor 11 is rendered non-conductive, and the sense amplifier is deactivated. However, when the bit lines BL and / BL are connected by the equalizer, the bit lines BL and / BL are set to the power supply potential VDD via the P-channel MOS transistors 7 and 8. When bit line / BL is set to "L" level by the write driver, P channel MOS transistor 8 is rendered conductive, bit line BL is set to power supply potential VDD, and bit line BL is set to "L" level. Channel MOS transistor 7 is turned on to set bit line / BL to power supply potential VDD.

  The drains of N channel MOS transistors 12 and 13 are connected to bit lines / BL and BL, respectively, and their gates both receive signal EN. The drains of N channel MOS transistors 14 and 15 are connected to the sources of N channel MOS transistors 12 and 13, respectively, their gates both receive reference potential VR, and their sources are connected to storage nodes N1 and N2, respectively.

  When signal EN is set to “H” level, N channel MOS transistors 12 and 13 are turned on, and when signal EN is set to “L” level, N channel MOS transistors 12 and 13 are turned off. The reference potential VR is set to 0V or 0.8V. When reference potential VR is set to 0V, N channel MOS transistors 14 and 15 are rendered non-conductive. When reference potential VR is set to 0.8 V, even when bit lines / BL and BL are set to power supply potential VDD and N channel MOS transistors 12 and 13 are turned on, the potentials at storage nodes N1 and N2 are the reference potential. It is limited to a potential obtained by subtracting the threshold voltage (0.4 V) of N-channel MOS transistors 14 and 15 from VR, that is, a potential of 0.8V−0.4V = 0.4V or less.

  The MRAM further includes an N channel MOS transistor 16, an AND gate 17, and tunnel magnetoresistive elements 21-23. N channel MOS transistor 16 is connected between a line of external power supply potential ExVDD (for example, 3 V) and storage node N1. AND gate 17 receives potential VBL of bit line BL and second write instruction signal WE 2, and its output signal is applied to the gate of N channel MOS transistor 16.

  When the potential VBL of the bit line BL is set to the “H” level (power supply potential VDD) and the second write instruction signal WE2 is set to the activation level “H” level, the N-channel MOS transistor 16 becomes conductive, External power supply potential ExVDD is applied to storage node N1.

  As shown in FIG. 2, the tunnel magnetoresistive element 21 is formed on the surface of the electrode 25, the fixed magnetization layer 26, the tunnel barrier layer 27, the free magnetization layer 28, and the free magnetization layer 28 that are sequentially stacked on the surface of the electrode 25. And the formed electrode 29. The fixed magnetization layer 26 is a ferromagnetic layer having a fixed fixed magnetization direction. The tunnel barrier layer 27 is formed of an insulator film. The free magnetic layer 28 is a ferromagnetic layer that is magnetized in a direction corresponding to an externally applied magnetic field. These pinned magnetic layer 26, tunnel barrier layer 27, and free magnetic layer 28 form a magnetic tunnel junction. Electrode 25 receives ground potential GND, and electrode 29 is connected to storage node N1.

  The free magnetic layer 28 is magnetized in the same direction as the fixed magnetic layer 26 or in the opposite direction by applying a strong magnetic field when the tunnel magnetoresistive element 21 is manufactured. The electric resistance value between the electrodes 25 and 29 is about 30 KΩ when the magnetization directions of the free magnetic layer 28 and the fixed magnetic layer 26 are the same, and when the magnetization directions of the free magnetic layer 28 and the fixed magnetic layer 26 are opposite to each other. It becomes about 36KΩ. Here, it is assumed that the magnetization directions of the free magnetic layer 28 and the fixed magnetic layer 26 are the same. When a high voltage is applied between the electrodes 25 and 29, the magnetic tunnel junction is broken, and the electric resistance value between the electrodes 25 and 29 is reduced to about 3 KΩ. The tunnel magnetoresistive elements 22 and 23 have the same configuration as the tunnel magnetoresistive element 21.

  Tunnel magnetoresistive element 21 is connected between storage node N1 and the ground potential GND line, and tunnel magnetoresistive elements 22 and 23 are connected in parallel between storage node N2 and the ground potential GND line. Therefore, when the magnetic tunnel junction of tunneling magneto-resistance element 21 is not broken, resistance value R1 between storage node N1 and the ground potential GND line is 30 KΩ, and storage node N2 and the ground potential GND line The resistance value R2 between the two is 15 KΩ, and R1> R2. When the magnetic tunnel junction of the tunnel magnetoresistive element 21 is broken, the resistance value R1 between the storage node N1 and the line of the ground potential GND becomes 3 KΩ, and the magnitude relationship between R1 and R2 is reversed and R2> R1. Become. Therefore, the storage unit including the tunnel magnetoresistive elements 21 to 23 has the first state of R1> R2 and the second state of R2> R1, and the data “0” and the data “1” of the data “0” depending on the first state. One data can be stored, and the other data can be stored according to the second state.

  Next, the operation of this MRAM will be described. FIG. 3 is a diagram showing an operation of latching the write data signal DI in the sense amplifier. Signals EN, EQ, and WE2 are all fixed at “L” level, and VR is fixed at 0V. Now, it is assumed that write data signal DI is at “H” level. At a certain time, sense amplifier activation signal SE falls to “L” level, which is an inactivation level, and N channel MOS transistor 11 is rendered non-conductive. Then, when first write instruction signal / WE1 is lowered to the “L” level of the activation level, N channel MOS transistor 3 is rendered conductive, and the potential of bit line / BL is lowered, via P channel MOS transistor 8. Thus, the potential of the bit line BL is raised. Next, when sense amplifier activation signal SE is raised to "H" level, N channel MOS transistor 11 is rendered conductive to activate the sense amplifier, and the potentials of bit lines BL and / BL are set to "H" level and " Latched to “L” level. When the first write instruction signal / WE1 is raised to the “H” level of the inactivation level, the write operation is finished. When write data signal DI is at “L” level, the potentials of bit lines BL and / BL are similarly latched at “L” level and “H” level, respectively.

  FIG. 4 is a diagram illustrating an operation for destroying the magnetic tunnel junction of the tunnel magnetoresistive element 21. Signals EN and EQ are both fixed at "L" level, signal / WE1 is fixed at "H" level, and VR is fixed at 0V. Now, it is assumed that the potential VBL of the bit line BL is set to the “H” level. When second write instruction signal WE2 rises to "H" level at a certain time, the output signal of AND gate 17 rises to "H" level, and N channel MOS transistor 16 becomes conductive, and storage node N1 is turned on. An external power supply potential ExVDD is applied. Thereby, the magnetic tunnel junction of the tunnel magnetoresistive element 21 is broken, and the resistance value R1 of the tunnel magnetoresistive element 21 is reduced from 30 KΩ to 3 KΩ. When second write instruction signal WE2 falls to "L" level, the output signal of AND gate 17 falls to "L" level, N channel MOS transistor 16 becomes non-conductive, and the write operation is completed. To do. When the potential VBL of the bit line BL is set to “L” level, the output signal of the AND gate 17 remains at “L” level even when the second write data signal WE2 is set to “H” level. Since the N channel MOS transistor 16 is not conductive, the magnetic tunnel junction of the tunnel magnetoresistive element 21 is not destroyed.

  FIG. 5 is a time chart showing an operation of reading data stored in the tunnel magnetoresistive elements 21 to 23 to the sense amplifier. Signal / WE1 is fixed at “H” level, and signal WE2 is fixed at “L” level. Now, the magnetic tunnel junction of the tunnel magnetoresistive element 21 is broken, the resistance value R1 between the storage node N1 and the ground potential GND line becomes 3KΩ, and between the storage node N2 and the ground potential GND line. The resistance value R2 is 15 KΩ, and R2> R1. When sense amplifier activation signal SE is lowered to "L" level and bit line equalize signal EQ is raised to "H" level of the activation level at a certain time, transistors 1 and 2 are turned on, and P channel The potentials of bit lines BL and / BL are equalized to “H” level via MOS transistors 7 and 8.

  When signal EN is raised to “H” level after reference potential VR is set to 0.8 V, N channel MOS transistors 12 and 13 are turned on, N bit MOS transistors 12 and 14 from bit line / BL, storage node Charge flows out to the ground potential GND line via N1 and tunnel magnetoresistive element 21, and ground potential from bit line BL via N channel MOS transistors 13 and 15, storage node N2 and tunnel magnetoresistive elements 22 and 23. Charge flows out to the GND line. At this time, the potentials of storage nodes N1 and N2 are limited to 0.4 V or less by N channel MOS transistors 14 and 15, and tunnel magnetoresistive elements 21 to 23 are prevented from being destroyed by the potentials of storage nodes N1 and N2. The If the potentials of the storage nodes N1 and N2 at this time are too low, the sense amplifier may not operate normally because the potential difference between the bit lines BL and / BL is too small.

  Here, since R2> R1, the potential of the bit line / BL is lower than the potential of the bit line BL. Next, signal EN is set to “L” level, N-channel MOS transistors 12 and 13 are rendered non-conductive, sense amplifier activation signal SE is set to “H” level to activate the sense amplifier, and bit lines BL, The potential of / BL is latched at the “H” level and “L” level, respectively. The reference potential VR is set to 0V and the reading operation is completed. That is, the equalizer, the sense amplifier, and the N channel MOS transistors 12 to 15 constitute a read circuit, and compares the resistance value R1 of the tunnel magnetoresistive element 21 with the resistance value R2 of the parallel connection body of the tunnel magnetoresistive elements 22 and 23. Then, data “1” or data “0” stored in the tunnel magnetoresistive elements 21 to 23 is read based on the comparison result. When R1> R2, the potentials of bit lines BL and / BL are latched at “L” level and “H” level, respectively.

  In this embodiment, the tunnel magnetoresistive element 21 is connected between the storage node N1 and the line of the ground potential GND, and two tunnel magnetoresistive elements 22 and 22 are connected between the storage node N2 and the line of the ground potential GND. 23 are connected in parallel, and data “1” or data “0” is stored depending on whether or not the magnetic tunnel junction of the tunnel magnetoresistive element 21 is broken. Therefore, the stored data is not destroyed by the influence of the external magnetic field.

  Further, when the magnetic tunnel junction of the tunnel magnetoresistive element 21 is not broken, the resistance value R1 between the storage node N1 and the ground potential GND line is 30 KΩ, and the storage node N2 and the ground potential GND line The resistance value R2 between the two is 15 KΩ, and R1 is twice R2. When the magnetic tunnel junction of the tunnel magnetoresistive element 21 is broken, the resistance value R1 between the storage node N1 and the line of the ground potential GND becomes 3KΩ, and R2 becomes five times R1. Therefore, noise resistance during the read operation is strong, and the data stored in the tunnel magnetoresistive elements 21 to 23 can be read stably.

  Further, since the write current only needs to flow through the tunnel magnetoresistive element 21, the number of transistors 16 through which the write current flows can be reduced, and the layout area can be reduced.

  In the initial state in which the magnetic tunnel junction of the tunnel magnetoresistive element 21 is not destroyed, the resistance value R1 between the storage node N1 and the ground potential GND line is always equal to the storage node N2 and the ground potential GND line. Since the initial data is determined to be larger than the resistance value R2, the initial data need not be written separately.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

It is a circuit diagram which shows the principal part of MRAM by one Embodiment of this invention. It is sectional drawing which shows the structure of the tunnel magnetoresistive element shown in FIG. 3 is a time chart showing an operation of latching a write data signal in a sense amplifier in the MRAM shown in FIG. 2 is a time chart showing an operation of destroying a magnetic tunnel junction of a tunnel magnetoresistive element in the MRAM shown in FIG. 1. 2 is a time chart showing an operation of latching data stored in tunnel magnetoresistive elements 21 to 23 in a sense amplifier in the MRAM shown in FIG. It is a circuit diagram which shows the principal part of the conventional MRAM.

Explanation of symbols

  1, 3, 4, 9-16, 54-59 N-channel MOS transistor, 2, 52, 53 P-channel MOS transistor, 5, 6 NOR gate, 17 AND gate, 21-23, 60, 61 tunnel magnetoresistive element, 25, 29 electrodes, 26 fixed magnetic layer, 27 tunnel barrier layer, 28 free magnetic layer.

Claims (4)

A semiconductor memory device,
A first magnetoresistive element connected between the first storage node and the reference potential line; and a plurality of second magnetism connected in parallel between the second storage node and the reference potential line. When the magnetic tunnel junction of the first magnetoresistive element is broken, the first logic signal is stored, and the magnetic tunnel junction of the first magnetoresistive element is not broken Is a storage unit for storing the second logic signal,
During a write operation, a write potential is applied to the first storage node to break the magnetic tunnel junction of the first magnetoresistive element, and the resistance value of the first magnetoresistive element is set to the plurality of second magnetoresistive elements. And a write circuit for making the resistance value of the parallel connection body of the plurality of magnetoresistive elements smaller than the resistance value of the parallel connection body of the plurality of second magnetoresistance elements. A semiconductor memory device comprising a read circuit that compares values and reads the first or second logic signal stored in the storage unit based on the comparison result. And a first data line and a second data line,
The writing circuit includes:
A first driving circuit for setting one data line of the first and second data lines to a first potential and setting the other data line to a second potential in accordance with a write data signal; A second drive circuit for applying the write potential to the first storage node in response to a preselected data line of the first and second data lines being set to the first potential; The semiconductor memory device according to claim 1. And a first data line and a second data line,
The readout circuit includes:
An equalizer for setting the first and second data lines to the same potential;
A switching circuit for connecting the first and second data lines, which are set to the same potential by the equalizer, to the first and second storage nodes, respectively, and a potential difference generated between the first and second data lines. The semiconductor memory device according to claim 1, comprising an amplifier circuit for amplifying.   The read circuit further includes a protection circuit for preventing a magnetic tunnel junction of the first and second magnetoresistive elements from being broken by a potential of the first and second data lines. 4. The semiconductor memory device according to 3.

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