JP2005217471A - Cmos image sensor difference signal detecting circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a difference signal detecting circuit for a CMOS image sensor which is suitably used for a monitoring camera for detecting movement of a monitored image in a still state or a digital video camera requiring movement detection to correct camera shake, detects a difference image signal with a previous frame, requires a small circuit scale, and can generate a large variation part with less saturation even if the level of an optical input signal is set at a value near 100%. <P>SOLUTION: Configuration of a pixel of a CMOS image sensor comprises a photodiode and two memories, electric charges of an optical signal input accumulated as an image pickup signal in the photodiode per one frame period are independently stored in the two memories alternately for every one frame, the stored signals are read as an imaging signal having one frame time difference, and the two image pickup signals which are read are alternately switched at a plurality of times in one frame period and applied to a CDS circuit, thereby obtaining the difference between the two imaging signals. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a CMOS image sensor, and is a difference from a previous frame suitable for use in a surveillance camera that detects the motion of a stationary surveillance image and a digital video camera that requires motion detection for camera shake correction or the like. The present invention relates to a differential signal detection circuit of a CMOS image sensor using a semiconductor that detects and outputs an image signal (hereinafter referred to as a differential signal).

  First, FIG. 5 shows an overall configuration diagram of a conventional CMOS image sensor 3, and FIG. 6 shows a configuration of one pixel portion, which will be described below.

 As shown in FIG. 5, the conventional CMOS image sensor 3 includes a vertical selection circuit 3a, a horizontal selection circuit 3b, and a pixel configuration unit 3c.

  The pixel configuration unit 3c is arranged with a plurality of pixels in a matrix that receives an optical object image and converts it into an analog electrical signal. The vertical selection circuit 3a generates a pulse sequence for selecting a pixel column of a vertical line to the pixel configuration unit 3c. The sending and horizontal selection circuit 3b is composed of a switch row for selecting a horizontal pixel of the pixel configuration unit 3c.

  The operation of the CMOS image sensor 3 will be described next. First, pixels (0, 0), (0, 1),..., In which a subject optical image is formed and electric charges corresponding to the amount of light of the subject optical image are accumulated. . . (N, m-1), (n, m) are converted into pulse trains row0, row1,. . . The pixel line of the vertical line is selected by “row”, and Sout0, Sout1,. . . Soutm-1, Soutm are sent to the horizontal selection circuit 3b, and the horizontal selection circuit uses the horizontal direction Sout0, Sout1,. . . Soutm-1 and Soutm are sequentially selected, and the subject optical image is converted into an analog electric signal S0 and output.

  Next, FIG. 6 shows a circuit example of one pixel constituting the pixel configuration unit 3c. This circuit includes transistors Tr1, Tr2, Tr3 and a photodiode PD1. The operation of this circuit example will be described.

 First, the transistor Tr1 is turned on by the PDRST1 pulse to reset the charge of the photodiode PD1. Next, Tr1 is turned off by the PDRST1 pulse. When light based on the subject optical image is formed on the photodiode PD1 in a state where the Tr1 is turned off, charges are supplied to the photodiode PD1 in accordance with the light amount of the subject optical image.

  After the charge supplied to the photodiode PD1 is accumulated for a predetermined time (for example, one frame), the transistor Tr3 is turned on by the ROWS1 pulse supplied from the vertical selection circuit 3a, and the charge accumulated in the photodiode PD1 is passed through Tr2 and Tr3. Then, the object optical image is taken out as an output signal Sout converted into an electric signal and applied to the horizontal selection circuit 3b.

  The horizontal selection circuit 3b selects the output signal Sout of the pixel in the horizontal direction and removes a part of noise by a CDS (Correlated Double Sampling) circuit (not shown) built in the horizontal selection circuit 3b, and then analog. It is output as an electric signal S0. At this time, since the charge accumulated in the photodiode PD1 is released as an output signal at the same time as Tr3 is turned ON, it disappears by one reading.

  Next, FIG. 7 shows a CDS circuit example. This CDS circuit is composed of SW0, SW1, SW2 and capacitors C0, C1. Before the signal Sout output from the CMOS image sensor is input to Sout-in of the CDS circuit, SW2 is turned OFF, SW0 and SW1 are turned ON, and the charge of the capacitor C1 is reset.

 When the subject optical image component is input to Sout, SW0 is turned off and SW1 is turned on to accumulate the charge of the subject optical image component in the capacitor C1. When the accumulation of the charge of the subject optical image component is completed, when SW1 is turned off and SW2 is turned on, an analog electric signal S0 obtained by removing noise from the signal Sout from Scds-out is output from the CDS circuit.

 An example of a digital differential signal detection system using the CMOS image sensor 3 described above is shown in FIG. This system includes an imaging lens 2, a CMOS image sensor 3, an analog / digital conversion circuit ADC 4, a digital differential signal processing circuit 5, and a frame memory 6.

 The operation of this digital difference signal detection system will be described. First, the subject optical image 1 is formed on the light receiving portion of the CMOS image sensor 3 by the imaging lens 2. An analog image signal S0 is output from the CMOS image sensor 3 and converted into a digital image signal D0 by the ADC.

 In the first frame, first, the digital image signal D 0 is stored in the frame memory 6 via the digital difference signal processing circuit 5. Then, in the next frame, the digital differential signal processing circuit 5 performs differential signal processing with the digital image signal D0 of the first frame, and outputs the differential signal Dsout from the digital differential signal processing circuit 5.

 An example of the differential signal obtained at this time is shown in FIG. The waveform shown in (a) is an analog signal S0 output from the CMOS image sensor 3 of FIG. 8 (A), and is obtained by capturing the subject optical image 1 at a level nearly 100%. Variations L1 and H1 are mixed in S0b of the second frame of the analog signal S0, and H1 is at a level of 100% or more.

 The CMOS image sensor output usually corresponds to the light quantity of the subject optical image 1 up to about 400% and is compressed from around 100% and converted to a level of 120% to 150%. However, accurate information is required as the differential signal, and therefore, a signal that is not compressed as much as possible is desirable. Therefore, the CMOS image sensor output is used as it is without being compressed.

 For this reason, when the analog signal S0 output from the CMOS image sensor 3 is converted into the digital signal D0 by the ADC 4, the signal level of 100% or more is limited to 100% in the ADC 4, and therefore, two frames mixed in the analog signal S0. Of the fluctuations L1 and H1 of the eye signal S0b, the level of 100% or more at H1 is limited to 100% and converted to the digital image signal D0.

 A digital difference signal processing circuit 5 generates a difference signal Dsout between the digital image signal D0 and the digital image signal Dmem stored in the frame memory 6 one frame before. Then, at this time, fluctuations L1 and H1 of S0b are generated as differential signals in Dsouta and Dsoutb (FIG. 9 (d)).

 By the way, as for H1, the fluctuation component which exceeds 100% is cut in ADC4. For this reason, as shown in FIG. 9 (e), the analog signal S0 is normally set to a level in the vicinity of approximately 50%, which is equal to or less than 100%, when converted into the digital signal D0, and even if fluctuations L2 and H2 occur, 100% Do not exceed the level. In this way, only the variation is accurately detected from the differential signal Dsout as shown in FIG. 9 (g).

 However, it is desirable to open the aperture of the imaging lens so that the signal level is close to 100% so that the signal level of the analog signal S0 is as large as possible and is not affected by noise components. Since the level of is greatly detected, accurate processing can be performed.

 For this reason, as shown in FIGS. 10 and 11, using a CMOS image sensor having two sets of analog memories for each pixel, the analog difference shown in FIG. 8B can detect fluctuations even in an analog signal S0 of 100% or more. There is a signal detection system.

 The analog differential signal detection system in FIG. 8B includes an imaging lens 2, a CMOS image sensor 3 having two sets of analog memories, an analog differential signal processing circuit 7, and an ADC 4.

 The operation of the analog difference signal detection system will be described. First, the subject optical image 1 is formed on the light receiving portion of the CMOS image sensor 3 by the imaging lens 2. Then, the analog signal Sa and the analog signal Sb stored in the analog memory having a time difference of one frame from the CMOS image sensor 3 are added to the analog differential signal processing circuit 7 to obtain an analog differential signal Sd.

 If this analog differential signal Sd is converted into a digital signal Dsout by the ADC 4, a good differential signal in which the level of fluctuation is not cut can be obtained.

 An example of the CMOS image sensor 3 used in FIG. 8B is shown in FIG. 10, and a pixel configuration example and an analog differential signal circuit example are shown in FIG. The analog memory is the stray capacitances C1 and C2 shown in FIG. 11, and alternately stores the charge from the PD1 every frame. Further, since the charge accumulated in the capacitor is handled as a voltage component and is retained even after being read, it is read and used continuously for two frame periods.

In the analog differential signal detection system, since there are two sets of analog memories, it is necessary to install each CDS circuit at each analog memory output as shown in FIG. As shown in FIG. Therefore, the scale of the circuit configuration is increased as compared with the conventional CMOS image sensor.
"JP 2000-32347 A"

  By the way, a differential signal detection circuit using a conventional CMOS image sensor that can obtain an accurate differential signal without saturation even if the level of the optical input signal is set near 100% is divided into two sets in the pixel portion of the CMOS image sensor. When two analog image signals having a time difference of one frame are generated by installing an analog memory, two sets of horizontal selection circuits to which a CDS circuit is added for difference processing performed using the two analog image signals. Therefore, there is a problem that an analog differential signal processing circuit is required, and the scale of the circuit configuration becomes larger than that of a conventional CMOS image sensor, making it difficult to reduce the size and increasing the cost.

  Therefore, the present invention solves the above-described problems, requires only a small circuit configuration, and can generate a large fluctuation without saturation even if the level of the optical input signal is set to around 100%. An object is to obtain a differential signal detection circuit using a CMOS image sensor.

  In order to achieve the above object, a differential signal detection circuit using a CMOS image sensor according to a first aspect of the present invention includes a first imaging signal for one frame obtained by imaging a subject optical image and the first imaging signal. The second imaging signal for one frame existing immediately before is set as one set, and the difference between the first imaging signal and the second imaging signal having a time difference for one frame is detected, In a CMOS image sensor differential signal detection circuit that outputs only an imaging signal related to the difference, light receiving means (CMOS image sensor 3) in which a large number of pixels for receiving the subject optical image and performing photoelectric conversion output are arranged in a matrix. Are connected to each of the pixels of the light receiving means, and output the photoelectric conversion outputs related to the first and second imaging signals of the set and output from each of the pixels, respectively. Within the erasure period, the first and second imaging signals are stored in such a manner that they can be rewritten alternately and sequentially with a time difference of one frame, and are stored so that they can be rewritten and have a time difference of one frame. From the photoelectric conversion output simultaneously read from the storage means ((pixel part + memory part) 3c ′) and the photoelectric conversion output read simultaneously from the storage means, the one set of the first and second imaging signals are read out. Differential means ((CDS unit + analog difference signal processing unit) 3cds ′) that generates and outputs the difference between the generated first and second imaging signals as the imaging signal related to the difference.

To achieve the above object, the differential signal detection circuit using the CMOS image sensor of the second invention is the CMOS image sensor differential signal detection circuit described in the first means,
The differential means obtains a difference between the first and second imaging signals by alternately switching the first and second imaging signals a plurality of times within one frame period and adding them to the CDS circuit.

  According to the CMOS image sensor differential signal detection circuit of the present invention, a large fluctuation can be generated as a differential signal due to a time difference of one frame, and the circuit configuration can be reduced in size, which can be easily reduced in size and reduced in cost. It is possible to obtain a CMOS image sensor differential signal detection circuit capable of saving and saving resources and power.

  The best mode for carrying out the present invention will be described below with reference to the drawings by way of preferred embodiments.

  FIG. 1 shows a part of a pixel and a peripheral circuit of a CMOS image sensor according to the present invention. The CMOS image sensor shown in FIG. 1 includes (pixel portion + memory portion) 3c ′ and (CDS portion + analog differential signal processing circuit) 3cds ′.

  First, (pixel unit + memory unit) 3c ′ will be described. The pixel portion is composed of a photodiode PD1, a reset transistor Tr1, and transfer gates Tr2 and Tr3, and the memory portion is stored in the floating capacitances C1 and C2 and transistors Tr8 and Tr9 that reset the charges accumulated in the floating capacitance and the floating capacitance. It comprises transistors Tr4 and Tr5 for reading out charges with a source follower and transistors Tr6 and Tr7 for selecting a line.

  First, Tr1 is turned on by a pulse PDRST1 to reset PD1. At the same time, the stray capacitances C1 and C2 are reset by turning ON the pulse orst of Tr8 and the pulse rst of Tr9.

 Next, all the pulses that are turned on are turned off, a subject optical image is formed on the photodiode PD1 by the imaging lens 2, and light from the subject optical image is accumulated as a charge. Then, after accumulating the charge due to the light of the subject optical image for one frame, Tr2 is turned on by the pulse gxlo, and the charge accumulated in the photodiode PD1 is transferred to the floating capacitor C1.

 After the charge accumulated in the photodiode PD1 for one frame is transferred to the floating capacitor C1, the pulse gxlo is turned off, the Tr1 is turned on by the pulse PDRST1, the photodiode PD1 is reset, and the Tr1 is turned off by the pulse PDRST1. In the next one frame period, the charge due to the light of the subject optical image is accumulated in the photodiode PD1 for the next one frame.

 Then, after accumulating charges from the light of the subject optical image for one frame, Tr3 is turned on by the pulse gxle, and the charges accumulated in the photodiode PD1 are transferred to the floating capacitor C2. After the charge accumulated in the photodiode PD1 for one frame is transferred to the stray capacitance C2, the pulse gxle is turned off.

 Further, after Tr1 is turned on by the pulse PDRST1 and the photodiode PD1 is reset, the Tr1 is turned off by the pulse PDRST1 and the second next one frame period of the photodiode PD1 is subjected to the light of the subject optical image for the next one frame. Accumulate charge.

  When the charge of the first frame is accumulated in the stray capacitance C1 and the charge of the next frame is accumulated in the stray capacitance C2, Tr6 and Tr7 are simultaneously turned ON by the pulse row, and the first frame accumulated in the stray capacitance C1 is turned on. The analog signal Souta due to the charge is output from Tr6 via Tr4, and the analog signal Soutb due to the charge of the next frame accumulated in the stray capacitance C2 is output from Tr7 via Tr5 at the same timing.

 Next, (cds portion + analog difference signal processing circuit) 3cds' will be described. This (CDS portion + analog differential signal processing circuit) 3cds' includes current sources I1, I2, switches S1, S2, S3, S4, capacitors C3, C4, and an amplifier A1.

The operation of this circuit will be described. First, when the switches S1 and S2 are turned OFF and S3 and S4 are turned ON, the voltage at the E point of C4 becomes Vref1, and this is stored as the charge Qref.
Qref = C4xVref1

Next, when the switches S2 and S3 are turned on and the switches S1 and S4 are turned off, the charge Qb accumulated in C3 is
Qb = C3x (Vref1-Vsb)
It becomes. (Vsb: voltage generated by the signal Soutb flowing to the current source I2)

When the switch S1 is turned on and the switches S2, S3, and S4 are turned off, the voltage Vd at the point D is
Vd = Vsa + (Vref1-Vsb)
= (Vsa-Vsb) + Vref1
It becomes. (Vsa: voltage generated by the signal Soutb flowing to the current source I1)

Next, when the switches S1 and S4 are turned on and the switches S2 and S3 are turned off, the voltage Ve at the point E is
Ve = C4 / (C4 + C3) × (Vsa−Vsb) + Vref1
It becomes.

When the amplification factor K of the amplifier A1 is (C4 + C3) / C4 and the offset voltage is −Vref1, the signal voltage Sd output from the amplifier A1 is
Sd = Vsa−Vsb
Thus, a difference signal Sd between the analog signal Souta based on the charge of the first frame and the analog signal Soutb based on the charge of the next frame is generated.

  Thus, (CDS part + analog differential signal processing circuit) 3cds ′ is composed of two conventional CDS parts and the analog differential signal processing circuit part of FIG. 11, and the scale of substantially one CDS circuit as shown in FIG. In this configuration, the CDS unit and the analog differential signal processing circuit unit can be operated. Therefore, two sets of horizontal selection circuits as shown in FIG. 10 are not necessary and one horizontal selection circuit may be used. For this reason, the circuit scale can be greatly reduced.

  Next, FIG. 2 shows a schematic diagram of the CMOS image sensor 3 according to the present invention. The CMOS image sensor 3 includes a vertical selection circuit 3a, a horizontal selection circuit 3b including the (CDS portion + analog difference signal processing circuit) 3cds ′ of FIG. 1, and a pixel configuration portion 3c ′ having two sets of memories for each pixel. Constitute.

  The operation of the CMOS image sensor 3 will be described next. First, pixels (0, 0), (0, 1),..., In which a subject optical image is formed and electric charges corresponding to the amount of light of the subject optical image are accumulated. . . (N, m-1), (n, m) are converted into pulse trains row0, row1,. . . The pixel line of the vertical line is selected by “row”, and Sout0, Sout1,. . . Soutm-1, Soutm are sent to the horizontal selection circuit 3b ", and the horizontal selection circuit 3b" outputs the horizontal Souta0, Sout1,. . . After selecting Soutm-1 and Soutm sequentially, a differential signal is generated, and the subject optical image is converted into an analog differential signal Sd and output (Sout0 = Souta0, Soutb0, and so on).

 FIG. 3 shows a timing chart of the CMOS image sensor 3 described with reference to FIGS. (B) is an enlarged view of the Vsync portion of (A). Further, FIG. 4 shows a waveform diagram of each part, and a state where a differential signal is obtained will be described. When the level of the difference signal Sd is small, the amplification factor G0 of the amplifier A1 in FIG. 1 is adjusted to the maximum value of about 100% as shown in FIG. 4 (i).

  FIG. 8C shows an example of an analog differential signal detection system using the CMOS image sensor 3 according to the present invention. Since the difference signal Sd is directly output from the CMOS image sensor 3, it may be used as it is as an analog difference signal or may be used as the digital difference signal Dsout via the ADC 4.

  Thus, according to the present invention, it is possible to obtain a differential signal processing system (C) having a simple configuration as compared with the conventional examples (A) and (B) of FIG.

It is a figure which shows the analog differential signal processing circuit example incorporated in the CMOS image sensor which concerns on this invention. It is a figure which shows the structural example of the CMOS image sensor which concerns on this invention. It is a figure which shows the timing chart of the CMOS image sensor which concerns on this invention. It is a figure which shows the wave form diagram of the CMOS image sensor which concerns on this invention. It is a figure which shows the structural example of the conventional CMOS image sensor. It is a figure which shows the pixel structural example of a CMOS image sensor. It is a figure which shows the CDS circuit example used for a CMOS image sensor. It is a figure which shows the example of a difference signal processing system. It is a figure which shows the waveform in the conventional digital difference signal processing. It is a figure which shows the structural example of the CMOS image sensor which incorporates the conventional memory. It is a figure which shows the circuit structural example of the CMOS image sensor which incorporates the conventional memory.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Subject optical image 2 Imaging lens 3 CMOS image sensor 3a Vertical selection circuit 3b Horizontal selection circuit 3c Pixel structure part 3c 'Pixel part + memory part (Storage means)
3cds CDS part 3cds' CDS part + analog differential signal processing part (differential means)
4 ADC
5 Digital difference signal processing circuit 6 Frame memory 7 Analog difference signal processing circuit

Claims (2)

One frame of the first imaging signal for one frame obtained by imaging the subject optical image and the second imaging signal for one frame existing immediately before the first imaging signal are combined into one set. In a CMOS image sensor differential signal detection circuit that detects a difference between the first imaging signal and the second imaging signal having a time difference of and outputs only the imaging signal related to the difference,
A light receiving means in which a number of pixels for receiving and photoelectrically outputting the subject optical image are arranged in a matrix; and
A blanking period for one frame, which is connected to each of the pixels of the light receiving means and outputs from each of the pixels and outputs the photoelectric conversion output related to the first and second imaging signals of the set, respectively. The first and second imaging signals of the set are stored in such a manner that they can be rewritten alternately and sequentially with a time difference of one frame, and are stored so that they can be rewritten and have a time difference of one frame. Storage means for simultaneously reading out the photoelectric conversion output;
The set of the first and second imaging signals is generated from the photoelectric conversion output read out simultaneously from the storage means, and the difference between the generated first and second imaging signals is captured according to the difference. Differential means for outputting as a signal,
A CMOS image sensor differential signal detection circuit comprising: In the CMOS image sensor differential signal detection circuit according to claim 1,
The differential means obtains a difference between the first and second imaging signals by alternately switching the first and second imaging signals a plurality of times within one frame period and adding them to a CDS circuit. A CMOS image sensor differential signal detection circuit.