JP2005217223A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device for reducing a load for a resist patterning process, and for reducing the dielectric constant of the interlayer insulating film in forming a dual damascene structure in an interlayer insulating film. <P>SOLUTION: A first insulating film (SiOC film) 6, a second insulating film (organic film) 7, a first mask formation layer (SiOC film) 21, a second mask formation layer (SiO<SB>2</SB>film) 22, and a third mask formation layer (SiN film) 23, are successively formed; and the third mask formation layer 23 is patterned so that a third mask 23A having a wiring groove pattern can be formed. A resist mask 12 is formed at the upper part, and etched to the second insulating film 7 so that a connection hole can be opened. The second mask formation layer 22 is etched from the upper part of the third mask so that a second mask having a wiring groove pattern can be formed, and the first insulating film 6 is etched to the middle so that the connection hole can be dug. The first mask formation layer 21 is etched from the upper part of the second mask so that the first mask having the wiring groove pattern can be formed, and the first insulating film 6 is etched so that the connection hole can be opened. The second insulating film 7 is etched from the first mask to the second mask so that a wiring groove 16 can be formed. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method of manufacturing a semiconductor device having a dual damascene multi-layer wiring structure in a low dielectric constant interlayer insulating film, and more particularly, a dual damascene wiring having a good shape for a low dielectric interlayer insulating film. The present invention relates to a method for manufacturing a semiconductor device having a structure.

  With the miniaturization and high integration of semiconductor devices, the delay of electrical signals due to the wiring time constant has become a serious problem. Therefore, low electrical resistance copper (Cu) wiring is introduced into the conductive layer used in the multilayer wiring structure instead of aluminum (Al) alloy wiring. Unlike metal materials such as Al used in conventional multilayer wiring structures, Cu is difficult to pattern by dry etching. Therefore, wiring is formed by forming wiring grooves in the insulating film and embedding Cu in the wiring grooves. A damascene method for forming a pattern is generally applied to a Cu multilayer wiring structure.

  In addition, in a highly integrated semiconductor device, an increase in wiring capacitance leads to a decrease in the operating speed of the semiconductor device. Therefore, it is indispensable to use a fine multilayer wiring that uses a low dielectric constant film as an interlayer insulating film to suppress an increase in wiring capacitance. It has become. As a material for the low dielectric constant interlayer insulating film, in addition to fluorine-containing silicon oxide (FSG) having a relative dielectric constant of about 3.5 which has been used for a long time, an organic polymer typified by polyaryl ether (PAE) is used. Examples thereof include low dielectric constant films having a relative dielectric constant of about 2.7, such as SiOC-based materials such as hydrogen-based silsesquioxane (HSQ) and methylsilsesquioxane (MSQ). Furthermore, in recent years, attempts have been made to apply low dielectric constant materials by making them porous so that the relative dielectric constant is around 2.2.

  By the way, when the dual damascene method is applied to the low dielectric constant interlayer insulating film, it is necessary to solve the following technical limitations.

  First, since the composition of the low dielectric constant film is close to that of the resist used for patterning, the low dielectric constant film is also easily damaged during the resist removal process. Specifically, when performing resist stripping after etching using a resist mask or resist regeneration when the processed resist pattern does not meet product specifications, damage to the low dielectric constant film is suppressed. It is essential to be able to do it.

  Second, it is possible to apply to a borderless structure in which there is no allowance between the wiring and the connection hole. Along with the miniaturization of semiconductor devices, it is assumed that a multi-layer wiring of the 0.18 μm generation or later adopts a processing process that can cope with a borderless structure. Therefore, even when wiring grooves and connection holes are simultaneously formed in an interlayer insulating film including a low dielectric constant film by a dual damascene method, it is important that the process has a small variation in via resistance due to misalignment.

  Third, in order to form the wiring groove with good depth controllability, it is desirable to interpose an etching stopper film near the bottom of the wiring groove. However, an etching stopper film having a relatively high relative dielectric constant is used as the interlayer insulating film. If intervening, the interlayer capacitance increases. Therefore, there is a demand for a dual damascene process having a low dielectric constant film interlayer structure capable of controlling the formation of wiring trenches and suppressing an increase in capacitance.

  As a dual damascene method capable of solving the technical limitations as described above, there has been proposed a method which will be described with reference to the sectional process diagram of FIG.

First, as shown in FIG. 6A, a deposited film composed of an organic film 2 and a silicon oxide (SiO ₂ ) film 3 is formed as an interlayer insulating film on a base insulating film 1 deposited on a substrate (not shown). Then, a buried wiring 4 of a copper (Cu) film is formed in the interlayer insulating film. Then, a silicon carbide (SiC) film 5, an SiOC film 6, and a polyaryl ether (PAE) film 7 are sequentially formed on the Cu embedded wiring 4 as an anti-oxidation layer for the Cu film. Subsequently, a first mask formation layer 8 made of silicon oxide (SiO ₂ ) and a second mask formation layer 9 made of silicon nitride (SiN) are sequentially formed, and a resist mask 10 having a wiring groove pattern is formed as a second mask. It is formed on the formation layer (SiN film) 9. Next, the second mask formation layer (SiN film) 9 is etched by a dry etching method using the resist mask 10 to form a second mask 9A made of a SiN film having a wiring groove pattern, and then the resist mask 10 is removed. .

Next, as shown in FIG. 6B, a resist mask 12 having a connection hole pattern is formed on the first mask formation layer (SiO ₂ ) 8 including the second mask 9A made of SiN. In this case, at least a part of the opening of the connection hole pattern of the resist mask 12 overlaps with the opening of the wiring groove pattern formed in the second mask 9A.

Thereafter, as shown in FIG. 6C, the second mask 9A made of the SiN film and the first mask formation layer (SiO ₂ film) 8 are etched and opened by a dry etching method using the resist mask 12 as an etching mask. Subsequently, the PAE film 7 is etched to open a connection hole 13 exposing the SiOC film 6. Here, the resist mask 12 can be simultaneously removed by etching the PAE film 7. Further, the resist mask 12 becomes thinner during the etching of the PAE film 7, but the first mask 8A having the connection hole 13 opened in the first mask formation layer (SiO ₂ film) 8 is present. By using the mask 8A as an etching mask, the connection hole 13 having a favorable opening shape can be opened.

Next, as shown in FIG. 6D, the SiOC film 6 is further etched, and the connection hole 13 is dug until the SiC film 5 is reached. At this time, the first mask 8A made of SiO ₂ is simultaneously removed by etching using the second mask 9A made of the SiN film having the wiring groove pattern as an etching mask to form a wiring groove pattern.

Thereafter, as shown in FIG. 6E, the PAE film 7 is etched using the first mask 8A having the wiring groove pattern as an etching mask, and the wiring groove is formed on the first mask 8A made of SiO ₂ and the APE film 7. 16 is formed. Thereafter, the SiC film 5 at the bottom of the connection hole 13 is etched to connect the connection hole 13 to the Cu embedded wiring 4. Thereby, a dual damascene shape in which the connection hole 13 is opened at the bottom of the wiring groove 16 is obtained. Note that the second mask (9A) made of SiN remaining outside the wiring trench formation region is removed in the course of etching the SiC film 5 at the bottom of the connection hole 13.

  After the above, the etching deposits remaining on the side walls of the wiring groove 16 and the connection hole 13 are removed by post-treatment using a chemical solution and RF sputtering, and the surface of the Cu embedded wiring 4 at the bottom of the connection hole 13 is altered. Normalize the layer. Then, as shown in FIG. 6F, a Ta film 17 is formed as a barrier metal by a sputtering method, a Cu film 18 is deposited by an electroplating method or a sputtering method, and a conductive film is formed in the wiring trench 16 and the connection hole 13. Is embedded. Next, unnecessary portions of the deposited Ta film 17 and Cu film 18 as a wiring pattern are removed by a chemical mechanical polishing (CMP) method. Thereby, a dual damascene multilayer wiring structure can be obtained. Further, for example, a SiC film 19 is formed as an antioxidant layer in the same manner as the Cu embedded wiring 4 in the lower layer.

  The application of the dual damascene method using the two-layer etching mask described above overcomes the above-described technical limitations on the low dielectric constant film structure and reduces the load on the resist patterning process. It has become.

  That is, the regeneration processing of the resist masks 10 and 12 that are not suitable for product planning can be performed on the first mask forming layer 9 or the second mask forming layer 8, and the removal of the resist mask 12 for opening the connection holes is Since the PAE film 7 is etched and the connection hole 13 is opened at the same time, the resist can be removed while suppressing damage to the low dielectric constant film.

  Further, as shown in FIG. 6C, since the connection hole 13 is opened from the second mask 9A made of the SiN film having the wiring groove pattern, misalignment between the wiring groove 16 and the connection hole 13 occurred. Even in this case, the dimensions of the connection hole 13 do not vary.

  Further, as shown in FIG. 6 (e), when the wiring groove 16 is formed in the PAE film 7, the PAE film 7 may be etched on the SiOC film 6. For this reason, it is easy to ensure the etching selectivity. Therefore, it is easy to control the depth of the wiring groove 16 without interposing an etching element film such as a SiN film having a high relative dielectric constant (see Patent Document 1 below).

JP 2001-44189 A

  However, in the dual damascene method as described above, the first mask that remains between the wirings even after the completion of the process is formed of a silicon oxide film. Therefore, since a silicon oxide film having a relative dielectric constant of about 4 remains between the wirings, even if the relative dielectric constant is lowered by using an organic insulating film or the like as the lower interlayer insulating film, it is effective between the wirings. The relative dielectric constant is difficult to decrease.

  Accordingly, the present invention provides a method for manufacturing a semiconductor device capable of reducing the dielectric constant of an interlayer insulating film while reducing the load on the resist patterning process when forming a dual damascene structure in the interlayer insulating film. For the purpose.

  In order to achieve such an object, a semiconductor device manufacturing method of the present invention is a first mask provided in the lowermost layer in a semiconductor device manufacturing method to which a dual damascene method using a three-layer mask or a two-layer mask is applied. Is made of a SiOC-based material, and is performed in the following procedure.

  In the first method, first, (a) a first insulating film made of an inorganic low dielectric material as an insulating film penetrating a connection hole on a substrate, and a second insulating film made of an organic material as an insulating film between wiring layers Are sequentially formed. Next, (b) a first mask forming layer made of an inorganic low dielectric material, a second mask forming layer made of a Si-based material different from the first mask, and the second on the second insulating film sequentially A third mask forming layer made of a Si-based material different from the mask forming layer is formed. Thereafter, (c) the third mask forming layer is patterned to form a third mask having a wiring groove pattern. Next, (d) a resist mask having a connection hole pattern is formed on the second mask formation layer including the third mask. Further, (e) using the resist mask as an etching mask, the third mask, the second mask forming layer, and the first mask forming layer are etched, and further, the second insulating film is etched to open connection holes. Thereafter, (f) using the third mask as an etching mask, the second mask forming layer is etched to form a second mask having a wiring groove pattern, and the first insulating film is etched halfway to form connection holes. Open. Next, (g) using the second mask as an etching mask, the first mask forming layer is etched to form a first mask having a wiring groove pattern, and the first insulating film remaining at the bottom of the connection hole Is etched to open a connection hole reaching the substrate. Next, (h) the second insulating film is etched using the first mask or the second mask as an etching mask, and a wiring groove is formed in the second insulating film. And (ii) removing the second mask and the third mask remaining after the formation of the wiring trench.

  In the second method, first, (a) a first insulating film made of an inorganic low dielectric material as an insulating film penetrating the connection hole, and a second insulating film made of an organic material as an insulating film between the wiring layers. A film is sequentially formed. Next, (b) a first mask forming layer made of an inorganic low dielectric material and a second mask forming layer made of a Si-based material different from the first mask are sequentially formed on the second insulating film. . Thereafter, (c) the second mask forming layer is patterned to form a second mask having a wiring groove pattern. Next, (d) forming a resist mask having a connection hole pattern on the first mask forming layer including the second mask, and (e) forming the second mask and the first mask using the resist mask as an etching mask. The layer is etched, and the second insulating film is further etched to open a connection hole. Further, (f) using the second mask as an etching mask, the first mask forming layer is etched to form a first mask having a wiring groove pattern, and the first insulating film remaining at the bottom of the connection hole is formed Etching is used to open connection holes. Thereafter, (g) the second insulating film is etched using the first mask or the second mask as an etching mask, and a wiring groove is formed in the second insulating film. And (h) removing the second mask remaining after the formation of the wiring trench.

  In the first manufacturing method and the second manufacturing method as described above, after the wiring groove is formed in the second insulating film using the first mask having the wiring groove pattern as an etching mask, the first mask is formed on the second insulating film. And is used as an insulating film constituting a wiring trench together with the second insulating film. Such a first mask is made of an inorganic low dielectric material. For this reason, the relative dielectric constant of the entire insulating film between the wirings including the first mask and between the wiring layers can be kept low. As the first mask and the first insulating film made of an inorganic low dielectric material, for example, a SiOC film formed by a CVD method, a SiOF film formed by a CVD method, and an MSQ formed by a spin coating method are used. A film or an HSQ film may be used, and a xerogel film or an MSQ film having a porous structure may be used.

  Further, in the above manufacturing method, a resist mask regeneration process that is not suitable for product planning can be performed on the first mask forming layer, the second mask forming layer, and further on the third mask forming layer, and further, the wiring. Since the connection hole is opened from above the mask having the groove pattern, the dimension of the connection hole does not change even when misalignment between the wiring groove and the connection hole occurs. In addition, when the wiring trench is formed in the second insulating film, the second insulating film made of an organic material may be etched on the first insulating film made of an inorganic low dielectric material such as an SiOC film. It is easy to ensure the etching selectivity. From the above, the load on the resist patterning process is reduced.

  Therefore, according to the method for manufacturing a semiconductor device of the present invention, when forming a dual damascene structure in an interlayer insulating film, the first mask that remains as an interlayer insulating film after the process is completed while reducing the load on the resist patterning process. It is possible to reduce the relative dielectric constant of the entire interlayer insulating film disposed between the wirings and between the wiring layers.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

<First Embodiment>
The first embodiment is an example of a semiconductor device manufacturing method according to the first invention method, and relates to the formation of a dual damascene structure using a triple mask. The first embodiment of the present invention will be described below with reference to the sectional process diagrams of FIGS. It should be noted that the same elements as those described with reference to FIG.

First, as shown in FIG. 1A, a laminated film composed of an organic film 2 and a silicon oxide (SiO ₂ ) film 3 is formed as an interlayer insulating film on a base insulating film 1 deposited on a substrate (not shown). Then, a copper (Cu) film embedded wiring (Cu wiring) 4 is formed so as to have a wiring thickness of 150 nm.

  Subsequently, a 30 nm-thickness silicon carbide (SiC) film 5 is formed on the Cu wiring 4 as an oxidation prevention and copper diffusion prevention layer. When the SiC film 5 is formed, for example, a parallel plate type plasma CVD apparatus is used, and methylsilane gas is used as a silicon source. As film formation conditions, the substrate temperature is set to 300 to 400 ° C., the plasma power is set to 150 to 350 W, and the pressure of the film formation atmosphere is set to about 100 to 1000 Pa. Thereby, the SiC film 5 having a relative dielectric constant of about 3.5 to 5.0 is formed. Note that SiC may contain a certain amount of nitrogen, hydrogen, oxygen atoms or the like by adjusting the film forming conditions.

  Then, a first insulating film 6 made of carbon-containing silicon oxide (SiOC) having a thickness of 120 nm is formed on the SiC film 5 as the first insulating film 6 that penetrates the connection hole. As the first insulating film, for example, instead of the SiOC film formed by the CVD method, an SiOF film formed by the CVD method, an MSQ film or an HSQ film formed by the spin coating method may be used. Furthermore, the xerogel An MSQ film having a porous structure may also be used.

  As an example, when the first insulating film 6 made of SiOC is formed, a parallel plate type plasma CVD apparatus is used and methylsilane is used as a silicon source. As film forming conditions, the substrate temperature is set to 300 to 400 ° C., the plasma power is set to 100 to 800 W, and the pressure of the film forming atmosphere is set to about 100 to 1350 Pa. A SiOC film having a lower relative dielectric constant can be obtained by adjusting the film forming conditions to form a porous film. Thereby, a first insulating film (SiOC film) 6 having a relative dielectric constant of about 2 to 3 is formed. In forming the first insulating film 6 as described above, an organic silica precursor may be applied by a spin coating method, followed by a curing process at 350 to 450 ° C. Of course, it is also possible to prepare a porous film by adjusting the precursor.

  Next, a second insulating film 7 made of an organic material having a relative dielectric constant of about 2.4 is formed on the first insulating film (SiOC film) 6. In this embodiment, an organic polymer material is used as the organic material, and the second insulating film 7 made of polyaryl ether (PAE) is formed with a film thickness of 100 nm as an example. The second insulating film 7 made of an organic polymer material is formed by performing a curing process at 350 to 450 ° C. after the precursor is deposited by spin coating. Of course, it is also possible to prepare a porous film by adjusting the precursor. As such an organic material, in addition to PAE, BCB, polyimide, and amorphous carbon can also be used.

  Subsequently, a first mask formation layer 21, a second mask formation layer 22, and a third mask formation layer 23 are sequentially formed on the second insulating film (organic material film) 7.

  First, the first mask formation layer 21 is made of an inorganic low dielectric material (here, a SiOC film formed by a CVD method) similar to the first insulating film 6 and is formed with a film thickness of about 150 nm. .

Next, the second mask forming layer 22 is made of a silicon-based material different from that of the first mask forming layer (SiOC film) 21. Among these, in particular, the first mask forming layer (SiOC film) 21 is made of a material that can be processed by a reactive ion etching method using the mask formed of the second mask forming layer 22 as an etching mask. preferable. Examples of such materials include silicon oxide (SiO ₂ ), silicon carbide (SiC), silicon carbonitride (SiCN), and silicon nitride (SiN).

Here, the second mask formation layer 22 made of silicon oxide (SiO ₂ ) is formed to a thickness of about 50 nm. The second mask formation layer 22 made of SiO ₂ is formed by plasma CVD using, for example, monosilane (SiH ₄ ) as a silicon source and dinitrogen monoxide (N ₂ O) gas as an oxidant. Incidentally, when the second mask forming layer (SiO ₂ ) 22 is formed, a silicon oxide film having more silicon than the stoichiometry is formed, so that the first mask by the mask constituted by the second mask forming layer is formed. The etching process of the formation layer (SiOC film) 21 can be optimized easily.

The next third mask formation layer 23 is made of a silicon-based material different from that of the second mask formation layer 22. Among these, it is particularly preferable that the second mask forming layer 22 is made of a material that can be processed by a reactive ion etching method using the mask formed of the third mask forming layer 23 as an etching mask. As a constituent material of the third mask formation layer 23, silicon nitride (SiN) can be exemplified. In particular, when the second mask forming layer 22 is made of SiC, SiCN, or SiN, SiO ₂ may be used as a constituent material of the third mask forming layer 23.

Here, the third mask formation layer 23 made of SiN is formed with a film thickness of about 50 nm. The third mask formation layer 23 made of SiN is formed by the same plasma CVD apparatus as the second mask formation layer 22 made of SiO ₂ , for example, monosilane (SiH ₄ ) as a silicon source and ammonia (NH ₃ as a nitriding agent). ) Gas is used by using dinitrogen monoxide (N ₂ O) gas as an oxidant and an inert gas as a carrier gas.

  The first mask forming layer 21, the second mask forming layer 22, and the third mask forming layer 23 are preferably selected from light-transmitting materials. Accordingly, as described below, when a resist mask is formed on these mask formation layers 21 to 23 by lithography, mask alignment can be performed based on a pattern formed on the base.

  Next, as shown in FIG. 1B, after forming the three-layered mask formation layer as described above, a resist mask 10 having a wiring groove pattern is formed on the third mask formation layer 23.

Next, the third mask formation layer 23 is etched by a dry etching method using the resist mask 10 as an etching mask to form a third mask 23A having a wiring groove pattern. Here, a general magnetron type etching apparatus is used, for example, difluoromethane (CH ₂ F ₂ ), oxygen (O ₂ ), and argon (Ar) are used as etching gases, and a gas flow rate ratio CH ₂ F ₂ : O. ₂ : Ar = 2: 1: 20, bias power 500 W, substrate temperature 40 ° C. In this etching condition, the etching selection ratio of SiN for SiO ₂ (SiN / SiO ₂₎ is about 4. For this reason, the third mask formation layer 23 made of SiN can be etched while suppressing the influence of the etching on the second mask formation layer (SiO ₂ ) 22 which is the base of the etching.

As described above, after the third mask 23A is formed, for example, an ashing process based on oxygen (O ₂ ) plasma and an organic amine chemical solution process are performed, and this occurs during the resist mask 10 and the etching process. Any remaining deposits are completely removed.

  Next, as shown in FIG. 1C, a resist mask 12 having a connection hole pattern is formed on the second mask formation layer 22 including the third mask 23A. At this time, the resist mask 12 is patterned so that at least a part of the connection hole pattern provided in the resist mask 12 overlaps the opening of the wiring groove pattern of the third mask 23A.

  When the resist mask 12 is formed, the level difference caused by the third mask 23A constituting the wiring groove pattern is suppressed to about 50 nm, which is the film thickness of the third mask 23A. Therefore, the resist mask is formed on the flat portion. The resist pattern shape of a good connection hole can be obtained with the lithography characteristics almost equivalent to the case of doing. In addition, even when a coating-type antireflection film (BARC or the like) is used in combination, the variation of the BARC embedding shape can be suppressed to a small extent due to the size and roughness of the wiring groove pattern, and the resist shape is deteriorated during exposure processing, Variations in depth of focus that cause fluctuations can be reduced.

  Subsequently, as shown in FIG. 2D, the third mask 23A, the second mask formation layer 22, and the first mask formation layer 21 are etched by a dry etching method using the resist mask 12 as an etching mask. The second insulating film 7 is etched. Thereby, the connection hole 13 exposing the first insulating film 6 is formed.

In such etching, the etching from the third mask (SiN) 23A to the first mask formation layer (SiOC film) 21 uses a general magnetron etching apparatus, for example, trifluoromethane (CHF ₃₎ as an etching gas. ), Oxygen (O ₂ ), and argon (Ar), the gas flow ratio is CHF ₃ : O ₂ : Ar = 5: 1: 50, the bias power is 1000 W, and the substrate temperature is 40 ° C. .

In this embodiment, the etching selectivity (SiN / SiO ₂ / SiOC) becomes around 1 under this etching condition, and the connection holes 13 are opened by etching the third mask 23A to the first mask forming layer 21 in one step. doing. However, the present invention is not limited to this, and when the resist selectivity, the etching conversion difference, or the like becomes a problem, the third mask 23A, the second mask forming layer 22, and the first mask forming layer 21 are sequentially formed by etching in two or more steps. Etching may be performed.

Then, the next second insulating film (PAE) 7 is etched using a normal high-density plasma etching apparatus, using, for example, ammonia (NH ₃ ) as an etching gas, RF power is set to 150 W, and the substrate temperature is set to 20 ° C. To do. Under this etching condition, the resist mask 12 and the second insulating film (PAE) 7 have substantially the same etching rate, so the resist mask 12 is reduced during the etching of the second insulating film (PAE) 7. Thus, after the resist mask 12 is completely removed, the second mask formation layer (SiO ₂ ) 22 functions as an etching mask (second mask 22A), and an excellent connection hole opening shape can be obtained. Incidentally, the etching selectivity of PAE to SiN, SiO ₂ , SiOC under the etching condition of the second insulating film (PAE) 7 is 100 or more.

As a result, the resist mask 12 is removed simultaneously with the etching of the second insulating film (PAE) 7. The remaining third mask (SiN) 23A serves as a mask for the wiring groove pattern. The lower second mask (SiO ₂ ) 22A serves as a connection hole pattern mask.

Next, as shown in FIG. 2E, the second mask (SiO ₂ ) 22A is etched by a dry etching method using the third mask (SiN) 23A as an etching mask. As a result, the second mask 22A becomes a mask for the wiring groove pattern. Further, the first mask layer 21 becomes the first mask 21A on which the connection hole pattern is formed.

In this dry etching, for example, a general magnetron type etching apparatus is used, and octafluorocyclopentene (C ₅ F ₈ ), oxygen (O ₂ ), and argon (Ar) are used as etching gases, and the gas flow rate ratio is set. C ₅ F ₈ : O ₂ : Ar = 2: 1: 50, the bias power is set to 1500 W, and the substrate temperature is set to 40 ° C. In such etching conditions, the etching selectivity of SiO ₂ to SiN (SiO ₂ / SiN) is about 3. Therefore, if the thickness of the third mask (SiN) 23A is about 50 nm, when the second mask (SiO ₂ ) 22A having a thickness of 50 nm is etched, the thickness of the third mask (SiN) 23A is reduced. The wiring groove pattern can be opened in the second mask (SiO ₂ ) 22A with a sufficient margin.

In this dry etching, the first insulating film (SiOC film) 6 exposed at the bottom of the connection hole 13 is etched halfway. Therefore, the connection hole 13 is dug down. Furthermore, in this etching conditions, it is possible to etch selectivity of SiO ₂ and (SiO ₂ / SiOC) slightly less than 1 with respect to SiOC. For this reason, the connection hole is formed to a depth of 25 to 75 nm in the first insulating film (SiOC film) 6 including the amount of over-etching required for etching the second mask (SiO ₂ ) 22A having a thickness of 50 nm. 13 will be dug down.

Next, as shown in FIG. 2F, the lower layer of the first insulating film (SiOC) 6 is etched using the first mask (SiOC) 21A as an etching mask, and the connection hole 13 is further dug down to form SiC. The film 5 is exposed. At this time, the first mask (SiOC) 21A is simultaneously removed using the second mask (SiO ₂ ) 22A as an etching mask, and the wiring groove 16 is formed in the first mask 21A.

For this etching, for example, a general magnetron type etching apparatus is used. For example, octafluorocyclopentene (C ₅ F ₈ ), nitrogen (N ₂ ), and argon (Ar) are used as etching gases, and the gas flow rate ratio is set. C ₅ F ₈ : N ₂ : Ar = 3: 200: 500, the bias power is set to 1000 W, and the substrate temperature is set to 40 ° C.

In this etching condition, the etching selection ratio of SiOC for SiO ₂ (SiOC / SiO ₂₎ is 10 or more. Therefore, when the first insulating film (SiOC film) 6 having a film thickness of 25 to 75 nm remaining at the bottom of the connection hole 13 is etched, if the second mask (SiO ₂ ) 22A is 50 nm, the second mask (SiO ₂ ). It is possible to obtain a favorable opening shape with a sufficient margin against the 22A film reduction and suppressing the spread above the wiring groove and the shoulder drop.

Subsequently, as shown in FIG. 3G, the second insulating film (PAE) 7 remaining at the bottom of the wiring trench 16 is etched using the second mask (SiO ₂ ) 22A as an etching mask. Thereby, the wiring groove 16 formed in the first mask 21A is further dug down, and the wiring groove 16 is formed in the first mask 21A and the second insulating film (PAE) 7. The second insulating film (PAE) 7 is etched using a normal high-density plasma etching apparatus, for example, ammonia (NH ₃ ) is used as an etching gas, the RF power is set to 150 W, and the substrate temperature is set to 10 ° C. To do. Under this etching condition, the etching selectivity of PAE to SiOC (PAE / SiOC) is 100 or more. As a result, the first insulating film (SiOC film) 6 serving as an etching base can be prevented from being reduced, and the wiring trench 16 can be dug without any variation in depth.

Next, the SiC film 5 at the bottom of the connection hole 13 is removed by etching using the first insulating film (SiOC film) 6 as a mask. Thus, the connection hole 13 opened at the bottom of the wiring groove 16 is communicated with the Cu buried layer 4 to complete predetermined dual damascene processing. Etching of the SiC film 5 is performed using, for example, a general magnetron etching apparatus, for example, using difluoromethane (CH ₂ F ₂ ), oxygen (O ₂ ), and argon (Ar) as an etching gas, and changing the gas flow rate ratio. CH ₂ F ₂ : O ₂ : Ar = 2: 1: 5, and the bias power is set to 100 W. However, under such etching conditions, the etching selectivity of SiC to SiOC is around 1. For this reason, if film digging of the first insulating film (SiOC film) 6 constituting the bottom of the wiring trench 16 becomes a problem, the SiC film 5 is formed before the wiring trench opening to the second insulating film (PAE) film 7. Etching may be performed.

The second mask (SiO ₂ ) 22A remaining on the first mask (SiOC) 21A may be removed in the course of etching the SiC film 5 at the bottom of the connection hole 13.

  After the above, the post-treatment using the chemical solution and the RF sputtering treatment remove the etching deposits remaining on the side walls of the wiring grooves 16 and the connection holes 13, and change the Cu altered layer at the bottom of the connection holes 13 to a normal Cu layer. Convert.

  Thereafter, as shown in FIG. 3 (h), for example, a barrier metal film 17 made of Ta is formed by sputtering, and a Cu film 18 is deposited by electrolytic plating or sputtering, to the wiring groove 16 and the connection hole 13. The conductive film is embedded at the same time.

  Next, as shown in FIG. 3I, a portion unnecessary for the wiring pattern (the portion left on the first mask 21A) of the Cu film 18 and the barrier metal film 17 is subjected to a chemical mechanical polishing (CMP) method. By removing by this, a multilayer wiring structure having a dual damascene structure can be formed. Then, for example, a SiC film 19 is formed as an oxidation preventing and copper diffusion preventing layer in a state of covering the Cu film 18.

  As described with reference to FIG. 1C, the dual damascene multi-layer wiring formed through this process has a step difference in the base layer when the resist mask 12 having the connection hole pattern is formed. Therefore, the resist mask 12 having a highly accurate connection hole pattern can be formed. As described with reference to FIG. 2D using the resist mask 12 as an etching mask, the connection hole 13 is formed, so that the connection hole 13 having a fine dimension can be stably formed without deterioration of the shape of the wiring groove. can do. Thereby, a favorable via-contant characteristic can be obtained.

  Further, as described with reference to FIG. 3G, after forming the wiring groove 16 in the second insulating film 7 using the first mask 21A having the wiring groove pattern as an etching mask, the first mask 21A is used as the second insulating film. It is left on the film 7 and is used as an insulating film constituting the wiring trench 16 together with the second insulating film 7. The first mask 21A is made of a SiOC material having a low dielectric constant. For this reason, the relative dielectric constant of the entire insulating film between the wirings including the first mask 21A and between the wiring layers can be kept low.

  Furthermore, in the above manufacturing method, as shown in FIG. 1B and FIG. 1C, the regeneration process of the resist masks 10 and 12 that are not suitable for product planning is performed on the third mask forming layer 23 or the second mask. Since the connection hole 13 is opened from above the third mask 23A having the wiring groove pattern as shown in FIG. 2D, what can be performed on the formation layer 22 is formed between the wiring groove (16) and the connection hole 13. Even when misalignment occurs, the dimensions of the connection hole 13 do not change. Moreover, as described with reference to FIG. 3G, when the wiring groove 16 is formed in the second insulating film 7, the second insulating film 7 made of an organic material is formed on the first insulating film 6 made of SiOC. Since etching only has to be performed, it is easy to ensure an etching selectivity. From the above, the load on the resist patterning process is reduced.

  Therefore, according to the manufacturing method of the semiconductor device of the first embodiment, when forming the dual damascene structure in the interlayer insulating film, the load on the resist patterning process is reduced and the interlayer insulating film is left even after the process is completed. The relative permittivity of the first mask 21A can be kept low, and the overall permittivity of the interlayer insulating film disposed between the interconnects and between the interconnect layers can be reduced.

Second Embodiment
The second embodiment is an example of a semiconductor device manufacturing method according to the second invention method and relates to the formation of a dual damascene structure using a dual mask. Hereinafter, a second embodiment of the present invention will be described with reference to cross-sectional process diagrams of FIGS. The same elements as those described with reference to FIG. 6 and FIGS. 1 to 3 are denoted by the same reference numerals for description.

First, as shown in FIG. 4A, a Cu wiring 4 is formed on a base insulating film 1 deposited on a substrate (not shown), and an SiC film 5, a first insulating film (SiOC) 6, The steps up to the step of sequentially forming the two insulating films (PAE) 7, the first mask forming layer (SiOC) 21, and the second mask forming layer (SiO ₂ ) 22 are performed in the same manner as in the first embodiment.

Next, as shown in FIG. 4B, a resist mask 10 having a wiring groove pattern is formed on the second mask formation layer (SiO ₂ ) 22. Then, the second mask formation layer (SiO ₂ ) 22 is etched by a dry etching method using the resist mask 10 as an etching mask to form a second mask 22B having a wiring groove pattern. Here, a general magnetron type etching apparatus is used, octafluorocyclopentene (C ₅ F ₈ ), oxygen (O ₂ ), and argon (Ar) are used as etching gases, and the gas flow rate ratio is C ₅ F _8. : O ₂ : Ar = 2: 1: 50, bias power is set to 1500 W, and substrate temperature is set to 40 ° C. In such etching conditions, the etching selectivity of SiO ₂ (SiO ₂ / SiOC) is about 15 to the SiOC. Therefore, the etching of the second mask forming layer 22 made of SiO ₂ can be performed while suppressing the influence of the etching on the first mask forming layer (SiOC) 21 that is the base of the etching.

As described above, after the second mask 22B is formed, an ashing process based on, for example, oxygen (O ₂ ) plasma and an organic amine chemical solution process are performed, and this occurs during the resist mask 10 and the etching process. Any remaining deposits are completely removed.

  Next, as shown in FIG. 4C, a resist mask 12 having a connection hole pattern similar to that of the first embodiment is formed on the first mask formation layer 21 including the second mask 22B. When the resist mask 12 is formed, the level difference caused by the second mask 22B constituting the wiring groove pattern is suppressed to about 50 nm which is the film thickness of the second mask 22B. Therefore, as in the first embodiment, it is possible to obtain a resist pattern shape having a good connection hole with substantially the same lithography characteristics as when a resist mask is formed on a flat portion, and an antireflection film for a coating system. Even when (BARC or the like) is used in combination, it is possible to reduce the depth of focus variation that causes the dimensional variation.

  Subsequently, as shown in FIG. 5D, the second mask 22B and the first mask formation layer 21 are etched by a dry etching method using the resist mask 12 as an etching mask, and the second insulating film 7 is further etched. Then, the connection hole 13 exposing the first insulating film 6 is formed.

In the etching described above, the etching from the second mask (SiO ₂ ) 22B to the first mask formation layer (SiOC film) 21 using the resist mask 12 as an etching mask and the etching of the second insulating film (PAE) 7 are performed as follows. In one embodiment, the process is performed as described with reference to FIG. As a result, the resist mask 12 is removed simultaneously with the etching of the second insulating film (PAE) 7. The remaining second mask (SiO ₂ ) 22B serves as a mask for the wiring groove pattern. In addition, the first mask 21B configured by the first mask forming layer 21 serves as a mask for the connection hole pattern.

Next, as shown in FIG. 5E, the first mask (SiOC) 21B is further etched using the second mask (SiO ₂ ) 22B having the wiring groove pattern as an etching mask, and the wiring groove is formed on the first mask 21B. 16 is formed. Thereby, the first mask 21B becomes a mask having a wiring groove pattern. In addition, here, the first insulating film (SiOC) 6 is also etched at the same time to dig down the connection hole 13 and expose the SiC film 5 at the bottom of the connection hole 13.

In this etching, for example, a general magnetron etching apparatus is used, for example, C ₅ F ₈ , oxygen (O ₂ ), and argon (Ar) are used as an etching gas, and the gas flow ratio is C ₅ F ₈ : O ₂ : Ar = 2: 1: 50, the bias power is set to 1500 W, and the substrate temperature is set to 40 ° C. In this etching condition, the etching selection ratio of SiOC for SiO ₂ (SiOC / SiO ₂₎ is about 15. For this reason, if the thickness of the second mask (SiO ₂ ) 22B is about 50 nm, when the first mask (SiOC) 21B having a thickness of 120 nm is etched, the thickness of the second mask (SiO ₂ ) 22B is reduced. Therefore, the wiring groove 16 can be opened with a sufficient margin.

Subsequently, the process shown in FIG. 5F is performed in the same manner as described with reference to FIG. 3G in the first embodiment, so that the second mask (SiO ₂ ) 22B is used as an etching mask to form a wiring trench. The second insulating film (PAE) 7 remaining at the bottom of 16 is etched and the wiring trench 16 is dug down. Next, the SiC film 5 at the bottom of the connection hole 13 is removed by etching using the first insulating film 6 as a mask. Thus, the connection hole 13 opened at the bottom of the wiring groove 16 is communicated with the Cu buried layer 4 to complete predetermined dual damascene processing. Further, the second mask (SiO ₂ ) 22A remaining on the first mask (SiOC) 21A may be removed in the course of etching the SiC film 5 at the bottom of the connection hole 13, as in the first embodiment. It is the same.

  The subsequent steps are performed in the same manner as in the first embodiment, so that the barrier metal film 17, the Cu film 18, and the antioxidant layer are the same as described with reference to FIG. 3I in the first embodiment. For example, a SiC film 19 is formed.

  Even in the manufacturing method of the second embodiment, as described with reference to FIG. 4C, when the resist mask 12 having the connection hole pattern is formed, the step of the base layer is substantially the second mask. Since the film thickness of 22BA is suppressed to about 50 nm, the resist mask 12 having a highly accurate connection hole pattern can be formed. Therefore, similarly to the first embodiment, the connection hole 13 having a fine dimension can be stably formed without deterioration of the shape of the wiring groove, and good via constant characteristics can be obtained.

  Further, as described with reference to FIG. 5F, after forming the wiring groove 16 in the second insulating film 7 using the first mask 21B having the wiring groove pattern as an etching mask, the first mask made of SiOC having a low dielectric constant is formed. The one mask 21B is left on the second insulating film 7. Therefore, as in the first embodiment, the relative dielectric constant of the entire insulating film between the wirings including the first mask 21B and between the wiring layers can be kept low.

  Furthermore, also in the above manufacturing method, as shown in FIGS. 4B and 4C, the regeneration process of the resist masks 10 and 12 that are not suitable for product planning is performed on the second mask forming layer 22 or the first mask. Since the connection hole 13 is opened from above the second mask 22B having the wiring groove pattern as shown in FIG. 5 (d), the wiring groove (16) and the connection hole 13 Even when the misalignment occurs, the dimension of the connection hole 13 does not change as in the first embodiment. Moreover, as described with reference to FIG. 5G, when the wiring trench 16 is formed in the second insulating film 7, the second insulating film 7 made of an organic material is formed on the first insulating film 6 made of SiOC. Etching is sufficient, and it is easy to ensure an etching selectivity. From the above, as in the first embodiment, the load on the resist patterning process is reduced.

  Therefore, even in the method of manufacturing the semiconductor device according to the second embodiment, when a dual damascene structure is formed in the interlayer insulating film, the load on the resist patterning process is reduced, and the interlayer insulating film remains after the process is completed. It is possible to suppress the relative dielectric constant of the first mask 21B to be low and to reduce the dielectric constant of the entire interlayer insulating film disposed between the wirings and between the wiring layers.

It is sectional process drawing (the 1) which shows the manufacturing method of 1st Embodiment. FIG. 6 is a sectional process diagram (part 2) illustrating the manufacturing method according to the first embodiment. It is sectional process drawing (the 3) which shows the manufacturing method of 1st Embodiment. It is sectional process drawing (the 1) which shows the manufacturing method of 2nd Embodiment. It is sectional process drawing (the 2) which shows the manufacturing method of 2nd Embodiment. It is sectional process drawing which shows the conventional manufacturing method.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Board | substrate, 6 ... 1st insulating film (SiOC film), 7 ... 2nd insulating film, 12 ... Resist mask, 13 ... Connection hole, 16 ... Wiring groove, 21 ... 1st mask formation layer (SiOC film), 21A , 21B ... first mask, 22 ... second mask forming layer, 22A, 22B ... second mask, 23 ... third mask forming layer, 23A ... third mask.

Claims (8)

In a method for manufacturing a semiconductor device including an interlayer insulating film including an organic insulating film,
(A) a step of sequentially forming a first insulating film made of an inorganic low dielectric material as an insulating film penetrating the connection hole and a second insulating film made of an organic material as an insulating film between the wiring layers on the substrate; ,
(B) On the second insulating film, a first mask forming layer made of an inorganic low dielectric material, a second mask forming layer made of a Si-based material different from the first mask, and the second mask forming layer Sequentially forming a third mask forming layer made of a Si-based material different from
(C) patterning the third mask forming layer to form a third mask having a wiring groove pattern;
(D) forming a resist mask having a connection hole pattern on the second mask formation layer including the third mask;
(E) etching the third mask, the second mask forming layer, and the first mask forming layer using the resist mask as an etching mask, and further etching the second insulating film to open connection holes; ,
(F) Using the third mask as an etching mask, the second mask formation layer is etched to form a second mask having a wiring groove pattern, and the first insulating film is etched halfway to open connection holes. And a process of
(G) Using the second mask as an etching mask, the first mask forming layer is etched to form a first mask having a wiring groove pattern, and the first insulating film remaining at the bottom of the connection hole is etched. And opening a connection hole reaching the substrate;
(H) etching the second insulating film using the first mask or the second mask as an etching mask and forming a wiring groove in the second insulating film;
(I) a method of removing the second mask and the third mask remaining after the formation of the wiring trench. In the manufacturing method of the semiconductor device according to claim 1,
In the step (b), the first mask forming layer, the second mask forming layer, and the third mask forming layer are formed of a light-transmitting material. In the manufacturing method of the semiconductor device according to claim 1,
In the step (b), using a material capable of processing the lower mask forming layer by a reactive ion etching method using the mask formed using the upper mask forming layer as an etching mask, the first mask forming layer, A method for manufacturing a semiconductor device, comprising: forming a second mask formation layer and a third mask formation layer. In the manufacturing method of the semiconductor device according to claim 1,
The method of manufacturing a semiconductor device, wherein the inorganic low dielectric material is SiOC formed by a CVD method. In a method for manufacturing a semiconductor device including an interlayer insulating film including an organic insulating film,
(A) a step of sequentially forming a first insulating film made of an inorganic low dielectric material as an insulating film penetrating the connection hole and a second insulating film made of an organic material as an insulating film between the wiring layers on the substrate; ,
(B) sequentially forming a first mask forming layer made of an inorganic low-dielectric material and a second mask forming layer made of a Si-based material different from the first mask on the second insulating film; ,
(C) patterning the second mask formation layer to form a second mask having a wiring groove pattern;
(D) forming a resist mask having a connection hole pattern on the first mask formation layer including the second mask;
(E) etching the second mask and the first mask formation layer using the resist mask as an etching mask, and further etching the second insulating film to open connection holes;
(F) Using the second mask as an etching mask, etching the first mask forming layer to form a first mask having a wiring groove pattern, and etching the first insulating film remaining at the bottom of the connection hole And opening the connection hole,
(G) etching the second insulating film using the first mask or the second mask as an etching mask to form a wiring groove in the second insulating film;
(H) a step of removing the second mask remaining after the wiring trench formation. A method for manufacturing a semiconductor device, comprising: In the manufacturing method of the semiconductor device according to claim 5,
In the step (b), the first mask forming layer and the second mask forming layer are formed of a light-transmitting material. In the manufacturing method of the semiconductor device according to claim 5,
In the step (b), the first mask forming layer and the second mask forming layer are formed using a material capable of processing the first mask forming layer by a reactive ion etching method using the second mask as an etching mask. A method of manufacturing a semiconductor device. In the manufacturing method of the semiconductor device according to claim 5,
The method of manufacturing a semiconductor device, wherein the inorganic low dielectric material is SiOC formed by a CVD method.

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