JP2005150179A - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
- Publication number
- JP2005150179A JP2005150179A JP2003382023A JP2003382023A JP2005150179A JP 2005150179 A JP2005150179 A JP 2005150179A JP 2003382023 A JP2003382023 A JP 2003382023A JP 2003382023 A JP2003382023 A JP 2003382023A JP 2005150179 A JP2005150179 A JP 2005150179A
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- Prior art keywords
- semiconductor
- semiconductor element
- carrier
- sealing resin
- electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
- H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
- H01L2224/26175—Flow barriers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Landscapes
- Wire Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
【解決手段】上面に複数の電極4と電極4と接続された配線パターンを有すると共に、電極4および配線と電気的に接続された外部接続用端子7を底面に有した絶縁性基板からなる半導体キャリア3と、半導体キャリア3上面の複数の電極4に対して導電性を有する複数の突起電極1により接合された半導体素子2と、半導体素子2と半導体キャリア3との隙間と前記半導体素子2の周辺端部を充填被覆している封止樹脂6からなる半導体装置であって、半導体キャリア3の表面上で、半導体キャリア3の外周端部に半導体素子2の周辺に平行に線状あるいは面状に突起部10を形成している。
【選択図】 図2
Description
また半導体素子2の外周端部を被覆する封止樹脂6の平面形状を半導体素子2の各辺に対し、平行に形成することで、半導体素子2の各辺の接続部分に発生する応力を均一化し、接続性を安定化し、高い品質・信頼性を実現できる半導体装置およびその製造方法を提供することを目的とするものである。
2 半導体素子
3 半導体キャリア
4 電極
5 導電性接着剤
6 封止樹脂
7
8 Auバンプ
9 キャピラリー
10 線状あるいは面状の突起部
Claims (4)
- 絶縁性基板を有しその上面に電極を有する半導体キャリアと、前記電極に突起電極により接合された半導体素子と、前記半導体素子と前記半導体キャリアとの間の隙間に前記半導体素子の周辺端部から注入されて前記半導体素子と前記半導体キャリア間および前記半導体素子の周辺端部に充填被覆された封止樹脂とを備えた半導体装置であって、前記半導体キャリア上の表面上で前記半導体素子の樹脂注入辺側に前記封止樹脂をせき止める突起部を形成したことを特徴とする半導体装置。
- 前記突起部は前記半導体素子の前記樹脂注入辺以外の三辺に対向する前記半導体キャリア表面上にも形成されている請求項1記載の半導体装置。
- 前記半導体素子の前記樹脂注入辺側の前記突起部と前記樹脂注入辺との間の距離は、前記半導体素子の前記樹脂注入辺以外の三辺とこれに対向する前記突起部との距離よりも大きい請求項2記載の半導体装置。
- 半導体素子の表面電極に突起電極を形成する工程と、前記突起電極が接合される電極を有する絶縁性基板からなる半導体キャリアの周辺端部に線状或いは面状の突起部を形成する工程と、前記半導体素子上の前記突起電極と前記突起電極に対応した前記半導体キャリアの前記電極とを接続する工程と、前記半導体素子と前記半導体キャリアとの間に形成された隙間に前記半導体素子の周辺部の前記突起部側から封止樹脂を注入し、前記封止樹脂を硬化させる工程とを含む半導体装置の製造方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003382023A JP2005150179A (ja) | 2003-11-12 | 2003-11-12 | 半導体装置およびその製造方法 |
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JP2003382023A JP2005150179A (ja) | 2003-11-12 | 2003-11-12 | 半導体装置およびその製造方法 |
Publications (1)
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JP2005150179A true JP2005150179A (ja) | 2005-06-09 |
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JP2003382023A Pending JP2005150179A (ja) | 2003-11-12 | 2003-11-12 | 半導体装置およびその製造方法 |
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009289999A (ja) * | 2008-05-29 | 2009-12-10 | Renesas Technology Corp | 半導体装置及びその製造方法 |
JP2010050481A (ja) * | 2009-11-04 | 2010-03-04 | Oki Semiconductor Co Ltd | 半導体装置の製造方法 |
US8541891B2 (en) | 2007-03-30 | 2013-09-24 | Lapis Semiconductor Co., Ltd. | Semiconductor device |
EP3300463A1 (en) * | 2016-09-26 | 2018-03-28 | Hitachi Power Semiconductor Device, Ltd. | Semiconductor device |
-
2003
- 2003-11-12 JP JP2003382023A patent/JP2005150179A/ja active Pending
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8541891B2 (en) | 2007-03-30 | 2013-09-24 | Lapis Semiconductor Co., Ltd. | Semiconductor device |
JP2009289999A (ja) * | 2008-05-29 | 2009-12-10 | Renesas Technology Corp | 半導体装置及びその製造方法 |
CN103367176B (zh) * | 2008-05-29 | 2016-03-16 | 瑞萨电子株式会社 | 半导体器件的制造方法 |
JP2010050481A (ja) * | 2009-11-04 | 2010-03-04 | Oki Semiconductor Co Ltd | 半導体装置の製造方法 |
EP3300463A1 (en) * | 2016-09-26 | 2018-03-28 | Hitachi Power Semiconductor Device, Ltd. | Semiconductor device |
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