JP2005033967A - Power conversion apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To stably start a power conversion apparatus including a switching semiconductor device which has lower withstand voltage than the maximum of DC voltage with a commercial high-voltage AC voltage rectified, is of low cost, and has a low forward voltage drop and a high switching speed. <P>SOLUTION: To conduct power conversion of high-voltage AC power voltage with an FET of low withstand voltage in the case that an input is a commercial high-voltage AC power supply or the like, two input capacitors are connected in series across an output terminal of an input DC power supply. Two inverters constituted of FET of low withstand voltage are connected to both terminals of the input capacitors, and control signals of the respective inverters are modulated so that input voltages of the respective inverters may be about 1/2 times as large as the input DC power voltage, respectively. By providing a start stability circuit in a particular configuration, the inverter can be stably started. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

The present invention relates to a power supply device for industrial equipment, and more particularly to a power conversion device suitable for performing power conversion of a commercial high voltage AC power supply system of AC 400V to 480V.

  A power supply device that supplies power to various discharge loads that use discharge energy, tubes such as laser tubes, and other high-voltage devices among industrial devices, although not shown, generally rectifies to convert commercial AC voltage to DC A single inverter circuit for converting the circuit and its DC output voltage into a high-frequency AC voltage is provided. The inverter circuit includes a transformer that boosts the high-frequency AC voltage, and the AC high voltage between the secondary windings of the transformer is converted into DC by a rectifier circuit to obtain a predetermined DC high voltage (for example, a patent) Reference 1).

Here, the AC input voltage of the power supply device that supplies power to the industrial equipment is generally AC200V to 220V, but the AC input voltage is AC400V to 480V with a large-capacity DC power supply. It is called AC power supply voltage. In AC200V to 220V, since the rectified output voltage of the rectifier circuit is about 300V, a low-cost, low on-resistance, low withstand voltage FET, for example, a withstand voltage of about 500V is used as the switching semiconductor element of the inverter circuit. However, when the input voltage is a high-voltage commercial AC power supply voltage of AC400V to 480V, the rectified output voltage of the rectifier circuit becomes a DC high voltage of about 620V to 744V at the maximum in consideration of fluctuations. The switching semiconductor element needs to have a breakdown voltage of at least about 1000 V, and a switching semiconductor element such as an FET or IGBT having a breakdown voltage of 1000 V or more is required.
JP 2001-145371 (page 6-8, FIG. 1)

  In the case of a 400V commercial high voltage AC power supply with an input voltage of AC400V to 480V, a FET or IGBT having a withstand voltage of 1000V or more is generally used, but generally a high withstand voltage FET has a high on-resistance and a large power loss. Also, IGBTs with a high breakdown voltage and a large current can be easily obtained, but the switching speed is slow and it is difficult to increase the frequency. For this reason, there exists a problem that a power converter device enlarges and it is difficult to reduce a ripple voltage.

The first object of the present invention is to provide a power conversion device that enables use of a switching semiconductor element having a withstand voltage lower than the input DC power supply voltage and having a high switching speed, and the power conversion device is stably started. This is the second problem.

  In order to solve this problem, according to the first aspect of the present invention, the first and second input capacitors connected in series between the output terminals of the DC input power supply and both ends of each of these input capacitors are connected. Are connected to the first and second inverters, and the first and second inverters are connected to the primary windings, and the secondary windings are electromagnetically coupled to the primary windings. First and second inverter circuits each including a first transformer and a second transformer having lines, first and second rectifier circuits for converting an alternating voltage of each secondary winding into a direct current, and the first A control circuit for generating a control signal for controlling the first and second inverters, and a balance resistor connected in parallel with each of the first and second input capacitors and having substantially equal resistance values, A power converter that synthesizes the DC output of a circuit The control circuit is an error signal between a signal corresponding to a detected value of any of the combined DC output power, output voltage, and output current of the rectifier circuit and a predetermined reference value. A first error amplifier that outputs one error signal e1, and a second error amplifier that compares the detected voltages of the voltages of the first and second input capacitors and outputs an error signal, A voltage balancing control circuit that outputs a second error signal e2 that serves as a control signal for balancing the voltages of the first and second input capacitors, the first error signal e1 and the second error signal e2. The second error signal e2 has a predetermined minimum voltage value before outputting the control signal and starting the inverter circuit with a start signal. And the maximum voltage value The voltage of the point is forcibly fixed to a zero value or the fixed value is released by the start signal, and the second error signal e2 is determined according to the detected voltage of the voltage of the first and second input capacitors. The output voltage of the inverter is changed from the voltage value at the middle point, and is increased by the control signal and connected to the input capacitor on the higher voltage side, and connected to the input capacitor on the lower voltage side. The present invention proposes a power conversion device characterized in that the inverter circuit is stably started by decreasing the output of the inverter and the voltages of the first and second input capacitors are balanced.

  According to the first aspect of the present invention, even in the case of a 400V commercial high voltage AC power supply with an input voltage of AC 400V to 480V, a switching semiconductor element capable of switching operation at a high speed with a low withstand voltage, particularly using a FET, A power conversion device that can perform power conversion of an AC power supply voltage and can be stably started can be provided.

  According to a second aspect of the present invention, in the first aspect, the inverter circuit is subjected to pulse width control, the pulse width of the pulse width modulation signal supplied to the inverter circuit on the higher voltage side of the input capacitor is widened, and The present invention proposes a power converter that narrows the pulse width of the pulse width modulation signal supplied to the inverter circuit on the lower voltage side.

  According to claim 2, in addition to the effect of claim 1, the voltage of a pair of input capacitors connected in series between the input terminals of the power converter can be balanced by widely used pulse width control. it can.

  According to a third aspect of the present invention, in the first or second aspect, the inverter circuit is controlled by frequency modulation, and the frequency of the frequency modulation signal supplied to the inverter circuit on the higher voltage side of the input capacitor. The power converter is characterized in that the frequency of the frequency modulation signal supplied to the inverter circuit on the lower side of the input capacitor is lowered.

  According to claim 3, in addition to the effect of claim 1, the voltage of a pair of input capacitors connected in series between the input terminals of the power converter can be balanced by widely used frequency control. .

  According to a fourth aspect of the present invention, in any one of the first to third aspects, the voltage balancing control circuit includes a second error amplifier of the second error amplifier to which a detection voltage of the voltage of the input capacitor is input. Proposed a power conversion device comprising a switch connected between an input terminal and a reference potential point, the switch short-circuiting the input terminal before startup and releasing the short-circuit by a startup signal To do.

  According to the fourth aspect, in addition to the effects obtained in the first to third aspects, the activation can be surely and safely performed.

  According to a fifth aspect of the present invention, in any one of the first to fourth aspects, the voltage balancing control circuit has a midpoint between the predetermined minimum voltage value and the maximum voltage value before startup. And an operational amplifier that outputs a voltage signal having a magnitude equal to the voltage value. The output of the operational amplifier has priority over the output of the second error amplifier before starting, and the output of the second error amplifier after starting. Has a priority over the output of the operational amplifier.

  According to the fifth aspect, in addition to the effects obtained in the first to third aspects, the activation can be surely and safely performed.

  According to a sixth aspect of the present invention, in any one of the first to fifth aspects, the first error signal eA is obtained by subtracting the second error signal e2 from the first error signal e1. A subtractor for outputting, a first PWM comparator for comparing the error correction signal eA and the triangular wave signal to generate a pulse width modulation signal, and a signal distributor for distributing the pulse width modulation signal to the first inverter. An adder that adds the second error signal e2 to the first error signal e1 and outputs a corrected error signal eB, and compares the error correction signal eB and the triangular wave signal to generate a pulse width modulation signal. The present invention proposes a power converter comprising a second PWM comparator that generates and a signal distributor that distributes the pulse width modulation signal to the second inverter.

  According to the sixth aspect, the voltage of the pair of input capacitors connected in series between the input terminals of the power converter can be balanced by a simple means using a commercially available control IC or the like.

  According to a seventh aspect of the present invention, in the sixth aspect, the first polarity inverting amplifier for inverting the polarity of the first error signal e1 to output the signal -e1, and the polarity of the second error signal e2 A second polarity inverting amplifier that inverts the signal and outputs a signal -e2, a signal -e1 in which the polarity of the first error signal e1 is inverted, and a signal -e2 in which the polarity of the second error signal e2 is inverted, Is a combination of a first inversion addition circuit that inverts and adds, and a second inversion addition circuit that inverts and adds the signal -e1 and the second error signal e2, and the correction error signal eA and The present invention proposes a power converter characterized by forming a correction error signal eB.

According to the seventh aspect, the voltage of the pair of input capacitors connected in series between the input terminals of the power converter can be balanced by a simple means using a commercially available control IC or the like.

According to the present invention, it is possible to configure a power converter using a switching semiconductor element having a withstand voltage lower than a maximum value of a DC voltage obtained by rectifying a commercial high voltage AC voltage such as a 400 V system, Moreover, the power converter can be started stably.

  First, a first embodiment showing the best mode for carrying out the present invention will be described.

  FIG. 1 shows a power conversion apparatus 100 according to the first embodiment of the present invention. The three-phase rectifier 1 rectifies the commercial high-voltage AC power supply voltage of three-phase AC400V, and the rectified voltage becomes a maximum of 620V in consideration of the input power supply voltage fluctuation. As the electrolytic capacitors 2A and 2B for smoothing the rectified voltage, since a normal electrolytic capacitor is about 450V, two 400V electrolytic capacitors are connected in series. Hereinafter, a circuit connected to the capacitor 2A is referred to as an A system circuit, and a circuit connected to the input capacitor 2B is referred to as a B system circuit. Since the A-system circuit and the B-system circuit have the same configuration, the parts of the B-system circuit are given the same reference numerals as the corresponding parts of the A-system circuit. The A system circuit will be described below.

  A voltage-type pulse width control (PWM) bridge inverter 3A connected to the input capacitor 2A converts the DC power supply voltage into high-frequency AC. The inverter 3A is composed of four FETs 4A to 7A which are inexpensive and have a withstand voltage of about 500V. In the case of IGBT, an antiparallel diode is required. The current limiting inductance 8A is connected between the AC output of the inverter 3A and the primary winding of the transformer 9A. The transformer 9A converts the output high-frequency voltage of the inverter 3A into an appropriate voltage, and insulates and isolates the commercial power supply system from the load device system. These constitute the inverter circuit of the A system circuit. A bridge rectifier circuit 10A is connected to the secondary winding 11A of the transformer 9A. The outputs of the bridge rectifier circuits 10 </ b> A and 10 </ b> B, which are the outputs of the A-system and B-system circuits, are connected to the same filter capacitor 12 and DC power is supplied to the load device 13.

  The DC output voltage is detected by the voltage detection circuit 14, and the output current is detected by the current detection circuit 15. These voltage detection signal and current detection signal are multiplied by the multiplier 16 in the control circuit 30 and detected as a power signal. The voltage corresponding to the detected power is compared with the reference voltage value Vr corresponding to the set reference power by the first error amplifier 17, and the first error amplifier 17 generates the first error signal e1. In the case of conventional control, this error signal is directly compared with a triangular wave by a comparator to generate a PWM signal, and the PWM signal is used as an ON signal for the FET. The present invention has the following configuration.

  The voltage V1 across the input capacitors 2A and 2B and the midpoint voltage V2 are detected by the detection resistors 20 and 21 at a ratio of 1: 2. For example, the both-end voltage V1 is detected at 5V when 600V, and the midpoint voltage V2 is detected at a ratio of 5V when 300V. Then, these two detection voltages are compared by a voltage balancing control circuit 22 including a second error amplifier, and a second error signal e2 is generated. The voltage balancing control circuit 22 has a circuit configuration as shown in FIG. 2 and will be described later. As a result of this comparison, the second error signal e2 is + 5V when the voltage of the input capacitor 2A of the A system circuit is relatively higher than the input capacitor 2B of the B system circuit, and is −5V when the voltage is low. When it changes and becomes balanced, it becomes an intermediate value, that is, almost zero.

  The first error signal e1 and the second error signal e2 are added to the subtracter 23 and the adder 24, and the subtractor 23 subtracts the second error signal e2 from the first error signal e1, and the A system. This is the circuit correction error signal eA. Further, the adder 24 adds the first error signal e1 and the second error signal e2 to obtain a correction error signal eB for the B-system circuit. The correction error signal eA of the A-system circuit is compared with a triangular wave given to its inverting terminal by the PWM comparator 25A to generate a PWM signal.

  Here, the first error signal e1 is a signal called an AVR signal in a normal power supply apparatus, and is an output voltage stabilization control signal for controlling the output voltage to a set value. The second error signal e2 is a control signal for the input capacitor voltage that controls the inverters 3A and 3B so that the charging voltages of the input capacitors 2A and 2B are equal to each other. It is fixed to an intermediate value between the value and the minimum value or zero value, and starts in a state that it is assumed that the voltages of the input capacitors 2A and 2B are equal. Therefore, the first error signal e1 can be read as an output voltage stabilization control signal, and the second error signal e2 can be read as a control signal for the input capacitor voltage.

  The correction error signal eB of the B system circuit is compared with a triangular wave applied to its inverting terminal by the PWM comparator 25B to generate a PWM signal. This triangular wave is generated from the same triangular wave generator, and its frequency is twice the conversion frequency of the inverter circuit. This is because, as will be described later, the signal is distributed to the inverters 3A and 3B in two phases by the signal distributors 26A and 26B, and thus becomes half the frequency of the triangular wave. The PWM signal of the PWM comparator 25A is alternately distributed to the two pairs of FETs 4A and 7A, 5A and 6A of the inverter 3A by the signal distributor 26A. Similarly, the PWM signal of the PWM comparator 25B is alternately distributed to the two pairs of FETs 4B and 7B, 5B and 6B of the inverter 3B by the signal distributor 26B.

  First, the basic operation of this power conversion device will be described. The individual circuits themselves such as the inverters 3A and 3B are conventional techniques, and their operation is well known, and therefore will be omitted.

  The two systems, the A system and the B system circuit, vary in the characteristics of electronic components such as FETs and transformers that are switching semiconductor elements. Therefore, even if the same PWM signal is applied to both inverters 3A and 3B, conversion is possible. A difference occurs in the power, and the power extracted from the input capacitors 2A and 2B is different. As a result, the voltages of the input capacitors 2A and 2B are always unbalanced, and if the unbalance becomes too large, the voltage of the input capacitors 2A and 2B exceeds the withstand voltage of the FET 4A-7A, causing a problem of destroying the FET. .

  Therefore, in this power conversion circuit 100, by performing pulse width control using the first error signal e1 corrected by the second error signal e2, a PWM signal of a system in which the voltage of the input capacitor is relatively high And reduce the input capacitor voltage by extracting more current. At the same time, the voltage of the input capacitor is raised by narrowing the PWM signal of the power change marking circuit of the system in which the voltage of the input capacitor is relatively low and extracting a small amount of current.

  The second error signal e2 generates a positive voltage when the voltage of the input capacitor 2A of the A system circuit is higher than the voltage of the input capacitor 2B of the B system circuit. In addition to the signal e1, a correction error signal eA of (e1 + e2) is sent to the PWM circuit of the A system circuit composed of the PWM comparator 25A and the like. Since the PWM comparator 25A generates an H level pulse when the correction error signal eA is higher than the triangular wave, the correction error signal eA of (e1 + e2) widens the pulse width of the PWM signal. At the same time, the second error signal e2 is subtracted from the first error signal e, and the correction error signal eB (e1-e2) is sent to the PWM circuit of the B-system circuit to narrow the pulse width of the PWM signal.

  As a result, in the A-system power conversion circuit in which the pulse width of the PWM signal is widened, the amount of power taken out from the input capacitor 2A increases, so the voltage of the input capacitor 2A decreases, and B in which the pulse width of the PWM signal is narrowed Since the electric power extracted from the system input capacitor 2B is small, the voltage of the input capacitor 2B rises. On the other hand, when the voltage of the input capacitor 2A in the A-system power conversion circuit is lower than the voltage of the input capacitor 2B in the B-system power conversion circuit, the second error amplifier 22 has a negative second error signal e2. And the reverse correction operation is performed.

  By repeating such a pulse width correction operation, the voltages of the input capacitors 2A and 2B in the A-system and B-system power conversion circuits are balanced, and no overvoltage is applied only to the FET of one inverter. Since it does not exceed the withstand voltage of the FET, even if a switching semiconductor element having a withstand voltage lower than the DC input voltage is used, it is not destroyed by overvoltage.

  Next, referring to FIG. 2, a specific example of the voltage balancing control circuit 22 that generates the second error signal e2 having an intermediate value at the time of startup will be described. The voltage balancing control circuit 22 avoids the second error signal e2 being fixed at either the positive or negative level, or the maximum value or the minimum value at the time of start-up, and is always in the middle ( It is characterized in that it is started from a voltage value of 1/2) (for example, almost zero level), thereby preventing an overvoltage from being transiently applied to the switching semiconductor element of either inverter.

  In FIG. 2, balance resistors 31 and 32 are connected in parallel with the input capacitors 2A and 2B, which are electrolytic capacitors. These balance resistors 31 and 32 statically balance the voltages of the input capacitors 2A and 2B before starting the inverters 3A and 3B.

  The voltages of the input capacitors 2A and 2B are detected by detection resistors 33, 34, 35 and 36 connected to the bridge. The detected voltage is input to the inverting input and the non-inverting input of the error amplifier 40 in the switching regulator IC 39, for example, MB3759 (Fujitsu Ltd.) through resistors 37 and 38, for example. The switching regulator IC 39 (MB3759) incorporates a pulse width modulation (PWM) circuit 41 including a triangular wave generation circuit, a comparator, and the like, converts the detection voltage into a PWM signal, and outputs two parallel-connected output transistors. The light emitting diode 45 of the photocoupler 44 is PWM-driven by current signals from the open collector terminals 42 and 43.

  Here, the basic operation of the pulse width modulation (PWM) circuit 41 of the switching regulator IC 39 will be described with reference to FIG. FIG. 3 (1) shows the relationship between the triangular wave Vt and the control voltage Vx that is the input of the PWM circuit 41, and FIG. 3 (2) shows the output voltage Vp of the receiving side amplifier 46 of the photocoupler 44 subjected to PWM modulation. (3) shows the second error signal voltage e2 smoothed by the resistor 48 and the capacitor 49 and outputted from the buffer amplifier 52, respectively. Sections A, B, and C show cases where the control voltage Vx is 1.5V, about 3V, and about 0V, respectively. If the control voltage Vx is 1.5V, the second error signal e2 is zero. The triangular wave oscillates from the minimum value of 0V to the maximum value of 3V.

  Since the two output transistors 42 and 43 are connected in parallel, the on-duty ranges from 0% to almost 100%. The photocoupler 44 includes a photodiode 45 and a receiving side amplifier 46 that amplifies the optical signal from the photodiode 45 and converts it into an electrical signal. The resistor 47 is for limiting the drive current of the photodiode 39. Here, the circuit of the photocoupler 44 is an insulation separation circuit of the signal transmission path between the commercial power system circuit and the DC output system circuit described above.

  The control voltage + Vcc1 and the reference potential COM1 are power supply voltages for the switching regulator IC 39 and the photocoupler 44. The second control power supply voltages + Vcc2 and -Vcc2 are insulated from the control voltage + Vcc1, and COM2 is a reference potential of the control power supply voltages + Vcc2 and -Vcc2.

  The receiving-side amplifier 46 outputs a PWM signal that swings to ± 15V when the second control power supply voltages + Vcc2 and −Vcc2 are ± 15V. The PWM signal is converted into a direct current by a filter circuit including a resistor 48 and a capacitor 49. The Zener diodes 50 and 51 having two anodes connected to each other limit the signal level to ± 5V. This signal level is -5V when the on-duty of the PWM signal is 0%, and + 5V when the on-duty is 100%. What is important is that when the on-duty is 50%, it becomes zero V which is an intermediate level of ± 5V.

  In this embodiment, another operational amplifier 53 incorporated in the switching regulator IC 39 (MB3759) is used. The inverting input of the operational amplifier 53 is connected to the output of the operational amplifier 53 and functions as a voltage buffer. The non-inverting input of the operational amplifier 53 is a voltage (for example, the maximum value of the triangular wave) at the connection point between the voltage dividing resistors 55, 56 of the voltage dividing resistors 54, 55, 56 that divides the reference voltage 5V built in the switching regulator IC 39. It is connected to 1.5V which is a voltage value of 1/2 of the minimum value. The two output signals of the error amplifier 40 and the operational amplifier 53 are added together to generate a control voltage Vx. Here, regarding the output signals of the error amplifier 40 and the operational amplifier 53, the output signal on the high level side that works to narrow the pulse width of the inverter has priority over the other low level output signals. The control voltage Vx is compared with the internal triangular wave by the PWM circuit 41, and the PWM circuit 41 outputs a PWM modulation signal.

  Further, the collector and emitter of the light receiving transistor 58 of the activation photocoupler 57 are connected across the resistors 55 and 56. The light emitting diode 59 of the photocoupler 57 is driven by the starting transistor 61 through the resistor 60 from the second control power source + Vcc2. Furthermore, an FET 62 is connected between the non-inverting terminal of the constant voltage control error amplifier 40 and the zero level reference potential point. The collector of the phototransistor 58 is connected to the gate of the FET 62 and to the connection point between the voltage dividing resistors 54 and 55.

  Next, the operation of the voltage balancing control circuit 22 shown in FIG. 2 will be described. Before the inverters 3A and 3B are activated, the voltages of the input capacitors 2A and 2B are statically balanced by the action of the balance resistors 31 and 32. However, as described above, the voltage is not completely the same due to variations in the characteristics of the electronic components. Therefore, if the circuit configuration shown in FIG. 2 is not used, the output voltage of the error amplifier 40 of the switching regulator IC 39 is the minimum value. Either zero level or the maximum voltage of 3V.

  In this embodiment, before activation, the activation transistor 61 is off and the light-emitting diode 59 of the photocoupler 57 is also off, so that the light-receiving transistor 58 is also off and its collector voltage is about 4V. Therefore, since the gate voltage of the FET 62 becomes H level, the FET 62 is on, and the non-inverting input of the error amplifier 40 is short-circuited to zero level. Therefore, the detection voltage of the voltage across the input capacitors 2A and 2B is set to zero level. On the other hand, the detection voltage of the midpoint voltage of the input capacitors 2A and 2B is input to the inverting input, and both detection voltages are compared with each other. However, the detection voltage of the voltage across the input capacitors 2A and 2B is zero level. For this reason, the output of the error amplifier 40 becomes zero.

On the other hand, since the phototransistor 58 is off, the non-inverting terminal of the operational amplifier 53 is 1.5V as described above, and the output voltage of the operational amplifier 53 is also 1.5V. Since the higher output voltage of the error amplifier 40 and the operational amplifier 53 has priority, the control voltage Vx that is the input of the PWM circuit 41 is 1.5 V that is the output voltage of the operational amplifier 53. Since the voltage value of 1.5 V is an intermediate voltage value between the maximum value and the minimum value of the triangular wave Vt as described above, the duty of the pulse width of the pulse width modulation signal output from the PWM circuit 41 is 50%. Since the 50% duty signal is applied to the non-inverting input of the operational amplifier 52 via the photocoupler 44 and the resistor 48, the error signal e2 of the operational amplifier 52 becomes zero as described above.

  Next, when the activation transistor 61 is turned on by the activation signal and the light emitting diode 59 of the photocoupler 57 emits light, the phototransistor 58 is turned on, the non-inverting input of the operational amplifier 53 is zero, and the output of the operational amplifier 53 is also zero. Become. As described above, since the output of the error amplifier 40 and the operational amplifier 53 is given higher priority, the output of the error amplifier 40 is given priority.

  On the other hand, since the FET 62 is turned off when the phototransistor 58 is turned on, the error amplifier 40 responds to the difference between the detected voltage of the voltage across the input capacitors 2A and 2B and the detected voltage of the midpoint voltage of the input capacitors 2A and 2B. This error signal becomes the control voltage Vx. At the time of start-up, the control voltage Vx always starts from an intermediate value of 1.5 V, so that the pulse width of the pulse width modulation signal output from the PWM circuit 41 Therefore, the second error signal e2, that is, the control signal of the input capacitor voltage is started from the zero level, and the control circuit 30 shifts to a normal operation according to the voltage imbalance immediately after starting.

  If the control circuit 30 does not have the voltage balancing control circuit 22 as shown in FIG. 2, the second error signal e2 is an error signal having a maximum value or a minimum value that is not an intermediate level, and thus the inverter 3A, The pulse width of one PWM signal of 3B becomes larger than that of the other, causing a transient overshoot, greatly imbalances the voltages of the input capacitors 2A and 2B, and damages the inverter FET.

  With reference to FIG. 4, a power converter 200 according to a second embodiment that controls the frequency of an inverter will be briefly described. In the case of frequency control, voltage controlled oscillators 27A and 27B are used instead of the PWM comparators 25A and 25B shown in FIG. The voltage controlled oscillator (VCO) generates an output voltage signal having a frequency that changes in accordance with the magnitude of the input voltage signal. Therefore, the voltage controlled oscillators 27A and 27B have the correction error signal eA and the correction error signal eB. A control signal having a frequency corresponding to the magnitude is generated.

  Increase the frequency of the control signal of the power converter circuit of the system where the input capacitor voltage is relatively high and reduce the voltage of the input capacitor by extracting a large amount of current. At the same time, the voltage of the system where the input capacitor voltage is relatively low As in the previous embodiment, the frequency of the control signal of the power conversion circuit is lowered, the voltage of the input capacitor is increased by taking out a small amount of current, and the voltages of both input capacitors 2A and 2B are balanced. . By repeating such a control signal frequency correction operation, the voltages of the input capacitors 2A and 2B in the A-system and B-system power conversion circuits are balanced, and no overvoltage is applied only to the FET of one inverter. Since it does not exceed the withstand voltage of the FET of the inverter, even if a switching semiconductor element having a withstand voltage lower than the DC input voltage is used, it is not destroyed by overvoltage.

  Also in the power conversion device 200 of the second embodiment, an overvoltage is not applied to the switching semiconductor element of one of the inverters 3A or 3B at the time of startup using the voltage balancing control circuit 22 having the configuration shown in FIG. However, since the operation is exactly the same as that of the power conversion apparatus 100, the description thereof is omitted.

  FIG. 5 shows a specific example in which the addition unit and the subtraction unit in the power conversion apparatus 100 shown in FIG. 1 are formed by operational amplifiers (operational amplifier μPC451 / NEC). The error amplifier 17 corresponds to the first error amplifier in FIG. 1 and outputs an error signal e1. When the error signal e1 becomes a high level, the DC output level of the power converter is increased. The error amplifier 22 corresponds to the start-up stabilization circuit 22 in FIG. 1 and outputs an error signal e2. The error signal e2 becomes high when the voltage of the input capacitor 2A becomes higher than that of the input capacitor 2B.

  The polarity inverting amplifiers 71 and 72 are well-known ones combined with resistors 73 and 74, 75 and 76 having the same resistance value, and error signals -e1 and errors obtained by inverting the error signals e1 and e2, respectively. The signal -e2 is output.

  The inverting adder circuits 77 and 78 are well-known circuits combined with resistors 79 and 80, 81 and 82 having the same resistance value. The inverting addition circuit 77 receives the error signal -e1 and the error signal -e2, inverts and adds the error signals, and outputs a corrected error signal eA (e1 + e2). The inverting addition circuit 78 receives the error signal −e1 and the error signal e2, inverts and adds the error signals, and outputs a corrected error signal eB (e1−e2). These correction error signals eA and eB are input to PWM comparators corresponding to the PWM comparators 25A and 25B in FIG. 1, and these PWM comparators provide PWM signals to the signal distributor as in FIG.

  In FIG. 2, the voltage V1 at both ends of the input capacitors 2A and 2B and the voltage V2 at the midpoint of the input capacitors 2A and 2B are detected by connecting four voltage detection resistors 33 to 36 to the bridge. Two resistors (not shown) are connected so as to form a bridge with the input capacitors 2A and 2B, a voltage detection signal is input to an error amplifier (for example, corresponding to the error amplifier of FIG. 1), and the voltage V1, The voltage V2 can also be detected. Further, Hall CT (not shown) using a Hall element as a current detector between the connection point of the input capacitors 2A and 2B and the connection point of the two resistors (not shown) in such a bridge configuration. And the voltage V1 and the voltage V2 can be detected by inputting a voltage detection signal detected by the Hall CT to the error amplifier.

In the above embodiment, the load voltage and the load current are detected and multiplied to obtain the output power, and the first error signal e1 is obtained from the voltage signal corresponding to the output voltage and the reference voltage. The first error signal e1 may be obtained simply from the voltage signal corresponding to one of the detected values of the load voltage and the load current and the reference voltage, and constant voltage control or constant current control may be performed. Although the DC outputs of the two inverters are parallel, it is of course possible to combine them in series.

As an application example of the present invention, it is suitable as an energy conversion device that supplies DC power to a discharge load that requires a relatively large load current at a relatively high voltage, such as an excimer laser device or an X-ray device.

It is a figure which shows the power converter device 100 of the 1st Example which concerns on this invention. It is a figure which shows the starting stabilization circuit 220 which is a part of the power converter device 100 of 1st Example based on this invention. It is a figure which shows the operation | movement waveform for demonstrating the power converter device. It is a figure which shows the power converter device 200 of the 2nd Example which concerns on this invention. An example of a circuit that generates a correction error signal used in the power conversion apparatus 100 or 200 is shown.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Input side rectifier 2A, 2B ... Input capacitor 3A, 3B ... A system, B system inverter 4A-7A ... Switching semiconductor element (FET)
4B-7B ... Switching semiconductor element (FET)
8A, 8B ... Current limiting inductance 9A, 9B ... Transformer 10A, 10B ... Output side rectifier circuit 13 ... Load 14 ... Output voltage detection resistor 15 ... Output current detection circuit 16 ... Multiplier 17 ... Error amplifier 22 ... Voltage balancing control circuit 23 ... Subtractor 24 ... Adder 25A, 25B ... Comparator 26A, 26B ... Signal distributor 27A, 27B: Voltage controlled oscillator (VCO)
30 ... Control circuit 31, 32 ... Balance resistor 33-36 ... Voltage detection resistor 39 ... Switching regulator IC
40 ... Error amplifier 41 ... PWM (pulse width modulation) circuit 44, 57 ... Photocoupler 52, 53 ... Operational amplifier

Claims (7)

First and second input capacitors connected in series to each other connected between output terminals of the DC input power supply;
Input terminals are connected to both ends of each of these input capacitors, and primary windings are connected to the first and second inverters and the first and second inverters, and electromagnetically coupled to the primary windings. First and second inverter circuits comprising first and second transformers having secondary windings,
First and second rectifier circuits for converting the alternating voltage of each secondary winding into direct current;
A control circuit for generating a control signal for controlling the first and second inverters;
A balance resistor connected in parallel with each of the first and second input capacitors and having a resistance value substantially equal to each other;
A power converter that synthesizes the DC output of each of these rectifier circuits,
The control circuit includes:
A first error signal e1 that is an error signal between a signal corresponding to a detected value of any one of the DC output power, output voltage, and output current synthesized by the rectifier circuit and a predetermined reference value is output. An error amplifier of
Control for balancing the voltages of the first and second input capacitors, comprising a second error amplifier that compares the detected voltages of the respective voltages of the first and second input capacitors and outputs an error signal. A voltage balancing control circuit for outputting a second error signal e2 serving as a signal;
A circuit for adding and subtracting the first error signal e1 and the second error signal e2, and outputting the control signal;
Before starting the inverter circuit with a start signal, the second error signal e2 is forcibly fixed to a midpoint voltage value or zero value between a predetermined minimum voltage value and a maximum voltage value, The fixation is released by the activation signal, and the second error signal e2 changes from the voltage value at the midpoint according to the detected voltage of the voltage of the first and second input capacitors,
The control signal increases the output of the inverter connected to the input capacitor on the higher voltage side and decreases the output of the inverter connected to the input capacitor on the lower voltage side, A power converter that stably starts the inverter circuit and balances the voltages of the first and second input capacitors. In claim 1,
The pulse width of the inverter circuit is controlled, the pulse width of the pulse width modulation signal supplied to the inverter circuit on the higher side of the input capacitor is widened, and the pulse supplied to the inverter circuit on the lower side of the input capacitor voltage A power converter that narrows a pulse width of a width modulation signal. In claim 1 or claim 2,
The inverter circuit is controlled by frequency modulation, the frequency of the frequency modulation signal supplied to the inverter circuit on the higher side of the input capacitor is increased, and the voltage of the input capacitor is supplied to the lower inverter circuit. A power converter that lowers the frequency of a frequency modulation signal. In any one of Claims 1 thru | or 3,
The voltage balancing control circuit includes a switch connected between an input terminal of the second error amplifier to which a detection voltage of the voltage of the input capacitor is input and a reference potential point, and the switch is not activated. The power converter is characterized in that the input terminal is short-circuited and the short-circuit is canceled by a start signal. In any one of Claims 1 thru | or 4,
The voltage balancing control circuit includes an operational amplifier that outputs a voltage signal having a magnitude equal to a midpoint voltage value between the predetermined minimum voltage value and maximum voltage value before startup, and before startup. The output of the operational amplifier has priority over the output of the second error amplifier, and the output of the second error amplifier has priority over the output of the operational amplifier after startup. In any one of Claims 1 thru | or 5,
A subtractor that subtracts the second error signal e2 from the first error signal e1 to output a first correction error signal eA;
A first PWM comparator that compares the error correction signal eA and the triangular wave signal to generate a pulse width modulation signal;
A signal distributor for distributing the pulse width modulation signal to the first inverter;
An adder that adds the second error signal e2 to the first error signal e1 and outputs a corrected error signal eB;
A second PWM comparator for comparing the error correction signal eB and the triangular wave signal to generate a pulse width modulation signal;
A power converter comprising: a signal distributor that distributes the pulse width modulation signal to the second inverter. In claim 6,
A first polarity inverting amplifier for inverting the polarity of the first error signal e1 to output a signal -e1;
A second polarity inverting amplifier for inverting the polarity of the second error signal e2 and outputting a signal -e2;
A first inversion addition circuit that inverts and adds the inverted signal -e1 of the first error signal e1 and the inverted signal -e2 of the second error signal e2.
A second inverting addition circuit for inverting and adding the signal -e1 and the second error signal e2;
A power conversion apparatus characterized in that the correction error signal eA and the correction error signal eB are formed by a combinational circuit.

Images