JP2004343039A - Semiconductor structure, semiconductor device, and method and apparatus for manufacturing them - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor structure, a semiconductor device, and a method and apparatus for manufacturing them which can improve the electric characteristic of an active element. <P>SOLUTION: The semiconductor device has a non-single-crystal semiconductor film (14), a supporting substrate (12) for supporting the non-single-crystal semiconductor film (14), and an active element (10) having a portion of the non-single-crystal semiconductor film (14) as its channel region (22). Especially, the channel region (22) has its oxygen and carbon concentration both of which do not exceed 1×10<SP>18</SP>atoms/cm<SP>3</SP>. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor structure in which a non-single-crystal semiconductor film is supported by a supporting substrate, a semiconductor device, a manufacturing method thereof, and a manufacturing apparatus.

  In a recent active matrix type liquid crystal display device, a polycrystalline semiconductor thin film transistor has been used as a pixel switching element. This polycrystalline thin film transistor has a channel region arranged in a polycrystalline semiconductor film including a plurality of crystal grains. The carriers (ie, electrons or holes) in the channel region move about 10 to 100 times faster than the carriers in the channel region arranged in the amorphous semiconductor film. Therefore, the polycrystalline semiconductor thin film transistor operates at high speed as a pixel switching element. In addition, by constructing an image processing circuit using a similar group of polycrystalline semiconductor thin film transistors and incorporating the same in a liquid crystal display device, it becomes possible to cope with a reduction in calculation time required as the number of pixels increases.

  The polycrystalline semiconductor film is obtained, for example, by melting and recrystallizing a semiconductor film of amorphous silicon or the like by an excimer laser crystallization method. This excimer laser crystallization method allows the crystal grains generated in the semiconductor film to grow to a large grain size, and significantly reduces the number of crystal grain boundaries that hinder carrier movement. It has been widely used in the past.

  Here, a manufacturing process of the polycrystalline semiconductor thin film transistor will be described. 1A to 1F show a process for manufacturing a polysilicon thin film transistor which is an example of a polycrystalline semiconductor thin film transistor. The channel region of the polysilicon thin film transistor is disposed in a polysilicon film formed by using the above-described excimer laser crystallization method.

  In the step shown in FIG. 1A, a base insulating layer 102 is formed on a glass substrate 101, an amorphous silicon film 103 is formed on the base insulating layer 102, and thereafter, a dehydrogenation treatment is performed. This is performed on the amorphous silicon film 103.

  In the step shown in FIG. 1B, the glass substrate 101 is moved in a direction indicated by an arrow 105, and an excimer laser beam is applied to the amorphous silicon film 103 which moves together with the glass substrate 101. By the scanning with the laser light, the amorphous silicon film 103 is melted and recrystallized into the polysilicon film 106 shown in FIG.

  In the step shown in FIG. 1D, the polysilicon film 106 is removed from the base insulating layer 102 except for a predetermined region required as a part of the thin film transistor. Subsequently, a gate insulating film 107 is formed to cover the polysilicon film 106 and the base insulating layer.

  In the step shown in FIG. 1E, the gate electrode layer 110 is formed on the gate insulating film 107. The gate electrode layer 110 also serves as a mask for implanting n-type or p-type impurities into the polysilicon film 106. This impurity is injected into the polysilicon film 106 via the gate insulating film 107, thereby forming a source region 108 and a drain region 109 located on both sides of the gate electrode layer 110 in the polysilicon film 106.

  In the step shown in FIG. 1F, an interlayer insulating film 111 is formed to cover the gate insulating film 107 and the gate electrode layer 110. After that, heat treatment is performed to activate impurities in the source region 108 and the drain region 109. The gate insulating film 107 and the interlayer insulating film 111 are partially removed so as to form a pair of contact holes exposing the source region 108 and the drain region 109, respectively, and the source electrode layer 112 and the drain electrode layer 113 are removed in these contact holes. It is formed to be in electrical contact with the source region 108 and the drain region 109. The metal wiring layer 114 is formed in contact with the drain electrode 113 as a wiring for transmitting an electric signal to the thin film transistor.

  The polysilicon thin film transistor is manufactured through the above manufacturing steps. In this thin film transistor, a gate voltage is applied to the gate electrode layer 110 to control a current flowing in a channel region 115 disposed between the source region 108 and the drain region 109. This polysilicon thin film transistor and its manufacturing method are disclosed in, for example, Japanese Patent Application Laid-Open No. 2002-289865, pp. 4-5 and FIG.

  However, the structure and manufacturing method of a conventional polycrystalline semiconductor thin film transistor include factors that degrade electrical characteristics of the thin film transistor, which are important for application to a liquid crystal display device.

  The following is the result of consideration by the present inventor.

  (1) The channel region contains an impurity element that causes an atomic structural defect. This defect acts as a trap for carriers that cause electrical conduction, thereby hindering the movement of carriers in the channel region. Such an impurity element is a contaminant that should be essentially distinguished from the impurity element implanted into the source and drain regions, and specifically includes elements contained in the atmosphere (light elements such as oxygen and carbon). Element). Such an element remains in a film formation chamber of a conventional semiconductor manufacturing apparatus and is mixed into a semiconductor film during a film formation process.

  (2) In addition, metal elements which are components of the inner wall material of the film formation chamber are physically or chemically separated or separated and float in the film formation chamber, and these elements are also mixed into the semiconductor film during the film formation process. Then, the electrical characteristics of the semiconductor itself are changed. Examples of such metal elements include chromium, potassium, sodium, aluminum, calcium, titanium, zinc, cobalt, copper, iron, nickel, molybdenum, manganese, vanadium, and tungsten.

  (3) Further, the supporting substrate for the semiconductor film is a glass substrate having a heat-resistant temperature of at most about 600 ° C. As this support substrate, annealed glass or plastic substrate can be used, but their heat-resistant temperatures are even lower. The above-described gettering process for removing a light element or a metal element from a semiconductor film requires a high temperature exceeding the heat-resistant temperature of the supporting substrate, so that the gettering process cannot be applied to the supporting substrate.

Further, JP 2002-289865 discloses an oxygen, the atomic number of impurity elements such as 1 cm ³ per 5 × ^{10 18} or less nitrogen, good characteristics by preferably reduced to 1 × ^{10 18} per 1 cm ³ Is obtained. However, this concentration is for a single light element and does not take into account the relationship between a plurality of light elements and minute defects in the atomic structure of the semiconductor film.

JP 2002-289865 A

  An object of the present invention is to provide a semiconductor structure, a semiconductor device, and a method and an apparatus for manufacturing the same, which can improve the electrical characteristics of an active element.

According to a first aspect of the present invention, there is provided a non-single-crystal semiconductor film including a channel region for an active element, and a supporting substrate for supporting the non-single-crystal semiconductor film, and each of the channel regions is 1 × 10 ¹⁸ atoms / A semiconductor structure having an oxygen concentration and a carbon concentration not exceeding cm ³ is provided.

  According to a second aspect of the present invention, there is provided a method for manufacturing a semiconductor structure including a non-single-crystal semiconductor film including a channel region for an active element and a support substrate supporting the non-single-crystal semiconductor film, the method comprising: The inner wall of the chamber is subjected to etching surface treatment with a fluorine-based gas, the inner wall is covered with an amorphous semiconductor film having a thickness of 50 nm to 1000 nm, the supporting substrate is accommodated in the film formation chamber, and a non-single-crystal semiconductor film is formed. A manufacturing method for heating and melting and recrystallizing a single crystal semiconductor film is provided.

  According to a third aspect of the present invention, there is provided an apparatus for manufacturing a semiconductor structure, comprising: a non-single-crystal semiconductor film including a channel region for an active element; and a support substrate for supporting the non-single-crystal semiconductor film, comprising: And a crystallization unit that melts and recrystallizes the non-single-crystal semiconductor film by containing a film in a film-forming chamber, and the film-forming chamber is made of a metal containing aluminum. A manufacturing device having an inner wall is provided.

According to a fourth aspect of the present invention, there is provided a non-single-crystal semiconductor film, a support substrate for supporting the non-single-crystal semiconductor film, and an active element having a part of the non-single-crystal semiconductor film as a channel region. Provide a semiconductor device having an oxygen concentration and a carbon concentration not exceeding 1 × 10 ¹⁸ atoms / cm ³ .

According to a fifth aspect of the present invention, there is provided a non-single-crystal semiconductor film, a support substrate for supporting the non-single-crystal semiconductor film, and an active element having a part of the non-single-crystal semiconductor film as a channel region. Provides a semiconductor device having an oxygen concentration not exceeding 1 × 10 ¹⁸ atoms / cm ³ and a stacking fault density not ^exceeding 1 × 10 ⁶ cm ^-3 .

  According to a sixth aspect of the present invention, there is provided a semiconductor device including a non-single-crystal semiconductor film, a support substrate supporting the non-single-crystal semiconductor film, and an active element having a part of the non-single-crystal semiconductor film as a channel region. In a manufacturing method, an inner wall of a film formation chamber is subjected to etching surface treatment with a fluorine-based gas, the inner wall is covered with an amorphous semiconductor film having a thickness of 50 nm to 1000 nm, and a supporting substrate is accommodated in the film formation chamber and non-single-united. A manufacturing method is provided in which a crystalline semiconductor film is formed, the non-single-crystal semiconductor film is melted and recrystallized by heating, and an active element having a part of the non-single-crystal semiconductor film as a channel region is provided.

In these semiconductor structures and semiconductor devices, the channel region has an oxygen concentration and a carbon concentration not exceeding 1 × 10 ¹⁸ atoms / cm ³ . In the case where at least the channel region in the non-single-crystal semiconductor film has such an oxygen concentration and a carbon concentration, minute defects generated in the crystal structure of the channel region due to these elements do not hinder practical use at 1 × 10 ⁶ cm ⁻ It can be reduced to a very small value of about ³ . Thereby, carriers in the channel region can move at high speed without being significantly hindered by these minute defects. Therefore, good electrical characteristics of the active element can be improved.

  In the method for manufacturing a semiconductor structure and the method for manufacturing a semiconductor device, the inner wall of the deposition chamber is subjected to an etching surface treatment with a fluorine-based gas and covered with an amorphous semiconductor film having a thickness of 50 nm to 1000 nm. As a result, contaminant elements are removed from the inner wall surface of the deposition chamber by the etching surface treatment, and fluorine mixed in the etching surface treatment can also be separated from the inner wall of the deposition chamber into the space in the deposition chamber by the amorphous semiconductor film. Disappears. Thus, contaminants mixed into the non-single-crystal semiconductor film during film formation can be reduced. Therefore, good electrical characteristics of the active element can be improved.

  Furthermore, in the apparatus for manufacturing a semiconductor structure, the film forming chamber has an inner wall made of a metal containing aluminum. As a result, when cleaning with a fluorine-based gas is performed, aluminum, which is a metal component of the inner wall, combines with fluorine to form a fluorine compound. When aluminum and fluorine are contained in the inner wall as a fluorine compound as described above, aluminum and fluorine separate from the inner wall of the deposition chamber into the space in the deposition chamber and contaminate the non-single-crystal semiconductor film during deposition. Is prevented from being mixed. Therefore, good electrical characteristics of the active element can be improved.

  Hereinafter, a semiconductor device according to an embodiment of the present invention will be described with reference to the drawings. This semiconductor device is used, for example, to incorporate it into an active matrix type liquid crystal display device.

  FIG. 2 shows a cross-sectional structure of the semiconductor device. The semiconductor device includes at least one active element 10, a support substrate 12, and a non-single-crystal semiconductor film 14 including a plurality of crystal grains. The support substrate 12 supports the non-single-crystal semiconductor film 14. The active element 10 is a thin film transistor that constitutes a pixel switching element or a component of a video processing circuit in the above-described active matrix liquid crystal display device, and has a part of the non-single-crystal semiconductor film 14 as a channel region. As the support substrate 12, for example, a semiconductor substrate containing silicon or another semiconductor, or an insulating substrate made of a material such as Corning 1737 glass, fused quartz, sapphire, plastic, or polyimide can be used. Here, a 1737 glass substrate is used as the support substrate 12. In addition, as the semiconductor film 14, a layer containing a semiconductor such as silicon (ie, Si) or silicon gen-rumanium (ie, SiGe) can be used. Here, the non-single-crystal semiconductor film 14 is made of silicon.

  As shown in FIG. 2, active element 10 includes a gate insulating film 16 covering non-single-crystal semiconductor film 14, and a gate electrode layer 18 disposed on gate insulating film 16. The semiconductor film 14 is formed on a base insulating layer 20 that covers the support substrate 12. However, the semiconductor film 14 may be formed directly on the support substrate 12 without the intermediary of the base insulating layer 20.

The semiconductor film 14 has a channel region 22 disposed below the gate electrode layer 18, and a source region 24 and a drain region 26 disposed on both sides of the channel region 22 and containing p-type or n-type impurities. Here, the source region 24 and the drain region 26 contain an n-type impurity. The gate insulating film 16 is made of, for example, an oxide such as silicon dioxide (that is, SiO ₂ ), and electrically insulates the gate electrode layer 18 from the channel region 22 so that the thin film transistor functions as an electric field transistor. The channel region 22 is a region for moving carriers such as electrons or holes between the source region 24 and the drain region 26. The movement of the carriers is caused by an electric field corresponding to the gate voltage applied to the gate electrode layer 18. Controlled.

The base insulating layer 20 serves to prevent impurities in the support substrate 12 such as a glass substrate from moving to the semiconductor film 14. Here, the base insulating layer 20 is made of SiO ₂ . The base insulating layer 20 is made of, for example, silicon dioxide (ie, SiO ₂ ), silicon nitride (ie, SiN), a two-layer structure of silicon nitride and silicon dioxide (ie, SiN / SiO ₂ ), alumina, mica, or the like. It may be made of an oxide. Further, when the base insulating layer 20 has a two-layer structure of the SiN layer covering the support substrate 12 and the SiO ₂ layer covering the SiN layer, the effect of preventing the migration of impurities is further enhanced.

Non-single-crystal semiconductor film 14 has a carbon concentration not exceeding oxygen concentration and 1 × ^{10 18} atoms / cm ³ not exceeding 1 × ^{10 18} atoms / cm ^3. That is, the number of carbon atoms and oxygen atoms is 1 × 10 ¹⁸ or less per 1 cm ³ . When at least the channel region 22 of the semiconductor film 14 has such an oxygen concentration and a carbon concentration, minute defects generated in the crystal structure of the channel region 22 due to these elements are reduced to 1 × 10 ⁶ / cm which does not hinder practical use. It can be set to an extremely small value of about ³ . Thus, carriers in the channel region 22 can move at high speed without being significantly hindered by these minute defects. Therefore, the thin film transistor can obtain favorable electric characteristics for performing high-speed switching operation.

Here, the non-single-crystal semiconductor film 14 is more preferably a carbon concentration not exceeding 5 × 10 ¹⁷ atoms / cm ³ oxygen concentration and 5 × 10 ¹⁷ atoms / cm ³ not exceeding. That is, the number of oxygen atoms and carbon atoms is 5 × 10 ¹⁷ or less per 1 cm ³ . When at least the channel region 22 of the semiconductor film 14 has such an oxygen concentration and a carbon concentration, the quality of the channel region 22 is improved.

Further, the non-single-crystal semiconductor film 14 preferably has a metal element concentration not exceeding 1 × 10 ¹⁷ atoms / cm ³ . That is, the number of metal atoms is 1 × 10 ¹⁷ or less per 1 cm ³ . When at least the channel region 22 of the semiconductor film 14 has such a concentration of the metal element, generation of a metal oxide which causes a decrease in the resistivity of the semiconductor film 14 is suppressed. When the number of metal atoms is 5 × 10 ¹⁶ or less per 1 cm ³ , generation of metal oxide is further suppressed, and the resistivity can be set to a value that does not hinder practical use.

In the non-single-crystal semiconductor film 14, a plurality of crystal grains have a growth direction set in the same direction. This growth direction matches the arrangement direction of the source region 24 and the drain region 26 described above. In other words, the source region 24, the channel region 22, and the drain region 26 are arranged along the crystal grain growth direction. Further, these crystal grains have a grain size greater than the length of the channel region 22 in the growth direction, and the channel region 22 is arranged in a single crystal grain. In this case, the crystal boundary does not exist in the channel region 22, and it is possible to eliminate the inhibition of carrier movement caused by the crystal boundary in the channel region 22. As described above, reducing the number of oxygen atoms and carbon atoms to 1 × 10 ¹⁸ or less per 1 cm ³ greatly contributes to reducing minute defects in the crystal structure. Practically, if the crystal grain size is at least one-quarter of the length of the channel region 22, for example, the crystal grain size at the time when the channel region 22 has a length of 2 μm is at least 0.5 μm, Can relatively reduce the number of crystal grain boundaries encountered in the channel region 22, which confirms the effect of eliminating impurity elements.

The length (drawing gate length) of the channel region 22 in the arrangement direction of the source region 24 and the drain region 26 is longer than the length (effective gate length) of the gate electrode layer 18 in the arrangement direction. At least in the range of the effective gate length, if there is no crystal grain boundary and the number of oxygen atoms and carbon atoms is 1 × 10 ¹⁸ or less per 1 cm ^{3, the} above-mentioned effect is exhibited. Further, within the range of the drawing gate length, the effect is further exhibited.

Next, in order to extremely reduce minute defects in the crystal structure of the channel region 22, the number of oxygen atoms and carbon atoms in the channel region 22 should not exceed 1 × 10 ¹⁸ per 1 cm ^3. The validity will be described in more detail.

  1. Correlation between oxygen and carbon and stacking fault density

1cm oxygen concentration is the number of oxygen atoms per ³ [atoms / cm ^3], a 1cm carbon concentration is the number of carbon atoms per ³ [atoms / cm ^3], per 1cm ³ of the semiconductor film 14 crystal structure The correlation with the stacking fault density [cm ⁻³ ], which is the amount of defects, was examined from a plurality of samples.

Each sample was prepared as follows. Here, equipment capable of maintaining low concentrations of contaminants such as oxygen and carbon was used only for experimentally prepared samples. A supporting substrate 12 made of Corning # 1737 glass was prepared, and a base insulating layer 20 was formed on the supporting substrate. The base insulating layer 20 has a double structure in which a silicon nitride (SiN _x ) layer having a thickness of 50 nm and a silicon oxide (SiO _x ) layer having a thickness of 100 nm are stacked in this order. On the base insulating layer 20, an amorphous silicon film was formed with a thickness of 200 nm.

For such a sample, the concentrations of the elements oxygen, carbon and nickel in the amorphous silicon film are measured by a secondary ion mass spectroscopy (SIMS) manufactured by CAMECA of Courbevoie, France. Was done. This apparatus irradiates the layer with an ion beam using ions of, for example, O ⁺ , Cs ^+, etc. as irradiation ions from above the layer, and secondary ions generated from atoms or molecules in the layer emitted from the layer surface by a sputtering phenomenon. Secondary ion mass spectrometry, which performs mass analysis of elements by detecting ions, is employed. The ion beam is continuously irradiated, whereby the layer is continuously etched by the sputtering phenomenon, and mass analysis is performed in the depth direction of the layer.

The concentrations of oxygen, carbon and nickel in the amorphous silicon film were measured as initial concentrations immediately after the formation of the amorphous silicon film. According to this measurement result, the initial concentration of oxygen is 2 × 10 ¹⁷ atoms / cm ³ or less, the initial concentration of carbon is 3 × 10 ¹⁶ atoms / cm ³ or less, and the initial concentration of nickel is 5 × 10 ¹⁵ atoms / cm ³ or less. there were. The initial concentration of nickel is a value less than the lower limit of analysis of a SIMA device manufactured by Kameka.

After confirming such initial concentrations of oxygen, carbon and nickel, oxygen and carbon were implanted into the amorphous silicon film of each sample by an ion implantation method. Here, as shown in FIG. 3, 15 types of samples were obtained by combining a three-stage carbon dose and a five-stage oxygen dose. The acceleration energy is energy for moving atoms so that the implanted element is implanted into the amorphous silicon film. The acceleration energy of carbon is 100 KeV, and the acceleration energy of oxygen is 130 KeV. The dose is represented by the number of implanted element atoms passing through a unit area of 1 cm ² .

FIG. 4 shows the concentration of carbon and oxygen obtained in the amorphous silicon film with respect to the dose shown in FIG. These carbon and oxygen concentrations are the average number of carbon and oxygen atoms present per unit volume of 1 cm ³ . On such an amorphous silicon film, an insulating layer (hereinafter, referred to as a “cap layer”) made of silicon oxide (SiO _x ) having a thickness of 300 nm is formed. Thereafter, a laser annealing process was performed on the amorphous silicon film. In this laser annealing process, the amorphous silicon film is irradiated with a KrF excimer laser beam through a phase shifter that modulates at least a part of the laser beam, and the amorphous silicon film is melted and recrystallized to form polysilicon. Changed to a membrane. Irradiation conditions were such that the number of times of irradiation was once and the irradiation fluence was 560 mJ / cm ² on average in the irradiation surface. Here, the cap layer prevents the ablation phenomenon in which silicon disappears from a part of the amorphous silicon film due to ablation due to irradiation with KrF excimer laser light.

  After the polysilicon film is obtained as a result of melting and recrystallization by the laser annealing process described above, minute defects in the crystal structure of the polysilicon film are detected by X-ray diffraction analysis of the polysilicon film. This was investigated by taking an X-ray diffraction image and analyzing the peak shift of the diffraction image.

  FIG. 5 shows the oxygen concentration dependency of the stacking fault density of the polysilicon film using the carbon concentration shown in FIG. 4 as a parameter. The lower limit of measurement indicated by a dotted line in FIG. 5 is determined in consideration of the reproducibility, that is, the reliability of the measured value in the measurement of the stacking fault density. In the analysis of the peak shift of the diffraction image at the present time in the X-ray diffraction apparatus, when the stacking fault density is extremely low, the analysis result depends on the analysis performance of the analysis apparatus or the interpretation of the analyst. Because it is different.

As can be seen from FIG. 5, when both the carbon concentration and the oxygen concentration are 1 × 10 ¹⁸ atoms / cm ³ , the stacking fault density decreases to a value slightly higher than the lower limit of measurement. Furthermore, when both the carbon concentration and the oxygen concentration are 5 × 10 ¹⁷ atoms / cm ³ , the stacking fault density decreases to a value lower than the lower limit of measurement.

  2. Correlation between stacking fault density and oxygen, carbon and metal elements

  Next, a case where not only oxygen and carbon but also nickel (that is, Ni) is implanted as a metal element into the amorphous silicon film of each sample in which the initial concentrations of oxygen, carbon, and nickel are confirmed as described above will be described. . Since nickel has a heavy atomic weight of about 59, it is difficult to sufficiently inject nickel into the amorphous silicon film via the cap layer existing on the amorphous silicon film. Therefore, nickel is implanted into the amorphous silicon film without passing through the cap layer after the formation of the amorphous silicon film, and oxygen and carbon are introduced into the amorphous silicon film through the cap layer formed after the nickel implantation process. Injected.

Here, as shown in FIG. 6, nine types of samples were produced with a combination of three stages of carbon dose, three stages of oxygen dose, and three stages of nickel dose. FIG. 7 shows the nickel concentration obtained in the amorphous silicon film with respect to the dose of nickel shown in FIG. This nickel concentration is the average number of nickel atoms present per unit volume of 1 cm ³ . After the preparation of the above-described samples, laser annealing was performed on the amorphous silicon film of each sample. In this laser annealing process, the KrF excimer pulse laser beam was irradiated to the amorphous silicon film via the phase shifter in the same manner as described above, and the amorphous silicon film was melted and recrystallized to be changed to a polysilicon film.

  Furthermore, after the polysilicon film is obtained as a result of melting and recrystallization by laser annealing, minute defects in the crystal structure of the polysilicon film are detected by X-ray diffraction analysis similar to the above. It was examined by imaging an X-ray diffraction image of the polysilicon film and analyzing the peak shift of the diffraction image.

  FIG. 8 shows the dependence of stacking fault density on carbon and oxygen concentrations using the nickel concentration shown in FIG. 7 as a parameter. The lower limit of measurement indicated by the dotted line in FIG. 8 is determined in consideration of the reproducibility, that is, the reliability of the measured value in the measurement of the stacking fault density, as in the case of the dotted line of FIG.

As can be seen from FIG. 8, when both the carbon concentration and the oxygen concentration are 1 × 10 ¹⁸ atoms / cm ³ and the nickel concentration is 1 × 10 ¹⁷ atoms / cm ³ , the stacking fault density is slightly lower than the lower limit of measurement. Drops to high values. Further, when both the carbon concentration and the oxygen concentration are 5 × 10 ¹⁷ atoms / cm ³ and the nickel concentration is 1 × 10 ¹⁷ atoms / cm ³ , the stacking fault density decreases to a value lower than the lower limit of measurement. Further, when the nickel concentration is 5 × 10 ¹⁶ atoms / cm ³ or less, the certainty that the stacking fault density decreases to a value lower than the lower limit of measurement increases.

  In the semiconductor device shown in FIG. 2, the support substrate 12 and the non-single-crystal semiconductor film 14 form a main semiconductor structure used as a panel substrate component of a liquid crystal display device. In consideration of impurity contamination during storage and transport, it is preferable that the non-single-crystal semiconductor film 14 is actually covered with at least an insulating film such as the gate insulating film 16. Such a semiconductor structure is a semi-finished product of a semiconductor device, and may not include all of the elements of the semiconductor device such as the gate electrode layer 18, the source region 24, and the drain region 26 shown in FIG. In this example, the non-single-crystal semiconductor film 14 includes a source region 24 and a drain region 26 on both sides of the channel region 22, and a contact hole or the like exposing the non-single-crystal semiconductor film 14 is formed in the gate insulating film 16 by etching. The unfinished semi-finished product was used as a panel substrate part of the liquid crystal display device.

  FIG. 9 schematically shows a manufacturing apparatus used for manufacturing the semiconductor device shown in FIG. In this manufacturing apparatus, a plasma-enhanced chemical vapor deposition (PECVD) apparatus 40 as shown in FIGS. 9 and 10 is used. The PECVD apparatus 40 includes a reaction chamber 42 which is an airtight semiconductor film formation chamber for accommodating the support substrate 12 on which a film is formed by the PECVD 40, a plasma generation source 44 for generating plasma used in PECVD, and a reaction chamber 42. A source gas supply system 46 for supplying a source gas for plasma generation and an exhaust processing system 48 for performing an exhaust process in the reaction chamber 42 are provided.

  The PECVD apparatus 40 is connected to a substrate transport system 50 for loading the support substrate 12 into the reaction chamber 42 at a predetermined degree of vacuum and unloading the substrate 12 from the reaction chamber 42.

  Further, a mass spectrometer 51 for specifying a gas in the reaction chamber 42 is connected to the reaction chamber 42. As the mass spectrometer 51, for example, a quadrupole mass spectroscope (QMS) is used.

  The source gas supply system 46 includes, for example, a source gas cylinder device 56 having a silane (SiH4) gas cylinder 52 and a hydrogen (H2) gas cylinder 54, and a mass flow controller 58. The raw material gas supply system 46 adjusts each flow rate of the silane gas and the hydrogen gas by the mass flow controller 58, and introduces the silane gas and the hydrogen gas whose flow rates have been adjusted into the reaction chamber 42 through the gas introduction pipe 82.

  The exhaust processing system 48 includes, for example, a turbo molecular pump (TMP) 60 and a dry pump 62. The dry pump 62 is connected to the turbo molecular pump 60 and the reaction chamber 42. The exhaust processing system 48 shown in FIG. 9 further includes an auto pressure controller (APC: Auto Pressure Controller) 64 disposed between the reaction chamber 42 and the turbo molecular pump 60, and an environment connected to the exhaust side of the dry pump 62. A gas cleaner 66 for purifying exhaust gas to prevent contamination.

  The substrate transfer system 50 includes a load chamber 68 for transferring a substrate and a robot chamber 70 for automatic sorting. The load chamber 68 has both functions of selecting a desired support substrate 12 from a substrate storage device (not shown) and transferring it to the robot chamber 70, and transferring the desired support substrate 12 from the robot chamber 70 to the substrate storage device. Having. The robot chamber 70 sorts the support substrate 12 transferred from the load chamber 68 into a predetermined substrate processing device. In FIG. 10, only the PECVD apparatus 40 is shown in a sectional view as a substrate processing apparatus.

  Here, it is necessary that the gas in the robot chamber 70 does not flow into the reaction chamber 42 when the door 72 between the reaction chamber 42 and the robot chamber 70 is opened. Therefore, the inside of the robot chamber 70 is maintained at a lower pressure than the inside of the reaction chamber 42 by an exhaust device (not shown) so that the degree of vacuum in the robot chamber 70 becomes higher than the degree of vacuum in the reaction chamber 42.

  As shown in FIG. 10, a heater 80 is wound, for example, in a coil shape around the outer periphery of the reaction chamber 42 in order to bake the inner wall 94 of the chamber. The heater 80 is used to increase the temperature inside the reaction chamber 42. The gas introduction pipe 82 is connected to the mass flow controller 58. The gas exhaust pipe 84 is connected to the turbo molecular pump 60 via the auto pressure controller 64. The gas exhaust pipe between the turbo-molecular pump 60 and the dry pump 62 is shown in FIG. 9 and is omitted in FIG.

  As shown in FIG. 10, the plasma generation source 44 includes a high frequency generator 86, and an upper electrode 88 and a lower electrode 90 that are electrically connected to the high frequency generator 86. The lower electrode 90 and the hermetic reaction chamber 42 are grounded. The upper electrode 88 has a mesh 92 having a plurality of openings, and is airtightly connected to a widened portion of the gas introduction pipe 82. The upper electrode 88 introduces the source gas G introduced through the gas introduction pipe 82 into the reaction chamber 42 through the mesh 92. The lower electrode 90 supports the support substrate 12 on which a film forming process is performed. In order to adjust the distance between the electrodes and the upper electrode 88, the lower electrode 90 is vertically movable in the figure by a drive mechanism (not shown).

  Next, a method for manufacturing the semiconductor device shown in FIG. 2 will be described with reference to FIGS. In manufacturing a semiconductor device, a degassing process is performed to remove gas mixed in the chamber inner wall 94 of the reaction chamber 42. In the degassing process, the baking process of the chamber inner wall 94 and the exhaust process of the reaction chamber 42 are performed in parallel. The baking process is performed by heating the inner wall 94 of the chamber with the heater 80. In this baking process, the chamber inner wall 94 is heated until it reaches a constant temperature of, for example, about 120 ° C., and is further heated to maintain this temperature for a certain time of about several hours. The exhaust process is performed by continuously exhausting the gas generated from the chamber inner wall 94 in the baking process from the reaction chamber 42 by the exhaust process system 48.

  Next, cleaning of the chamber inner wall 94 is performed by supplying a fluorine-based gas such as a fluorine trinitride gas from a cylinder (not shown) to the reaction chamber 42 and etching the surface of the chamber inner wall 94 with the fluorine-based gas (inner wall). Cleaning process). Next, for example, an amorphous semiconductor film 95 having a thickness of 50 nm to 1000 nm is formed so as to cover the surface of the chamber inner wall 94 (inner wall coating process). This semiconductor film 95 is made of the same material as the semiconductor film 14 of the semiconductor device, and prevents fluorine mixed into the chamber inner wall 94 during the etching surface treatment from being released from the chamber inner wall 94 into the space of the reaction chamber 42.

The support substrate 12 is installed in the reaction chamber 42 after the above-described inner wall cleaning processing and inner wall coating processing. When the base insulating layer 20 is used, the base insulating layer 20 is formed on the supporting substrate 12 in advance by a plasma enhanced chemical vapor deposition (PECVD) method. When the base insulating layer 20 is, for example, a SiO ₂ layer, this SiO ₂ layer is a gas cylinder device including a silane (SiH ₄ ) gas cylinder, a nitrogen oxide (N ₂ O) gas cylinder, and a nitrogen (N ₂ ) gas cylinder, and tetraethyl ortho. It is formed by using a gas cylinder device provided with a silicate (ie, TEOS: Tetra Ethyl Ortho Silicate) gas cylinder and an oxygen (O ₂ ) gas cylinder.

  The support substrate 12 is placed in the reaction chamber 42 after forming the base insulating layer 20 in this manner.

  For a CVD apparatus for mass production, the inner wall cleaning process needs to be performed in a vacuum in consideration of the use environment and use frequency. Further, since the film thickness of the semiconductor film 95 is cumulatively increased by repeating the inner wall coating process, the inner wall cleaning process using a halogen-based gas or a fluoride gas is performed every time the accumulated film thickness of the semiconductor film 95 becomes, for example, 10 μm, or 1 hour. It is preferable to carry out at a cycle such as for each lot.

  When the supporting substrate 12 is set in the reaction chamber 42 which has been subjected to the inner wall cleaning processing and the inner wall coating processing as described above, for example, the amorphous silicon film 14a shown in FIG. The semiconductor film is formed by a plasma enhanced chemical vapor deposition (PECVD) method.

Here, the film forming conditions when the amorphous silicon film 14a is formed by the PECVD method in the reaction chamber 42 shown in FIG. 9 will be described. The mixing ratio (SiH ₄ / H ₂ ) of the silane gas and the hydrogen gas supplied into the reaction chamber 42 is set to 1: 4 by the flow ratio. The total gas pressure in the reaction chamber 42 is adjusted by the APC 64 to be 150 Pa (1.1 Torr). Thus, the degree of vacuum in the reaction chamber 42 is maintained at a predetermined level. The deposition rate is determined by the plasma power and the flow rate of the silane gas. The temperature of the support substrate 12 is maintained at a constant temperature, for example, 280 ° C. by a heating device (not shown). The distance between the upper electrode 88 and the lower electrode 90 or the distance between the upper electrode 88 and the support substrate 12 is set to 15 mm during the film forming process. Under such conditions, the amorphous silicon film 14a is formed.

  Next, as shown in FIG. 11, an insulating layer having a thickness of 300 nm and made of silicon oxide is formed as a cap layer 130 on the amorphous silicon film 14a. Thereafter, dehydrogenation of the amorphous silicon film 14a is performed.

Next, laser annealing of the amorphous silicon film 14a is performed using a laser beam irradiation apparatus shown in FIG. The laser light irradiation device irradiates at least a part of the amorphous silicon film 14a with the KrF excimer laser light L generated by the laser device 132 via the optical system 134. As the irradiation conditions of the KrF excimer laser light L, the number of irradiations is set to one, and the irradiation fluence is set to an average of 560 mJ / cm ² in the irradiation surface. The KrF excimer laser light L is applied to the amorphous silicon film 14a via the phase shifter 136 and the cap layer 130, and melts and recrystallizes the amorphous silicon film 14a to change it to a polysilicon film. Here, the cap layer 130 prevents the heat generated in the amorphous silicon film 14a due to the irradiation of the excimer laser light L from being dissipated outside the silicon layer 14a. As a result, the excimer laser light L is efficiently converted into thermal energy in the crystallization of the amorphous silicon film 14a.

  The above-described phase shifter 136 is made of, for example, a transparent medium such as a quartz base material, and has two regions having different thicknesses so as to obtain a phase difference of, for example, 180 degrees. In general, a step required to obtain a phase difference of 180 degrees, that is, a film thickness difference t between two regions is represented by Expression (1).

  Here, λ is the wavelength of the laser light, and n is the refractive index of the transparent medium for the laser light. When a quartz substrate is used as the transparent medium, the wavelength difference of the KrF excimer laser beam is 248 nm, and the refractive index of the quartz substrate with respect to the KrF excimer laser is 1.508. It is necessary to obtain a phase difference of degrees.

For example, when the first region is made thinner than the second region, the phase shifter 136 can be obtained by selectively performing gas phase or liquid phase etching of the transparent medium in a range corresponding to the first region. Further, the phase shifter 136 is formed by forming a light transmitting film such as SiO ₂ on a transparent medium by plasma CVD, low pressure CVD, or the like, and patterning the light transmitting film so as to remain in a range corresponding to the second region. You can also get.

  In such a phase shifter 136, the transmitted light in the second region is delayed from the transmitted light in the first region. The excimer laser light L is spatially modulated by diffracting and interfering with a step obtained at a boundary X between the first and second regions. As a result, the light intensity distribution shown in FIG. 13 is obtained on the amorphous silicon film 14a. The light intensity is lowest at a position along the boundary X. The amorphous silicon film 14a is set to a temperature gradient corresponding to this intensity distribution, and is melted and recrystallized. Nuclei of silicon grains are generated at the lowest temperature portions and grow laterally toward higher temperature portions. Here, the nucleus generation position is limited to the vicinity of the position of the amorphous silicon film which has the lowest light intensity opposite to the boundary X in order to grow the crystal grains to a large grain size.

  After the above-described laser annealing, the cap layer 130 is removed by, for example, a wet etching method using buffered hydrofluoric acid. The polysilicon film obtained by melting and recrystallizing the amorphous silicon film 14a is patterned so as to leave a plurality of island-shaped portions respectively assigned to the plurality of active elements 10. The non-single-crystal semiconductor film 14 shown in FIG. 2 is a polysilicon film left as an island portion, and a part of the non-single-crystal semiconductor film 14 forms the active element 10, that is, the channel region 22 of the thin film transistor.

Thereafter, for example, an SiO ₂ layer is formed as a gate insulating film 16 covering the non-single-crystal semiconductor film 14 by a plasma enhanced chemical vapor deposition method. Subsequently, the gate electrode layer 18 is formed on the gate insulating film 16 so as to face a part of the non-single-crystal semiconductor film 14 to be the channel region 22. The gate electrode layer 18 is used as a mask for implanting n-type or p-type impurities into the non-single-crystal semiconductor film 14. N-type or p-type impurities are implanted on both sides of the gate electrode layer 18 via the gate insulating film 16 to form a source region 24 and a drain region 26 in a part of the semiconductor film 14. As a result, the channel region 22 is arranged below the gate electrode layer 18 and between the source region 24 and the drain region 26. A semi-finished product of the semiconductor device is obtained at this stage.

  When the active element 10 is completed in the semi-finished product of the semiconductor device, an interlayer insulating film is formed in the same manner as the interlayer insulating film 111 shown in FIG. 1F, and then the activation of impurities in the source region 24 and the drain region 26 is performed. The conversion is performed by a heat treatment. Thereafter, a pair of contact holes are formed in the gate insulating film 16 and the interlayer insulating film in the same manner as the contact holes shown in FIG. 1F, and the source region 24 and the drain region 26 are partially exposed. Next, a source electrode layer and a drain electrode layer are formed in the same manner as the source electrode layer 112 and the drain electrode layer 113 shown in FIG. 1F, and electrically contact the source region 24 and the drain region 26 in these contact holes. Further, a metal wiring layer for transmitting an electric signal is formed in the same manner as the metal wiring layer 114 shown in FIG. Thereby, the active element 10 is completed as a thin film transistor. In this thin film transistor, a current flows through the channel region 22 between the source region 24 and the drain region 26 according to the gate voltage applied to the gate electrode layer 18.

  In the above-described degassing process, the baking process is performed on the chamber inner wall 94 at a temperature of 120 ° C. However, if the temperature is in the range of 80 ° C. to 150 ° C., the impurity element contained in the chamber inner wall 94 is separated or separated. Further, the impurity element is exhausted from the reaction chamber 42 by the exhaust processing system 48. Therefore, the formation of the amorphous silicon film 14a including the impurity element from the chamber inner wall 94 is prevented. Therefore, good crystallinity can be obtained when the amorphous silicon film 14a is melted and recrystallized.

  Hereinafter, the residual gas in the reaction chamber 42 will be described.

FIG. 14 shows a mass spectrum for specifying the residual gas in the reaction chamber 42. This mass spectrum is the result of mass analysis of the residual gas in the reaction chamber by the mass spectrometer 51 shown in FIG. As the mass spectrometer 51, a quadrupole mass spectrometer (QMS) is used. In FIG. 14, the ion current [A] obtained as the residual amount of the impurity gas from the mass spectrometer 51 is shown with respect to the ratio M / Z between the mass corresponding to the gas mass unit and the charge number. M / Z = 1 corresponds to H (hydrogen). M / Z = 2 corresponds to _{H 2.} M / Z = 17 corresponds to OH. M / Z = 18 corresponds to H ₂ O. M / Z = 28 and the front and rear thereof correspond to _{N 2} or CO.

FIG. 15 shows the result of measuring the ion current [A] of the main residual gas in the reaction chamber 42 with respect to the degassing rate [Torr 1 / s]. Referring to FIG. 14, M / Z = 17, M / Z = 18 and M / Z = 28 are the main residual gases. In FIG. 15, the black triangles indicate the measurement results for M / Z = 18, the white circles indicate the measurement results for M / Z = 17, and the black diamonds indicate the measurement results for M / Z = 28. As can be seen with reference to the straight line having a 45-degree slope added to FIG. 15, the magnitude of the ion current decreases linearly with an increase in the degassing rate in the reaction chamber 42. In H ₂ O (mass unit 17 or 18), oxygen is considered as an impurity element serving as a contaminant. In N ₂ (mass unit 28), nitrogen is considered to be an impurity element serving as a contaminant. In the case of CO or other hydrocarbons (mass unit 28, 12 to 16), carbon is considered as an impurity element serving as a pollutant. Therefore, it can be seen that the partial pressure of these impurity elements in the formation of the silicon film 14a is proportional to the degassing rate from the reaction chamber 42.

FIG. 16 shows the profile of the oxygen concentration in the depth direction measured on a sample obtained by depositing the silicon film used as the semiconductor film 14 shown in FIG. 2 on the substrate Sb at four different deposition rates. On the upper surface of the substrate Sb, a SiO ₂ layer is provided as a base insulating layer. In FIG. 16, S1 represents a silicon film formed at a film formation rate of 3.0 nm / s, S2 represents a silicon film formed at a film formation rate of 2.3 nm / s, and S3 represents a silicon film formed at a film formation rate of 2.3 nm / s. S4 represents a silicon film formed at a film formation rate of 5 nm / s, and S4 represents a silicon film formed at a film formation rate of 0.8 nm / s. The silicon films S1, S2, S3 and S4 were deposited on the substrate Sb in this order. These deposition rates were changed by adjusting the plasma power. The oxygen concentration was measured while sputter etching the silicon films S1, S2, S3, and S4. Referring to FIG. 16, it can be seen that the oxygen concentration decreases as the deposition rate increases. That is, the oxygen concentration decreases in the order of the silicon films S4, S3, S2, and S1, and has the smallest value of about 1.4 × 10 ¹⁷ atoms / cm ^{3 in} the silicon film S1. The oxygen concentration profile has a high peak near the boundary between the substrate Sb and the silicon film S1, and this peak is caused by oxygen in the SiO ₂ layer of the substrate Sb.

FIG. 17 shows that the relationship between the concentration of silane gas introduced as a source gas into the reaction chamber 42 and the oxygen concentration in the silicon film depends on the leak rate of the source gas. The source gas concentration is represented by the ratio of 1 / SiH ₄ to 1 / FSiH 4 [SCCM ⁻¹ ] of the silane gas. FSiH4 is a flow rate value of the silane gas. The straight line L3 is a relationship obtained when the degassing process and the inner wall cleaning process are performed (leak rate = 6.7 × 10 ⁻⁴ ), and the straight line L4 is not performed for the degassing process and the inner wall cleaning process (the leak speed is not changed). = 3.3 × 10 ⁻³ ). As can be seen from FIG. 17, the slope of the straight line L3 is one fifth of the slope of the straight line L4. That is, when the leak rate was reduced to 1/5, the inclination was reduced to 1/5. The oxygen concentration is lower when the degassing process and the inner wall cleaning process are performed than when these processes are not performed. It is characteristic that the intercept values of the two straight lines L3 and L4 are extremely close.

  The oxygen concentration shown in FIG. 17 will be described in detail using the following equation (2).

  Here, Coxygen is the oxygen concentration in the silicon film, Cgas is the oxygen concentration in the source gas (for example, silane gas), Foutgas is the flow rate of contaminants as a gas generated by degassing, FSiH4 is the flow rate of silane gas, NSi represents the number (density) of silicon atoms per unit volume in the silicon film. Cgas is a constant value for the source gas (for example, silane gas). (Foutgas / FSiH4) × NSi≡Coutgas in the equation (2) indicates the concentration of oxygen generated by degassing, and is proportional to 1 / FSiH4.

  FIG. 18 shows that the proportional relationship between the reciprocal of the flow rate of silane gas introduced as a source gas into the reaction chamber 42 and the oxygen concentration in the silicon film is defined by a characteristic line having a slope proportional to the flow rate of contaminant gas generated by degassing. It indicates that. In FIG. 18, a straight line L5 represents a proportional relationship between the reciprocal of the flow rate FSiH4 of the silane gas and the oxygen concentration Coxygen in the silicon film. The slope of the straight line L5 is proportional to the flow rate Foutgas of the contaminant gas, and satisfies Expression (2).

FIG. 19 is an enlarged view of the range indicated by the circle shown in FIG. The oxygen concentration Cgas in the source gas (e.g., silane gas) substantially falls within a range of 4 × 10 ¹⁶ atoms / cm ^{3 to} 5 × 10 ¹⁶ atoms / cm ³ (corresponding to approximately 1 ppm). The difference between the oxygen concentration Cgas in the source gas (for example, silane gas) and the oxygen concentration Cbomb caused by the source gas cylinder corresponds to impurities from the source gas supply system. The oxygen concentration Cbomb due to the source gas cylinder is less than 0.5 ppm.

In the above semiconductor device, the number of oxygen atoms and carbon atoms in the channel region 22 is 1 × 10 ¹⁸ or less per 1 cm ³ , or the number of oxygen atoms, carbon atoms, and metal atoms in the channel region is Are 1 × 10 ¹⁸ or less, 1 × 10 ¹⁸ or less, and 1 × 10 ¹⁷ or less per 1 cm ³ . These numbers are numerical values when the manufacture of the semiconductor device is completed. Therefore, when manufacturing a semiconductor device, for example, an amorphous or polycrystalline non-single-crystal semiconductor film in which the number of oxygen and carbon atoms exceeds the above-described values is formed in advance, and in a subsequent manufacturing process, for example, at a low temperature. Excess atoms may be removed by performing a gettering process or the like, whereby the numbers of oxygen and carbon atoms may be adjusted to the above-mentioned numerical values or less.

  The manufacturing apparatus shown in FIG. 9 is, for example, a single wafer type plasma CVD apparatus with a load lock. The chamber inner wall 94 does not include a SUS-based metal material containing iron, nickel, cobalt, or the like that is separated into the space in the reaction chamber 42 and mixed into the semiconductor film. Instead, the inner wall 94 is composed of a material comprising an aluminum-containing metal. As a result, aluminum, which is the metal component of the inner wall 94, combines with fluorine during cleaning with a fluorine-based gas to form a fluorine compound. When aluminum and fluorine are contained in the inner wall 94 as a fluorine compound as described above, aluminum and fluorine separate from the chamber inner wall 94 into the space in the reaction chamber 42 and are mixed as contaminants into the semiconductor film being formed. Is prevented.

  The material of the inner wall 94 is preferably an aluminum-magnesium-based metal material (A5000-series metal material according to Japanese Industrial Standards material number, for example, A5052-based material). Further, an aluminum-magnesium-silicon-based metal material (A6000-series metal material) or an aluminum copper-based material (A2000-series metal material, for example, A2219-based material) is more preferable as the material of the inner wall 94.

  The surface of the inner wall 94 of the reaction chamber 42 preferably has a roughness of 6.4 micrometers or less. Accordingly, the inner wall 94 has a smooth surface such that adhesion of the impurity element is suppressed, and the clean state of the inner wall 94 can be maintained for a long period of time.

  Further, for example, a magnesium aluminum fluoride layer formed by combining with fluorine is provided on the surface of the inner wall 94, and the surface of the inner wall 94 is covered with an amorphous semiconductor film having a thickness of 50 nm to 1000 nm, Fluorine atoms contained in the inner wall 94 are prevented from leaving the space in the reaction chamber 42 and entering the semiconductor film being formed as contaminants.

  The reaction chamber 42 is shut off from the outside via an O-ring made of fluorine rubber having heat resistance. This can reduce damage to the O-ring due to heat during baking of the inner wall 94. Instead of the O-ring, for example, two O-rings made of a heat-resistant fluorine-based rubber and having different diameters may be overlapped, and the reaction chamber 42 may be shut off from the outside via the two O-rings. Thereby, the reaction chamber 42 is more reliably shut off from the outside. Further, damage to each O-ring can be further reduced. Further, the reaction chamber 42 may be configured to include an exhaust device that removes contaminant gas from the gap between these double O-rings.

  In the semiconductor device shown in FIG. 2, the supporting substrate 12 serves as a base for the base insulating layer 20, the base insulating layer 20 serves as a base for the non-single-crystal semiconductor film 14, and the non-single-crystal semiconductor film 14 serves as a base for the gate insulating film 16. And a stacked structure in which the gate insulating film 16 becomes a base of the gate electrode layer 18. This laminated structure may be modified, for example, as shown in FIG.

  FIG. 20 shows a first modification of the semiconductor device shown in FIG. In this modification, the supporting substrate 12 serves as a base for the base insulating layer 20, the base insulating layer 20 serves as a base for the gate electrode layer 18, the gate electrode layer 18 serves as a base for the gate insulating film 16, and the gate insulating film 16 serves as a semiconductor film. It has a layered structure that serves as a base for fourteen.

  In the manufacture of the semiconductor device of the first modified example, after the formation of the base insulating layer 20, the gate electrode layer 18 is formed, and the gate insulating film 16 is formed so as to cover the gate electrode layer 18. The gate insulating film 16 is formed so as to extend also on the base insulating layer 20.

  Next, for example, an amorphous silicon film is deposited as an amorphous semiconductor film on the gate insulating film 16 by a plasma chemical vapor deposition method. The amorphous silicon film is formed using a PECVD apparatus 40 shown in FIG. The inner wall 94 of the reaction chamber 42 is degassed before the formation of the amorphous silicon film, is cleaned by performing an etching surface treatment with a fluorine-based gas, and is further covered with the amorphous semiconductor film 95. An amorphous silicon film is formed in such a reaction chamber 42. Next, a cap layer is formed on the amorphous silicon film, and dehydrogenation of the amorphous silicon layer is performed. Next, laser annealing of the amorphous silicon film is performed. In this laser annealing process, for example, KrF excimer laser light is applied to the amorphous silicon film via the phase shifter under the above-described irradiation conditions. As a result, the amorphous silicon film is melted and recrystallized to change to a polysilicon film. The non-single-crystal silicon film 14 shown in FIG. 20 is a polysilicon film formed in this manner. Thereafter, the above-described cap layer is removed by, for example, a wet etching method using buffered hydrofluoric acid.

  Next, a resist layer is formed on the channel region 22 in a pattern substantially equal to the pattern size of the gate electrode layer 18, and n-type or p-type impurities are injected into the semiconductor film 14 using the resist layer as a mask. As a result, the source region 24 and the drain region 26 are formed on the semiconductor film 14 on both sides of the channel region 22. In this case, the dimensions of the source region 24 and the drain region 26 can be adjusted by the pattern dimensions of the resist layer. The semi-finished product of the semiconductor device shown in FIG. 20 is obtained at this stage.

  Thereafter, the same processing as in the semiconductor device shown in FIG. 2 is performed. That is, an interlayer insulating film is formed to cover semiconductor layer 14, and then impurities in source region 24 and drain region 26 are activated by heat treatment. Thereafter, a pair of contact holes is formed in the gate insulating film 16 and the interlayer insulating film to partially expose the source region 24 and the drain region 26. Next, a source electrode layer and a drain electrode layer are formed so as to make electrical contact with the source region 24 and the drain region 26 in these contact holes. Further, a metal wiring layer for transmitting an electric signal is formed. Thereby, the active element 10 is completed as a thin film transistor.

  FIG. 21 shows a second modification of the semiconductor device shown in FIG. Although the semiconductor device shown in FIG. 2 has a structure in which the gate insulating film 16 covers the non-single-crystal semiconductor film 14, the structure is changed to a structure in which the gate insulating film 16 covers only the channel region 22 of the semiconductor film 14 as shown in FIG. You may. In this case, gate electrode layer 18 is formed on gate insulating film 16, and interlayer insulating film 28 is formed to cover gate electrode layer 18, source region 24 and drain region 26. The source electrode layer 30 and the drain electrode layer 32 are formed so as to be in contact with the source region 24 and the drain region 26 at a pair of contact holes formed in the interlayer insulating film 28, and a metal wiring layer 34 is formed on the drain electrode 32. It is formed to be connected. Thereby, the active element 10 is completed as a thin film transistor.

  In the semiconductor device illustrated in FIG. 2, the cap layer 130 is entirely removed. However, the cap layer 130 may be etched to have the same thickness as the gate insulating film 16 and used as the gate insulating film 16.

  In the manufacture of the semiconductor device shown in FIG. 2, laser annealing is performed to melt and recrystallize the amorphous silicon film 14a, which is a non-single-crystal semiconductor film. In this laser annealing process, the amorphous silicon film 14a is irradiated with KrF excimer laser light via the phase shifter 136. The excimer pulsed laser light may be directly applied to the amorphous silicon film 14a one or more times without passing through the phase shifter 136. The method without the phase shifter 136 cannot grow crystal grains as large as the method using the phase shifter 136. However, since the irradiation fluence of light irradiation is relatively small as compared with the method using the phase shifter 136, the cap layer 130 cannot be formed. No need to form.

  Further, the melting and recrystallization of a non-single-crystal semiconductor film such as the amorphous silicon film 14a may be performed by a lamp annealing process using energy light other than laser light. Further, the melting and recrystallization of the non-single-crystal semiconductor film may be performed by, for example, a solid-phase growth method in a nitrogen atmosphere, instead of the method of irradiating energy light. In any case, the non-single-crystal semiconductor film is preferably melted and crystallized at a heating position for a heating time of 10 seconds or less. This heating time is more preferably 1 second or less. Thus, contamination of the semiconductor film generated in a molten state can be suppressed.

As described above, in the present embodiment, the channel region 22 has an oxygen concentration and a carbon concentration that do not exceed 1 × 10 ¹⁸ atoms / cm ³ . When at least the channel region 22 of the non-single-crystal semiconductor film 14 has such an oxygen concentration and a carbon concentration, minute defects generated in the crystal structure of the channel region 22 due to these elements can be reduced to 1 × 10 An extremely small value of about ⁶ / cm ³ can be obtained. Thus, carriers in the channel region 22 can move at high speed without being significantly hindered by these minute defects. Therefore, the thin film transistor can obtain favorable electric characteristics for performing high-speed switching operation.

Also, if having a carbon concentration not exceeding oxygen concentration and 5 × 10 ¹⁷ atoms / cm ³ at least the channel region 22 does not exceed 5 × 10 ¹⁷ atoms / cm ³ of the non-single-crystal semiconductor film 14, the channel region 22 Quality is improved.

Further, when the non-single-crystal semiconductor film 14 has a concentration of a metal element not exceeding 1 × 10 ¹⁷ atoms / cm ³ , generation of a metal oxide which causes a decrease in the resistivity of the semiconductor film 14 is suppressed. When the number of metal atoms is 5 × 10 ¹⁶ or less per 1 cm ³ , generation of metal oxide is further suppressed, and the resistivity can be set to a value that does not hinder practical use.

  In the non-single-crystal semiconductor film 14, the source region 24, the channel region 22, and the drain region 26 are arranged along the crystal grain growth direction, and the channel region 22 has a size larger than the length of the channel region 22 in this growth direction. It is located within a single grain having a diameter. In this case, the crystal boundary does not exist in the channel region 22, and it is possible to eliminate the inhibition of carrier movement caused by the crystal boundary in the channel region 22.

  In the manufacture of a semiconductor device, when the inner wall 94 of the reaction chamber 42, which is a film formation chamber for accommodating the support substrate 12, is made of an aluminum-containing metal such as an aluminum magnesium-based material, an aluminum magnesium silicon-based material, or an aluminum copper-based material. In addition, it is possible to prevent the metal element of the inner wall 94 from entering the space of the reaction chamber 42 during the film formation and entering the non-single-crystal semiconductor film 14. When the surface of the inner wall 94 has a roughness of 6.4 micrometers or less, it is possible to suppress the impurity element from adhering to the smooth surface of the inner wall 94, and to keep the inner wall 94 clean for a long period of time.

  Further, the inner wall 94 of the reaction chamber 42 is subjected to etching surface treatment with a fluorine-based gas, and is covered with an amorphous semiconductor film 95 having a thickness of 50 nm to 1000 nm. As a result, contaminant elements are removed from the surface of the chamber inner wall 94 by the etching surface treatment, and fluorine mixed in the etching surface treatment cannot be separated from the chamber inner wall 94 into the space of the reaction chamber 42 by the amorphous semiconductor film 95. Thus, contaminants mixed into the non-single-crystal semiconductor film 14 during film formation can be reduced.

  Further, when the reaction chamber 42 is shut off from the outside via an O-ring made of a heat-resistant fluorine-based rubber, damage to the O-ring can be reduced by heat generated during the baking process of the inner wall 94. In place of the O-ring, two O-rings made of heat-resistant fluorine-based rubber having different diameters, for example, are superposed and the reaction chamber 42 is shut off from the outside via the two O-rings. 42 can be more reliably shut off from the outside, and damage to each O-ring can be reduced. Further, if the reaction chamber 42 includes an exhaust device that removes gas that becomes a contaminant from the gap between the double O-rings, the influence of the contaminant can be eliminated.

4A to 4F are cross-sectional views illustrating a manufacturing process of a conventional polysilicon thin film transistor. FIG. 1 is a view showing a cross-sectional structure of a semiconductor device according to one embodiment of the present invention. 3 is a table showing doses of carbon and oxygen injected into an amorphous silicon film of a sample in order to verify a correlation between carbon and oxygen in the semiconductor film shown in FIG. 2 and stacking fault density. 4 is a table showing the concentrations of carbon and oxygen obtained in an amorphous silicon film with respect to the dose shown in FIG. 3. 5 is a graph showing the dependency of stacking fault density on oxygen concentration using the carbon concentration shown in FIG. 4 as a parameter. FIG. 4 shows doses of carbon, oxygen, and nickel (metal element) injected into a plurality of samples to verify a correlation between carbon, oxygen, and metal elements in the semiconductor film illustrated in FIG. 2 and stacking fault density. table. 7 is a table showing the nickel concentration obtained with respect to the dose of nickel shown in FIG. 6. 8 is a graph showing the dependence of stacking fault density on carbon and oxygen concentrations using the nickel concentration shown in FIG. 7 as a parameter. FIG. 3 schematically shows a manufacturing apparatus used for manufacturing the semiconductor device shown in FIG. 2. FIG. 10 is a diagram schematically showing a reaction chamber and a plasma generation source shown in FIG. 9. FIG. 3 is a view showing a cap layer formed in the manufacture of the semiconductor device shown in FIG. 2. FIG. 12 is a diagram schematically showing a laser beam irradiation apparatus used for melting and recrystallization of the amorphous silicon film shown in FIG. 11. FIG. 13 is a diagram showing the relationship between the structure of the phase shifter shown in FIG. 12 and the intensity distribution of laser light transmitted through the phase shifter. FIG. 11 is a graph showing a mass spectrum for specifying a residual gas in the reaction chamber shown in FIG. 10. 11 is a graph showing the result of measuring the ion current of the main residual gas in the reaction chamber shown in FIG. 10 with respect to the degassing rate. 3 is a graph showing a profile of oxygen concentration in a depth direction measured on a sample in which a silicon film used as the semiconductor film shown in FIG. 2 is deposited on a supporting substrate at four different deposition rates. 11 is a graph showing that the relationship between the concentration of silane gas introduced as a source gas into the reaction chamber shown in FIG. 10 and the oxygen concentration in the silicon film depends on the leak rate of the source gas. The proportional relationship between the reciprocal of the flow rate of silane gas introduced as a source gas into the reaction chamber shown in FIG. 10 and the oxygen concentration in the silicon film is defined by a characteristic line having a slope proportional to the flow rate of contaminant gas generated by degassing. A graph indicating that. The graph which expands and shows the range of the mark shown in FIG. FIG. 3 is a diagram showing a cross-sectional structure of a first modification of the semiconductor device shown in FIG. 2. FIG. 6 is a view showing a cross-sectional structure of a second modification of the semiconductor device shown in FIG. 2.

Explanation of reference numerals

  DESCRIPTION OF SYMBOLS 10 ... Active element, 12 ... Support substrate, 14 ... Non-single-crystal semiconductor film, 14a ... Amorphous silicon film, 16 ... Gate insulating film, 18 ... Gate electrode layer, 20 ... Base insulating layer, 22 ... Channel region, 24 ... source region, 26 ... drain region, 30 ... source electrode layer, 32 ... drain electrode layer, 34 ... metal wiring layer, 40 ... plasma vapor deposition apparatus, 42 ... reaction chamber, 44 ... plasma generation source, 46 ... source gas Supply system, 48: Exhaust treatment system, 50: Substrate transfer system, 51: Mass spectrometer, 52: Silane gas cylinder, 54: Hydrogen gas cylinder, 56: Source gas cylinder apparatus, 58: Mass flow controller, 60: Turbo molecular pump, 62 ... Dry pump, 64: Auto pressure controller, 66: Gas cleaner, 68: Load chamber, 70: Robot chamber, 72: Door, 0: heater, 82: gas introduction pipe, 84: gas exhaust pipe, 86: high frequency generator, 88: upper electrode, 90: lower electrode, 92: mesh, 94: chamber inner wall, 95: amorphous semiconductor film, 130 ... Cap layer, 132 laser device, 134 optical system, 136 phase shifter.

Claims (19)

A non-single-crystal semiconductor film including a channel region for an active element; and a support substrate for supporting the non-single-crystal semiconductor film, wherein the channel region has an oxygen concentration and an oxygen concentration not exceeding 1 × 10 ¹⁸ atoms / cm ^3. A semiconductor structure having a carbon concentration. 2. The semiconductor structure according to claim 1, wherein the oxygen concentration and the carbon concentration do not exceed 5 × 10 ¹⁷ atoms / cm ³ . 2. The semiconductor structure according to claim 1, wherein the channel region contains a metal element at a concentration not exceeding 1 × 10 ¹⁷ atoms / cm ³ . 4. The semiconductor structure according to claim 3, wherein the concentration of the metal element does not exceed 5 × 10 ¹⁶ atoms / cm ³ .   A method for manufacturing a semiconductor structure, comprising: a non-single-crystal semiconductor film including a channel region for an active element; and a support substrate that supports the non-single-crystal semiconductor film, wherein an inner wall of a deposition chamber is etched with a fluorine-based gas. Performing a surface treatment, covering the inner wall with an amorphous semiconductor film having a thickness of 50 nm to 1000 nm, accommodating the support substrate in the film formation chamber, and forming the non-single-crystal semiconductor film, A method for producing a semiconductor structure, comprising: melting and recrystallizing a semiconductor by heating.   The method according to claim 5, wherein the inner wall is baked at a temperature of 80C to 150C.   The method for manufacturing a semiconductor structure according to claim 5, wherein energy light is applied to heat the non-single-crystal semiconductor film.   The method according to claim 5, wherein the non-single-crystal semiconductor film is heated at a heating position for a heating time not exceeding 10 seconds.   The method according to claim 7, wherein the heating time does not exceed 1 second.   An apparatus for manufacturing a semiconductor structure including a non-single-crystal semiconductor film including a channel region for an active element and a support substrate that supports the non-single-crystal semiconductor film, wherein the support substrate is housed in a deposition chamber. A film formation unit for forming the non-single-crystal semiconductor film, and a crystallization unit for melting and recrystallizing the non-single-crystal semiconductor film, wherein the film formation chamber has an inner wall made of a metal containing aluminum. Characteristic semiconductor manufacturing equipment.   The apparatus of claim 10, wherein a surface of the inner wall includes a fluorine atom and is covered with an amorphous semiconductor film having a thickness of 50 nm to 1000 nm. A non-single-crystal semiconductor film, a support substrate supporting the non-single-crystal semiconductor film, and an active element having a part of the non-single-crystal semiconductor film as a channel region, wherein each of the channel regions is 1 × 10 ¹⁸ A semiconductor device having an oxygen concentration and a carbon concentration not exceeding atoms / cm ³ .   9. The non-single-crystal semiconductor film, wherein the active element is a thin film transistor including source and drain regions disposed on both sides of the channel region and a gate electrode layer insulated from the channel region by an insulating film. 13. The semiconductor device according to item 12.   14. The semiconductor device according to claim 13, wherein the channel region is arranged in a single crystal grain having a crystal growth direction coinciding with an arrangement direction of the source and drain regions. 13. The semiconductor device according to claim 12, wherein both the oxygen concentration and the carbon concentration do not exceed 5 × 10 ¹⁷ atoms / cm ³ . 13. The semiconductor device according to claim 12, wherein the non-single-crystal semiconductor film contains a metal element at a concentration not exceeding 1 × 10 ¹⁷ atoms / cm ³ . 17. The semiconductor device according to claim 16, wherein the concentration of the metal element does not exceed 5 × 10 ¹⁶ atoms / cm ³ . A non-single-crystal semiconductor film, a support substrate supporting the non-single-crystal semiconductor film, and an active element having a part of the non-single-crystal semiconductor film as a channel region, wherein the channel region is 1 × 10 ¹⁸ atoms / wherein a has a stacking fault density not exceeding the oxygen concentration and 1 × 10 ⁶ cm ^-3 does not exceed cm ^3.   A method of manufacturing a semiconductor device, comprising: a non-single-crystal semiconductor film; a support substrate supporting the non-single-crystal semiconductor film; and an active element having a part of the non-single-crystal semiconductor film as a channel region. The inner wall of the chamber is subjected to etching surface treatment with a fluorine-based gas, the inner wall is covered with an amorphous semiconductor film having a thickness of 50 nm to 1000 nm, and the supporting substrate is accommodated in the film forming chamber and the non-single-crystal semiconductor film is removed. Forming the active element having a part of the non-single-crystal semiconductor film as a channel region by melting and recrystallizing the non-single-crystal semiconductor film.

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