JPH08153711A - Etching device - Google Patents

Abstract

PURPOSE: To etch a semiconductor without causing damage. CONSTITUTION: Etching is done with the use of halogen fluoride gas such as ClF3 . At the time, an etching device provided with substrate carrier chambers 701 and 820, a substrate carry-in chamber 702 and a substrate carry-out chamber 830, is used. The halogen fluoride gas is, instead of being made into plasma, allowed to etch under depressed atmosphere. Relating to etching with the use of halogen fluoride gas, since no plasma damage follows etching, the etching method is optimum for forming an active layer of a thin film transistor.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The invention disclosed in this specification relates to an apparatus for etching a silicon semiconductor. In particular, the present invention relates to an etching apparatus used when forming an active layer of a thin film transistor by etching.

[0002]

2. Description of the Related Art In recent years, attention has been paid to active matrix type liquid crystal display devices. This is to arrange a thin film transistor using a silicon thin film on each of pixel electrodes arranged in a matrix of several hundreds × several hundreds or more, and control charges to be held in each pixel by the thin film transistor.

Since a liquid crystal display device needs to transmit light in principle, it is necessary to use a material that transmits visible light as a substrate. Examples of the material that transmits visible light include a quartz substrate and a glass substrate. Among them, the quartz substrate is expensive and it is not preferable to use it from the viewpoint of economy. Therefore, a glass substrate is generally used. The problem in this case is how to obtain a high-performance thin film transistor on a glass substrate.

In order to enhance the characteristics of the thin film transistor, it is most effective to enhance the crystallinity of the silicon thin film used. However, when a glass substrate is used, it is difficult to obtain a silicon thin film having a single crystal or a crystallinity similar to that of a single crystal due to the heat resistant temperature of glass. What is generally obtained is a silicon thin film having an incomplete crystalline state called polycrystal or microcrystal.

When a thin film transistor is formed by using a silicon thin film having such a structure called polycrystal or microcrystal, the OFF current characteristic is a major technical problem to be overcome. When a thin film transistor is formed by using a silicon thin film having a structure generally called polycrystal or microcrystal, there is a fact that the value of OFF current is large. OF
The F current is a current flowing between the source and the drain when the thin film transistor is off.

For example, consider a structure in which a thin film transistor arranged in a pixel has a source connected to a source line and a drain connected to a pixel electrode. Here, when the thin film transistor is turned on, a predetermined charge flows from the source line to the pixel electrode through the thin film transistor. Then, when the thin film transistor is turned off, a predetermined charge is held in the pixel electrode. Turn off the thin film transistor here
If the current is significantly high, the electric charges will gradually flow out from the pixel electrode. Of course, in this case, since the predetermined charges are not held in the pixel electrode for a predetermined time, the required display cannot be performed.

It is considered that the problem of the OFF current is caused by the movement of carriers via the crystal grain boundaries. For example, in the case of an N-channel type thin film transistor, the channel becomes N by applying a positive potential to the gate electrode.
It becomes a mold and becomes ON operation. Further, by applying a negative potential to the gate electrode, the channel becomes a P-type and the OFF operation is performed.

During this OFF operation, the source / drain is of N type and the channel is of P type, so that an NPN structure is formed between the source and drain, and no current flows theoretically between the source / drain. However, this is an ideal case that holds when the silicon thin film that constitutes the active layer has a single-crystal structure. In reality, the carrier level passes through the trap levels existing at the crystal grain boundaries. Will move.
Then, this carrier movement causes an OFF current.

As described above, the crystalline thin film silicon semiconductor formed on the glass substrate has a state of polycrystal or microcrystallinity, and innumerable crystal grain boundaries exist in the film. There is. And many trap levels exist in these crystal grain boundaries.

The movement of carriers via this trap level becomes remarkable especially in a region to which a high electric field is applied. This phenomenon is particularly remarkable at the interface between the channel region and the drain region and in the vicinity thereof. Therefore, a lightly doped region or an offset region (also referred to as an offset gate region) is formed as an electric field relaxation region between the channel region and the drain region, and carrier movement is suppressed in this region via a trap level. The method is known. These structures are technologies called LDD (light doped drain) structures and offset gate structures.

When a silicon thin film having crystallinity is actually formed on a glass substrate to form a thin film transistor using this silicon thin film, the LDD structure and the offset structure described above are effective to some extent, and the OFF current is lowered to some extent. be able to. However, at present, it is difficult to obtain the required low OFF current characteristics.

[0012]

Generally, the active layer is formed by forming a resist in a predetermined pattern by using a photolithography process and performing dry etching using plasma with the resist as a mask.

As a result of intensive studies on the problem of OFF of the thin film transistor, the present inventors have obtained the following findings.

First, plasma damage occurs on the side surface of the active layer during etching by the dry etching method in forming the active layer. Due to this plasma damage, trap levels are formed at high density on the side surface of the active layer.

This phenomenon is remarkable especially in the crystalline silicon film having a polycrystalline or microcrystalline structure in which trap levels are easily generated at high density, and the trap levels are densely formed on the side surface of the active layer. Will be formed.

If a large number of trap levels on the side surface of the active layer formed due to such plasma damage are present at high density, carrier movement through these trap levels becomes significant. That is, the OFF current increases. This problem becomes particularly noticeable in the case of a film quality such as a polycrystalline silicon film or a microcrystalline silicon film having an infinite number of crystal grain boundaries. This is because the trap levels are likely to be unevenly distributed in the crystal grain boundaries and are easily generated.

The trap level density formed on the side surface of the active layer is extremely higher than that inside the active layer (in the thin film). Therefore, even if the LDD structure or the offset structure is adopted, the number of charges moving via the trap level on the side surface of the active layer cannot be suppressed so much. That is, the value of the OFF current cannot be reduced so much.

The LDD structure and the offset structure alleviate the electric field strength in the region where the electric field is concentrated, and thereby suppress the movement of carriers which causes the OFF current (more precisely, the number of moving carriers is reduced). Reduce). However, if the density of trap levels, which causes carrier movement, is extremely high, the total number of moving carriers cannot be reduced so much even if the electric field strength is weakened.

The problem here is the trap levels concentratedly present on the side surface of the active layer. Therefore, if the trap level density on the side surface of the active layer can be reduced, the problem of the OFF current can be improved. As described above, the trap level concentratedly present on the side surface of the active layer is mainly caused by plasma damage at the time of forming the active layer. Therefore, if the plasma damage at the time of forming the active layer can be reduced, the problem of the OFF current of the thin film transistor can be improved.

As a method of eliminating the plasma damage on the side surface of the active layer, it is necessary to form
A method using a wet etching method can be mentioned. However, the method using the wet etching method is (1) suitable for selectively etching only the silicon film with good controllability and reproducibility, but there is no etchant. (2) The temperature control of the etchant and the etching conditions are delicate. There are various problems.

An object of the present invention disclosed in the present specification is to provide an etching apparatus capable of performing a process in which trap levels are not concentratedly formed on the side surface of an active layer.

[0022]

One of the main inventions disclosed in the present specification is to provide a chamber for performing an etching process using the halogen fluoride gas without ionizing or converting the halogen fluoride gas into plasma. It is characterized by having.

As the halogen fluoride gas, ClF ₃ ,
ClF, BrF ₃ , IF ₃ , BrF, BrF ₅ , IF ₅
One or more kinds of gas selected from the above can be used. The halogen fluoride gas does not have to be used at 100%, and can be used after diluting it with an appropriate diluent gas.

The reason why the etching process is carried out without ionizing or converting the halogen fluoride gas into plasma is to reduce plasma damage during the etching process.

According to another aspect of the invention, there is provided a first chamber in which etching is performed, a second chamber for accommodating a large number of substrates, and a substrate arranged between the first chamber and the second chamber. And a third chamber capable of depressurization having a means for transporting, in the first chamber, an etching treatment using the halogen fluoride gas without ionizing or plasmatizing the halogen fluoride gas. Is performed.

A specific configuration having the above configuration is shown in FIG. FIG. 1 shows an etching chamber 800 that is a first chamber in which etching is performed, and a second chamber that stores a large number of substrates.
A substrate loading chamber 702 which is a chamber of the substrate, a substrate which is arranged between the etching chamber 800 which is the first chamber and the substrate loading chamber 702 which is the second chamber, and which has a robot arm 710 which is a means for transporting the substrate Transport room 70
1 is shown.

According to another aspect of the present invention, there is provided a chamber having a means for introducing a halogen fluoride gas, and the halogen fluoride gas is not ionized or turned into plasma in the chamber. The etching process used is performed, and the chamber is provided with means for measuring the light transmitted through the material to be etched and detecting the etching state.

A specific configuration having the above configuration is shown in FIG. In FIG. 1, a gas introduction system 812 for introducing a halogen fluoride gas is provided, an etching chamber 800 for performing an etching process without ionizing or converting the halogen fluoride gas into plasma, and a light for transmitting a material to be etched. A means 806 for emitting light and a means 804 for detecting the transmitted light are provided.

According to another aspect of the invention, a substrate loading chamber, a first substrate transfer chamber connected to the substrate loading chamber, an etching chamber connected to the first substrate transfer chamber, and an etching chamber are provided. It has a connected second substrate transfer chamber and a substrate unloading chamber connected to the second substrate transfer chamber. The substrate loading chamber and the substrate unloading chamber accommodate a large number of substrates. Has a function,
The first transfer chamber and the second transfer chamber have means for transferring a substrate, and have a function of performing etching in the etching chamber without ionizing or plasmatizing halogen fluoride gas as an etching gas. , Is characterized by.

A concrete structure having the above structure is shown in FIG. In FIG. 1, a substrate loading chamber 702 and a first substrate transport chamber 7 are shown.
01, etching chamber 800, second substrate transfer chamber 820,
A substrate unloading chamber 830 and robot arms 710 and 821 that are means for transporting substrates are shown. FIG. 1
0 is a top view of the etching apparatus shown in FIG.

When an active layer of a thin film transistor is formed by using the etching apparatus as shown in FIG. 1, it is important not to plasmaize (ionize) the halogen fluoride gas in order to prevent plasma damage to the active layer. Is. In order to prevent plasma generation, it is sufficient to prevent the gas from being excited and ionized. Further, in order to prevent the gas from being ionized, it is sufficient to apply no electromagnetic energy. Here, electromagnetic energy refers to high frequency energy or microwave energy.

In order to prevent the plasma from being generated, it is sufficient to apply no electromagnetic energy to the halogen fluoride gas so that the gas is not ionized or excited. Halogen fluoride gas, especially ClF ₃ gas has a very strong etching action on silicon and can etch silicon at a high speed without applying electromagnetic energy such as high frequency energy.

In the etching, the pressure during the etching is set to 0.001 so that the etching does not proceed rapidly.
A pressure range of -100 Torr is desirable. More preferably, the range is 0.01 to 1 Torr. This is the pressure range where the etching rate can be made appropriate.

According to another aspect of the invention, there is provided a first chamber in which an etching process using the halogen fluoride gas is carried out without ionizing or converting the halogen fluoride gas into plasma, and a second chamber for stripping the resist. , The first
And a chamber provided with a means for transporting the substrate, which is connected to the second chamber and the second chamber.

Further, in the above-mentioned structure, it is effective to adopt a structure in which etching is performed while heating. This is because the etching rate can be increased by heating. It is also useful to keep the etching at a predetermined temperature. This is to prevent a large change in the etching state due to a high etching rate and a slight difference in the etching temperature in the etching using ClF ₃ as the etching gas.

[0036]

【Example】

[Embodiment 1] FIG. 1 shows a schematic sectional view of an etching apparatus shown in this embodiment. The etching apparatus shown in FIG. 1 can continuously process a large number of substrates (samples) one by one. In the etching apparatus shown in FIG. 1, a large number of substrates 711 stored in a cassette 712 in a substrate loading chamber 702 are transferred to one substrate.
It is characterized in that the substrates are etched one by one in the etching chamber 800 and the substrates after the etching process are stored in a cassette 835 in the substrate unloading chamber 830. That is, it is characterized in that a large number of substrates are continuously etched one by one. Note that FIG. 10 is a top view of FIG.

(Explanation of Apparatus) A large number of substrates (samples) 711 for carrying out the etching process are loaded into the substrate loading chamber 702 from the outside in a state where a large number of substrates are stored in the cassette 712. As the substrate 711, a glass substrate or a quartz substrate on which a silicon semiconductor layer to be etched is formed is used. The substrate loading chamber 702 is provided with a nitrogen gas (or inert gas) introduction means (not shown) and a discharge means (not shown), and can be purged with nitrogen gas as necessary. Has become. The substrate loading chamber is not particularly configured to be in a depressurized state.

Cassette 71 containing a large number of substrates 711
2 is arranged on the stage 754. Stage 754
Moves slightly up and down by the elevator 753. The substrate loading chamber 702 is connected to a substrate transfer chamber 701 equipped with a robot arm 710 via a gate valve 706.

The substrate transfer chamber 701 is equipped with a gas introduction system 794 for introducing nitrogen gas or an inert gas. The flow rate of the gas introduced from the gas introduction system 794 is controlled by the valve 793. Further, the substrate transfer chamber 701 is provided with a high vacuum exhaust system including a valve 790 and a vacuum exhaust pump 791.

The substrate transfer chamber 701 has a gate valve 801.
It is connected to the etching chamber 800 via. In the etching chamber 800, a stage 803 made of quartz on which a substrate is placed is placed. Also laser light source 8
06, mirror 807, laser light etching chamber 800
A quartz window 805 to be introduced inside and an optical sensor 804 for detecting laser light are provided.

The etching gas is introduced into the etching chamber 800 from the gas introduction system 812 via the valve 810. Further, nitrogen or an inert gas is introduced from the gas introduction system indicated by 813 through the valve 811. A vacuum exhaust pump 809 is provided via a valve 808 for exhausting unnecessary gas and maintaining a predetermined depressurized state in the etching chamber.

The etching chamber 800 is provided with a gate valve 814.
It is connected to another substrate transfer chamber 820 via. The substrate transfer chamber 820 is a chamber for carrying out the substrate 822 after the etching process from the etching chamber 800 by the robot arm 821. The substrate transfer chamber 820 is provided with a gas introduction system 827 for introducing nitrogen gas or an inert gas. Gas introduction system 827
The flow rate of the gas introduced from is controlled by the valve 826. Further, an exhaust system including a valve 825 and a vacuum exhaust pump 823 is arranged.

The substrate transfer chamber 820 is provided with a gate valve 828.
It is connected to the substrate unloading chamber 830 via. In this chamber, a cassette 835 (the same as 712) that can store a large number of substrates 831 is arranged. The cassette 835 is arranged on a stage 833 which is slightly moved up and down by the elevator 832.

(Example of Operation Procedure) An example of operation when etching is described below. First, all the gate valves 706, 801, 814, 828 are closed. Then, the substrate transfer chambers 701 and 820 and the etching chamber 800 are brought to a high vacuum state. Further, an empty cassette 835 is arranged in the substrate unloading chamber 830 to be in a state filled with nitrogen gas (normal pressure).

In this state, the cassette 712 accommodating the required number of substrates 711 is loaded into the substrate loading chamber 702 from outside the apparatus. After loading the cassette 712, the substrate loading chamber 7
02 is filled with nitrogen gas under normal pressure.

After the cassette 712 is housed in the substrate loading chamber 702, nitrogen gas is introduced into the substrate transport chamber 701 to bring it into a normal pressure state. When the substrate transfer chamber 701 is in a normal pressure state, the gate valve 706 is opened and the robot arm 710 is opened.
Then, one substrate 711 is taken out from the cassette 712. At this time, the elevator 753 is finely moved up and down to adjust the positional relationship between the robot arm 710 and the substrate 711. After the substrate 711 is transferred to the substrate transfer chamber 701 by the robot arm 710, the gate valve 706 is closed.

Then, the substrate transfer chamber 701 is placed in a high vacuum state. If the substrate 701 is in a high vacuum state, the gate valve 8
01 is opened, and the substrate is placed on the stage 803. After that, the gate valve 801 is closed.

Next, ClF ₃ gas is introduced into the etching chamber 800 to etch the semiconductor thin film formed on the substrate surface under a predetermined reduced pressure. The etching state can be confirmed by the transmission state of the short wavelength laser light emitted from the light source 806.

For example, a crystalline silicon thin film having a film thickness of 500 nm has a transmittance of about 50% for light of 500 nm.
Further, the light of 500 nm is transmitted through the stage 803 made of a glass substrate or quartz with a transmittance of almost 80% or more. Therefore, when the crystalline silicon film formed on the glass substrate is etched in the state where the light source 806 irradiates the light of 500 nm, the optical sensor 804 detects the etching of the crystalline silicon film. The intensity of light will change rapidly. Therefore, when the light detected by the optical sensor 804 suddenly changes, the gas introduction system 812
If the flow of the etching gas is stopped and the nitrogen gas is made to flow from the gas introduction system 813 at the same time, unnecessary etching (for example, wraparound of the etching in the lateral direction) can be prevented.

After the etching is completed, the etching chamber 800
The inside is in a high vacuum state. Then, the gate valve 814 is opened, and the substrate 822 is taken out of the etching chamber 800 by the robot arm 821. And the gate valve 81
4 is closed and the inside of the substrate transfer chamber 820 is filled with nitrogen gas. The gate valve 828 is opened while the substrate transfer chamber 820 is at normal pressure, and the substrate 822 is stored in the cassette 835. Then, the gate valve 828 is closed and the substrate transfer chamber 82
0 is brought to a high vacuum state again.

In this state, the substrate loading chambers 702 and 830 are filled with nitrogen gas (normal pressure), and the substrate transportation chambers 701 and 820 and the etching chamber 800 are in a high vacuum state. Also all gate valves 828, 814, 8
01 and 706 are in the closed state. In this state, the substrate transfer chamber 701 is again brought to a normal pressure state, the gate valve 706 is opened, and the second substrate is taken out from the cassette 712 into the substrate transfer chamber 701 by the robot arm 710, thereby etching the second substrate. The process will start.

In this manner, all the substrates (samples) stored in the cassette 712 are continuously etched one by one. This etching process can be automatically performed by controlling with a computer.

In the structure shown in FIG. 1, the etching state is judged by measuring the transmitted light using a laser beam of short wavelength. However, the configuration may be such that reflected light is measured instead of transmitted light. This is because the etching of the silicon film changes the state of reflection of light of a specific wavelength, and changes in the intensity of reflected light and changes in interference fringes of reflected light are observed.

[Embodiment 2] This embodiment shows an example in which the invention disclosed in this specification is used in manufacturing a thin film transistor on a glass substrate. 2A to 2D show manufacturing steps of the thin film transistor shown in this embodiment. First, a silicon oxide film 102 as a base film is formed on a glass substrate (Corning 1737 glass substrate or Corning 7059 glass substrate) 101 by a plasma CVD method or a low pressure thermal CVD method.
Form a film with a thickness of 3000Å. This silicon oxide film 102
Is for preventing diffusion of impurities from the glass substrate 101 and for relaxing stress between the glass substrate 101 and an active layer formed later.

After the silicon oxide film 102 is formed, an amorphous silicon film 103 is formed on the silicon oxide film 102 by plasma CVD to a thickness of 500 Å.
Method or low pressure thermal CVD method. The amorphous silicon film 103 will later become a starting film for forming an active layer of a thin film transistor. (Fig. 2 (A))

After forming the amorphous silicon film 103, the amorphous silicon film 103 is crystallized by an appropriate means. As a method of crystallizing the amorphous silicon film, a method of heating, a method of irradiating laser light, a method of using both of them, and the like are known. In this embodiment, a crystallization method by heating using a metal element that promotes crystallization of silicon is adopted.

The crystallization method adopted in this embodiment will be described below. Here, nickel (Ni) is used as a metal element that promotes crystallization of silicon. First, a nickel acetate solution containing nickel element at a predetermined concentration is applied to the surface of the amorphous silicon film by spin coating. The concentration of the nickel element contained in this nickel acetate solution is 1 × 10 ¹⁶ c when the nickel element introduced into the amorphous silicon film is
It is necessary to adjust the concentration to be in the concentration range of about m ^{-3 to} 5 × 10 ¹⁹ cm ^-3 . This is because if the introduction amount of the nickel element is too large, nickel silicide is formed and the characteristics as a semiconductor are impaired, and if the introduction amount of nickel is too small, the action of promoting crystallization cannot be obtained. is there.

A nickel acetate solution is applied to the surface of the amorphous silicon film 103, and when the nickel element is kept in contact with the surface of the amorphous silicon film, a heat treatment is performed to make it amorphous. The silicon film 103 is crystallized. This heat treatment is performed at 550 ° C. for 4 hours. Generally, an amorphous silicon film does not crystallize at a temperature of about 550 ° C. even if a treatment for several tens of hours or more is applied. However, as shown in this example, when nickel element is used, crystallization can be performed by a heat treatment at a lower temperature and a shorter time than conventional. Incidentally, in the crystallization of the amorphous silicon film by heating in the conventional technique, heating at a temperature of 600 ° C. or more for several tens of hours or more is required.

In general, a crystalline silicon film obtained by crystallizing an amorphous silicon film by heating or irradiating a laser beam has a high density of defects in the film and has a high trap level density. The crystalline silicon film produced by the manufacturing method shown in this embodiment also has a high trap level density.

After obtaining the crystalline silicon film, the crystalline silicon film is patterned using the apparatus shown in FIG. 1 to form the active layer of the thin film transistor. Here, first, FIG. 2 (B)
A mask 100 for forming an active layer is formed using a photoresist as shown in FIG. Then, as shown in FIG. 2B, etching using ClF ₃ gas is performed to form the active layer 104 of the thin film transistor. The etching using ClF ₃ gas can be performed at room temperature or can be performed without plasma. Therefore, as a matter of course, plasma damage to the side surface of the active layer can be eliminated. This etching is performed according to the procedure shown in Example 1 using the apparatus shown in FIG.

The etching using ClF ₃ gas is also characterized in that there is almost no damage to the resist. This is because when an RIE method using plasma or a wet etching method is used, the damage to the resist is large, and the residue of the resist (in many cases, it cannot be removed and remains) remains. This is an advantage in that it is a big problem in the manufacturing process of the semiconductor device. It should be noted that the etching using ClF ₃ gas is an isotropic etching.

The etching conditions for forming this active layer 104 are shown below. Etching gas ClF ₃ Reaction pressure 0.4 Torr Reaction temperature Normal temperature Etching rate 500Å / min Mask Photoresist

Although an example in which etching is performed at room temperature is shown here, heating within a range where the etching gas is not ionized is useful for increasing the reaction rate.

After the etching is completed, the resist mask 10 is formed.
4 is removed to obtain the state shown in FIG. Figure 2
After forming the active layer 104 as shown in FIG.
As shown in (A), a gate insulating film 105 is formed by plasma CVD to a thickness of 1000Å. Next, a film containing aluminum as a main component is formed to a thickness of 6000Å by a sputtering method. Then, the gate electrode 106 is formed by performing patterning. Further, by performing anodic oxidation using the gate electrode 106 as an anode in an electrolytic solution,
An anodic oxide layer 107 is formed to a thickness of 2000Å.
(Fig. 3 (A))

After the state of FIG. 3A is obtained, as shown in FIG. 3B, P (phosphorus) ions are implanted by the plasma doping method so that the source region 108 and the drain region 110 are self-aligned. Form. At this time, the anodic oxide layer 107 around the gate electrode 106 serves as a mask to form the offset region 111. This offset area 111 is
Phosphorus ions are not implanted and it is substantially intrinsic, does not function as a channel, and functions as an electric field relaxation region between the channel and the source / drain regions. (Fig. 3
(B))

After completion of the above doping, laser light or intense light is irradiated to activate the source region and the drain region.

Then, as shown in FIG. 3C, a silicon oxide film 112 is formed as an interlayer insulating film to a thickness of 7,000 Å by the plasma CVD method. Then, contact holes are formed, and a source electrode 113 and a drain electrode 115 are formed using aluminum or another metal. Finally, heat treatment is performed in a hydrogen atmosphere at 350 ° C. for 1 hour to complete the thin film transistor shown in FIG.

FIG. 4 is a diagram schematically showing the state of the active layer in the case of adopting the structure shown in this embodiment. By patterning the active layer by etching using ClF ₃ gas as shown in the present embodiment, 300
Plasma damage on the side surface of the active layer indicated by can be eliminated. Therefore, the trap level density on the side surface 300 of the active layer due to plasma damage can be almost eliminated. As a result, the number of carriers moving on the route indicated by 302 can be reduced.

In the conventional dry etching method using plasma (generally, the RIE method is used), trap levels are formed at a high density on the side surface 300 of the active layer due to plasma damage. There was a route for carriers to move. The conduction of carriers in the route indicated by 302 is through the trap level and exists regardless of whether a channel is formed in the channel formation region 109. Therefore, if a voltage is applied between the source region 108 and the drain region 110 even if the offset region as shown by 111 is formed, carrier movement occurs via the route as shown by 302. Will end up. The OFF current increases due to the movement of the carriers.

However, when the structure shown in this embodiment is adopted, the trap level density on the side surface 300 of the active layer can be lowered, so that the number of carriers conducted by the route indicated by 302 can be suppressed. On the other hand, the original movement of carriers moving on the channel indicated by 301 is not impaired at all. Therefore, the effect of the offset gate region 111 can be maximized,
It is possible to obtain the characteristic that the OFF current is small.

[Embodiment 3] This embodiment shows a process used in manufacturing an active matrix type liquid crystal display device. In this embodiment, a thin film transistor (pixel transistor) formed in the active matrix region,
A step of simultaneously manufacturing a thin film transistor of a peripheral driver circuit for driving the thin film transistor arranged in the active matrix region is shown.

FIG. 5 shows a manufacturing process of the thin film transistor shown in this embodiment. First, a silicon oxide film 102 is formed as a base film on a glass substrate 101 to a thickness of 3000 Å by a sputtering method. Next, an amorphous silicon film is formed to a thickness of 500Å by plasma CVD method or low pressure thermal CVD method. Further, the amorphous silicon film is crystallized by heating or irradiation with laser light to obtain a crystalline silicon film 103.

Then, a resist mask 40 for forming an active layer of a thin film transistor which constitutes a peripheral drive circuit.
1 and a resist mask 4 for forming an active layer of a thin film transistor arranged in a matrix region (pixel region)
02 is formed. (Figure 5 (A))

Here, using the apparatus shown in FIG. 1, ClF ₃
Etching is performed. 40 in this etching process
The active layers designated by 3 and 404 are formed. Here, etching is performed under the following conditions. Etching gas ClF ₃ Reaction pressure 2 Torr Reaction temperature Normal temperature Etching rate 1000Å / min Mask Photoresist

After the etching process is completed, the resist mask is removed to obtain the state shown in FIG. FIG. 5 (B)
In, the active layer indicated by 403 is a thin film transistor which constitutes a peripheral drive circuit. The active layer indicated by 404 is the active layer of the thin film transistor arranged in the pixel region.

After forming the active layer, a film containing aluminum as a main component is formed to a thickness of 6000 Å by an electron beam vapor deposition method and patterned to form a gate electrode 40.
5 and 406 are formed. Then, anodic oxidation is performed in the electrolytic solution using the gate electrodes 405 and 406 as anodes to form anodic oxide layers 407 and 408 to a thickness of 2000 Å. Due to the presence of this oxide layer, the offset gate region can be formed in the subsequent impurity ion implantation step. (Fig. 5 (C))

When the state shown in FIG.
Impurity ions are implanted to form the drain region by an ion implantation method or a plasma doping method.
Here, phosphorus ions are implanted by a plasma doping method in order to form an N-channel thin film transistor. (FIG. 5 (D))

By implanting phosphorus ions, the source regions 409 and 413, the drain regions 412 and 416, the channel forming regions 411 and 415, and the offset gate regions 410 and 416 can be formed in a self-aligned manner. Further, regions where impurity ions are not implanted are defined as channel forming regions 411 and 415 and offset gate regions 410 and 414. (FIG. 5 (D))

After the implantation of the impurity ions is completed, laser light irradiation or intense light irradiation is performed to anneal the region into which the impurity ions are implanted. In this annealing step, recrystallization of the source / drain regions amorphized by the implantation of the impurity ions and activation of the implanted impurities are performed. (Fig. 6 (A))

After the formation of the source / drain regions is completed, as shown in FIG. 6B, a silicon oxide film 501 is formed as an interlayer insulating film by plasma CVD to a thickness of 6000Å. Then, a contact hole is formed. Then, using aluminum, the source electrode 502 and the drain electrode 50 of the thin film transistor arranged in the peripheral drive circuit region are formed.
3 is formed. At the same time, the source electrode 504 of the thin film transistor arranged in the pixel region is formed.

Further, a silicon oxide film having a thickness of 3000 Å is formed by a plasma CVD method, and after forming a contact hole,
An ITO electrode 506 that constitutes a pixel electrode is formed. This ITO electrode is directly connected to the drain region 416 of the thin film transistor arranged in the pixel region. (FIG. 6
(B))

Finally, a hydrogenation treatment is performed in a hydrogen atmosphere at 350 ° C. for 1 hour to obtain the result shown in FIG.
Complete the configuration as shown. When the configuration as shown in this embodiment is adopted, the presence of the OFF current passing through the side surface of the active layer of the thin film transistor can be remarkably reduced, so that the effect of reducing the OFF current by adopting the offset gate structure is maximized. You can make the most of it.
That is, a thin film transistor with a small OFF current can be obtained. Such a thin film transistor having a small OFF current value is very useful as a thin film transistor arranged in a pixel region of an active matrix type liquid crystal display device as shown in FIG. 6B.

[Embodiment 4] This embodiment relates to the structure of a thin film transistor in which at least one pixel region is arranged in each of the pixel regions arranged in a matrix of an active matrix type liquid crystal display device.

FIG. 7 shows a manufacturing process of the thin film transistor shown in this embodiment. First, as shown in FIG. 7A, a silicon nitride film 602 is formed as a base film on a glass substrate 601 by a plasma CVD method. Further, a silicon oxide film 603 is formed by a sputtering method. Next, an amorphous silicon film 604 is formed to a thickness of 500Å by plasma CVD method or low pressure thermal CVD method. Then, a mask 605 made of a silicon oxide film is formed by a known photolithography process. This mask 60
5 partially exposes the amorphous silicon film 604.

Then, a nickel acetate solution containing a predetermined concentration of nickel element which is a metal element for promoting crystallization of silicon is applied by spin coating. In this state, a nickel element layer 606 or a nickel element layer 606 is formed. (Figure 7 (A))

Then, heat treatment is applied for 4 hours in an atmosphere of 550 ° C. By applying this heat treatment, FIG.
Crystal growth as indicated by an arrow 600 in (B) is performed. This crystal growth proceeds in a direction parallel to the substrate in a needle shape or a column shape. In FIG. 7B, reference numeral 607 indicates a region in which the crystal has grown in the direction parallel to the substrate. Further, 608 is a region into which the nickel element is directly introduced, which is a region in which the nickel element is present at a high concentration. Also, as indicated by 609 and 610,
This is the end point of crystal growth. It has been confirmed that the nickel element is present at a high concentration also in the region at the end point of this crystal growth.

Further, the nickel concentration (maximum measured concentration) in the region indicated by 607 is 1 × 10 ¹⁶ cm.
^{-3 to} 5 × 10 ¹⁹ cm ^-3 , as shown in FIG.
It is necessary to adjust the concentration of nickel element in the nickel acetate solution spin-coated in the step (A).
The nickel element concentration is a value obtained by the maximum measurement value of SIMS (secondary ion analysis method).

Next, utilizing the invention disclosed in this specification,
An active layer 611 shown in FIG. 7C is formed by etching. In this step, a resist mask is formed on a region to be an active layer by a photolithography process, and then etching using ClF ₃ gas is performed to form an active layer 611. Detailed conditions and the like may be those shown in the first or second embodiment.

Next, a silicon oxide film 612 is formed as a gate insulating film.
Is formed to a thickness of 1000Å by the plasma CVD method. Further, an aluminum film containing scandium is formed to a thickness of 6000Å by a sputtering method. Next, the aluminum film is etched using the mask 614 made of photoresist. The resist mask 614 is left after the etching process is completed. And the resist mask 61
Using the aluminum film remaining in the state where 4 remains as an anode, anodization is performed in an electrolytic solution to form a porous anodic oxide layer 615 to a thickness of about 5000 Å. This anodic oxidation step is performed by using 3-20% oxalic acid (30 ° C.) as an electrolytic solution and applying a voltage of 10 V to the remaining aluminum film. After this step, the portion 613 where the aluminum remains remains becomes the gate electrode. (Fig. 7 (C))

Next, the resist mask 614 is removed and p
Anodization is performed again using the gate electrode 613 as an anode in an ethylene glycol solution containing H at about 7 and containing 1 to 3% tartaric acid. In this step, a dense barrier type anodic oxide layer 616 is formed to a thickness of 2000Å.

Next, the exposed gate insulating film 612 is RIEed.
Etching is performed by dry etching according to the method. At this step, the anodic oxides 615 and 616 are hardly etched due to the difference in etching rate. This etching is finished in a state where the active layer 611 is exposed. Thus, the remaining gate insulating film 612 'is obtained as shown in FIG.

After obtaining the state shown in FIG. 7D, the polar-anodic anodic oxide layer 615 is removed. And FIG.
After obtaining the state shown in (E), boron (B) ions are implanted into the active layer 611 by a plasma doping method. This impurity ion implantation is performed at a low acceleration voltage of about 10 kV. Therefore, intrusion of boron ions is suppressed in the exposed portion of the gate insulating film 612 ′, and boron (B) ions are not implanted in the region indicated by 622. On the other hand, boron ions are implanted in the region indicated by 617. Thus
The region indicated by 622 is defined as an offset region without implanting impurity ions. (Fig. 7 (E))

Next, the doped impurity ions are activated by performing heat treatment at 500 ° C. for 4 hours. And to further enhance the effect of annealing, KrF
Irradiate excimer laser. At this time, 617 and 622
The boundary surface with and (where the PI junction is formed) is sufficiently activated by the laser light that has passed through the gate insulating film (silicon oxide film 612 ′). The presence of the trap level at the interface between the region 617 serving as the source / drain region and the region 622 serving as the offset region causes the OFF current to flow. Therefore, activation or annealing for this region reduces the OFF current. Very effective for.

Next, a silicon oxide film 618 is formed as an interlayer insulating film by plasma CVD to a thickness of 3000 Å. Then, a contact hole is formed and a source electrode 619 made of an aluminum film is formed. Further, a silicon nitride film 620 is formed as an interlayer insulating film to a thickness of 3000 Å. Then, a contact hole is formed and an ITO electrode 621 which will be a pixel electrode is formed. Thus, a P-channel thin film transistor having the offset region 622 can be obtained. (Fig. 7 (F) (G))

When a crystalline silicon film is formed by using a metal element that promotes crystallization of silicon and the active layer is formed by patterning the crystalline silicon film, plasma damage is given to the surface of the active layer. As a result, a trap level is formed due to the metal element. As described above, in the formation of the active layer, plasma damage particularly occurs on its side surface.

When the active layer is formed by an etching method without plasma damage as shown in this embodiment, a metal element that promotes crystallization of silicon is used in the production of the crystalline silicon film forming the active layer. Even in such a case, the trap level density on the side surface of the active layer does not become particularly high. Therefore, the movement of carriers via the side surface of the active layer can be suppressed low, and a thin film transistor with a small OFF current can be obtained. Further, since the movement of carriers via the side surface of the active layer can be suppressed, the significance (effect) of providing the offset region and the lightly doped region can be maximized.

[Embodiment 5] FIG. 8 shows an example of an etching apparatus disclosed in this specification. The etching apparatus shown in FIG. 8 includes an etching chamber 902 and a substrate (sample) transfer chamber 90.
0, a substrate loading chamber 903, and a substrate unloading chamber 904. The etching chamber 902 has a stage 9 for placing a substrate (sample) to be etched.
10 are installed. The stage 910 is equipped with a heating / cooling mechanism for controlling the substrate within a predetermined temperature of ± 5 ° C.

The etching chamber 902 and the substrate transfer chamber 900 are connected by a gate valve 905. In the substrate transfer chamber 900, a robot arm 908 for transferring the substrate 909 is arranged. In the substrate transfer chamber 900,
The substrate loading chamber 903 and the substrate unloading chamber 905 are connected via gate valves 906 and 907, respectively. In the substrate loading chamber 903 and the substrate unloading chamber 904, a cassette 911 that can store a large number of substrates is arranged.

FIG. 8A is a top view of the device.
A cross section taken along the line AA ′ of (A) is shown in FIG. As shown in FIG. 8B, this etching apparatus includes a high vacuum exhaust system 92 in the etching chamber 902 and the substrate transfer chamber 900.
1 and 913. In the figure, reference numerals 912 and 920 are vacuum exhaust system valves.

The substrate transfer chamber 900 has a supply system 915 of nitrogen gas or inert gas, and the substrate transfer chamber 90
The inside of 0 can be purged as needed. In the etching chamber 902, a nitrogen gas or inert gas supply system 918 and an etching gas (for example, C
1F ₃ ) supply system 919. Reference numerals 912 and 920 are valves for the gas supply system.

Cassette 9 containing a large number of substrates 909
11 is arranged on the elevator stage 923, and finely moves up and down by the fine vertical movement of the elevator 922. This mechanism is used when the substrate 909 is transferred by the robot hand 908.

Although not shown in the figure, a high vacuum exhaust system is arranged in the substrate loading chamber 903 and the substrate unloading chamber 904,
It would be useful to be able to evacuate these chambers to a high vacuum. If such a configuration is adopted, the etching chamber 9
The component of the etching gas mixed from 02 can be always exhausted, and the etching accuracy can be improved and the process stability can be secured.

[Sixth Embodiment] FIG. 9 shows a substrate loading chamber 1002 and a substrate unloading chamber 1006, at least one of which is an etching chamber 1003 to 1005, and a common substrate transfer chamber 1.
001, a substrate transfer chamber 1001 and an etching apparatus including gate valves 1007 to 1011 connecting the chambers.

As a concrete structure of the etching apparatus shown in FIG. 9, the chamber indicated by 1003 is an etching chamber using ClF _3, and the chamber indicated by 1004 is for removing the resist mask used at the time of etching. The ashing chamber and the chamber denoted by 1005 may be used as a chamber for removing the resist residue by irradiation with UV light.

Further, in the manufacturing process of the insulating gate type field effect transistor having the silicide gate, the process of etching the silicide, then the silicon, and then the gate insulating film is required. In that case, 1003 may be an etching chamber using ClF ₃ , 1004 may be a chamber for etching the gate insulating film, and 1005 may be an ashing chamber for removing the resist.

Further, 1003 may be an etching chamber for etching silicide, 1004 may be an etching chamber for etching silicon, and 1005 may be an ashing chamber for removing the resist. In this case, 1
Both the etching chamber 003 and the etching chamber 1004 may be an etching chamber using ClF ₃ gas.
However, since the etching conditions for silicide and silicon are different, the etching chamber should be set under one condition,
The feature is to improve work efficiency.

[0107]

EFFECTS OF THE INVENTION When forming an active layer of a thin film transistor, by adopting an etching method without plasma damage, it is possible to prevent generation of trap levels on the side surface of the active layer. By doing so, the movement of carriers via the trap level existing on the side surface of the active layer can be suppressed, and the value of the OFF current can be reduced.

[Brief description of drawings]

FIG. 1 shows an outline of an etching apparatus of an embodiment.

2A to 2D are diagrams showing manufacturing steps of a thin film transistor of an example.

3A to 3D are diagrams showing manufacturing steps of a thin film transistor of an example.

FIG. 4 is a schematic view showing an enlarged state of an active layer.

5A to 5D are diagrams showing a manufacturing process of a thin film transistor arranged in a peripheral driver circuit region and a pixel region.

6A to 6C are diagrams showing a manufacturing process of a thin film transistor arranged in a peripheral driver circuit region and a pixel region.

7A to 7C are diagrams showing a manufacturing process of a thin film transistor arranged in a pixel region.

FIG. 8 is a diagram showing an outline of an etching apparatus of an embodiment.

FIG. 9 is a diagram showing an outline of an etching apparatus of an embodiment.

FIG. 10 is a diagram showing a top view of the etching apparatus shown in FIG.

[Explanation of symbols]

712, 835 Cassettes 711, 822 Substrates (samples) 702 Substrate loading chambers 754, 833 Stages 753, 832 Elevators 706, 801, 814 Gate valves 828 701, 820 Substrate transport chambers 710, 821 Robot arms 794, 812, 812 Gas introduction system 827 793, 790, 810 valve 811, 826, 825 808 791, 809, 823 vacuum exhaust pump 101, 601 glass substrate 102, 603 base film (silicon oxide film) 602 base film (silicon nitride film) 103, crystalline silicon film 100 Resist Mask 104 Active Layer 105 Gate Insulating Film (Silicon Oxide Film) 106 Gate Electrode Mainly Containing Aluminum 107 Anodic Oxide Layer 108 Source Region 109 Channel Forming Region 110 Drain Region 111 Offset Region 112 interlayer insulating film (silicon oxide film) 113 source electrode 115 drain electrode 300 side surface of active layer 301 route of carrier moving channel 302 route of carrier moving via side surface of channel 401, 402 resist mask 403 periphery Active layer 404 of thin film transistor arranged in driving circuit region 404 Active layer of thin film transistor arranged in pixel region 405, 406 Gate electrodes 407, 408 mainly composed of aluminum Anodic oxide layers 409, 413 Source regions 410, 414 Offset gate Regions 411, 415 Channel formation regions 412, 416 Drain regions 501, 505 Interlayer insulating films (silicon oxide films) 502, 504 Source electrodes 503 Drain electrodes 506 Pixel electrodes (ITO electrodes) 604 Amorphous silicon films 6 05 Mask made of silicon oxide film 606 Nickel film or film containing nickel 607 Crystal-grown region 608 Nickel-directly introduced region with high nickel element concentration 609, 610 Crystal growth end point 600 Crystal growth direction 611 Activity Layer 612 Gate insulating film (silicon oxide film) 613 Gate electrode containing aluminum as a main component 614 Resist mask 615 Porous anodic oxide layer 616 Dense barrier type anodic oxide layer 612 'Remaining gate insulating film 622 Offset region 617 Impurity regions to be source / drain regions 618 Interlayer insulating film (silicon oxide film) 619 Source electrode 620 Interlayer insulating film (silicon nitride film) 621 Pixel electrode (ITO electrode)

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication location H01L 21/336 9056-4M H01L 29/78 627 C

Claims (10)

[Claims] 1. An etching apparatus comprising a chamber in which an etching process using the halogen fluoride gas is performed without ionizing or plasmatizing the halogen fluoride gas. 2. A first chamber for etching, a second chamber for accommodating a large number of substrates, and means for transporting the substrate arranged between the first chamber and the second chamber. And a third chamber capable of depressurizing, wherein in the first chamber, an etching treatment using the halogen fluoride gas is performed without ionizing or converting the halogen fluoride gas into plasma. Characteristic etching equipment. 3. A chamber having a means for introducing a halogen fluoride gas, wherein an etching process using the halogen fluoride gas without ionizing or plasmatizing the halogen fluoride gas is performed in the chamber. The etching apparatus is characterized in that the chamber is provided with means for measuring the light transmitted through the material to be etched and detecting the etching state. 4. A substrate carrying-in chamber, a first substrate carrying chamber connected to the substrate carrying-in chamber, an etching chamber connected to the first substrate carrying chamber, and a second substrate connected to the etching chamber. And a substrate unloading chamber connected to the second substrate transporting chamber, wherein the substrate loading chamber and the substrate unloading chamber have a function of storing a large number of substrates, The first transfer chamber and the second transfer chamber have means for transferring a substrate, and have a function of performing etching in the etching chamber without ionizing or converting a halogen fluoride gas as an etching gas into a plasma. The etching apparatus is characterized in that 5. The halogen fluoride gas according to claim 1, wherein ClF ₃ , ClF, BrF ₃ and IF are used as the halogen fluoride gas.
An etching apparatus characterized by using one or more kinds of gas selected from ₃ , BrF, BrF ₅ , and IF ₅ . 6. The etching apparatus according to claim 1, wherein the etching is performed at a pressure of 0.01 to 1 Torr. 7. The etching apparatus according to claim 1, wherein the etching is performed at a pressure of 0.001 to 100 Torr. 8. The etching apparatus according to claim 1, wherein the etching is performed while heating. 9. The etching apparatus according to claim 1, wherein the etching is performed at a predetermined temperature. 10. A first chamber in which an etching process using the halogen fluoride gas is performed without ionizing or plasmatizing the halogen fluoride gas, a second chamber for stripping the resist, and the first chamber. An etching apparatus comprising: a chamber and a chamber that is connected to the second chamber and that conveys a substrate.