JP2004320042A - Process for producing wiring board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring board in which noise can be removed surely by incorporating a capacitor and the inductance of wiring can be lowered, and to provide an inexpensive wiring board capable of incorporating a capacitor having a high capacitance. <P>SOLUTION: The wiring board 100 incorporates a capacitor 20 in a recess 11 formed in a core substrate body 10 and provided with resin insulating layers 41-43 and 51-53 and wiring layers 45, 46, 55 and 56 above and below the capacitor 20. The capacitor 20 can be connected vertically through pads 21 and 22 on the upper surface 20A and lower surface 20B and when a bottom through hole conductor 12 connected with the pad 21 or 22 is connected with the wiring layers 45 and 55, it is connected with a flip-chip pad 101 or an LGA pad 103 through a large number of upper capacitor connecting lines 60 or lower capacitor connecting lines 70. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

The present invention is a wiring board comprising a capacitor, and more particularly, a built-in capacitor in the core substrate by stacking the upper and lower resin insulating layer and the wiring layer, a method of manufacturing a wiring board that noise can be reliably removed.

  Although the operation of IC chips has been increasingly accelerated due to the progress of integrated circuit technology, noise may be superimposed on power supply wiring and the like to cause malfunctions. Therefore, in order to remove noise, for example, as shown in FIG. 11, a chip capacitor 3 is separately mounted on the upper surface 2A or the lower surface 2B of the wiring board 2 on which the IC chip 1 is mounted, and connected to the two electrodes of the capacitor 3, respectively. The capacitor connection wiring 4 is provided inside the wiring board 2. Thus, the chip capacitor 3 is connected to the IC chip 1 via the capacitor connection wiring 4 and the flip chip pad 5.

  However, according to the above-described method, it is necessary to separately mount the chip capacitor 3 after the completion of the wiring board 2, so that the number of steps is increased and the cost is increased. In addition, the reliability of the wiring board may be reduced depending on the connection reliability of the chip capacitor 3 such that the quality of the connection of the chip capacitor affects the quality of the entire wiring board. In addition, it is necessary to secure an area for mounting the chip capacitor 3 in advance, which reduces the degree of freedom in mounting other electronic components and fixing a reinforcing member for reinforcing the wiring board. Further, the length of the capacitor connection wire 4 connecting the IC chip 1 and the chip capacitor 3 is long and easily narrowed by being limited to other wires and the like. It is not easy to meet the demand for low resistance and low inductance.

  Therefore, of the wiring board, the resin insulating layer formed above and below the core substrate and a part of the wiring layer are formed into a capacitor structure in which the resin insulating layer is sandwiched between opposing wiring layers (electrode layers) as a dielectric layer, It is conceivable to incorporate a capacitor. However, if the capacitor becomes defective due to short-circuit or insulation resistance failure, the entire value-added wiring board will be discarded, resulting in a large amount of loss. Is difficult. In addition, the relative dielectric constant of the resin insulating layer is generally expected to be at most about 40 to 50 even if high dielectric constant ceramic powder or the like is mixed, so that it is difficult to sufficiently increase the capacitance of the built-in capacitor. .

The present invention has been made in view of the above problems, and by incorporating a capacitor, a noise can be reliably removed, and furthermore, a wiring board that can reduce the resistance and inductance of wiring connected to the capacitor, has less loss amount even if a defect in the capacitor, inexpensive, and to provide a method for manufacturing a built-capable circuit base plate capacitor of a large capacitance.

  The solution is to inspect the characteristics of the capacitor on the capacitor built-in core substrate incorporating the capacitor, and a characteristic inspection process of removing the non-standard core substrate with a built-in capacitor. A method of forming an insulating layer wiring layer for forming a resin insulating layer and a wiring layer.

  If a failure of the capacitor is found in the state of the wiring board on which the resin insulating layer and the wiring layer are formed, the wiring board has to be discarded. However, in general, forming a resin insulating layer or a wiring layer on a core substrate requires a large number of steps and time. Therefore, a wiring board on which a resin insulating layer or a wiring layer is formed has a high added value. Discarding will increase the amount of loss. On the other hand, in the method of manufacturing a wiring board of the present invention, the characteristics of the capacitor built in the core board are inspected in advance by using the core board having the built-in capacitor, and the resin insulating layer and the wiring are formed by using only those within the standard. Since the layer is formed, the risk of discarding the wiring board due to a failure of the capacitor after manufacturing the wiring board can be reduced, and the amount of loss accompanying the disposal can be suppressed. Therefore, a wiring board having a built-in capacitor can be manufactured at a low cost.

A wiring having an upper surface of the wiring substrate and a lower surface of the wiring substrate, a plurality of IC connection terminals for connecting an IC chip on the upper surface of the wiring substrate, and a plurality of connection terminals on the lower surface of the wiring substrate, and a built-in capacitor; A core substrate main body upper surface, a core substrate main body lower surface, a bottomed concave portion for capacitor built-in opening on the core substrate main body upper side, and a bottom portion of the concave portion penetrating from the bottom surface to the lower surface of the core substrate main body. A core substrate body including a plurality of bottom through-hole conductors extending to the lower surface of the main body, and a plurality of core through-hole conductors formed so as to penetrate between the upper surface of the core substrate main body and the lower surface of the core substrate main body; and a capacitor. The upper surface, the lower surface of the capacitor, a pair of electrodes or electrode groups insulated from each other, or the electrode formed on the upper surface of the capacitor and any one of the pair of electrodes or the electrode group; Are a plurality of upper surface connection pads each electrically connected to the electrode group, a plurality of upper surface connection pads each of which is electrically connected to at least one of the plurality of upper surface connection pads, and the capacitor A plurality of lower surface connection pads formed on the lower surface and electrically connected to any one of the pair of electrodes or electrode groups, respectively, wherein each of the pair of electrodes or electrode groups is connected to the plurality of lower surface connections. A plurality of lower surface connection pads electrically connected to at least one of the pads, wherein the plurality of bottom through-hole conductors are embedded and fixed in the capacitor built-in recesses of the core substrate body, and correspond to the plurality of lower surface connection pads. And the one or more capacitors stacked above the upper surface of the core substrate body and the upper surface of the capacitor. A plurality of upper resin insulation layers, one or more lower resin insulation layers laminated below the lower surface of the core substrate main body, and a plurality of upper resin insulation layers penetrating through the upper resin insulation layers or passing through the interlayers. A plurality of upper capacitor connection wirings respectively connecting the IC connection terminals and a plurality of upper connection pads of the capacitor corresponding thereto, and extending to the lower surface of the core substrate main body through the lower resin insulating layer or through the interlayer. A plurality of lower capacitor connection wirings respectively connecting the exposed bottom through-hole conductors and a plurality of connection terminals on the lower surface of the wiring board, and the wiring board passing through or through the upper resin insulating layer; A plurality of upper cores respectively connecting the plurality of IC connection terminals on the upper surface and the corresponding plurality of core through-hole conductors on the upper surface of the core substrate body A plurality of lower portions for connecting the connection wiring and the core through-hole conductor on the lower surface of the core substrate body and the corresponding plurality of connection terminals on the lower surface of the wiring substrate, respectively, through the lower resin insulating layer or through the interlayer. it is preferable that the wiring board, characterized in comprising a core connecting line, the.

Wiring board of this is to form a capacitor built recess in the core substrate main body, a built-in capacitor therein, to form an upper resin insulating layer and the lower resin insulating layer, IC connection terminals and the top surface connection, such as a flip-chip pads The pad is connected to the upper capacitor connection wiring, and the bottom through-hole conductor and the connection terminal are connected to the lower capacitor connection wiring. Further, each of the pair of electrodes or the electrode group is configured to conduct with at least one of the plurality of upper surface connection pads. The same applies to the lower surface connection pads. Therefore, both poles of the capacitor can be taken out above and below the capacitor. Therefore, both poles of the capacitor can be connected from the upper surface connection pad to the IC connection terminal and further to the IC chip through the upper capacitor connection wiring. Similarly, both electrodes of the capacitor can be connected to the connection terminal from the lower surface connection pad through the bottom through-hole conductor and the lower capacitor connection wiring. For this reason, the capacitor can be arranged very close to the IC connection terminal connected to the IC chip or the connection terminal connected to the power supply wiring or the ground wiring of another wiring board such as a motherboard. Therefore, both the upper capacitor connection wiring and the lower capacitor connection wiring can be formed very short.

  Further, in a normal IC chip, a power supply potential and a ground potential are required in various places, so that the number of power supply terminals and grounds is sometimes set to be closer to half of the number of connection terminals (connection pads and connection bumps) formed in the IC chip. Many terminals are formed respectively. On the other hand, the upper surface and the lower surface of the capacitor are provided with a plurality of upper surface connection pads and a plurality of lower surface connection pads. Therefore, if a number of upper surface connection pads are formed corresponding to the power supply terminal and the ground terminal of the IC chip, and a number of upper capacitor connection lines are formed in parallel so as to connect these, respectively, the inductance and resistance of the upper capacitor connection line can be obtained. Can be further reduced as a whole. Similarly, for the lower capacitor connection wiring for connecting the bottom through-hole conductor corresponding to the lower surface connection pad and each connection terminal on the lower surface of the wiring board in parallel, the inductance and resistance can be further reduced as a whole. That is, since both the upper capacitor connection wiring and the lower capacitor connection wiring can be reduced in length and the number thereof can be increased, the resistance and inductance can be reduced, and noise can be effectively and reliably removed by the capacitor. .

  In addition, since the capacitor is built in the wiring board, it is not necessary to attach the capacitor later, and the cost for mounting the chip capacitor is not required, so that an inexpensive wiring board can be obtained. In addition, there is a high degree of freedom in mounting other electronic components and the like and fixing a reinforcing plate. In addition, since the capacitor is built in the capacitor built-in recess formed in the core substrate body, the upper resin insulation layer or lower resin insulation layer or upper capacitor connection wiring, lower capacitor connection wiring, upper core connection wiring, and lower core connection The wiring can be formed at a low cost in that any of the wirings can be formed by using a known method of manufacturing a resin insulating layer or a wiring layer. Further, since the capacitance of the built-in capacitor can be freely selected, a large-capacitance capacitor using high-dielectric-constant ceramic can be built-in, and the noise elimination ability can be further improved.

  In particular, it is preferable that at least a part of the plurality of IC connection terminals is located above the capacitor. When the IC connection terminal such as a flip chip pad is located above the capacitor, the length of the upper capacitor connection wire connecting the IC connection terminal and the upper surface connection pad of the capacitor can be particularly reduced. Therefore, the inductance and resistance of the upper capacitor connection wiring can be further reduced, so that the noise elimination ability can be further improved.

In addition, it has a wiring substrate upper surface and a wiring substrate lower surface, a plurality of IC connection terminals for connecting an IC chip to the wiring substrate upper surface, a plurality of connection terminals on the wiring substrate lower surface, and a capacitor. A wiring board to be incorporated, wherein the upper surface of the core substrate main body, the lower surface of the core substrate main body, the bottomed capacitor-containing recess opening on the lower side of the core substrate main body, the bottom of the concave portion penetrating from the bottom surface to the upper surface of the core substrate main body. A plurality of bottom through-hole conductors extending to the upper surface of the core substrate main body, and a core through-hole conductor formed by penetrating between the upper surface of the core substrate main body and the lower surface of the core substrate main body; The upper surface of the capacitor, the lower surface of the capacitor, a pair of electrodes or electrode groups insulated from each other, or any one of the pair of electrodes or the electrode group formed on the upper surface of the capacitor. Are a plurality of upper surface connection pads each electrically connected to the electrode group, a plurality of upper surface connection pads each of which is electrically connected to at least one of the plurality of upper surface connection pads, and the capacitor A plurality of lower surface connection pads formed on the lower surface and electrically connected to any one of the pair of electrodes or electrode groups, respectively, wherein each of the pair of electrodes or electrode groups is connected to the plurality of lower surface connections. A plurality of lower surface connection pads electrically connected to at least one of the pads, wherein the plurality of bottom through-hole conductors are embedded and fixed in the capacitor built-in recess of the core substrate body, and correspond to the plurality of upper surface connection pads. And one or more upper resin insulation layers laminated above the upper surface of the core substrate main body. One or more lower resin insulation layers laminated below the lower surface of the core substrate main body and the lower surface of the capacitor; and a plurality of IC connection terminals on the upper surface of the wiring substrate through the upper resin insulation layer or through the interlayer. Correspondingly, a plurality of upper capacitor connection wirings respectively connecting a plurality of bottom through-hole conductors extending to the upper surface of the core substrate main body, and the lower surface of the capacitor penetrating through the lower resin insulating layer or through the interlayer. A plurality of lower capacitor connection wirings respectively connecting the connection pads and a plurality of connection terminals on the lower surface of the wiring board corresponding thereto, and a plurality of lower capacitor connection wirings penetrating through the upper resin insulating layer or passing through the interlayer to form a plurality of lower capacitor connection wirings. A plurality of upper core connections respectively connecting the IC connection terminals and the corresponding plurality of core through-hole conductors on the upper surface of the core substrate body. A plurality of lower core connections for connecting the continuation wiring and the plurality of connection terminals on the lower surface of the wiring substrate with the core through-hole conductors on the lower surface of the core substrate body through the lower resin insulating layer or through the interlayer; preferably in the wiring board, characterized in that it comprises wiring and, a.

Wiring board of this is to form a capacitor built recess in the core substrate main body, a built-in capacitor therein, to form an upper resin insulating layer and the lower resin insulating layer, IC connection terminals such as flip chip pads and the bottom through The hole conductor is connected to the upper capacitor connection wiring, and the lower connection pad and the connection terminal are connected to the lower capacitor connection wiring. Further, each of the pair of electrodes or the electrode group is configured to conduct with at least one of the plurality of upper surface connection pads. The same applies to the lower surface connection pads. Therefore, both poles of the capacitor can be taken out above and below the capacitor. Therefore, both poles of the capacitor can be connected from the upper surface connection pad to the IC connection terminal through the bottom through hole conductor and the upper capacitor connection wiring, and further to the IC chip. Similarly, both poles of the capacitor can be connected from the lower surface connection pad to the connection terminal through the lower capacitor connection wiring. For this reason, the capacitor can be arranged very close to the IC connection terminal connected to the IC chip or the connection terminal connected to the power supply wiring or the ground wiring of another wiring board such as a motherboard. Therefore, both the upper capacitor connection wiring and the lower capacitor connection wiring can be formed very short.

  Further, as described above, in an ordinary IC chip, a large number of power terminals and a large number of ground terminals are formed. On the other hand, the upper surface and the lower surface of the capacitor are provided with a plurality of upper surface connection pads and a plurality of lower surface connection pads. Therefore, by forming a large number of bottom through-hole conductors and top connection pads corresponding to the power supply terminal and the ground terminal of the IC chip, and forming a large number of upper capacitor connection wirings in parallel so as to connect these, respectively, the upper capacitor connection wiring The overall inductance and resistance of the device can be further reduced. Similarly, for the lower capacitor connection wiring for connecting the lower connection pad and each connection terminal on the lower surface of the wiring board in parallel, the inductance and the resistance can be further reduced as a whole. That is, since both the upper capacitor connection wiring and the lower capacitor connection wiring can be reduced in length and the number thereof can be increased, the resistance and inductance can be reduced, and noise can be effectively and reliably removed by the capacitor. .

  In addition, since the capacitor is built in the wiring board, it is not necessary to attach the capacitor later, and the cost for mounting the chip capacitor is not required, so that an inexpensive wiring board can be obtained. In addition, there is a high degree of freedom in mounting other electronic components and the like and fixing a reinforcing plate. In addition, since the capacitor is built in the capacitor built-in recess formed in the core substrate body, the upper resin insulation layer or lower resin insulation layer or upper capacitor connection wiring, lower capacitor connection wiring, upper core connection wiring, and lower core connection The wiring can be formed at a low cost in that any of the wirings can be formed by using a known method of manufacturing a resin insulating layer or a wiring layer. Further, since the capacitance of the built-in capacitor can be freely selected, a large-capacitance capacitor using high-dielectric-constant ceramic can be built-in, and the noise elimination ability can be further improved.

Thereon, the wiring board of this, the upper is the bottom of the concave portion for a built-in capacitor, i.e., since the IC connection terminal side, an upper resin insulating layer is formed on the core substrate main body on the upper surface of the capacitor built-in recess is not open, further An IC connection terminal is formed. Therefore, the upper resin insulating layer can be easily flattened, the coplanarity of the IC connection terminal can be improved, and the connection reliability with the IC chip can be further improved.

  In particular, it is preferable that at least a part of the plurality of IC connection terminals is located above the capacitor. With this configuration, since the IC connection terminal such as a flip chip pad is located above the capacitor, the length of the upper capacitor connection wiring connecting the IC connection terminal and the bottom through-hole conductor can be particularly reduced. Therefore, the inductance and resistance of the upper capacitor connection wiring can be further reduced, so that the noise elimination ability can be further improved.

To yet another, the core substrate main body top surface, a core substrate main body bottom surface, the core substrate main body upper surface bottomed capacitor built recess of opening to and through the bottom of the recess from the bottom surface to the core substrate main body lower surface A core substrate body including a plurality of bottom through-hole conductors extending to a lower surface of the core substrate body, a capacitor upper surface, a capacitor lower surface, a pair of electrodes or electrode groups insulated from each other, and the pair of electrodes formed on the capacitor upper surface; Alternatively, a plurality of upper surface connection pads each electrically connected to any one of the electrodes or the electrode group, and each of the pair of electrodes or the electrode group is electrically connected to at least one of the plurality of the upper surface connection pads. A plurality of upper surface connection pads, and one of the pair of electrodes or electrode groups formed on the lower surface of the capacitor; A plurality of lower surface connection pads, each of which is electrically connected to a group, wherein each of the pair of electrodes or the electrode group is electrically connected to at least one of the plurality of lower surface connection pads; It is preferable to provide a core substrate with a built-in capacitor including: a capacitor built and fixed in the capacitor built-in concave portion of the main body, the capacitors being respectively connected to the plurality of bottom through-hole conductors corresponding to the plurality of lower surface connection pads.

The capacitor built core substrate this, form a capacitor built recess in the core substrate main body has a built-in capacitor therein. Further, each of the pair of electrodes or the electrode group is configured to conduct with at least one of the plurality of upper surface connection pads. The same applies to the lower surface connection pads. Therefore, both poles of the capacitor can be taken out above and below the core substrate through the upper surface connection pads on the upper surface of the capacitor and the bottom through-hole conductors on the lower surface of the core substrate body.
Therefore, if this capacitor built-in core substrate is used, a wiring board having a built-in capacitor can be easily formed by using a known method of forming a resin insulating layer or a wiring layer. Further, when the wiring board is formed in this way, the capacitor can be arranged at a very short distance from another wiring board such as an IC chip or a mother board on which the wiring board is mounted, and can be connected to each other with a very short wiring. Therefore, the characteristics of the built-in capacitor can be sufficiently exhibited and noise can be reliably removed.

Further, as described above, in an ordinary IC chip, a large number of power terminals and a large number of ground terminals are formed. In contrast, in the capacitor built core capacitor substrate this, the lower surface condenser top and a capacitor, a plurality of top surface connection pads and the lower surface connecting pads. Therefore, if a large number of bottom through-hole conductors and top connection pads are formed corresponding to the power terminals and the ground terminals of the IC chip, and a large number of wiring layers are formed in parallel so as to connect these, respectively, these wiring layers have Inductance and resistance can be further reduced as a whole. Similarly, with respect to the wiring for connecting the lower surface connection pad and another wiring board in parallel, the inductance and resistance can be further reduced as a whole. That is, the length of the wiring formed above and below the capacitor built-in core substrate can be shortened and the number of wirings can be increased, so that the resistance and inductance can be reduced, and noise can be effectively and reliably removed by the capacitor. Further, since the capacitance of the built-in capacitor can be freely selected, a large-capacitance capacitor using high-dielectric-constant ceramic can be built-in, and the noise elimination ability can be further improved.

Moreover, since the capacitor is built into the core board, there is no need to attach a separate capacitor after forming the resin insulation layer and wiring layer, and the cost for mounting the chip capacitor is unnecessary, so the wiring board can be made inexpensive. Can be manufactured.
In addition, since the quality of the built-in capacitor can be determined through the upper surface connection pad or the bottom through-hole conductor, the core substrate having the built-in capacitor having a defect such as a short circuit can be removed before forming the resin insulating layer or the like. it can. For this reason, a resin insulating layer and a wiring layer, which require a lot of man-hours, are formed, and the risk of discarding a high-value-added wiring board can be reduced. be able to.

  Here, the capacitor built-in core substrate, on the upper surface of the capacitor, or on the upper surface of the core substrate body and the upper surface of the capacitor, provided with a filler resin layer, the filler resin layer on the upper surface of the capacitor, the upper surface of the core substrate body or The core substrate with a built-in capacitor may be characterized in that the filling resin layer on the upper surface of the core substrate body is substantially flush with the filling resin layer, and the plurality of upper surface connection pads are exposed substantially flush with each other.

  In this capacitor built-in core substrate, the filling resin layer on the upper surface of the capacitor and the upper surface of the core substrate main body or the filling resin layer on the upper surface of the core substrate main body are substantially flush with each other, and a plurality of upper surface connection pads are substantially flush. It is exposed to. For this reason, when forming a wiring board by laminating resin insulation layers and wiring layers on the top and bottom of this core board, it is caused by the difference in height of the concave part for capacitor built-in and the height difference between the top face of the core board body and the top face of the capacitor. Thus, it is possible to prevent a step from occurring in the resin insulating layer and the wiring layer formed thereon. Therefore, the resin insulating layer and the wiring layer can be easily formed, and no troubles such as disconnection or short circuit of the wiring layer occur. Further, the coplanarity of the IC connection terminals formed on the upper and lower surfaces of the wiring substrate and the connection terminals can be improved, and the connectivity with the IC chip and other wiring substrates can be improved.

Still further , the upper surface of the core substrate main body, the lower surface of the core substrate main body, the recessed bottom with a built-in capacitor that opens to the upper side of the core substrate main body, and the bottom of the concave portion penetrates from the bottom surface to the lower surface of the core substrate main body. a plurality of bottom through-hole conductors extending on the lower surface core substrate main body Te, when a core substrate body with a preferred.

In this core substrate main body, since a capacitor built recess, by incorporating a capacitor in the recess, it is possible to easily form the wiring board with a built-in capacitor. In addition, since the bottom of the concave portion for incorporating a capacitor has a plurality of bottom through-hole conductors, the electrodes of the capacitor can be drawn out to the lower surface side of the core substrate main body through the bottom through-hole conductors. It can be connected to the capacitor easily and from a short distance.

To yet another includes a capacitor top surface, a capacitor lower surface, and a pair of electrodes or electrode group are insulated from each other, are formed on the capacitor upper surface, and either the electrode or electrode group of said pair of electrodes or electrode groups A plurality of upper surface connection pads each conducting, each of the pair of electrodes or electrode groups being formed on a plurality of upper surface connection pads electrically conductive with at least one of the plurality of upper surface connection pads, and a lower surface of the capacitor; A plurality of lower surface connection pads each electrically connected to any one of the pair of electrodes or the electrode group, and at least one of the plurality of lower surface connection pads for the pair of electrodes or the electrode group. It is preferable that the capacitor is provided with a plurality of lower surface connection pads that are electrically connected to one.

This capacitor, a plurality of top surface connection pads to the capacitor upper surface, comprising a plurality of lower surface connection pads on the lower surface condenser, addition, at least one conducting of any plurality of top surface connection pads of the pair of electrodes or electrode groups In addition, both the pair of electrodes or the electrode group are electrically connected to at least one of the plurality of lower surface connection pads. Therefore, both poles of the capacitor can be taken out from the upper surface of the capacitor. Similarly, both poles of the capacitor can be taken out from the lower surface of the capacitor. Therefore, on both the upper surface and the lower surface of the capacitor, connection with connection surfaces of IC chips, wiring boards, and other electronic components on which pads and bumps are formed becomes possible.

  Further, both poles of the capacitor can be taken out from both the upper surface and the lower surface of the capacitor. For this reason, for example, by being interposed between the wiring board and the IC chip, the power supply wiring and the ground wiring, which supply power from the wiring board to the IC chip, serve as a part of the wiring for connecting the power wiring and the ground wiring, respectively. The power supply wiring and the ground wiring are connected by this capacitor, and the function of removing noise superimposed on these wirings can also be achieved.

Further, by incorporating and fixing in the concave portion for capacitor incorporation of the core substrate body having the concave portion for capacitor incorporation, a core substrate with a built-in capacitor is formed, and a resin insulating layer and a wiring layer are further formed. It can be.
The upper surface connection pads and the lower surface connection pads may be formed at positions and numbers corresponding to the terminals and wiring layers of the IC chip and the like to be connected. It is preferable to form a large number of upper surface connection pads and lower surface connection pads because resistance and inductance generated between the IC chip and the like can be suppressed as a whole.

  Further, in the above-mentioned capacitor, dielectric layers and electrode layers are alternately laminated substantially parallel to the capacitor upper surface and the capacitor lower surface, and the electrode layers are each formed by a via conductor penetrating the dielectric layer. The plurality of upper surface connection pads are electrically connected to each other and form a pair of electrodes that are insulated from each other. Formed, the top dielectric layer or the top dielectric layer and a via conductor penetrating the dielectric layer located thereunder, and are electrically connected to the electrode layer belonging to any one of the pair of electrode groups, The plurality of lower surface connection pads are formed on the lower surface of the capacitor of the bottom dielectric layer which is located at the bottom of the dielectric layer and which is the lower surface of the capacitor, and The capacitor may be formed in such a manner that it is electrically connected to the electrode layer belonging to any of the pair of electrode groups by a via conductor penetrating through the layer or the bottom dielectric layer and the dielectric layer located thereabove. .

This capacitor has a pair of electrode groups each electrode layer is conduction via conductors to each other, the plurality of upper surface connection pads and a plurality of lower surface connection pads, belonging to one of the electrode group by any of a via conductor electrode Conducted with the layer. For this reason, it is not necessary to separately provide a common electrode for connecting every other electrode layer on the side surface of the dielectric layer after laminating the dielectric layer and the electrode layer, as is generally used for a multilayer capacitor, and it is inexpensive. Can be formed.
In addition, since the upper surface connection pad and the lower surface connection pad are electrically connected to one of the electrode layers by the via conductor, each upper surface connection pad or the lower surface connection pad can be formed at an arbitrary position to be electrically connected to the electrode layer. That is, the degree of freedom in selecting the position of each pad can be increased.

  Further, in the above capacitor, the dielectric layer is made of a high dielectric ceramic, and the electrode layer, the via conductor, the upper connection pad, and the lower connection pad are made of metal, all of which are formed by simultaneous firing. It is good to make a capacitor characterized by the above.

The high-dielectric ceramic has a high relative dielectric constant εr of several tens of thousands, and a desired capacitance can be easily obtained according to the composition, and a capacitor having a small capacitance and a large capacitance can be formed. Thus, in this condenser, by using the dielectric layer made of a high dielectric constant ceramic, the capacitance of the capacitor can be made large enough. Further, since this capacitor is formed by simultaneous firing, it can be formed all at once by firing, so that an inexpensive capacitor can be obtained.

Furthermore, the other, a manufacturing method of the capacitor, the perforations forming a plurality of through-holes at predetermined positions of the high dielectric constant ceramic green sheet mainly composed of high dielectric constant ceramic, perforated plurality An unsintered via conductor filling step of filling a through hole with a metal paste to form a plurality of unsintered via conductors; and forming the unsintered via conductors on the upper surface of the high dielectric constant ceramic green sheet on which the unsintered via conductors are formed. An unsintered electrode layer applying step of applying a metal paste in a predetermined shape to be in contact with one of the sintered via conductors to form an unsintered electrode layer; The dielectric constant ceramic green sheets are laminated in a predetermined order, and the high dielectric constant ceramic green sheets in which the unfired electrode layer is not formed on the uppermost layer and the unfired via conductor is formed are laminated. A lamination bonding step of forming the crimp to laminate, preferably in the method of manufacturing the capacitor, characterized in that it comprises a firing step of firing the laminate.

In the manufacturing method of this capacitor, and perforation of the high dielectric constant ceramic green sheet and filled with a metal paste to form an unfired via conductors, to form a green electrode layer by applying a metal paste to a predetermined shape, then Then, high-permittivity ceramic green sheets are laminated and fired to form the capacitor. This eliminates the need to form a common electrode on the side surface unlike a conventional multilayer capacitor, and can be formed at low cost.

Still other, of the bottom core substrate body having a core substrate main body underside core substrate main body top and bottom for bottom in the recess formation area, the core substrate main body upper surface and the bottom core substrate main body bottom surface for the bottom A bottom through-hole conductor forming step of forming a plurality of bottom through-hole conductors penetrating therethrough, having a wall core substrate main body upper surface and a wall core substrate main body lower surface; The lower surface of the wall core substrate main body of the wall core substrate main body having a through hole for a recess penetrating between the lower surface of the core substrate main body and the upper surface of the bottom core substrate main body of the bottom core substrate main body And a bonding step of exposing and bonding the plurality of bottom through-hole conductors in the through-holes for concave portions, and bonding the conductors.

In the manufacturing method of this core substrate main body, a bottom through-hole conductors formed in the core substrate main body bottom, then bond the core substrate main body core substrate main body and the bottom wall portion having a recess for the through-hole core The substrate body is manufactured. As described above, the core substrate body for the bottom portion and the core substrate body for the wall portion are manufactured separately, and then the both are bonded to each other, whereby the core substrate body having the concave portion with the bottom can be easily formed. Further, the bottom through-hole conductor located at the bottom of the concave portion can be easily manufactured by a known technique.

To yet another, the core substrate main body top surface, a core substrate main body bottom surface, the core substrate main body upper surface bottomed capacitor built recess of opening to and through the bottom of the recess from the bottom surface to the core substrate main body lower surface A capacitor upper surface, a capacitor lower surface, a pair of electrodes or electrode groups insulated from each other, and a capacitor upper surface of the core substrate main body including a plurality of bottom through-hole conductors extending to the lower surface of the core substrate main body; A plurality of upper surface connection pads, each of which is electrically connected to any one of the pair of electrodes or electrode groups, and each of the pair of electrodes or electrode groups is the plurality of upper surface connection pads. A plurality of upper surface connection pads electrically connected to at least one of the above, and the pair of electrodes or electrode groups formed on the lower surface of the capacitor. A plurality of lower surface connection pads each electrically connected to any one of the electrodes or the electrode group, wherein a plurality of lower surface connections each of which is electrically connected to at least one of the plurality of lower surface connection pads. Pad, a capacitor connection step of connecting the plurality of lower surface connection pads and the corresponding plurality of bottom through-hole conductors corresponding thereto, and injecting a filling resin into the capacitor built-in recess. Curing the filling resin, fixing the capacitor in the capacitor built-in recess with the filling resin, and a filling resin layer on the upper surface of the core substrate main body or the upper surface of the core substrate main body and the lower surface of the core substrate main body. A core through-hole forming step of forming a core through-hole conductor penetrating between the capacitors. Preferably in the method of manufacturing.

In this capacitor built core substrate fabrication method, the capacitor connected to the recess capacitor built, fixed by filling the filling resin in the concave portion for a capacitor built. Therefore, problems such as breakage of the connection between the lower surface connection pad of the capacitor and the bottom through-hole conductor due to vibration are suppressed, and the reliability of the core substrate with a built-in capacitor can be improved.

  Further, in the method of manufacturing a core substrate with a built-in capacitor, in the capacitor fixing step, in addition to the inside of the concave portion with a built-in capacitor, among the upper surface of the capacitor and the upper surface of the core substrate body, at least the upper surface of the capacitor is coated with a filling resin. Capacitor fixing to be cured-Filling resin application curing step, prior to the core through hole forming step, on the upper surface of the capacitor, or on the upper surface of the capacitor and the upper surface of the core substrate body, polishing the filling resin The plurality of upper surface connection pads are exposed substantially flush with each other, and the filling resin layer on the upper surface of the capacitor and the upper surface of the core substrate main body or the filling resin layer on the upper surface of the capacitor and the filling on the upper surface of the core substrate main body are filled. A built-in capacitor characterized by having a polishing and leveling step of leveling the resin layer to a substantially flat surface. May the method of manufacturing A substrate.

In this capacitor built core substrate fabrication method, and a capacitor in the recess capacitor built, in addition to further secure with the filling resin to expose the plurality of top connection pads substantially flush, moreover, the filling of the capacitor top Forming a core through hole after aligning the resin layer and the top surface of the core substrate main body, or the filling resin layer on the top surface of the capacitor and the filling resin layer on the top surface of the core substrate main body to a substantially flat surface. . Therefore, when forming one or a plurality of resin insulating layers or wiring layers above the upper surface of the core substrate main body and the upper surface of the capacitor, no step is generated between the upper surface of the core substrate main body and the upper surface of the capacitor. The resin insulating layer, the wiring layer, and the like can be easily formed, or the occurrence of disconnection or short circuit of each wiring layer can be suppressed. Further, the coplanarity of the IC connection terminals and the connection terminals can be reduced, and the connectivity with the IC chip and other wiring boards can be improved.

(Embodiment 1)
Embodiments of a wiring board and the like of the present invention will be described with reference to the drawings. A wiring board 100 having a built-in capacitor of the present invention shown in FIG. 1 has a substantially square plate shape, and a flip chip which is an IC connection terminal for connecting to an IC chip 1 shown by a broken line on its upper surface (upper surface of the wiring substrate) 100A. A large number of pads 101 are formed, and on each flip chip pad 101, a substantially hemispherical flip chip bump 102 made of high-temperature solder is formed. On the other hand, on the lower surface 100B of the wiring board, a large number of LGA pads 103, which are connection terminals for connecting to another wiring substrate such as a motherboard, are formed. Further, the wiring board 100 has a core substrate body 10 having a capacitor 20 built therein, resin insulating layers 41, 42, 43, 51, 52 , 53 laminated above and below these, and penetrating through the resin insulating layers between these layers. Wiring layers 60, 70, 80, 90 formed by the above method.

  The core substrate body 10 has a substantially square plate shape and is made of a glass-epoxy resin composite material, and has a substantially square shape in plan view, which is open toward the upper surface 10A of the core substrate body, and has a bottomed bottom. A recess (hereinafter simply referred to as a recess) 11 is provided. A plurality of bottom through-hole conductors 12 penetrating therethrough are formed between the bottom 11T of the recess 11 for incorporating a capacitor, that is, between the bottom surface 11B and the lower surface 10B of the core substrate body. Also, a capacitor 20 is built in the recess 11. A large number of core through-hole conductors 33 penetrating between the upper surface 10A of the core substrate main body and the lower surface 10B of the core substrate main body are formed on the periphery of the core substrate main body 10.

  As shown in FIGS. 2 (a) and 2 (b), the capacitor 20 alternates between a dielectric layer 24 mainly composed of a high dielectric ceramic, specifically, BaTiO3 and an electrode layer 25 mainly composed of Pd. This is a laminated ceramic capacitor having a substantially square plate shape laminated on the substrate. However, it is used for chip capacitors, etc., and takes out two electrodes (common electrode) that form both poles of the capacitor from the side surfaces of the laminated dielectric layer and electrode layer. Is different. That is, as shown in FIG. 2C, a plurality of upper surface connection pads 21 (21A, 21B, 21C in FIG. 2C) and lower surface connection pads 22 (FIG. 2C) are respectively provided on the upper surface 20A and the lower surface 20B of the capacitor. (C), 22A, 22B, and 22C) are provided, and these pads 21 and 22 can be connected to the upper side or the lower side in the figure within the capacitor upper surface 20A and the capacitor lower surface 20B.

As shown in FIG. 2 (c), the electrode layer 25 of the capacitor 20 is divided into a pair of electrode layer groups 25E and 25F that are electrically connected every other layer with via conductors 26E and 26F, respectively. Has been. Moreover, the electrode layers 25E and 25F are insulated from each other. Therefore, the two electrode groups 25 </ b> E and 25 </ b> F facing each other across the dielectric layer 24 form two electrodes of the capacitor 20. Also, part of the upper surface connecting pad 21 (in the figure right and left pads 21A, 21C) includes a top electrode layer 25ET belonging to the position to one of the electrode group 25E uppermost of the electrode layer 25, the dielectric The layers 24 are connected by a via conductor 27E penetrating the top dielectric layer 24T located at the uppermost position. Another part of the upper surface connecting pad 21 (in the drawing the center of the pad 21B) includes an electrode layer 25 belonging to the other electrode group 25F positioned lower than the top electrode layer 25ET, the via conductors 27F and 26F Connected. As described above, the large number of upper surface connection pads 21 are connected to any one of the pair of electrode groups 25E and 25F forming the two electrodes of the capacitor, and each of the pair of electrode groups 25E and 25F has a plurality of electrodes. It is connected to at least one of the upper connection pads 21. That is, one of the upper surface connection pads 21 (for example, 21A) among the many upper surface connection pads 21 is connected to one electrode group 25E. Further, a certain upper surface connection pad 21 (for example, 21B) is connected to the other electrode group 25F. For this reason, it is possible to conduct with any of the pair of electrode groups 25E and 25F from above the capacitor 20 through the upper surface connection pad 21.

Similarly, part of the lower surface connection pads 22 (in the figure right and left pads 22A, 22C) is located in a layer above the lowermost bottom electrode layer 25FD of the electrode layer 25, belonging to the one electrode group 25E The electrode layer 25 is connected to the electrode layer 25 by via conductors 28F and 26F penetrating the bottom dielectric layer 24D located at the lowest position among the dielectric layers 24. Another part of the lower surface connection pads 22 (in the drawing the center of the pad 22B) includes the bottom electrode layer 25FD belonging to the other electrode group 25F, are connected by the via conductors 28F. As described above, the large number of lower surface connection pads 22 are connected to one of the pair of electrode groups 25E and 25F forming the two electrodes of the capacitor, and both of the pair of electrode groups 25E and 25F are connected to the lower side. It is connected to at least one of the surface connection pads 22. In other words, the lower surface connection pads 22 with a number of lower surface connection pads 22 (e.g., 22A) is connected to one electrode group 25E. There is also a lower surface connecting pad 22 (e.g., 22B) is connected to the other electrode group 25F. For this reason, it is possible to conduct to either of the pair of electrode groups 25E and 25F from below the capacitor 20 through the lower surface connection pad 22.

  Further, as shown in FIG. 1, in capacitor 20, on lower surface 20 </ b> B of capacitor, lower surface connection pad 22 and corresponding bottom through-hole conductor 12 are electrically connected and connected by solder layer 23 made of Ag-Sn solder. ing. As a result, the capacitor 20 built in the core substrate body 10 can be connected to the upper connection pad 21 in the upper part of the drawing and to the bottom through-hole conductor 12 connected to the lower connection pad 22 in the lower part of the drawing. I have. Further, the capacitor 20 is fixed in the capacitor built-in recess 11 by a filling resin 32 made of epoxy resin, and is integrated with the core substrate main body 10.

  Further, above the upper surface 10A of the core substrate main body and the upper surface 20A of the capacitor, three upper resin insulating layers 41, 42 and 43 mainly composed of epoxy resin are provided. On the other hand, below the core substrate main body lower surface 10B, three lower resin insulating layers 51, 52, and 53 are also provided. Furthermore, wiring layers 45 and 46 made of Cu plating are formed between the upper resin insulating layers 41 and 42 and between the upper resin wiring layers 42 and 43, respectively, penetrating the upper resin insulating layers 41 and 42, respectively. . Similarly, wiring layers 55 and 56 made of Cu plating are formed between the lower resin insulating layers 51 and 52 and between the lower resin wiring layers 52 and 53, respectively, penetrating the lower resin insulating layers 51 and 52, respectively. ing.

Among these, wirings penetrating through the interlayers of the upper resin insulating layers 41, 42, 43 and through the upper resin insulating layers 41, 42, respectively, connecting the flip chip pads 101 and the corresponding upper surface connection pads 21 of the capacitor 20. The layers 45 and 46 constitute the upper capacitor connection wiring 60. Further, wiring layers 45, which penetrate through the interlayers of the upper resin insulating layers 41, 42, 43 and the upper resin insulating layers 41, 42, respectively, and connect the flip chip pads 101 and the corresponding core through-hole conductors 33, respectively. 46 constitutes the upper core connection wiring 80. On the other hand, the interlayer of the lower resin insulating layer 51, 52, 53, through respective及beauty upper resin insulating layers 51 and 52, the wiring layer 55 connecting the LGA pads 103 respectively corresponding thereto and the bottom through-hole conductors 12, 56 constitutes the lower capacitor connection wiring 70. Further, wiring layers 55 and 56 penetrating between the lower resin insulating layers 51, 52 and 53 and through the lower resin insulating layers 51 and 52 and connecting the core through-hole conductor 33 and the corresponding LGA pad 103 respectively. Constitutes the lower core connection wiring 90.

Thereby, the IC chip 1 connected to the flip chip bump 102 is connected to the pair of electrode groups 25E and 25F of the capacitor 20 through the flip chip pad 101, the upper capacitor connection wiring 60, and the upper surface connection pad 21, respectively. .
Further, the LGA pad 103 is connected to the pair of electrode groups 25E and 25F of the capacitor 20 via the lower capacitor connection wiring 70, the bottom through-hole conductor 12, and the lower surface connection pad 22, respectively.
Therefore, as shown in FIG. 2D, the upper capacitor connection wiring 60 and the lower capacitor connection wiring 70 that connect the flip chip pad 101 and the LGA pad 103 and are connected to one electrode group 25E, and the other, similarly. The capacitor 20 is inserted between the upper capacitor connection wiring 60 and the lower capacitor connection wiring 70 connected to the electrode group 25F.

For this reason, the power supply potential and the ground potential supplied from the motherboard or the like connected to the LGA pad 103 are from the LGA pad 103 to the lower capacitor connection wiring 70, the bottom through-hole conductor 12, the capacitor 20, the upper capacitor connection wiring 60, the flip chip It can be supplied to the IC chip 1 through the pad 101 and the flip chip bump 102. Further, noise superimposed on the power supply potential or the ground potential by the capacitor 20 can be removed.
Moreover, since the capacitor 20 is built in the core substrate main body 10, it can be arranged very close to the IC chip 1, so that the length of the upper capacitor connection wiring 60 can be reduced. Therefore, the noise removing ability of the capacitor 20 can be further enhanced. In particular, in the present embodiment, since the capacitor 20 is arranged immediately below the IC chip 1 and thus directly below the flip chip pad 101, the length of the upper capacitor connection wiring 60 can be extremely reduced. Therefore, since the distance between the IC chip 1 and the capacitor 20 can be made very short, noise is less likely to be superimposed between them, which is particularly effective for noise removal.

Also, a number of upper capacitor connection wirings 60 are formed, and a number of flip chip pads 101 and a number of upper surface connection pads 21 are connected in parallel. Therefore, by forming a large number of upper capacitor connecting wires 60, the resistance and inductance of the upper capacitor connecting wires 60 connecting the IC chip 1 (flip chip pad 101) and the capacitor 20 are reduced as a whole. From this point, it is also advantageous for noise removal. Similarly, a large number of lower capacitor connection wirings 70 are formed, and a large number of LGA pads 103 and a large number of bottom through-hole conductors 12 are connected in parallel. Therefore, by forming a large number of lower capacitor connecting wires 70, the resistance and inductance of the lower capacitor connecting wire 70 connecting the LGA pad 103 and the capacitor 20 and the bottom through-hole conductor 12 are reduced as a whole. From this point, it is also advantageous for noise removal.

On the other hand, the wiring connecting the IC chip 1 and the motherboard without connecting to the capacitor 20 such as a signal line is connected to the core through-hole conductor 33 from the flip chip pad 101 through the upper core connection wiring 80, and the core substrate body 10 is connected. It penetrates and connects from the lower core connection wiring 90 to the LGA pad 103. This structure is the same as a normal build-up wiring board using a core board on which a through-hole conductor is formed.
As described above, in the wiring board 100 of the present embodiment, the capacitor 20 is built in very close to the IC chip 1 to effectively remove noise, and the signal lines and the like have the same structure as the conventional one. it can.

  Next, a method of manufacturing the wiring board 100 will be described, including a method of manufacturing the capacitor 20 and the core substrate body 10 which are individual members. First, a method for manufacturing the capacitor 20 will be described with reference to FIG. First, as shown in FIG. 3A, a number of high dielectric ceramic green sheets (hereinafter, simply referred to as sheets) 124 mainly containing BaTiO3 powder are manufactured by a known green sheet manufacturing technique. Next, as shown in FIG. 3B, a via hole 124H penetrating between the front and back surfaces 124A and 124B is formed at a predetermined position of the sheet 124 by punching.

  Further, as shown in FIG. 3C, Pd paste is filled in the via holes 124H of each sheet 124 to form unfired via conductors 126, 127, and 128. Further, the upper surface 124A side of each sheet 124 Next, unfired electrode layers 125E and 125F of a predetermined shape made of Ag-Pd paste are formed. Of these, one unfired electrode layer 125E is connected to the left and right two of the three unfired via conductors 126 and 127 formed in FIG. 3C, and is connected to the center unfired via conductors 126 and 127. It is formed in a pattern that does not. On the other hand, the other unfired electrode layer 125F is connected to the center unfired via conductors 126 and 127 of the three unfired via conductors 126 and 127, and not to the left and right ones. Is formed.

Note that the vias 126 and 127 that are not connected to the unfired via pads 125E or 125F are placed above the unfired via conductors 126 and 127 in order to ensure that the via conductors contact and conduct with each other in the vertical direction during lamination described later. It is preferable to form the cover pad 129 simultaneously with the fired electrode layers 125E and 125F.
Further, neither the unfired electrode layers 125E and 125F are formed on the unfired dielectric layer 124D which is laminated on the uppermost layer at the time of lamination described below, and only the cover pad 122 is provided above each unfired via conductor 128. To form.

  Next, as shown in FIG. 3D, the sheet 124 on which the unsintered electrode layer 125E is stacked and the sheet 124 on which the unfired electrode layer 125F is stacked are alternately stacked. Then, at the top, a sheet 124D on which only the cover pad 122 is formed without forming any of the unfired electrode layers 125E and 125F is stacked, and these are pressed to form the stacked body 120. As a result, the unfired dielectric layers 124 and the unfired electrode layers 125E and 125F are alternately stacked, and the unfired electrode layers 125E and 125F are arranged every other layer. The unfired electrode layers 125E and 125E are connected to each other via unfired via conductors 126 and 127, respectively. Similarly, the unfired electrode layers 125F and 125F are connected to each other via the unfired via conductors 126 and 127, respectively. Connected. In addition, the group of unfired electrode layers 125E and the group of 125F are not in contact with each other, and are insulated from each other.

  Thereafter, the laminated body 120 is turned upside down to form a cover pad on the upper surface of the laminated body 120 where the unfired via conductor 127 is exposed, and then the laminated body 120 is fired (simultaneous firing). The capacitor 20 shown is formed. Since the capacitor 20 is formed in this manner, for example, it is not necessary to form a common electrode for connecting to the electrode layer 25E or 25F on the side surface of the dielectric layer 24 after firing, and the capacitor is used immediately after firing. be able to. The via conductors 26, 27, and 28 (unfired via conductors 126, 127, and 128) are formed of the dielectric layer 24 in consideration of the positions of the upper and lower via conductors, the distance between adjacent via conductors 24, and the like. It can be formed at any position in the plane.

  Therefore, the ease of routing the upper capacitor connection wiring 60 and the lower capacitor connection wiring 70, the number of flip chip pads 101 connected to the upper capacitor connection wiring 60, the number of LGA pads 103 connected to the lower capacitor connection wiring 70, etc. Accordingly, the positions and numbers of the upper surface connection pads 21 and the lower surface connection pads 22 can be arbitrarily selected and formed. Furthermore, even when the capacitor 20 is not built in the wiring board 100, the positions and numbers of the upper surface connection pads 21 and the lower surface connection pads 22 are arbitrarily selected according to the terminal arrangement of electronic components such as IC chips to be vertically connected. Can be formed. The upper surface connection pad 21 or the lower surface connection pad 22 made of Pd may be subjected to Ni-Au plating, Cu plating, or the like in consideration of solderability and connectivity with the wiring layer 45 made of Cu. it can. Further, a solder resist layer made of ceramic, resin, or the like may be formed around the upper surface connection pad 21 and / or the lower surface connection pad 22 by a known method.

  The completed capacitor 20 has the presence or absence of a short circuit, the capacitance value, the insulation resistance value between the electrode groups 25E and 25F, the conduction between the upper surface connection pads 21 and the lower surface connection pads 22, and the electrode groups 25E and 25F. Various checks such as insulation check are performed, and the defective capacitor 20 is discarded. This can reduce the risk of using a defective capacitor 20 in a process described below.

  Next, the core substrate body 10 and a method of manufacturing the same will be described. First, the core substrate body 10 is brought into the state shown in FIG. That is, the core substrate main body 10 shown in FIG. 4 has a core substrate main body upper surface 10A and a core substrate main body lower surface 10B, and a bottom core substrate main body 13 made of a glass-epoxy resin composite material. A wall core substrate body 16 made of a material is adhered to an adhesive layer 17 and formed. Further, a bottomed concave portion 11 penetrating the core substrate body 16 for a wall is opened in the upper surface 10A of the core substrate body, and a bottom surface 11B of the concave portion 11 and a lower surface 10B of the core substrate main body are formed in the bottom portion 11T. A bottom through-hole conductor 12 made of Cu plating and penetrating through the gap is formed at a position corresponding to the lower surface connection pad 22 of the capacitor 20.

  The core substrate main body 10 does not have a core through-hole conductor 33 penetrating between the core substrate main body upper surface 10A and the core substrate main body lower surface 10B. This is because the core through-hole conductor 33 is formed after the above-described capacitor 20 is built in the concave portion 11 of the core substrate body 10.

  Further, a connection wiring 15 extending from the bottom through-hole conductor 12 is also formed on the lower surface 10B of the core substrate main body. The bottom through-hole conductor 12 has a shape in which a filling resin 14 containing Cu powder is filled inside a cylindrical through-hole conductor made of Cu plating, and the upper and lower portions thereof are also closed by Cu plating. Therefore, as shown in FIG. 1, the bottom through-hole conductor 12 is soldered by directly welding solder (eg, solder 23), or by plating or the like directly above or below the wiring layer (eg, wiring layer 55, etc.). ) Can be formed.

  As described above, when the inside of the bottom through-hole conductor 12 is filled with a conductive resin, an insulating resin, or the like, and is further plated in a lid shape, the interval between the adjacent bottom through-hole conductors 12 can be reduced. This is suitable for high-density mounting, which is convenient when it is desired to form the bottom through-hole conductors 12 at narrow intervals or when it is desired to form more lower surface connection pads 22 and lower capacitor connection wires 70. On the other hand, if there is a sufficient space between the bottom through-hole conductors 12, a pad extending from the bottom through-hole conductor 12 is formed on the bottom surface 11 </ b> B of the recess 11, and this pad is connected to the lower surface connection pad 22. It can also be done. Further, a connection wiring extending from the bottom through-hole conductor 12 may be formed on the lower surface 10B of the core substrate body, and the connection wiring may be connected to the lower capacitor connection wiring 60 (specifically, the wiring layer 55). .

The core substrate body 10 is manufactured as follows. That is, first, as shown in FIG. 5 (a), the glass - the upper and lower surfaces on copper foils 13AC epoxy resin composite material bottom core substrate main body 13, providing a double-sided copper-clad board 13P having a 13BC. Next, as shown by a broken line in FIG. 5B, a through-hole 13H that penetrates the double-sided copper-clad substrate 13P in the thickness direction is drilled in the recess forming region 13RA where the recess 11 (see FIG. 4) is formed. Form. When it is desired to reduce the interval or diameter of the through-holes 13H, it is preferable to pierce the holes with a laser (CO2, YAG, etc.).

  Thereafter, the through-hole conductor 12 is formed in the through-hole 13H by a known through-hole conductor forming method (see FIG. 5C). For example, specifically, electroless Cu plating and electrolytic Cu plating are performed to form a cylindrical Cu plating layer in the through-hole 13H. After that, the inside of the cylindrical Cu plating in the through-hole is filled with a filling resin 14 containing Cu powder and cured. Thereafter, the upper surface of the copper foil 13AC and the lower surface of the 13BC are polished and leveled, and then the upper and lower surfaces are subjected to electrolytic Cu plating, and the upper and lower surfaces of the filling resin 14 are covered with electrolytic plating layers. Thereafter, a resist layer is formed on the upper and lower surfaces, exposed and developed to open an unnecessary portion, and an unnecessary copper plating layer and copper foil are removed by etching, so that a bottom portion made of Cu is formed in the through-hole 13H and its periphery. The through-hole conductor 12 and the connection wiring 15 extending therefrom are formed.

On the other hand, as shown in FIG. 5 (d), similarly Glass - an epoxy resin composite material is prepared the bottom core substrate main body core thicker wall thicknesses than 13 substrate main body 16. In the core substrate body 16 for the wall portion, a through hole 16H for a concave portion is formed in advance at a position corresponding to the concave portion 11 by punching.

Then, as shown in FIG. 5 (e), a core substrate main body top surface 13A for the bottom, and a core substrate main body lower surface 16B wall portion, made from a semi-cured epoxy resin, be adapted to the recess for the through-hole 16H in substantially It is sandwiched, heated, and pressure-bonded via an adhesive sheet 17R formed into a square shape. Thereby, both 13 and 16 are adhered via adhesive layer 17, and core substrate main body 10 shown in FIG. 4 can be produced.

  In order to form the core substrate main body 10 having the concave portion 11 as in the present embodiment, the bottom core substrate main body 13 configuring the bottom of the concave portion 11 in advance and the wall core substrate configuring the wall portion of the concave portion 11 are formed. If it is manufactured separately from the main body 16 and then bonded together, the bottomed concave portion 11 can be formed easily and accurately. Further, the bottom through-hole conductor 12 at the bottom can be easily formed by using a known method. Therefore, the core substrate body 10 can be formed at low cost.

  Next, a process of forming the core through-hole conductor 33 by incorporating the capacitor 20 in the core substrate body 10 will be described. First, as shown in FIG. 6A, the above-described capacitor 20 is disposed in the concave portion 11 of the core substrate main body 10 with the capacitor lower surface 20 </ b> B down, and the bottom through-hole conductor 12 corresponding to the lower surface connection pad 22 is formed. Is connected by soldering 23 made of Ag-Sn. Specifically, a solder paste is printed on the lower surface connection pads 22 in advance, and after overlapping with the bottom through-hole conductor 12, the solder paste is melted by passing through a reflow furnace and soldered.

  After the flux in the concave portion 11 is removed by washing, as shown in FIG. 6B, a filling resin 32 mainly composed of epoxy resin is placed on the upper surface 10A of the core substrate main body and the upper surface 20A of the capacitor in addition to the concave portion 11. Inject, apply and cure. Thus, the capacitor 20 is connected to the bottom through-hole conductor 12 and is fixed in the concave portion 11 with the filling resin 32 (32A), is built in the core substrate main body 10, and is exposed to heat, vibration, or the like. Breakage between the connection pad 22 and the bottom through-hole conductor 12 is prevented.

  Further, as shown in FIG. 6 (c), the filling resin layers 32B and 32C on the upper surface 10A of the core substrate main body and the upper surface 20A of the capacitor are polished to flat surfaces to expose the upper surface connection pads 21. 21 and the filled resin layers 32B and 32C left on the capacitor upper surface 20A and the core substrate main body upper surface 10A are substantially flush with each other. In the core substrate with a built-in capacitor manufactured in this way, the concave portion 11 is formed in the core substrate main body 10, and the generation of the step due to the incorporation of the capacitor 20 therein is absorbed, and the upper resin insulating layer 41 to be formed later is absorbed. And the wiring layer 45 and the like are not distorted due to the step, and problems such as disconnection and short circuit do not occur. Further, since there is no influence of the step on the flip chip pad 101 (or the flip chip bump 102), the coplanarity of the flip chip pad 101 and the like can be improved.

  Further, as shown in FIG. 7, on the periphery of the concave portion 11 of the core substrate body 10, between the upper surface 10A of the core substrate body and the lower surface 10B of the core substrate body, and further, the upper surface 32CU of the filling resin layer 32C and the core substrate body. A core through hole 30H penetrating between the lower surface 10B is formed by a drill. When it is desired to reduce the hole diameter or the interval, it is preferable to use a laser (CO2, YAG, etc.) to make the holes.

  Next, a core through-hole conductor 33 made of Cu is formed in the core through-hole hole 30H and the periphery thereof by a known through-hole conductor forming technique. Note that connection wirings 34 and 35 extending from the core through-hole conductor 33 and connecting to the wiring layers 45 and 55 are also formed on the upper surface 32CU of the filling resin layer and the lower surface 10B of the core substrate main body. Further, the upper surface connection pads 21 flush with the filling resin layer 32B are also increased in thickness by Cu plating so as to protrude above the filling resin layer 32B. In this way, a core substrate 30 with a built-in capacitor (hereinafter, simply referred to as a core substrate) is prepared.

  The core board 30 has a capacitor 20 built in the recess 11 in addition to the core board body 10. However, the core substrate upper surface 30A (filled resin layer upper surface 32CU) and the core substrate 30B (core substrate main body lower surface 10B) have a core through-hole conductor 33 penetrating between them at a predetermined position, or the upper surface connection terminal 21 or the bottom portion. The through-hole conductor 12, the connection wirings 15, 34 and 35 are formed, and the upper surface 30A of the core substrate (the upper surface 32CU of the filling resin layer) is flattened. Therefore, it can be used in the same manner as a core board used for a normal wiring board without a built-in capacitor.

  A specific manufacturing method of the core through-hole conductor 33 is, for example, as follows. That is, first, electroless Cu plating is applied to the entire surface of the core substrate main body 10, and an electroless Cu plating layer is formed in the through-hole 30H, the filling resin layer upper surface 32CU, and the core substrate main body lower surface 10B. Thereafter, a dry film is adhered on the upper surface 32CU of the filling resin layer 32C and the lower surface 10B of the core substrate main body, and is exposed and developed to open an electroplating formed portion such as a periphery of a core through-hole. Further, after passing an electric current using the electroless Cu plating layer as a common electrode to perform electrolytic Cu plating and removing the dry film, the unnecessary electroless Cu plating layer is removed by soft etching to remove the core through-hole conductor 33 and the connection wiring. 34, 35, etc. are formed. The upper surface connection pad 21 is also subjected to electroless Cu plating and electrolytic Cu plating. On the other hand, the bottom through-hole conductor 12 and the connection wiring 15 exposed on the lower surface 10B of the core substrate main body are pasted with a protective film so as not to be plated. However, in the present embodiment, since the capacitor 20 is built in the concave portion 11 before the core through-hole hole 30H is formed, the exposed bottom through-hole conductor 12 in the concave portion 11 is not plated or etched. In addition, there is no need to form a protective film or the like. Alternatively, the bottom through-hole conductor and the connection wiring 15 are also subjected to electroless Cu plating without using the protective film. Thereafter, the bottom through-hole conductor 12 and the connection wiring are covered with a dry film to prevent electrolytic plating from being formed thereon. After the electrolytic plating, the dry film may be peeled off, and the formed electroless Cu plating layer may be removed by soft etching. In this case, the step of attaching the protective film becomes unnecessary.

  In addition, in the present embodiment, the core through-hole conductor 33 is formed in a substantially cylindrical shape formed on the inner periphery and the periphery of the core through-hole hole 30H. A resin may be filled, and the upper and lower portions may be closed with a plating layer. With this configuration, the wiring layers 45 and 55 can be directly connected to the core through-hole conductors 33 without passing through the connection wirings 34 and 35. Therefore, the intervals between the core through-hole conductors 33 can be formed at a high density. Can be.

  As will be described later, before forming a resin insulating layer or a wiring layer on the core substrate 30 having the built-in capacitor 20, it is preferable to perform a characteristic test of the built-in capacitor 20. That is, in the state where the capacitor 20 is built in the core substrate 30, the presence or absence of a short circuit, the capacitance value, the insulation resistance value between the pair of electrode groups 25E and 25F, the respective upper surface connection pads 21 and the respective lower surface through hole conductors are provided. Various inspections such as a check of continuity or insulation between the electrode substrate 12 and each of the electrode groups 25E and 25F are performed, and the core substrate 30 containing the defective capacitor 20 is discarded. As a result, after forming a resin insulating layer or a wiring layer which requires a lot of man-hours as will be described later, it becomes clear that there is a defect in the capacitor 20, and there is a danger that the entire high value-added wiring board 100 must be discarded. Sex can be reduced.

  After that, using the core substrate 30, a resin insulating layer or a wiring layer is formed using a known resin insulating layer forming technique or a known wiring layer forming technique, and the wiring board 100 may be formed. In the present embodiment, the following processing is performed before forming the resin insulating layer. That is, as shown in FIG. 8A, in addition to the inside of the core through-hole conductor 33, above the filling resin layers 32B and 32C, above the upper surface connection pads 21, the connection wirings 34, the core substrate body lower surface 10B and the bottom through hole. Flattening resins 36, 37 and 38 mainly composed of epoxy resin are filled and coated on the hole conductors 12 and the connection wirings 15 and 35 (downward in the figure) and are cured. Alternatively, after planarizing resin 36 is first filled in core through-hole conductor 33 and cured, planarizing resins 37 and 38 may be applied and cured.

  Further, as shown in FIG. 8B, the upper or lower surfaces of the flattening resins 37 and 38 are polished to be flat. At the same time, the upper surface connection pad 21, the core through-hole conductor 33 and the connection wiring 34 are exposed substantially flush with the flattening resin layer 37. Further, the bottom through-hole conductor 12, the connection wirings 15, 35, and the core through-hole conductor 33 are exposed substantially flush with the flattening resin layer 38. As a result, the upper surface connection pad 21, the core through-hole conductor 33, the connection wirings 15, 34, 35, the bottom through-hole conductor 12, and the like are formed so as to protrude from the core substrate upper surface 30A or the core substrate lower surface 30B. The influence on the resin insulating layers 41 and 51 and the wiring layers 45 and 55 formed above and below can be eliminated. Therefore, disconnection or short circuit of the wiring layer 45 or the like can be prevented, or coplanarity of the flip chip pad 101 or the like can be improved.

  Thereafter, a photosensitive film containing an epoxy resin as a main component is attached to the upper surface 37U of the flattening resin layer 37 and the lower surface 38D of the flattening resin layer 38. Further, exposure and development are performed to form via holes 41VH and 51VH at positions where the upper surface connection pads 21, the connection wirings 15, 34 and 35, the bottom through-hole conductors 12 and the like are exposed on the bottom surface, and the photosensitive film is cured. As shown in FIG. 9A, resin insulating layers 41 and 51 are formed, respectively. After the resin insulating layers 41 and 51 are formed of a non-photosensitive resin, the via holes 41VH and 51VH may be formed by using a laser (CO2, YAG, etc.).

  Furthermore, electroless Cu plating is applied, a dry film is attached and exposed and developed to open only an electrolytic plating layer forming portion, and an electrolytic Cu plating layer is formed in the opening using the electroless Cu plating layer as a common electrode. After the removal, the unnecessary electroless Cu plating layer is removed by soft etching. Accordingly, wiring layers 45 and 55 having via portions 45V and 55V respectively penetrating through the resin insulating layers 41 and 51 in the via holes 41VH and 51VH and connecting to the upper surface connection pads 21 and the like are formed insulated from each other. . The wiring layers 45 and 55 are disposed between the resin insulating layers 41 and 42 or the resin insulating layers 51 and 52 when the resin insulating layers 42 and 52 are further formed thereon.

  Thereafter, in the same manner, the resin insulating layers 42 and 52, the wiring layers 46 and 56, the flip chip pads 101, the resin insulating layers (solder resist layers) 43 and 53 are sequentially formed, and the flip exposed from the resin insulating layer 43 is formed. By applying a solder paste to the chip pad 101 and performing reflow, a flip chip bump 102 made of solder is formed. Thus, the wiring board 100 shown in FIG. 1 is completed. Note that a Ni-Au plating layer may be formed on the surface of the LGA pad 103 to prevent oxidation.

  In the present embodiment, after the capacitor 20 is built in the concave portion 11 of the core substrate body 10 and fixed with the filling resin 32, the upper surfaces of the filling resin layers 32B and 32C are polished and leveled. Further, even after the core through-hole conductor 33 and the like were formed, the upper surfaces of the flattening resin layers 37 and 38 were polished and leveled. For this reason, the step caused by incorporating the capacitor 20 in the recess 11 is eliminated, and the step caused by the protrusion of the core through-hole conductor 33 and the upper surface connection pad 21 is also eliminated. And the coplanarity of the flip chip pads 101 and the flip chip bumps 102 can be improved.

  In the present embodiment, as described above, the resin insulating layers 41, 42, 43, 51, 52, and 53 are formed by photolithography using a photosensitive resin film, and the wiring layers 45 and 55 are formed by so-called Formed by the semi-additive method. However, the resin insulating layer 41 and the like may be formed by other methods such as applying a resin paste, and the wiring layer 45 and the like may be formed by a subtractive method, a full additive method, and other methods. That is, the resin insulating layer 41 and the like, the wiring layer 45 and the like may be formed by any known method.

(Embodiment 2)
Next, a wiring board 200 according to a second embodiment will be described with reference to FIG. In the wiring board 100 of the first embodiment, the concave portion 11 of the core substrate main body 10 containing the capacitor 20 opens upward in the figure. On the other hand, the wiring board 200 of the present embodiment is different in that the recess 211 of the core board main body 210 containing the capacitor 220 is open downward in the figure, and the other parts are the same. The description will focus on the parts, and the description of similar parts will be omitted or simplified.

In the wiring substrate 200, a large number of flip chip pads 101 and flip chip bumps 102 for connection to the IC chip 1 indicated by broken lines are formed on the upper surface 200A of the wiring substrate. On the other hand, a large number of LGA pads 103 are formed on the lower surface 200B of the wiring board. Further, the wiring board 200 has a core substrate body 210 having a built-in capacitor 220, resin insulating layers 41, 42, 43, 51, 52 , 53 laminated above and below, and penetrating between the resin insulating layers and between these layers. Wiring layers 60, 70, 80, 90 formed by the above method.

  Among them, the core substrate main body 210 has a substantially square plate shape in a plan view, is made of a glass-epoxy resin composite material, and has a bottomed concave portion 211 which is opened at the substantially center of the core substrate main body lower surface 210B. A plurality of bottom through-hole conductors 212 penetrating therethrough are formed between the bottom portion 211T located above the concave portion 211 in the drawing, that is, between the bottom surface 211B and the upper surface 10A of the core substrate main body. In addition, a capacitor 220 is built in the recess 211. A large number of core through-hole conductors 233 penetrating between the upper surface 210A of the core substrate main body and the lower surface 210B of the core substrate main body are formed on the periphery of the core substrate main body 210.

The capacitor 220 is a multilayer ceramic capacitor having the same material and structure as the capacitor 20 described in the first embodiment (see FIGS. 2A, 2B, and 2C). The capacitor upper surface 220A and the capacitor lower surface 220B are provided with a large number of upper surface connection pads 221 and lower surface connection pads 222, respectively. Can be connected to.
The upper surface connection pad 221 of the capacitor 220 and the corresponding bottom through-hole conductor 212 are electrically connected to each other by a solder layer 223 made of Ag-Sn solder. Thereby, the capacitor 220 built in the core substrate main body 210 can be connected to the bottom through-hole conductor 212 connected to the upper surface connection pad 221 in the upper part in the figure and to the lower surface connection pad 222 in the lower part in the figure. ing. Further, the capacitor 220 is fixed in the concave portion 211 by a filling resin 232 made of an epoxy resin, and is integrated with the core substrate main body 210.

  Further, similarly to the first embodiment, three upper resin insulating layers 41, 42, and 43 mainly composed of epoxy resin are provided above the upper surface 210A of the core substrate main body. On the other hand, the lower surface 210B of the core substrate main body and the lower surface 220B of the capacitor are also provided with three lower resin insulating layers 51, 52, and 53, respectively. Furthermore, wiring layers 45 and 46 made of Cu plating are formed between the upper resin insulating layers 41 and 42 and between the upper resin wiring layers 42 and 43, respectively, penetrating the upper resin insulating layers 41 and 42, respectively. . Similarly, wiring layers 55 and 56 made of Cu plating are formed between the lower resin insulating layers 51 and 52 and between the lower resin wiring layers 52 and 53, respectively, penetrating the lower resin insulating layers 51 and 52, respectively. ing.

  Among these, the wiring layers 45 and 46 connecting the flip chip pad 101 and the corresponding bottom through-hole conductor 212 respectively constitute the upper capacitor connection wiring 60, and the flip chip pad 101 and the corresponding core through-hole conductor The wiring layers 45 and 46 respectively connecting to the upper core connection wiring 33 constitute the upper core connection wiring 80. On the other hand, the wiring layers 55 and 56 connecting the lower surface connection pad 222 of the capacitor 20 and the corresponding LGA pad 103 respectively constitute the lower capacitor connection wiring 70, and the core through-hole conductor 33 and the corresponding LGA pad 103 And the wiring layers 55 and 56 respectively forming the lower core connection wiring 90.

Thus, the IC chip 1 connected to the flip chip bump 102 is connected to each of the pair of electrodes of the capacitor 220. Further, the LGA pad 103 is connected to a pair of electrode groups of the capacitor 220, respectively.
For this reason, the power supply potential and the ground potential supplied from the motherboard or the like connected to the LGA pad 103 are from the LGA pad 103 to the lower capacitor connection wiring 70, the capacitor 220, the bottom through-hole conductor 212, the upper capacitor connection wiring 60, the flip chip It can be supplied to the IC chip 1 through the pad 101 and the flip chip bump 102. Further, noise superimposed on the power supply potential or the ground potential by the capacitor 220 can be removed.

  Moreover, since the capacitor 220 is built in the core substrate main body 210, it can be arranged very close to the IC chip 1, so that the length of the upper capacitor connection wiring 60 can be reduced. Therefore, the noise removal capability of the capacitor 220 can be further improved. In particular, in the present embodiment, since the capacitor 220 is arranged directly below the IC chip 1 and thus directly below the flip chip pad 101, the length of the upper capacitor connection wiring 60 can be extremely reduced. Therefore, since the distance between the IC chip 1 and the capacitor 220 can be made extremely short, noise is less likely to be superimposed between them, which is particularly effective for noise removal.

  Also, a number of upper capacitor connection wirings 60 are formed in parallel. Similarly, a large number of lower capacitor connection wirings 70 are formed. For this reason, the resistance and inductance of the upper capacitor connection wiring 60, the lower capacitor connection wiring 70, and the bottom through-hole conductor 12 are reduced as a whole, which is also advantageous for noise removal.

On the other hand, the wiring connecting the IC chip 1 to the motherboard and the like without connecting to the capacitor 220 such as a signal line is connected to the core through-hole conductor 33 from the flip chip pad 101 through the upper core connection wiring 80, and the core substrate body 210 is connected. It penetrates and connects from the lower core connection wiring 90 to the LGA pad 103. This structure is the same as a normal build-up wiring board using a core board on which a through-hole conductor is formed.
As described above, also in the wiring board 200 of the present embodiment, the capacitor 220 is built in very close to the IC chip 1 to effectively remove noise, and the signal lines and the like have the same structure as the conventional one. it can.

Further, in the wiring board 200 of the present embodiment, since the concave portion 211 is opened downward and the bottom portion 211T is located upward in the drawing, the resin insulating layers 41, 42, 43 and the wiring layers 45, 46, and further, The flip chip pads 101 and the flip chip bumps 102 can be formed without being affected by the concave portions 211. Therefore, the coplanarity of the flip chip pad 101 and the like does not decrease due to the occurrence of a step due to the concave portion 211 and the capacitor 220, so that stable connectivity with the IC chip 1 can be obtained.
In this wiring board 200, a capacitor 220 and a core board main body 210 similar to the capacitor 20 and the wiring board main body 10 of the first embodiment are manufactured, and the capacitor 220 is built in the core board main body 210, and is turned upside down. Since it can be manufactured by forming the resin insulating layer 41 and the like and the wiring layer 45 and the like in the same manner as in the first embodiment, detailed description thereof will be omitted.

In the above, the present invention has been described in accordance with the embodiments. However, it is needless to say that the present invention is not limited to the above embodiments, and can be appropriately modified and applied without departing from the gist thereof.
For example, in the above embodiment, the core substrate main body 10 and, more, as the material of the bottom core substrate main body 1 3及 beauty wall core substrate main body 16, the glass - is used an epoxy resin composite material, the core substrate body May be selected in consideration of heat resistance, mechanical strength, flexibility, ease of processing, and the like. Therefore, for example, a glass fiber-resin composite material of a glass fiber such as a glass woven fabric or a glass non-woven fabric and a resin such as an epoxy resin, a polyimide resin, or a BT resin, or a composite material of an organic fiber and a resin such as a polyamide fiber, A resin-resin composite material obtained by impregnating a resin such as an epoxy resin with a fluorine-based resin having a three-dimensional network structure such as PTFE having pores can be used.

Further, as the resin insulating layer 41 and the like, an epoxy resin as a main component is used, but it may be appropriately selected in consideration of heat resistance, pattern moldability, and the like. For example, polyimide resin, BT resin, PPE resin, A resin-resin composite material obtained by impregnating a resin such as an epoxy resin with a fluorine-based resin having a three-dimensional network structure such as PTFE having continuous pores is exemplified.
Similarly, the wiring layer 45 and the like are formed by electroless Cu plating and electrolytic Cu plating, but may be formed by other materials, for example, Ni, Ni-Au, or the like. The wiring layer 45 and the like may be formed by a method such as applying a conductive resin.

  In the above embodiment, a large number of flip chip pads 101 and flip chip bumps 102 are provided on the upper surfaces 100A and 200A of the wiring board for connection with the IC chip 1. However, as the IC connection terminal, an appropriate one may be selected according to the terminal formed on the IC chip to be connected. In addition to the one having the flip chip bump formed thereon, the one having only the flip chip pad, or the one having the wire Examples include a bonding pad and a pad on which a TAB connection pad is formed.

In the above embodiment, one concave portion is provided at substantially the center of the core substrate body. However, it is not necessary to form the concave portion at substantially the center, and a plurality of concave portions may be provided as necessary to incorporate a capacitor. May be. Conversely, a plurality of capacitors may be built in one recess in order to cope with a plurality of power supply potentials.
Further, as the capacitor 20, a multilayer ceramic capacitor in which the dielectric layer 24 and the electrode layer 25 are stacked substantially parallel to the capacitor upper surface 20A and the capacitor lower surface 20B is shown. However, the built-in capacitor only needs to have the upper surface connection pad 21 and the lower surface connection pad 22 formed on the capacitor upper surface 20A and the capacitor lower surface 20B. For example, the dielectric layer and the electrode layer are substantially orthogonal to the capacitor upper surface. The lamination direction and the internal structure of the capacitor, such as lamination in the direction, can be appropriately changed. In the first embodiment, the via conductors 26, 27, and 28 formed in the capacitor are all formed at positions vertically overlapping other via conductors (FIG. 2C). It is not necessary to limit the position to other via conductors above or below, and the arrangement of the via conductors 26 and the like or the number thereof can be appropriately selected.

Further, in the above embodiment, a high dielectric ceramic mainly composed of BaTiO3 is used for the dielectric layer 24, but the material of the dielectric layer is not limited to this, and for example, PbTiO3, PbZrO3, TiO2, SrTiO3, CaTiO3. , MgTiO3, KNbO3, NaTiO3, KTaO3, RbTaO3, (Na1 / 2Bi1 / 2) TiO3, Pb (Mg1 / 2W1 / 2) O3, (K1 / 2Bi1 / 2) TiO3. What is necessary is just to select suitably according to a capacity | capacitance etc.
Although Pd is used for the electrode layer 25 and the via conductor 26, the material may be selected in consideration of the compatibility with the material of the dielectric layer and the like. For example, Pt, Ag, Ag-Pt, Ag- Pd, Cu, Au, Ni and the like can be mentioned.
Further, a capacitor is obtained by combining a dielectric layer mainly composed of a high dielectric ceramic or an electrode layer made of Ag-Pd, and a via layer or a wiring layer made of a resin layer, Cu plating, Ni plating or the like. Can also be used.

In the above embodiment, the lower surface connection pad 22 or the upper surface connection pad 221 and the bottom through-hole conductors 12 and 212 are connected by Ag-Sn solder. However, the ease of soldering, the soldering temperature, and the like are taken into consideration, and the solder material is appropriately determined. You just have to select For example, Pb-Sn high temperature solder, Au-Si, Sn-Ag, Sn-Cu, Sn-Bi, Sn-Zn, Sn-Au, Sn-Ag-Bi, Sn-Zn-Bi, Sn-Ag- Various solders such as Cu can be used. Further, for example, an anisotropic conductive resin sheet that conducts only in the vertical direction only at a portion sandwiched between the lower surface connection pad 22 and the bottom through-hole conductor 12 is used, and this is connected to the capacitor 20 (lower surface connection pad 22) and the bottom portion. The two may be connected by being interposed between the through-hole conductor 12 and the through-hole conductor 12.
Further, in the above embodiment, after the capacitor 20 is built in the recess 11, the filling resin 32 (32A) is filled in the recess 11, and the filling resin layer is also formed on the capacitor upper surface 20A and the core substrate main body upper surface 10A. 32B and 32C were formed (see FIG. 6). However, it is sufficient that the capacitor 20 can be fixed in the recess 11 by at least the filling resin 32 (32A). Therefore, the filling resin 32 may be injected only into the recess 11.

  Alternatively, it is also possible to form only the filling resin layer 32B in addition to the filling resin 32 (32A). That is, when the dimensions of the concave portion 11 and the capacitor 20 are adjusted, and the capacitor 20 is connected in the concave portion 11, the upper surface 20A of the capacitor is lower than the upper surface 10A of the core substrate main body, and the upper surface connection pad 21 is It should be higher than the upper surface 10A of the substrate main body. Next, in addition to injecting the filling resin 32 into the recess 11, a filling resin layer 32B is also formed on the capacitor upper surface 20A. Thereafter, the upper surface connection pads 21 may be exposed on the upper surface of the filling resin layer, and the upper surface may be flush with the upper surface 10A of the core substrate main body. Even in this case, the step caused by the incorporation of the concave portion 11 and the capacitor 20 can be eliminated, and furthermore, when the upper resin insulating layer 41 or the like or the wiring layer 45 or the like is formed as an upper layer, disconnection or short circuit of the wiring layer 45 or the like can be prevented. This can prevent the coplanarity of the flip chip pad 101 and the like from being lowered.

In the above-described embodiment, the core through-hole conductor 33 is formed in the core substrate body 10 after the capacitor 20 is built in. However, the core through hole conductor 31 that penetrates between the core substrate body upper surface 10A and the core substrate body lower surface 10B in advance is provided. A hole conductor may be formed before the capacitor 20 is built in the recess 11. That is, after bonding the bottom core substrate main body 13 and the wall portion for the core substrate main body 16 (see FIGS. 4 and 5), a through hole passing through between the core substrate main body top surface 10A and the core substrate main body lower surface 10B Then, a core through-hole conductor is formed by a known method. At this time, the bottom through-hole conductor 12 and the connection wiring 15 are protected by a protective film so as not to be plated or etched. Thereafter, the capacitor 20 is built in the recess 11 in the same manner as described above. By doing so, it is possible to avoid the danger that the capacitor 20 or the filling resin 32 may have a problem such as a crack due to vibration or impact generated when the core through hole 30H is formed after the capacitor 20 is built. it can.

  Further, in the above-described embodiment, after the core through-hole conductor 33 and the connection conductors 34 and 35 are formed, flattening resins 36, 37 and 38 are formed to flatten the upper and lower portions of the core substrate 30. However, the resin insulating layers 41 and 51 may be formed without using the flattening resin, that is, after filling the inside of the core through-hole conductor 33 with resin from the state shown in FIG. In this case, the wiring board can be formed at lower cost.

FIG. 3 is a cross-sectional view of the wiring board according to the first embodiment, in which a capacitor is built in a recess formed in the core substrate main body and opening upward in the drawing. (A) is a plan view, (b) is a perspective view, (c) is a cross-sectional explanatory view for describing an internal structure of the capacitor, and (d) is a capacitor and an LGA pad of the capacitor incorporated in the wiring board according to the first embodiment. FIG. 4 is a circuit diagram showing a relationship between the first embodiment and flip chip pads. FIG. 3 is an explanatory diagram illustrating a method for manufacturing the capacitor in FIG. 2. FIG. 3 is a partially enlarged cross-sectional view of a core substrate main body having a recess for incorporating a capacitor in the wiring board according to the first exemplary embodiment. FIG. 5 is an explanatory diagram illustrating a method for manufacturing the core substrate body of FIG. 4. FIG. 5 is an explanatory view of a method of manufacturing a core board with a built-in capacitor in which the capacitor of FIG. 2 is connected and built into the core board body of FIG. 4. It is a partial expanded sectional view of a core board with a built-in capacitor. FIG. 8 is an explanatory diagram illustrating a step of further flattening the upper and lower surfaces of the core substrate with a built-in capacitor of FIG. 7. FIG. 9 is an explanatory view showing a step of forming a resin insulating layer and each wiring layer on and under the planarized core substrate with built-in capacitor in FIG. 8. FIG. 13 is a cross-sectional view of a wiring board according to the second embodiment, in which a capacitor is built in a recess formed in the core substrate main body and opening downward in the figure. FIG. 9 is an explanatory diagram illustrating a state of a capacitor connection wiring in a conventional wiring board having a capacitor mounted on an upper surface or a lower surface.

Explanation of reference numerals

100, 200 (Built-in capacitor) Wiring substrate 100A, 200A Wiring substrate upper surface 100B, 200B Wiring substrate lower surface 101 Flip chip pad 102 Flip chip bump 103 LGA pad (connection terminal)
10, 210 Core substrate main body 10A, 210A Core substrate main body upper surface 10B, 210B Core substrate main body lower surface 11, 211 Capacitor built-in concave portion 11B, 211B Bottom of capacitor built-in concave portion 11T, 211T Bottom portion of capacitor built-in concave portion 12, 212 Bottom through Hole conductor 20, 220 Capacitor 20A, 220A Capacitor upper surface 20B, 220B Capacitor lower surface 21, 221 Upper surface connection pad 22, 222 Lower surface connection pad 23 Solder 24 Dielectric layer 25 Electrode layer 25E, 25F (One pair) electrode group 30 Core substrate 32 , 232 Filled resin 32B, 32C Filled resin layer 33, 233 Core through-hole conductors 41, 42, 43, 51, 52, 53 Resin insulating layers 45, 46, 55, 56 Wiring layer 60 Upper capacitor connecting wiring 70 Lower capacitor connecting wiring 80 above Lower core connection wiring 90 Lower core connection wiring

Claims (13)

A wiring board having a wiring board upper surface and a wiring board lower surface, a plurality of IC connection terminals for connecting to an IC chip on the wiring board upper surface, a plurality of connection terminals on the wiring board lower surface, and a built-in capacitor; So,
The upper surface of the core substrate body,
Under the core board body,
A bottomed recess for incorporating a capacitor, which is open on the upper side of the core substrate body,
A plurality of bottom through-hole conductors extending through the bottom of the recess from the bottom surface to the lower surface of the core substrate body and extending to the lower surface of the core substrate body;
And a plurality of core through-hole conductors formed to penetrate between the core substrate body upper surface and the core substrate body lower surface,
A core substrate body comprising:
Capacitor top,
Capacitor bottom,
A pair of electrodes or electrode groups insulated from each other,
A plurality of upper surface connection pads formed on the upper surface of the capacitor and electrically connected to any one of the electrodes or the electrode group of the pair of electrodes or the electrode group. A plurality of upper surface connection pads electrically connected to at least one of the upper surface connection pads;
And a plurality of lower surface connection pads formed on the lower surface of the capacitor and electrically connected to any one of the pair of electrodes or electrode groups, wherein each of the pair of electrodes or electrode groups is A plurality of lower surface connection pads electrically connected to at least one of the plurality of lower surface connection pads;
With
Built-in and fixed in the capacitor built-in recess of the core substrate body, the capacitors are respectively conductive to the plurality of bottom through-hole conductors corresponding to the plurality of lower surface connection pads,
One or more upper resin insulation layers laminated above the core substrate body upper surface and the capacitor upper surface,
One or a plurality of lower resin insulation layers laminated below the lower surface of the core substrate body, and a plurality of IC connection terminals on the upper surface of the wiring board corresponding to the plurality of IC connection terminals through the upper resin insulation layer or through the interlayer. A plurality of upper capacitor connection wirings respectively connecting the plurality of upper surface connection pads of the capacitor,
A plurality of lower capacitors each penetrating through the lower resin insulating layer or passing through the lower resin insulating layer and connecting a bottom through-hole conductor extending to the lower surface of the core substrate body and a corresponding plurality of connection terminals on the lower surface of the wiring substrate. Connection wiring,
A plurality of upper cores penetrating through the upper resin insulating layer or through the interlayer to connect the plurality of IC connection terminals on the upper surface of the wiring board and the corresponding plurality of core through-hole conductors on the upper surface of the core substrate body. Connection wiring,
A plurality of lower core connection wirings that respectively connect the core through-hole conductors on the lower surface of the core substrate body and the corresponding plurality of connection terminals on the lower surface of the wiring substrate through the lower resin insulating layer or through the interlayer; ,
A wiring board, comprising: A wiring board having an upper surface of the wiring substrate and a lower surface of the wiring substrate, a plurality of IC connection terminals for connecting an IC chip to the upper surface of the wiring substrate, and a plurality of connection terminals on the lower surface of the wiring substrate; So,
The upper surface of the core substrate body,
Under the core board body,
A bottomed recess for incorporating a capacitor, which is open on the lower side of the core substrate body,
A plurality of bottom through-hole conductors extending through the bottom of the recess from the bottom surface to the top surface of the core substrate body and extending to the top surface of the core substrate body;
And a core through-hole conductor formed so as to penetrate between the upper surface of the core substrate main body and the lower surface of the core substrate main body,
A core substrate body comprising:
Capacitor top,
Capacitor bottom,
A pair of electrodes or electrode groups insulated from each other,
A plurality of upper surface connection pads formed on the upper surface of the capacitor and electrically connected to any one of the electrodes or the electrode group of the pair of electrodes or the electrode group. A plurality of upper surface connection pads electrically connected to at least one of the upper surface connection pads;
And a plurality of lower surface connection pads formed on the lower surface of the capacitor and electrically connected to any one of the pair of electrodes or electrode groups, wherein each of the pair of electrodes or electrode groups is A plurality of lower surface connection pads electrically connected to at least one of the plurality of lower surface connection pads;
With
The capacitor is embedded and fixed in the capacitor built-in recess of the core substrate body, and the plurality of upper surface connection pads are respectively connected to the plurality of bottom through-hole conductors corresponding to the capacitors,
One or more upper resin insulation layers laminated above the upper surface of the core substrate body, one or more lower resin insulation layers laminated below the lower surface of the core substrate body and the lower surface of the capacitor,
A plurality of IC connection terminals on the upper surface of the wiring board and a plurality of corresponding bottom through-hole conductors extending to the upper surface of the core substrate body correspondingly through the upper resin insulating layer or through the interlayer. Upper capacitor connection wiring of
A plurality of lower capacitor connection wirings that respectively connect the lower surface connection pads of the capacitor and a plurality of connection terminals on the lower surface of the wiring board corresponding thereto through the lower resin insulation layer or through the interlayer;
A plurality of upper cores penetrating through the upper resin insulating layer or through the interlayer to connect the plurality of IC connection terminals on the upper surface of the wiring board and the corresponding plurality of core through-hole conductors on the upper surface of the core substrate body. Connection wiring,
A plurality of lower core connection wirings that respectively connect the core through hole conductors on the lower surface of the core substrate main body and the corresponding plurality of connection terminals on the lower surface of the wiring substrate through the lower resin insulating layer or through the interlayer;
A wiring board, comprising: The upper surface of the core substrate body,
Under the core board body,
A bottomed recess for incorporating a capacitor, which is open on the upper side of the core substrate body,
And, a plurality of bottom through-hole conductors extending from the bottom surface of the concave portion to the lower surface of the core substrate by penetrating from the bottom surface to the lower surface of the core substrate body,
A core substrate body comprising:
Capacitor top,
Capacitor bottom,
A pair of electrodes or electrode groups insulated from each other,
A plurality of upper surface connection pads formed on the upper surface of the capacitor and electrically connected to any one of the electrodes or the electrode group of the pair of electrodes or the electrode group. A plurality of upper surface connection pads electrically connected to at least one of the upper surface connection pads;
And a plurality of lower surface connection pads formed on the lower surface of the capacitor and electrically connected to any one of the pair of electrodes or electrode groups, wherein each of the pair of electrodes or electrode groups is A plurality of lower surface connection pads electrically connected to at least one of the plurality of lower surface connection pads;
With
A capacitor built in and fixed in the capacitor built-in recess of the core substrate body, each of which is electrically connected to the plurality of bottom through-hole conductors corresponding to the plurality of lower surface connection pads,
Core substrate with built-in capacitor. The core substrate with a built-in capacitor according to claim 3,
Provided with a filling resin layer on the capacitor upper surface, or on the core substrate body upper surface and the capacitor upper surface,
The filling resin layer on the upper surface of the capacitor and the filling resin layer on the upper surface of the core substrate body or the upper surface of the core substrate body are substantially flush with each other, and the plurality of upper surface connection pads are respectively exposed substantially flush. A core substrate with a built-in capacitor. An upper surface of the core substrate body,
A lower surface of the core substrate body,
A bottomed recess for incorporating a capacitor that opens on the upper side of the core substrate body,
A plurality of bottom through-hole conductors extending from the bottom surface of the concave portion to the lower surface of the core substrate by penetrating from the bottom surface to the lower surface of the core substrate body,
A core substrate body comprising: The top of the capacitor,
A bottom surface of the capacitor;
A pair of electrodes or electrode groups insulated from each other,
A plurality of upper surface connection pads formed on the upper surface of the capacitor and electrically connected to any one of the electrodes or the electrode group of the pair of electrodes or the electrode group. A plurality of upper surface connection pads electrically connected to at least one of the upper surface connection pads;
A plurality of lower surface connection pads formed on the lower surface of the capacitor and electrically connected to any one of the pair of electrodes or electrode groups, wherein each of the pair of electrodes or electrode groups is the plurality of electrodes. A plurality of lower surface connection pads electrically connected to at least one of the lower surface connection pads;
A capacitor comprising: The capacitor according to claim 6, wherein
Dielectric layers and electrode layers are alternately stacked substantially parallel to the capacitor upper surface and the capacitor lower surface,
The electrode layer is electrically connected to every other layer by via conductors penetrating the dielectric layer to form the pair of electrodes insulated from each other,
The plurality of upper surface connection pads,
A top dielectric layer located on the top of the dielectric layer and forming the upper surface of the capacitor is formed on the upper surface of the capacitor,
By the via conductor penetrating the top dielectric layer or the top dielectric layer and the dielectric layer located thereunder, it is electrically connected to the electrode layer belonging to any of the pair of electrode groups,
The plurality of lower surface connection pads,
A bottom dielectric layer located at the bottom of the dielectric layer and forming the lower surface of the capacitor is formed on the lower surface of the capacitor,
The bottom dielectric layer or the via conductor penetrating the bottom dielectric layer and the dielectric layer located above the bottom dielectric layer is electrically connected to the electrode layer belonging to any of the pair of electrode groups. Capacitors. The capacitor according to claim 7, wherein
The dielectric layer is made of a high dielectric ceramic,
The capacitor, wherein the electrode layer, the via conductor, the upper connection pad, and the lower connection pad are made of metal, and all of them are formed by simultaneous firing. It is a manufacturing method of the capacitor of Claim 8, Comprising:
A perforation step of forming a plurality of through holes at predetermined positions of a high dielectric constant ceramic green sheet containing a high dielectric constant ceramic as a main component,
An unfired via conductor filling step of filling a plurality of perforated through holes with a metal paste to form a plurality of unfired via conductors,
On the upper surface of the high dielectric constant ceramic green sheet on which the unfired via conductor is formed, a metal paste is applied in a predetermined shape to be in contact with any of the plurality of unfired via conductors to form an unfired electrode layer. Firing electrode layer application step,
A high dielectric constant ceramic green sheet having the unfired via conductor and the unfired electrode layer formed thereon is laminated in a predetermined order, and the unfired via conductor is formed without forming the unfired electrode layer on the uppermost layer. Pressure bonding step of laminating ceramic green sheets and pressing and forming a laminate.
A firing step of firing the laminate,
A method for manufacturing a capacitor, comprising: In the bottom core substrate body having the bottom core substrate main body upper surface and the bottom core substrate main body lower surface, a plurality of the plurality of holes penetrating between the bottom core substrate main body upper surface and the bottom core substrate main body lower surface in the recess forming region. A bottom through-hole conductor forming step of forming a bottom through-hole conductor of
A wall portion having an upper surface of the core substrate for the wall portion and a lower surface of the core substrate for the wall portion, and having a through hole for a recess penetrating between the upper surface of the core substrate for the wall portion and the lower surface of the core substrate for the wall portion. A lower surface of the core substrate body for the wall portion of the core substrate body for
The bottom core substrate body upper surface of the bottom core substrate body,
A bonding step of exposing the plurality of bottom through-hole conductors in the through holes for the concave portion, and bonding.
A method for manufacturing a core substrate body, comprising: The upper surface of the core substrate body,
Under the core board body,
A bottomed recess for incorporating a capacitor, which is open on the upper side of the core substrate body,
And, a plurality of bottom through-hole conductors extending from the bottom surface of the concave portion to the lower surface of the core substrate by penetrating from the bottom surface to the lower surface of the core substrate body,
In the core board body concave portion of the core substrate body having
Capacitor top,
Capacitor bottom,
A pair of electrodes or electrode groups insulated from each other,
A plurality of upper surface connection pads formed on the upper surface of the capacitor and electrically connected to any one of the electrodes or the electrode group of the pair of electrodes or the electrode group. A plurality of upper surface connection pads electrically connected to at least one of the upper surface connection pads;
And a plurality of lower surface connection pads formed on the lower surface of the capacitor and electrically connected to any one of the pair of electrodes or electrode groups, wherein each of the pair of electrodes or electrode groups is A plurality of lower surface connection pads electrically connected to at least one of the plurality of lower surface connection pads;
Place a capacitor with
A capacitor connection step in the recess for connecting the plurality of lower surface connection pads and the corresponding plurality of bottom through-hole conductors corresponding thereto,
Injecting a filling resin into the capacitor built-in recess, curing the filling resin, and fixing the capacitor in the capacitor built-in recess with the filling resin, a capacitor fixing step,
A core through-hole forming step of forming a core through-hole conductor penetrating between the core substrate body upper surface or the filled resin layer on the core substrate body upper surface and the core substrate body lower surface,
A method for manufacturing a core substrate with a built-in capacitor, comprising: It is a manufacturing method of the core substrate with a built-in capacitor of Claim 11, Comprising:
The capacitor fixing step is a capacitor fixing-filling resin coating and curing step of applying and curing a filling resin also on at least the capacitor upper surface among the capacitor upper surface and the core substrate body upper surface, in addition to the inside of the capacitor built-in concave portion,
Prior to the core through-hole forming step, the filling resin on the upper surface of the capacitor or on the upper surface of the capacitor and the upper surface of the core substrate main body is polished to expose the plurality of upper surface connection pads substantially flush. At the same time, the filling resin layer on the upper surface of the capacitor and the upper surface of the core substrate main body, or the filling resin layer on the upper surface of the capacitor and the filling resin layer on the upper surface of the core substrate main body are arranged to be substantially flush with each other. A method for producing a core substrate with a built-in capacitor, comprising a polishing and leveling step of facing. A characteristic inspection step of inspecting the characteristics of the capacitor on the core substrate with a built-in capacitor incorporating the capacitor and removing the non-standard core substrate with a built-in capacitor;
An insulating layer wiring layer forming step of forming a resin insulating layer and a wiring layer on the upper and lower surfaces of the core substrate with a built-in capacitor within the standard,
A method for manufacturing a wiring board, comprising:

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