JP4509550B2 - Relay board, relay board with semiconductor element, board with relay board, structure comprising semiconductor element, relay board and board - Google Patents

Description

  The present invention relates to a relay board, a relay board with a semiconductor element, a board with a relay board, and a structure including a semiconductor element, a relay board, and a board.

  In recent years, various types of structures are known in which an IC chip and a wiring board are not directly connected but an intermediary board called an interposer is interposed between the IC chip and the wiring board to connect them together. By the way, although the operation of the IC chip is further increased due to the advancement of the integrated circuit technology, noise may be superimposed on the power supply wiring and the like to cause malfunction. Therefore, even in the above structure, measures are taken to remove noise and to supply a good power to the IC chip. For example, it has already been proposed to embed a capacitor on the wiring board side and to connect the capacitor and the IC chip via a conductor in the interposer (see, for example, Patent Document 1).

JP 2000-349225 A (FIGS. 26, 28, etc.)

  Generally, when there is a wiring (capacitor connection wiring) that connects a capacitor and an IC chip, the longer the capacitor connection wiring, the higher the possibility that noise will be superimposed at that location. Therefore, in order to increase the noise removal capability, it is preferable that the capacitor connection wiring is as short as possible.

  However, in the structure in which the capacitor is embedded on the wiring board side, the length of the wiring (capacitor connection wiring) connecting the capacitor and the IC chip is inevitably longer than the thickness of the interposer. Therefore, in order to achieve further reduction in noise and improve the reliability of the structure, it has been considered that it is necessary to take some new measures.

  Moreover, in the above structure in which capacitors are embedded on the wiring board side, the entire wiring board with added value must be discarded even if only the capacitor becomes defective due to a short circuit or defective insulation resistance. . For this reason, the amount of loss increases, and it becomes difficult to manufacture cheaply after all.

  Furthermore, as one method for achieving low resistance and low inductance, it is conceivable to increase the size of the capacitor (in other words, increase the capacity). However, in recent wiring boards, conductor circuits are often formed densely over a plurality of layers, and there is not enough space to embed a large capacitor in the first place. Also, if a large capacitor is forcibly embedded, the degree of freedom in forming the conductor circuit is reduced, and the formation of the conductor circuit may be extremely difficult.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a structure including a semiconductor element, a relay substrate, and a substrate that has excellent noise removal capability, is inexpensive, and is easy to manufacture. .
Another object of the present invention is to provide a relay board, a relay board with a semiconductor element, and a board with a relay board, which are suitable for realizing the excellent structure described above.

And as means for solving the above-mentioned problem, a first surface including a semiconductor element having a surface connection terminal, a substrate having a surface connection pad, and a semiconductor element having the surface connection terminal mounted thereon, and A substantially board-shaped relay substrate body having a second surface mounted on the surface of the substrate, and a plurality of relays that linearly penetrate the first surface and the second surface and are connected to the surface connection terminals A plurality of capacitor-side conductor pillars connected to the relay board body-side conductor pillars, which have a substrate body-side conductor pillar and a front surface and a back surface, and pass through the front surface and the back surface and are linearly penetrated ; possess a capacitor disposed in front Symbol second surface, the thermal expansion coefficient of the connecting board is higher than the semiconductor element while lower than the capacitor and the substrate, the Young's modulus of the connecting board substrate But 200GP Exceeded by and the capacitor, and comprising the high relay substrate than the Young's modulus of the substrate and the semiconductor device, the structure comprising a semiconductor element and the relay substrate and the substrate, there is.

Further, in order to realize the above-described structure including the semiconductor element, the relay substrate, and the substrate, the first surface on which the semiconductor element having surface connection terminals is mounted and the surface mounted on the surface of the substrate are preferable. a plurality of connecting board substrate side conductor post linearly therethrough, to be connected to the surface connecting terminals and the connecting board having a substantially disk shape, the first surface and the second surface having a second surface which is, has a surface and a back surface, having said surface and a plurality of capacitors side conductor post to be connected to the linearly penetrated the connecting board side conductor post while penetrating the back surface, before Symbol second surface The relay board body has a thermal expansion coefficient lower than that of the capacitor and the board, but higher than that of the semiconductor element, and the relay board body has a Young's modulus of 200 GPa or more, and Capacitor Relay board and being higher than the Young's modulus of the substrate and the semiconductor element, there is.

Furthermore, a substantially plate-shaped relay substrate body comprising a semiconductor element having surface connection terminals and having a first surface on which the semiconductor element is mounted and a second surface mounted on the surface of the substrate; A plurality of relay board body side conductor pillars that linearly penetrate the surface and the second surface, and are connected to the surface connection terminals, and a front surface and a back surface, and linearly penetrate through the front surface and the back surface. a plurality of capacitors side conductor post which is connected to the pierced the connecting board side conductor posts, have a before Symbol capacitor disposed on the second surface side, the thermal expansion coefficient of the connecting board is, the capacitor and higher than the semiconductor element while lower than the substrate, the Young's modulus of the connecting board is, and the capacitor comprising at least 200 GPa, a high relay substrate than the Young's modulus of the substrate and the semiconductor element Semiconductor device with a relay substrate which is characterized in that there was example, are also suitable. In addition, a substantially board-shaped relay board main body having a board having surface connection pads and having a first surface and a second surface mounted on the surface of the substrate, the first surface and the second surface The relay board has a plurality of relay board body side conductor pillars that are linearly penetrated and connected to the surface connection terminals, and a front surface and a back surface, and penetrates the front surface and the back surface and is linearly penetrated. a plurality of capacitors side conductor post which is connected to the main body side conductor columns, have a before Symbol capacitor disposed on the second surface side, the thermal expansion coefficient of the connecting board is from the capacitor and the substrate The relay substrate body has a Young's modulus of 200 GPa or more and higher than the Young's modulus of the capacitor, the substrate, and the semiconductor element. Relayed Plate with the substrate, are also suitable.

Therefore, according to the structure described above, the capacitor is arranged on the second surface side of the relay substrate , so that the semiconductor element and the capacitor are close to each other as compared with the conventional structure, and as a result, the wiring that connects the semiconductor element and the capacitor ( Capacitor connection wiring) can be made very short. Therefore, noise entering between the semiconductor element and the capacitor can be extremely reduced, and high reliability can be obtained without causing malfunctions such as malfunctions .

  Further, even if a defect occurs in the capacitor, the capacitor is not embedded in the substrate side, so it is sufficient to discard the relay substrate and the capacitor, and the entire substrate is not discarded. Therefore, compared with the conventional structure in which the capacitor is embedded on the substrate side, the loss amount is small and it is possible to manufacture at a low cost. In addition, since the capacitor is not embedded in the board, it is less susceptible to space constraints, making it easier to increase the size of the capacitor (capacity increase) and manufacturing the board. It becomes easy.

  Here, as the semiconductor element, one having a surface connection terminal is used. The surface connection terminal refers to a terminal for electrical connection, which is connected by surface connection. In addition, surface connection refers to the case where pads or terminals are formed in a line shape or a lattice shape (including a staggered shape) on the plane of an object to be connected, and these are connected to each other. Although the size and shape of the semiconductor element are not particularly limited, it is preferable that the semiconductor element is a large semiconductor element having at least one side of 10 mm or more. The thermal expansion coefficient of the semiconductor element is preferably 2.0 ppm / ° C. or more and less than 5.0 ppm / ° C. Specific examples of such a semiconductor element include a semiconductor integrated circuit chip (IC chip) made of silicon having a thermal expansion coefficient of about 3.0 ppm / ° C.

  In this specification, the term “thermal expansion coefficient” means a thermal expansion coefficient (CTE) in a direction (XY direction) orthogonal to the thickness direction (Z direction), and is 0 ° C. to 100 ° C. It means the value measured by TMA (thermomechanical analyzer). “TMA” refers to thermomechanical analysis, such as that defined in JPCA-BU01.

  A substrate having a surface connection pad is used as the substrate. Examples of the substrate include a substrate on which a semiconductor element or other electronic component is mounted, and particularly a wiring substrate on which a semiconductor element or other electronic component is mounted and having a conductor circuit that electrically connects them. . The material for forming the substrate is not particularly limited, and can be appropriately selected in consideration of cost, workability, insulation, mechanical strength, and the like. Examples of the substrate include a resin substrate, a ceramic substrate, and a metal substrate.

  Specific examples of the resin substrate include an EP resin (epoxy resin) substrate, a PI resin (polyimide resin) substrate, a BT resin (bismaleimide-triazine resin) substrate, and a PPE resin (polyphenylene ether resin) substrate. In addition, a substrate made of a composite material of these resins and organic fibers such as glass fibers (glass woven fabric or glass nonwoven fabric) or polyamide fibers may be used. Alternatively, a substrate made of a resin-resin composite material obtained by impregnating a thermosetting resin such as an epoxy resin with a three-dimensional network fluorine-based resin base material such as continuous porous PTFE may be used. Specific examples of the ceramic substrate include an alumina substrate, a beryllia substrate, a glass ceramic substrate, and a substrate made of a low-temperature fired material such as crystallized glass. Specific examples of the metal substrate include a copper substrate, a copper alloy substrate, a substrate made of a single metal other than copper, and a substrate made of an alloy of a metal other than copper. Most of the resin substrates and ceramic substrates listed here have a thermal expansion coefficient of 5.0 ppm / ° C. or higher.

  The surface connection pad refers to a terminal pad for electrical connection, which is connected by surface connection. Such surface connection pads are formed in, for example, a linear shape or a lattice shape (including a staggered shape).

  The relay substrate has a substantially plate-shaped relay substrate body. The relay substrate main body includes a first surface and a second surface. A semiconductor element is mounted on the first surface, and a second surface is mounted on the surface of the substrate.

  The capacitor is disposed on the first surface side or the second surface side of the relay substrate body. The first surface and the second surface on which the capacitor is disposed may be flat or uneven.

  For example, the relay board body has a second surface in which a recess is formed, the relay board body-side conductor pillar passes through the first surface and the bottom surface of the recess, and the capacitor is in the recess. It may be arranged.

  According to this configuration, it is possible to stably hold the capacitor on the second surface side by disposing the capacitor in the recess. The number of the recesses may be singular or plural. Further, the shape and size of the recess are not particularly limited as long as the capacitor can be disposed inside. In addition, about the side surface and bottom face of the recessed part opened only in a 2nd surface, it grasps | ascertains that it is a part of 2nd surface.

  Alternatively, the relay board body has a first surface in which a recess is formed, the relay board body-side conductor pillar penetrates the second surface and the bottom surface of the recess, and the capacitor is in the recess. It may be arranged.

  According to this configuration, the capacitor can be stably held on the first surface side by disposing the capacitor in the recess. The number of the recesses may be singular or plural. Further, the shape and size of the recess are not particularly limited as long as the capacitor can be disposed inside. In addition, it is grasped | ascertained that it is a part of 1st surface about the side surface and bottom face of the recessed part opened only in a 1st surface.

  The thermal expansion coefficient of the relay substrate body is preferably lower than the thermal expansion coefficient of the substrate, and specifically, it is preferably less than 10.0 ppm / ° C. The thermal expansion coefficient of the relay substrate body is preferably 2.0 ppm / ° C. or more and less than 5.0 ppm / ° C., particularly in the range of 2.0 ppm / ° C. or more and less than 5.0 ppm / ° C. It is better that the value is larger than the thermal expansion coefficient of the semiconductor element. The reason is that if the thermal expansion coefficient of the relay substrate body is less than 10.0 ppm / ° C. (especially less than 5.0 ppm / ° C.), the difference in thermal expansion coefficient from the semiconductor element can be made sufficiently small, and the thermal stress on the semiconductor element. This is because the influence of the above can be sufficiently reduced. Therefore, for example, when a silicon IC chip having a thermal expansion coefficient of about 3.0 ppm / ° C. is selected, it is preferable to use a relay substrate body having a thermal expansion coefficient of 3.0 ppm / ° C. or more and less than 5.0 ppm / ° C. It can be said that. It is more preferable that the relay substrate body has a lower thermal expansion than the capacitor. In this case, even if a capacitor having a large thermal expansion coefficient is used, the thermal expansion coefficient of the entire relay board can be kept low by using the relay board body.

  The relay substrate body preferably has not only low thermal expansion as described above but also high rigidity (for example, high Young's modulus). That is, the rigidity (for example, Young's modulus) of the relay substrate body is preferably at least higher than that of the semiconductor element, and specifically, the Young's modulus is preferably 200 GPa or more, particularly 300 GPa or more. The reason is that if the relay board body has high rigidity, even if a large thermal stress is applied to the relay board body, the relay board body can withstand the thermal stress. Therefore, it is possible to prevent warping of the relay substrate body itself and cracks at the joint portion of the semiconductor element. In addition, it is more preferable that the relay substrate body has higher rigidity (for example, high Young's modulus) than the capacitor. In this case, even if a capacitor with low rigidity is used, it can be reinforced and protected by the relay board body, so that the rigidity of the relay board as a whole can be increased.

  Furthermore, it is more preferable that the relay substrate body has not only low thermal expansion and high rigidity as described above but also high heat dissipation. The reason is that if a relay substrate body having high heat dissipation is used, the heat generated by the semiconductor element can be quickly transmitted and dissipated, so that thermal stress can be mitigated. Therefore, a large thermal stress does not act, and it is possible to prevent warping of the relay substrate body itself and cracks at the joint portion of the semiconductor element.

  The relay board body preferably further has an insulating property. The reason is that in the relay board body having no insulating property, it is necessary to provide an insulating layer in advance at the time of forming the conductor pillars. Therefore, it is possible to avoid a complicated structure and an increase in man-hours.

  From the above, it is preferable that the relay substrate body is formed using a nitride-based insulating engineering ceramic material, and in particular, aluminum nitride, silicon nitride, or a mixed ceramic of aluminum nitride and silicon nitride. Most preferably, it is formed using a material. This is because the materials mentioned here have low thermal expansion, high rigidity, high heat dissipation, and insulation.

  Of course, alumina-based ceramic materials also have higher thermal expansion than nitride-based insulating engineering ceramic materials, but they have favorable thermal and mechanical properties, making them suitable as materials for relay substrate bodies. Yes. Alumina-based ceramic materials have the advantage of being less expensive than nitride-based insulating engineering ceramic materials. In addition, although it is inferior in mechanical properties to an alumina-based ceramic material, it is also possible to use a low-temperature fired ceramic having a low thermal expansion as a material for the relay substrate body. In order to reduce the resistance of the conductor column, it can be said that it is preferable to use a low-temperature fired ceramic material such as glass ceramic or crystallized glass. The reason is that a conductor pillar can be formed using copper or silver which is a good conductor if it is a low-temperature fired ceramic material.

  The relay board has a plurality of relay board body side conductor pillars. The relay substrate main body side conductor column penetrates the first surface and the second surface, one end of which is electrically connected to the surface connection terminal or the surface connection pad, and the other end is electrically connected to the capacitor side conductor column. The relay board passes through the first surface and the second surface, and has one end electrically connected to the surface connection terminal and the other end electrically connected to the surface connection pad. May further be included.

  The relay substrate includes a so-called via array type capacitor (capacitor) having a plurality of capacitor-side conductor columns. The capacitor side conductor column is formed through the front and back surfaces of the capacitor, one end of which is electrically connected to the relay substrate body side conductor column, and the other end is electrically connected to the surface connection terminal or the surface connection pad. Is done.

  The relay substrate body side conductor column and the capacitor side conductor column are formed by providing a columnar conductive material in a through hole formed in the relay substrate body or the capacitor. Although it does not specifically limit as said electrically-conductive material, For example, the metal containing 1 type, or 2 or more types selected from copper, gold | metal | money, silver, platinum, palladium, nickel, tin, lead, solder, tungsten, molybdenum, titanium etc. is mentioned. be able to. In addition, in forming the relay substrate body side conductor pillar and the capacitor side conductor pillar, a well-known method can be adopted, for example, filling of a paste containing a conductive metal, plating of a conductive metal, pin-like conductive metal material There is such as press-fitting. In the case where the conductive pillar is formed by filling the through hole of the ceramic relay substrate body or the capacitor with the conductive paste, a simultaneous firing method may be employed or a post firing method may be employed.

  The shape of the relay substrate body side conductor column may be appropriately selected according to the shape of the surface connection terminal, capacitor side conductor column, and surface connection pad to be connected. In addition, the shape of the capacitor-side conductor column may be appropriately selected according to the shape of the connecting board main body side to be connected and the surface connection pad.

  The relay substrate main body and the capacitor may be integrated, and the relay substrate main body side conductor column and the capacitor side conductor column may be directly connected without a protruding electrode. When such an integrated configuration is adopted, the protruding electrode for electrically connecting the relay substrate body and the capacitor can be omitted, so that the configuration is simplified. Further, by directly connecting the relay substrate body side conductor column and the capacitor side conductor column, it is possible to reduce the resistance of the relay substrate. Note that the relay substrate having the integrally configured relay substrate body and the capacitor can be manufactured by, for example, laminating ceramic unsintered materials and simultaneously firing them.

  Alternatively, the relay substrate body and the capacitor may be configured separately, and the relay substrate body side conductor column and the capacitor side conductor column may be connected via a protruding electrode. When such a separate configuration is adopted, the range of selection of materials for forming the relay board main body and the capacitor and the range of selection of methods for manufacturing the relay board are widened.

[First Embodiment]
Hereinafter, a first embodiment of the present invention will be described in detail with reference to FIGS. FIG. 1 is a schematic cross-sectional view showing a semiconductor package (structure) 131 of this embodiment including an IC chip (semiconductor element) 21, a capacitor built-in interposer 91, and a wiring board (substrate) 41. FIG. 2 is a schematic cross-sectional view showing a capacitor built-in interposer 91 constituting the semiconductor package 131. FIG. 3 is a schematic cross-sectional view showing a capacitor built-in interposer with IC chip (capacitor with semiconductor element) 111 constituting the semiconductor package 131. FIG. 4 is a schematic cross-sectional view showing a state when the interposer 111 with a built-in capacitor with IC chip is mounted on the wiring board 41.

  As shown in FIG. 1 and the like, the semiconductor package 131 of this embodiment is an LGA (land grid array) including the IC chip 21, the capacitor built-in interposer 91, and the wiring board 41 as described above. Note that the form of the semiconductor package 131 is not limited to LGA alone, and may be BGA (ball grid array), PGA (pin grid array), or the like.

  The IC chip 21 having a function as an MPU is a 10 mm square rectangular flat plate made of silicon having a thermal expansion coefficient of about 3.0 ppm / ° C. Circuit elements (not shown) are formed on the upper surface of the IC chip 21. On the other hand, a plurality of bump-shaped surface connection terminals 22 are provided in a lattice shape on the lower surface side of the IC chip 21.

  The wiring board 41 is a so-called multilayer wiring board made of a rectangular flat plate member having an upper surface 42 and a lower surface 43 and having a plurality of resin insulation layers 44 and a plurality of layers of conductor circuits 45. In the case of this embodiment, specifically, the resin insulating layer 44 is formed of an insulating base material obtained by impregnating a glass cloth with an epoxy resin, and the conductor circuit 45 is formed of a copper foil or a copper plating layer. The thermal expansion coefficient of the wiring board 41 is 13.0 ppm / ° C. or more and less than 16.0 ppm / ° C. On the upper surface 42 of the wiring board 41, a plurality of surface connection pads 46 are formed in a lattice shape for electrical connection with the interposer 91 side with a built-in capacitor. On the lower surface 43 of the wiring substrate 41, a plurality of surface connection pads 47 for electrical connection with a mother board (not shown) are formed in a lattice shape. The surface connection pads 47 for connecting the motherboard have a wider pitch than the surface connection pads 46 for interposer connection. Via hole conductors 48 are provided in the resin insulating layer 44, and the conductor circuits 45, the surface connection pads 46, and the surface connection pads 47 of different layers are electrically connected to each other via these via hole conductors 48. . In addition to the interposer 111 with a built-in IC chip capacitor shown in FIG. 3, a semiconductor element and other electronic components (all not shown) are mounted on the upper surface 42 of the wiring board 41.

  As shown in FIGS. 1 and 2, the interposer 91 (relay substrate) with a built-in capacitor according to the present embodiment is a rectangular flat plate-shaped interposer body 98 having an upper surface 92 (first surface) and a lower surface 93 (second surface). (Relay substrate body). The interposer body 98 is made of an aluminum nitride substrate having a laminated structure. Such an aluminum nitride substrate has a thermal expansion coefficient of about 4.4 ppm / ° C. and a Young's modulus of about 350 GPa. Therefore, the thermal expansion coefficient of the interposer body 98 is smaller than the thermal expansion coefficient of the wiring board 41 and larger than the thermal expansion coefficient of the IC chip 21. That is, it can be said that the interposer 91 with a built-in capacitor according to the present embodiment has a lower thermal expansibility than the wiring substrate 41, and rather has a thermal expansibility close to that of the IC chip 21. Further, since the Young's modulus of the aluminum nitride substrate is higher than that of the IC chip 21, the interposer 91 with a built-in capacitor of this embodiment has high rigidity.

  The interposer body 98 is formed with a substantially rectangular recess 99 in a plan view so as to open at the lower surface 93. In the recess 99, a substantially rectangular capacitor 101 is also disposed in the same plan view. The capacitor 101 is fixed in the recess 99 by an adhesive layer 108 made of resin. However, a form without the adhesive layer 108 is also possible.

  In the interposer body 98 constituting the interposer 91 with a built-in capacitor, a plurality of vias penetrating the upper surface 92 and the lower surface 93 and a plurality of vias 96 penetrating the bottom surface of the upper surface 92 and the recess 99 are formed in a lattice shape. These vias 96 correspond to the positions of the surface connection pads 46 of the wiring board 41. In the via 96, a relay board body side conductor column 95 made of columnar Pb—Sn solder is provided. On the upper end surface of each relay substrate body side conductor column 95, a substantially hemispherical upper end surface side bump 97 is provided. These upper end surface side bumps 97 protrude from the upper surface 92 and are connected to the surface connection terminals 22 on the IC chip 21 side. On the lower end surface of each relay substrate body side conductor column 95, lower end surface side bumps 94, 100 having a substantially hemispherical shape are provided. The lower end surface side bumps 100 protrude from the lower surface 93 of the interposer body 98 and are connected to the surface connection pads 46 on the wiring board 41 side. On the other hand, the lower end surface side bump 94 protrudes from the bottom surface of the recess 99 and is connected to the upper end surface of the capacitor side conductor column 105 on the capacitor 101 side.

  As shown in FIGS. 1, 2, etc., the capacitor 101 of this embodiment is also a via array type capacitor, and has a rectangular plate-shaped capacitor body 104 having an upper surface 102 and a lower surface 103. The capacitor body 104 is made of a barium titanate substrate having a laminated structure. That is, the capacitor 101 is a multilayer ceramic capacitor having a high dielectric body as the capacitor body 104. In the semiconductor package 131 of this embodiment, only one capacitor 101 is provided. However, the present invention is not limited to this, and a plurality of capacitors 101 may be provided.

  In the capacitor main body 104 constituting the capacitor 101, a plurality of vias penetrating the upper surface 102 and the lower surface 103 are formed in a lattice shape. A plurality of capacitor-side conductor columns 105 made of Pb-Sn are provided in the via. On the lower end surface of each capacitor side conductor column 105, a substantially hemispherical lower end surface side bump 107 is provided. These lower end surface side bumps 107 protrude to the same extent as the lower end surface side bumps 100 and are connected to the surface connection pads 46 on the wiring board 41 side.

  Further, in the barium titanate substrate constituting the capacitor body 104, the inner layer electrode 106 is formed in a layered manner through a barium titanate layer which is a dielectric layer. More specifically, the capacitor side conductor column 105 is divided into two groups of a first capacitor side conductor column and a second capacitor side conductor column, and the inner layer electrode 106 is referred to as a first inner layer electrode and a second inner layer electrode. Divided into two groups. The first inner layer electrode and the second inner layer electrode are alternately stacked at a predetermined interval, the first inner layer electrode is connected to the first capacitor side conductor column, and the second inner layer electrode is connected to the second capacitor side conductor column. It is connected.

  Therefore, in the semiconductor package 131 having such a structure, the wiring substrate 41 side and the IC chip 21 side are electrically connected via the conductor pillars 95 and 105 of the interposer 91 with a built-in capacitor. Therefore, input / output of signals is performed between the wiring board 41 and the IC chip 21 via the capacitor built-in interposer 91, and power for operating the IC chip 21 as an MPU is supplied. In this case, since the signal flows through the relay substrate body side conductor column 95 penetrating the upper surface 92 and the lower surface 93 of the interposer body 98, the signal is directly input / output to / from the IC chip 21 without flowing through the capacitor 101. On the other hand, power is supplied via the interposer body 98 and the capacitor 101. That is, the power source flows through the capacitor side conductor column 105 in the capacitor 101 and also flows through the relay substrate body side conductor column 95 penetrating the upper surface 92 of the interposer body 98 and the bottom surface of the recess 99. Since the semiconductor package 131 is provided with the capacitor 101, noise superimposed on the power supply potential and the ground potential is surely removed.

  Here, a procedure for manufacturing the semiconductor package 131 having the above structure will be described.

  First, a plurality of barium titanate green sheets having vias in a lattice shape are formed at corresponding positions by a known ceramic green sheet forming technique. Then, vias penetrating both the front and back surfaces are formed at predetermined positions in each green sheet by punching or the like. Further, a nickel paste is filled into the vias of each green sheet, and a paste filling layer that will later become the capacitor-side conductor pillar 105 is formed. Also, a nickel paste is printed on one side of each green sheet, and a paste printing layer having a predetermined pattern that will later become the inner layer electrode 106 is formed. And after laminating | stacking and crimping | bonding these green sheets, it bakes at a predetermined temperature in a reducing atmosphere (simultaneous baking), A barium titanate and a nickel paste are sintered. As a result, the capacitor main body 104 having the capacitor side conductor column 105 and the inner layer electrode 106 is manufactured. Further, a solder paste is printed on the lower end surface of the capacitor side conductor column 105 of the capacitor body 104. In this state, reflow is performed to melt the solder paste. Then, the solder paste swells in a substantially hemispherical shape to form a lower end surface side bump 107. As a result, the capacitor 101 shown in FIG. 2 is completed.

In addition, the interposer body 98 is manufactured in the following manner.
That is, a plurality of aluminum nitride green sheets having vias 96 (through holes) formed in a lattice shape at corresponding positions are produced by a known ceramic green sheet forming technique. A part of the green sheet is provided with a rectangular opening by punching or the like. Such an opening becomes a recess 99 later. And each green sheet is laminated | stacked and crimped | bonded. Further, after applying a tungsten paste to the inner peripheral surface of the via 96, the green sheet laminate is fired in a reducing atmosphere to produce an interposer body 98 made of an aluminum nitride sintered body. In the interposer body 98, a base metal layer (not shown) mainly composed of tungsten is formed on the inner peripheral surface of the via 96. Further, after applying electroless nickel-gold plating on the base metal layer, a high melting point solder ball having a diameter of 0.9 mm made of 90% Pb-10% Sn is placed in the upper end opening of each via 96. This is heated to melt. As a result, the molten high melting point solder moves downward by gravity and is injected into the via 96 and welded to the metal layer on the inner peripheral surface of the via 96, thereby forming the relay substrate body-side conductor column 95. Further, the upper end surface and the lower end surface of the relay board main body side conductor column 95 swell into a substantially hemispherical shape by the action of surface tension, and become an upper end surface side bump 97 and lower end surface side bumps 94 and 100. As a result, the interposer body 98 having the recess 99 is completed.

  An uncured thermosetting adhesive is applied to the recess 99 of the interposer body 98 thus manufactured, and the capacitor 101 is placed in the recess 99 in this state, and heated to a predetermined temperature. As a result, the relay board main body side conductor column 95 and the capacitor side conductor column 105 are joined via the lower end surface side bump 94 reflowed by heat. Further, the thermosetting adhesive is cured, so that the capacitor 101 is securely bonded and held in the recess 99. As a result, the capacitor built-in interposer 91 shown in FIG. 2 is completed.

  Next, the IC chip 21 is placed on the upper surface 92 of the completed interposer 91 with a built-in capacitor. At this time, the surface connection terminal 22 on the IC chip 21 side and the upper end surface side bump 97 on the capacitor built-in interposer 91 side are aligned. And by heating and reflowing each upper end surface side bump 97, the upper end surface side bump 97 and the surface connection terminal 22 are joined. As a result, a capacitor built-in interposer 111 with an IC chip shown in FIG. 3 is completed.

  Next, the bumps 100 and 107 on the lower surface side of the interposer 111 with a built-in IC chip and the surface connection pads 46 on the wiring board 41 side are aligned (see FIG. 4), and the IC chip is placed on the wiring board 41. The interposer 111 with a built-in capacitor is placed. Then, by heating and reflowing the lower end surface side bumps 100 and 107, the lower end surface side bumps 100 and 107 and the surface connection pad 46 are joined. As a result, the semiconductor package 131 shown in FIG. 1 is completed.

  Therefore, according to the present embodiment, the following effects can be obtained.

  (1) In the case of the semiconductor package 131 (structure) of the present embodiment, the IC chip 21 and the capacitor 101 are closer to each other than the conventional structure by disposing the capacitor 101 in the recess 99 of the interposer 91. As a result, the wiring (capacitor connection wiring) connecting the IC chip 21 and the capacitor 101 can be made very short. Therefore, noise entering between the IC chip 21 and the capacitor 101 can be made extremely small, and high reliability can be obtained without causing problems such as malfunctions.

  (2) Also, even if a problem occurs in the capacitor 101, the capacitor 101 is not embedded in the wiring board 41 side, so it is sufficient to discard only the interposer 91 with a built-in capacitor, and the entire wiring board 41 is discarded. Not accompanied. Therefore, compared with the conventional structure in which the capacitor 101 is embedded on the wiring board 41 side, the loss amount is small and it is possible to manufacture at a low cost. In addition, since the capacitor 101 is not embedded in the wiring board 41 side, there is no space limitation, and it is possible to increase the size (capacity) of the capacitor 101 relatively easily. 41 also becomes easy to manufacture. Further, if the capacitor 101 is increased in size, it leads to lower resistance and lower inductance, so that the noise removal capability can be improved.

(3) In this semiconductor package 131, by using the substantially plate-shaped interposer body 98 having a thermal expansion coefficient of less than 5.0 ppm / ° C., the difference in thermal expansion coefficient from the IC chip 21 becomes small, and the IC chip 21 Large thermal stress does not act directly on Therefore, even if the IC chip 21 is large and generates a large amount of heat, cracks and the like are unlikely to occur. Therefore, high reliability can be imparted to the chip bonding portion and the like in the semiconductor package 131.
In the present embodiment, several modifications are possible as follows.

(Modification 1-1)
As shown in FIG. 5, first, a capacitor-embedded interposer 91 is joined to the upper surface 42 of the wiring substrate 41 by soldering or the like, so that a wiring substrate 121 with a capacitor-embedded interposer (substrate with a relay substrate) is produced in advance. Thereafter, the IC chip 21 is bonded to the upper surface 92 of the interposer 91 with a built-in capacitor to form a desired semiconductor package 131.

(Modification 1-2)
The interposer 91 (relay substrate) with a built-in capacitor shown in FIG. 1 and the like has a structure in which the interposer main body 98 and the capacitor 101 are separately formed and connected through an adhesive layer 108 and a lower end surface side bump 94. Was. In contrast, in the interposer 141 with a built-in capacitor shown in FIGS. 6 and 7, the interposer body 98 and the capacitor 101 are integrally configured. That is, the interposer body 98 and the capacitor 101 are directly connected without the adhesive layer 108 and the lower end surface side bump 94 interposed therebetween. In this case, since the lower end surface side bump 94 for electrically connecting the interposer body 98 and the capacitor 101 can be omitted, the configuration can be simplified. Further, by directly connecting the relay board main body side conductor column 95 and the capacitor side conductor column 105, it is possible to reduce the resistance of the capacitor built-in interposer 141.

  Next, a manufacturing method of the capacitor built-in interposer 141 will be described. First, a plurality of alumina green sheets (ceramic unsintered bodies) having vias 96 (through holes, first conductor column forming holes) formed in a grid pattern at corresponding positions by a known ceramic green sheet forming technique. Make it. Some of these green sheets are provided with rectangular openings by punching or the like. Such an opening becomes a recess 99 later. These green sheets become the interposer body 98 after sintering. The through holes of these green sheets are filled with a paste (conductive material) such as nickel in advance by printing, for example. The nickel paste in each through hole later becomes the relay substrate body side conductor column 95 or the capacitor side conductor column 105.

  A predetermined number of the green sheets filled with the conductive material are stacked. Next, when each green sheet provided with a rectangular opening is laminated and pressure-bonded on this laminate, each time a green sheet is stacked and pressure-bonded, a pattern of, for example, ceramic paste is screen-printed on the opening. Form. The thickness of the ceramic printed layer after drying is substantially the same as the thickness of the green sheet laminated immediately before. The ceramic material that is screen printed later becomes the ceramic dielectric layer. Therefore, a ceramic material that has a higher dielectric constant than alumina after sintering should be selected. In this embodiment, a slurry that becomes barium titanate after sintering is used as the ceramic material. The ceramic material is preferably one that can be fired simultaneously with the green sheet. Next, a nickel paste layer is patterned on the surface of the already printed ceramic material layer by further printing nickel paste (conductive material). At this time, the nickel paste printed in the hole-like portion where the ceramic layer is not formed later becomes the conductor pillar 105 of the capacitor portion. The nickel paste layer on the surface of the printed ceramic material layer later becomes the inner layer electrode 106.

  And after making lamination | stacking by repeating lamination | stacking of each green sheet provided with the rectangular-shaped opening part, crimping | bonding, printing of ceramic paste, and printing of nickel paste, the laminated body is baked in oxidizing atmosphere. That is, a green sheet (ceramic unsintered body), an unsintered ceramic material layer, and an unsintered nickel paste are heated together to sinter them simultaneously.

  And according to this manufacturing method, the capacitor built-in interposer 141 shown in FIGS. 6 and 7 can be obtained with certainty.

(Modification 1-3)
In the interposer 91 with a built-in capacitor shown in FIG. 1 and the like, the concave portion 99 opened on the lower surface 93 side of the interposer body 98 is formed, and the capacitor 101 is disposed in the concave portion 99. On the other hand, in the interposer 151 with a built-in capacitor (relay substrate) shown in FIG. 8, a recess 99 is formed on the upper surface 92 side of the interposer body 98, and the capacitor 101 is disposed in the recess 99. . Therefore, the relay substrate body side conductor column 95 penetrates the lower surface 93 (second surface) and the bottom surface of the recess 99, and the upper end thereof is electrically connected to the lower end surface of the capacitor side conductor column 105 via the bump 152. Has been.

[Second Embodiment]
Hereinafter, a third embodiment of the present invention will be described in detail with reference to FIGS. FIG. 9 is a schematic cross-sectional view showing a semiconductor package (structure) 161 of this embodiment including an IC chip (semiconductor element) 21, an interposer 171 with a capacitor (relay substrate), and a wiring substrate (substrate) 41. . FIG. 10 is a schematic cross-sectional view showing an interposer 171 with a capacitor that constitutes the semiconductor package 161.

  As shown in FIG. 9, the semiconductor package 161 of this embodiment is an LGA (land grid array) including the IC chip 21, the interposer 171 with a capacitor, and the wiring board 41 as described above. The form of the semiconductor package 161 is not limited to the LGA alone, and may be, for example, a BGA (ball grid array) or a PGA (pin grid array). About the IC chip 21 and the wiring board 41, since the same thing as the said 1st Embodiment is used, the detailed description is abbreviate | omitted.

  The interposer 171 (relay board) with a capacitor of this embodiment has a rectangular flat plate-shaped interposer body 98 (relay board body) having an upper surface 92 (first surface) and a lower surface 93 (second surface). The interposer body 98 is made of an alumina substrate having a laminated structure. Such an alumina substrate has a thermal expansion coefficient of 5.0 ppm / ° C. or more and less than 7.0 ppm / ° C., and a Young's modulus of about 300 GPa. Therefore, the thermal expansion coefficient of the interposer body 98 is smaller than the thermal expansion coefficient of the wiring board 41 (here, about 12.0 ppm / ° C.) and larger than the thermal expansion coefficient of the IC chip 21.

  In the case of this embodiment, the upper surface 92 and the lower surface 93 of the interposer body 98 are flat surfaces, and the recess 99 for disposing the capacitor 101 is not particularly formed. The capacitor 101 constituting the capacitor-equipped interposer 171 is larger than that of the first embodiment and has substantially the same outer dimensions as the interposer body 98. Such a large capacitor 101 is arranged on the lower surface 93 side of the interposer body 98. The capacitor 101 includes a capacitor side conductor column 105 at a position corresponding to the relay substrate body side conductor column 95. The lower end of each relay substrate main body side conductor column 95 is electrically connected to the upper end surface of each capacitor side conductor column 105 via the lower end surface side bump 100. The lower end surface of each capacitor-side conductor column 105 is electrically connected to the surface connection pad 46 on the wiring board 41 side via the bump 107.

  In this embodiment, since the interposer body 98 is made of an alumina-based ceramic material having higher rigidity than the capacitor 101, the capacitor 101 having low rigidity can be reinforced and protected. Therefore, the rigidity of the interposer 171 as a whole can be increased. In addition, since the interposer body 98 is made of an alumina ceramic material having a lower thermal expansion coefficient than the capacitor 101, the thermal expansion coefficient of the interposer 171 as a whole can be kept low. For the above reasons, the connection reliability of the interposer 171 and thus the connection reliability of the semiconductor package 161 can be improved.

  In the present embodiment, the following modifications are also conceivable.

(Modification 2)
The interposer with a capacitor 171 shown in FIG. 10 and the like has a structure in which the interposer main body 98 and the capacitor 101 are separately formed and connected via the lower end surface side bumps 100. In contrast, in the interposer with a capacitor 171 of the modification shown in FIGS. 11 and 12, the interposer body 98 and the capacitor 101 are integrally configured. That is, the interposer body 98 and the capacitor 101 are directly connected without the lower end surface side bump 100 being interposed. In this case, since the lower end surface side bump 100 for electrically connecting the interposer body 98 and the capacitor 101 can be omitted, the configuration can be simplified. Further, by directly connecting the relay board main body side conductor column 95 and the capacitor side conductor column 105, it is possible to reduce the resistance of the interposer 171 with a capacitor.

  The embodiment of the present invention may be modified as follows without departing from the spirit of the invention. For example, in the first embodiment, the example in which the concave portion 99 is provided at one location in the approximate center of the interposer body 98 has been described. However, the concave portion 99 is not necessarily formed in the approximate center. Moreover, the recessed part 99 may be provided in several places as needed, and you may make it arrange | position the capacitor | condenser 101 in each recessed part 99 (refer FIG. 13). Although not shown, a plurality of capacitors 101 may be arranged in one recess 99. In this case, the capacitors 101 may be laminated in the thickness direction of the interposer 91, or the capacitors 101 may be arranged side by side in the surface direction of the interposer 91.

  Next, the technical ideas grasped by the embodiment described above are listed below.

  (1) It has a first surface on which a semiconductor element having a thermal expansion coefficient of 2.0 ppm / ° C. or more and less than 5.0 ppm / ° C. and having a surface connection terminal is mounted, and a second surface on which a recess is formed. And a plurality of relay board bodies having a substantially plate shape having a thermal expansion coefficient of less than 5.0 ppm / ° C., a plurality of holes to penetrate the first surface and the bottom surface of the recess and to be electrically connected to the surface connection terminals. A relay substrate body side conductor column, and a plurality of capacitor side conductor columns that have a front surface and a back surface, pass through the front surface and the back surface, and are electrically connected to the relay substrate body side conductor column; And a capacitor disposed on the relay board.

  (2) The relay board according to the technical idea (1), wherein the relay board body is made of an insulating material.

  (3) The relay board according to the technical idea (1), wherein the relay board body is made of a material having a lower thermal expansion coefficient than the board.

  (4) The relay board according to the technical idea (1), wherein the relay board body is made of a material having rigidity higher than that of silicon.

  (5) The relay board according to the technical idea (1), wherein the relay board body is made of a material having a low coefficient of thermal expansion and high rigidity.

  (6) The relay board according to the technical idea (1), wherein the relay board body is made of a material having a Young's modulus of 200 GPa or more.

  (7) The relay board according to the technical idea (1), wherein the relay board body is made of an insulating ceramic material having a Young's modulus of 200 GPa or more.

  (8) The relay board according to the technical idea (1), wherein the relay board body is made of a nitride-based engineering ceramic.

  (9) The relay board according to the technical idea (1), wherein the relay board body is formed using aluminum nitride, silicon nitride, or a mixed ceramic material of aluminum nitride and silicon nitride.

  (10) The relay substrate according to the technical idea (1), wherein at least one side of the semiconductor element is 10 mm or more.

  (11) A first surface on which a semiconductor element having a surface connection terminal having a thermal expansion coefficient of 2.0 ppm / ° C. or more and less than 5.0 ppm / ° C. and a thermal expansion coefficient of 7.0 ppm / ° C. or more A relay board body having a substantially plate shape made of an alumina-based ceramic material having a second surface arranged toward the substrate side of the substrate and having a thermal expansion coefficient of 5.0 ppm / ° C. or more and less than 7.0 ppm / ° C., A plurality of relay board body-side conductor pillars that penetrate one surface and the second surface and are to be electrically connected to the surface connection terminals; and a front surface and a back surface; A relay board comprising a plurality of capacitor-side conductor pillars electrically connected to the board body-side conductor pillars, and a capacitor disposed on the second surface side.

  (12) A substantially plate-shaped relay substrate body having a first surface and a second surface on which a semiconductor element having surface connection terminals is mounted, and the surface connection penetrating through the first surface and the second surface. A plurality of relay substrate body side conductor columns connected to the terminals, and a front surface and a back surface, and a plurality of capacitor side conductor columns passing through the front surface and the back surface and connected to the relay substrate body side conductor columns. In the method of manufacturing a relay substrate comprising a capacitor disposed on the first surface side or the second surface side, a step of producing a ceramic unsintered body having a recess and a first conductor column forming hole, Filling the first conductor pillar forming hole with a conductive material to form a non-sintered relay substrate body side conductor pillar, and filling the ceramic material into the concave portion of the ceramic unsintered body, Unsintered ceramic dielectric that will later become the relay substrate body Forming a second conductor pillar forming hole in the unsintered ceramic dielectric layer, filling the second conductor pillar forming hole with a conductive material, and forming an unsintered capacitor A step of forming a side conductor column, the unsintered ceramic unsintered body, the unsintered ceramic dielectric layer, the unsintered relay substrate body side conductor column, and the unsintered capacitor side conductor And a step of simultaneously heating the columns and sintering them simultaneously.

1 is a schematic cross-sectional view showing a semiconductor package (structure) according to a first embodiment including an IC chip (semiconductor element), a capacitor built-in interposer (relay substrate), and a wiring substrate (substrate). The schematic sectional drawing which shows the capacitor built-in interposer which comprises a semiconductor package. The schematic sectional drawing which shows the interposer with a built-in capacitor | condenser with an IC chip (relay substrate with a semiconductor element) which comprises a semiconductor package. The schematic sectional drawing which shows a state when mounting the interposer with a built-in capacitor | condenser with an IC chip on a wiring board. FIG. 6 is a schematic cross-sectional view showing a state when an IC chip is mounted on a wiring board with a capacitor-embedded interposer (a board with a relay board) in a modification of the first embodiment. The schematic sectional drawing which shows the semiconductor package (structure) of another modification in 1st Embodiment which consists of IC chip (semiconductor element), a capacitor built-in interposer (relay board), and a wiring board (board | substrate). The schematic sectional drawing which shows the capacitor built-in interposer which comprises a semiconductor package. FIG. 6 is a schematic cross-sectional view showing a semiconductor package (structure) of still another modification example of the first embodiment including an IC chip (semiconductor element), a capacitor-embedded interposer (relay substrate), and a wiring substrate (substrate). FIG. 6 is a schematic cross-sectional view showing a semiconductor package (structure) according to a second embodiment including an IC chip (semiconductor element), an interposer with capacitors (relay substrate), and a wiring substrate (substrate). The schematic sectional drawing which shows the interposer with a capacitor | condenser which comprises a semiconductor package. The schematic sectional drawing which shows the semiconductor package (structure) of the modification of 2nd Embodiment which consists of an IC chip (semiconductor element), an interposer with a capacitor (relay substrate), and a wiring substrate (substrate). The schematic sectional drawing which shows the interposer with a capacitor | condenser which comprises a semiconductor package. The schematic sectional drawing which shows the semiconductor package (structure) of another embodiment which consists of an IC chip (semiconductor element), a capacitor built-in interposer (relay substrate), and a wiring substrate (substrate).

Explanation of symbols

DESCRIPTION OF SYMBOLS 21 ... IC chip as a semiconductor element 22 ... Surface connection terminal 41 ... Wiring board as a substrate 46 ... Surface connection pad 91, 141, 151 ... Interposer with built-in capacitor as a relay substrate 92 ... First surface (of the relay substrate body) 93 ... Second surface of relay board body 95 ... Conductor board body side conductor column 98 ... Interposer body with built-in capacitor as relay board body 99 ... Recess 101 ... Capacitor 102 ... Front surface of capacitor 103 ... Back surface of capacitor 105 ... Condenser side conductor pillar 111 ... Interposer with built-in capacitor with IC chip as relay board with semiconductor element 121 ... Wiring board with interposer with built-in capacitor as board with relay board 131,161,191 ... Consists of semiconductor element, relay board and board Semiconductor package as a structure 171 ... Interposer with capacitor as relay board

Claims (7)

A substantially plate-shaped relay substrate body having a first surface on which a semiconductor element having surface connection terminals is mounted, and a second surface mounted on the surface of the substrate;
A plurality of relay board body side conductor pillars that linearly penetrate the first surface and the second surface and are connected to the surface connection terminals;
Has a surface and a back surface, having said surface and a plurality of capacitors side conductor post to be connected to the linearly penetrated the connecting board side conductor post while penetrating the back surface, before Symbol second surface With a placed capacitor ,
The thermal expansion coefficient of the relay substrate body is lower than the capacitor and the substrate while being higher than the semiconductor element,
The relay substrate, wherein the relay substrate main body has a Young's modulus of 200 GPa or more and higher than the Young's modulus of the capacitor, the substrate, and the semiconductor element .   2. The relay according to claim 1, wherein the relay substrate body and the capacitor are integrally configured, and the relay substrate body side conductor column and the capacitor side conductor column are directly connected without a protruding electrode. substrate.   2. The relay board according to claim 1, wherein the relay board main body and the capacitor have separate structures, and the relay board main body side conductor column and the capacitor side conductor column are connected via a protruding electrode. . It said connecting board, the relay board according to any one of claims 1 to 3 Young's modulus is characterized by having the above ceramic material 300 GPa. Comprising a semiconductor element having a surface connection terminal; and
A substantially board-shaped relay substrate body having a first surface on which the semiconductor element is mounted and a second surface mounted on the surface of the substrate; linearly penetrating the first surface and the second surface; A plurality of relay board body side conductor columns connected to the surface connection terminals, and have a front surface and a back surface, and are connected to the relay board body side conductor columns that penetrate the front surface and the back surface and are linearly penetrated. a plurality of capacitors side conductor columns, have a before Symbol capacitor disposed on the second surface side, the thermal expansion coefficient of the connecting board is than the semiconductor element while lower than the capacitor and the substrate And a relay substrate having a semiconductor element, wherein the relay substrate body has a Young's modulus of 200 GPa or more and higher than the Young's modulus of the capacitor, the substrate, and the semiconductor element . Comprising a substrate having surface connection pads, and
A substantially plate-shaped relay substrate body having a first surface and a second surface mounted on the surface of the substrate, and linearly penetrates the first surface and the second surface and is connected to the surface connection terminal. A plurality of relay substrate body side conductor pillars, and a plurality of capacitor side conductor pillars that have a front surface and a back surface, pass through the front surface and the back surface, and are connected linearly to the relay board body side conductor pillars. have, have a before Symbol capacitor disposed on the second surface side, the thermal expansion coefficient of the connecting board is higher than the semiconductor element while lower than the capacitor and the substrate, the relay substrate A substrate with a relay substrate, comprising a relay substrate having a Young's modulus of a main body of 200 GPa or higher and higher than the Young's modulus of the capacitor, the substrate, and the semiconductor element . Comprising a semiconductor element having a surface connection terminal;
Comprising a substrate having surface connection pads, and
A first board on which a semiconductor element having the surface connection terminal is mounted, a substantially plate-shaped relay board body having a second surface mounted on the surface of the board, the first surface, and the second surface. The relay board has a plurality of relay board body side conductor pillars that are linearly penetrated and connected to the surface connection terminals, and a front surface and a back surface, and penetrates the front surface and the back surface and is linearly penetrated. a plurality of capacitors side conductor post which is connected to the main body side conductor columns, have a before Symbol capacitor disposed on the second surface side, the thermal expansion coefficient of the connecting board is from the capacitor and the substrate The relay substrate body has a Young's modulus of 200 GPa or more and higher than the Young's modulus of the capacitor, the substrate, and the semiconductor element. did, Structure comprising a conductive element and the relay substrate and the substrate.

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