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JP2004311697A - Semiconductor device - Google Patents

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Publication number
JP2004311697A
JP2004311697A JP2003102842A JP2003102842A JP2004311697A JP 2004311697 A JP2004311697 A JP 2004311697A JP 2003102842 A JP2003102842 A JP 2003102842A JP 2003102842 A JP2003102842 A JP 2003102842A JP 2004311697 A JP2004311697 A JP 2004311697A
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Japan
Prior art keywords
layer
semiconductor device
metal layer
wiring
pad metal
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JP2003102842A
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Japanese (ja)
Inventor
Kazuhisa Hatanaka
和久 畑中
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Toshiba Corp
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Toshiba Corp
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Priority to JP2003102842A priority Critical patent/JP2004311697A/en
Publication of JP2004311697A publication Critical patent/JP2004311697A/en
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which has no decline in bonding strength and thereby has a high reliability and a high yield. <P>SOLUTION: The semiconductor device comprises a semiconductor substrate 1, a first insulation layer 4 formed on top of the semiconductor substrate 1, a Cu wiring layer 2 having a prescribed pattern which is embedded in the first insulation layer 4 in such a manner that the top face may be essentially flush with that of the first insulation layer 4, a pad metal layer 6 having a prescribed pattern which is formed on top of the first insulation layer 4 and the Cu wiring layer 2 and is electrically connected with the Cu wiring layer 2, and a second insulation layer 8 for covering these layers. The semiconductor device is also provided with an opening 9 which is formed from the front surface of the second insulation layer 8 and reaches the pad metal layer 6. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体装置に関し、特にボンディングパッド部における信頼性の向上を図った半導体装置に関する。
【０００２】
【従来の技術】
近年、半導体装置の微細化、高速化の要求に対して、従来のＡｌ配線に代わるＣｕ配線の導入が進められている。Ｃｕ配線により、素子の微細化により高抵抗化する配線抵抗を低減し、信号伝達時の遅延時間を短縮、処理速度の向上を図ることができる。しかしながら、Ｃｕ配線はＡｌ配線と異なり、深さ方向に酸化が進行する、ダイレクトなボンディングが難しいという問題がある。
【０００３】
このような問題を解決するために、一般にボンディングパッドとして最上層にＡｌ合金層を形成する手法が採られている。図６にそのボンディングパッド部の構造を示す。図に示すように、素子領域の形成された半導体基板１上にライナーバリアメタル層３３を介して形成されたＣｕ配線３２上に、バリアメタル層３５を介してＡｌ合金からなるパッドメタル層３６が形成されており、それぞれ層間絶縁膜３４、３４’中にパターニングされている。最上層にはパッシベーション膜３８が形成され、パッドメタル層に達するボンディングパッド開口部３９が設けられている。
【０００４】
そして、このようなボンディングパッド部は、以下のように従来のＡｌ多層配線形成プロセスを用いて形成される。先ず、半導体基板に素子領域を形成した後、層間絶縁膜３４を形成し、所定パターンの溝を形成した後、ライナーバリアメタル３２を形成、Ｃｕ配線３２をダマシン技術により形成する。次いでＣｕ酸化防止のためのＳｉＮ層３７、層間絶縁膜３４’を順次全面に形成し、Ｃｕ配線３２上の所定の位置にコンタクトホールを形成、スパッタリングによりコンタクトホールを含む全面にバリアメタル層３５、パッドメタル層３６を形成し、これをコンタクトホール内部に残すようにパターニングし、さらにパッシベーション膜３８を形成、所定位置にパッドメタル層３６に達するボンディングパッド開口部３９を形成する。
【０００５】
【発明が解決しようとする課題】
しかしながら、このようなボンディングパッド部の構造では、ボンディングパッド開口部直下にＣｕ配線が形成されているため、図７に示すようにボンディングパッドに直径数十μｍ程度のプローブ４０を接触（プロービング）させて動作テストを行うＤ／Ｓテスト（Ｄｉｅ Ｓｏｒｔ：良／不良の判別）工程において、下地のＣｕ配線３２が露出、酸化し、ボンディング強度が低下する、という問題が発生していた。そこで、図８に示すような、Ｃｕ配線４２とパッドメタル層４６を、ヴィア５０を介して接続する手法により、ボンディングパッド開口部直下にはＣｕ配線４２が形成されず、プロービングによるＣｕの露出はなくなるが、ヴィア５０開口後のフォトレジストアッシング時や、ＳｉＮ膜４７エッチング時に層間絶縁膜表面がダメージを受け、この上に形成されるバリアメタル層４５、パッドメタル層４６との密着強度が劣化することから、ボンディング強度は低下してしまう。さらに、パッドメタル層４６はヴィア５０を含む領域上にスパッタリングにより形成されるため、ヴィア５０部分のステップカバレッジ劣化によるエレクトロマイグレーション不良が懸念される。
【０００６】
そこで、本発明は、従来の半導体装置における欠点を取り除き、ボンディング強度の低下を抑え、信頼性、歩留りの高い半導体装置を提供することを目的とするものである。
【０００７】
【課題を解決するための手段】
本発明の半導体装置は、半導体基板上に形成された第１の絶縁層と、この第１の絶縁層中に、上面が実質的に同一平面となるよう埋め込まれた所定パターンのＣｕ配線層と、前記第１の絶縁層及び前記Ｃｕ配線層の上面上に形成され、前記Ｃｕ配線層と電気的に接続された所定パターンのパッドメタル層と、これら各層を被覆する第２の絶縁層を備え、この第２の絶縁層表面より前記パッドメタル層に達する開口部を有することを特徴とするものである。
【０００８】
また、本発明の半導体装置においては、前記パッドメタル層の前記開口部直下には、前記Ｃｕ配線層が形成されていないことを特徴としている。
【０００９】
そして、本発明の半導体装置においては、前記第２の絶縁層は、ＳｉＮ層を介して形成されることを特徴としている。
【００１０】
さらに、本発明の半導体装置においては、前記Ｃｕ配線層上には、前記パッドメタル層を介して前記第２の絶縁層が形成されていることを特徴としている。
【００１１】
【発明の実施の形態】
以下本発明の実施形態について、図を参照して説明する。
【００１２】
（実施形態１）
図１に第１の実施形態に係る半導体装置の構造を示す。素子領域の形成された半導体基板１上に、所定パターンのＣｕ配線２、２’がライナーバリアメタル層３を介してＴＥＯＳ層間膜（第１の絶縁層）４に埋め込み形成されており、Ｃｕ配線２を含む上層の一部に所定パターンのバリアメタル層５、Ａｌ合金からなるパッドメタル層６が形成されている。最上層にはＳｉＮ層７を介してパッシベーション膜８（第２の絶縁層）が形成されており、パッドメタル層６の所定領域に達するボンディングパッド開口部９が設けられている。
【００１３】
このような半導体装置は以下のように形成される。先ず、図２（ａ）に示すように、ＴＥＯＳ層間膜４に所定パターンの溝を形成し、ライナーバリアメタル層３をスパッタリングした後、メッキにより溝内部にＣｕ配線２、２’を形成する。（ｂ）に示すように、溝部分以外のＣｕ、ライナーバリアメタルをＣＭＰ法により除去し、さらにＴＥＯＳ層間膜を削り、全面を平坦化し、Ｃｕ配線２、２’、ライナーバリアメタル層３及びＴＥＯＳ層間膜４を形成する。この上に（ｃ）に示すように、バリアメタルち５、パッドメタル６を順次スパッタリングし、（ｄ）に示すように、リソグラフィー技術によりフォトレジスト１０を所定パターンに加工する。
【００１４】
そして図３（ａ）に示すように、ＲＩＥ技術により所定パターンのバリアメタル層５／パッドメタル層６を形成し、（ｂ）に示すように、露出したＣｕ配線２’の酸化防止のためのＳｉＮ層７、パッシベーション膜８をＣＶＤにより順次堆積した後、（ｃ）に示すように、フォトレジスト１０’をパターニングする。このとき、Ｃｕ配線２、２’上には開口部が形成されることなく、レジストパターンが形成されている。そしてＲＩＥ技術により、パッシベーション膜８、ＳｉＮ層７にパッドメタル層６に達するボンディングパッド開口部９を形成し、フォトレジスト１０’を除去して図１に示すような半導体装置を形成する。
【００１５】
このようにして形成された半導体装置においては、ヴィアを形成する必要がないため、エレクトロマイグレーション不良は抑えられ、また、Ｃｕ配線２、２’上にはボンディングパッド開口部９が形成されていないため、プロービングによる影響を受けることもなく、高い信頼性、歩留りを得ることができる。
【００１６】
（実施形態２）
図４に第２の実施形態に係る半導体装置の構造を示す。所定パターンの実施形態１より幅広のＣｕ配線１２がライナーバリアメタル層１３を介してＴＥＯＳ層間膜１４に埋め込み形成されており、これらの上層に所定パターンのバリアメタル層１５、Ａｌ合金からなるパッドメタル層１６が形成されている。最上層にはＳｉＮ層１７を介してパッシベーション膜１８が形成されており、パッドメタル層１６のＣｕ配線１２上を含む領域に達するボンディングパッド開口部１９が設けられている。このような半導体装置は、パターンが異なるが、実施形態１と同様に形成される。
【００１７】
本実施形態に係る半導体装置においては、ボンディングパッド開口部１９を広く取ることにより、露出したパッドメタル層１６に、ボンディング領域１６ａとプロービング領域１６ｂをそれぞれ設けることができる。すなわち、露出したパッドメタル層１６のＣｕ配線１２上の領域をボンディング領域１６ａとし、Ｃｕ配線１２上以外の領域をプロービング領域１６ｂとすることにより、プロービング領域１６ｂにおいてプロービングを行ったとしても、ボンディングはボンディング領域１６ａにおいてを行うため、Ｃｕ酸化によるボンディング強度劣化を生じることはない。このとき、ボンディング領域１６ａとプロービング領域１６ｂは同一パッドメタル層に形成される必要があるが、必ずしも開口部は連続していなくても良く、パッシベーション膜１８で分離されていても良い。
【００１８】
（実施形態３）
図５に第３の実施形態に係る半導体装置の構造を示す。所定パターンのＣｕ配線２２、２２’がライナーバリアメタル層２３を介してＴＥＯＳ層間膜２４に埋め込み形成されており、Ｃｕ配線２２、２２’を全て被覆するように所定パターンのバリアメタル層２５、２５’、Ａｌ合金からなるパッドメタル層２６、２６’が形成されている。最上層にはＳｉＮ層を介することなくパッシベーション膜２８が形成されており、パッドメタル層２６の所定領域に達するボンディングパッド開口部２９が設けられている。本実施形態においては実施形態１、２と異なり、ボンディングパッド開口部２９の形成されないＣｕ配線２２’上にもバリアメタル層２５’、パッドメタル層２６’が形成されている。このような半導体装置は、パターン、ＳｉＮ層は形成されない点で異なるが、実施形態１と同様に形成される。
【００１９】
本実施形態に係る半導体装置においては、Ｃｕ配線２２’が、バリアメタル層２５、パッドメタル層２６のパターニングの際に露出しないので、酸化防止のためのＳｉＮ層を形成する必要がない。また、パターニングの際オーバーエッチングされ、実質的なＣｕ配線厚の目減りにより配線抵抗が増大する懸念もなくなる。従って、ＳｉＮ層形成工程を削減することができるとともに、信頼性、特性安定性を向上することができる。
【００２０】
本実施形態においては、Ｃｕ配線上にはボンディングパッド開口部を形成していないが、実施形態２と同様にボンディング領域、プロービング領域を形成してもよい。
【００２１】
これら実施形態において、パッドメタル層にＡｌ合金を用いているが、ＡｌＣｕ、ＡｌＳｉＣｕといった合金や、Ａｌ単体も用いることができる。また、バリアメタル層には、Ｔａ／ＴａＮ、Ｔｉ／ＴｉＮ、Ｔａ／ＴａＮ／Ｔｉ／ＴｉＮ等の積層膜を用いることができる。そして、ライナーバリアメタルには、ＴａＮ／Ｔａ等同様の積層膜を用いることができる。
【００２２】
【発明の効果】
本発明によれば、ボンディング強度の低下を抑え、信頼性、歩留りの高い半導体装置を提供することができる。
【図面の簡単な説明】
【図１】本発明の第１の実施形態に係る半導体装置の構造を示す図。
【図２】本発明の半導体装置の製造工程を示す図。
【図３】本発明の半導体装置の製造工程を示す図。
【図４】本発明の第２の実施形態に係る半導体装置の構造を示す図。
【図５】本発明の第３の実施形態に係る半導体装置の構造を示す図。
【図６】従来の半導体装置の構造を示す図。
【図７】従来の半導体装置の問題を示す図。
【図８】従来の半導体装置の構造を示す図。
【符号の説明】
１ 素子領域の形成された半導体基板
２、２’、１２、２２、２２’、３２、４２ Ｃｕ配線
３、１３、２３、３３、４３ ライナーバリアメタル層
４、１４、２４、３４、３４’、４４、４４’ ＴＥＯＳ層間膜
５、１５、２５、２５’、３５、４５ バリアメタル層
６、１６、２６、２６’、３６、４６ パッドメタル層
１６ａ ボンディング領域
１６ｂ プロービング領域
７、１７、３７、４７ ＳｉＮ層
８、１８、２８、３８、４８ パッシベーション膜
９、１９、２９、３９、４９ ボンディングパッド開口部
１０、１０’フォトレジスト
４０ プローブ
５０ ヴィア[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device with improved reliability in a bonding pad portion.
[0002]
[Prior art]
In recent years, in response to demands for miniaturization and high speed of semiconductor devices, introduction of Cu wiring instead of conventional Al wiring has been promoted. By using the Cu wiring, it is possible to reduce the wiring resistance which is increased by miniaturization of the element, shorten the delay time during signal transmission, and improve the processing speed. However, unlike the Al wiring, the Cu wiring has a problem that oxidation proceeds in the depth direction and direct bonding is difficult.
[0003]
In order to solve such a problem, a method of forming an Al alloy layer as an uppermost layer as a bonding pad is generally adopted. FIG. 6 shows the structure of the bonding pad portion. As shown in the figure, a pad metal layer 36 made of an Al alloy is formed on a Cu wiring 32 formed on a semiconductor substrate 1 on which an element region is formed via a liner barrier metal layer 33 via a barrier metal layer 35. And are patterned in the interlayer insulating films 34 and 34 ', respectively. A passivation film 38 is formed on the uppermost layer, and a bonding pad opening 39 reaching the pad metal layer is provided.
[0004]
Then, such a bonding pad portion is formed using a conventional Al multilayer wiring forming process as described below. First, after forming an element region on a semiconductor substrate, an interlayer insulating film 34 is formed, a groove having a predetermined pattern is formed, a liner barrier metal 32 is formed, and a Cu wiring 32 is formed by a damascene technique. Next, a SiN layer 37 for preventing Cu oxidation and an interlayer insulating film 34 'are sequentially formed on the entire surface, a contact hole is formed at a predetermined position on the Cu wiring 32, and a barrier metal layer 35 is formed on the entire surface including the contact hole by sputtering. A pad metal layer 36 is formed, patterned so as to remain inside the contact hole, a passivation film 38 is formed, and a bonding pad opening 39 reaching the pad metal layer 36 is formed at a predetermined position.
[0005]
[Problems to be solved by the invention]
However, in such a structure of the bonding pad portion, since the Cu wiring is formed immediately below the opening of the bonding pad, as shown in FIG. 7, a probe 40 having a diameter of about several tens μm is brought into contact (probing) with the bonding pad. In a D / S test (Die Sort: determination of good / bad) in which an operation test is performed, the underlying Cu wiring 32 is exposed and oxidized, and the bonding strength is reduced. Therefore, as shown in FIG. 8, the Cu wiring 42 is not formed immediately below the opening of the bonding pad by the technique of connecting the Cu wiring 42 and the pad metal layer 46 via the via 50, and the exposure of Cu by probing is not performed. However, the surface of the interlayer insulating film is damaged at the time of photoresist ashing after the opening of the via 50 or at the time of etching the SiN film 47, and the adhesion strength with the barrier metal layer 45 and the pad metal layer 46 formed thereon is deteriorated. Therefore, the bonding strength is reduced. Further, since the pad metal layer 46 is formed on the region including the via 50 by sputtering, there is a concern that electromigration failure due to step coverage deterioration of the via 50 portion may occur.
[0006]
SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device having high reliability and a high yield, which eliminates the drawbacks of the conventional semiconductor device, suppresses a decrease in bonding strength, and provides a high reliability.
[0007]
[Means for Solving the Problems]
A semiconductor device according to the present invention includes a first insulating layer formed on a semiconductor substrate, and a Cu wiring layer having a predetermined pattern embedded in the first insulating layer so that the upper surface is substantially flush with the first insulating layer. A pad metal layer having a predetermined pattern formed on the upper surface of the first insulating layer and the Cu wiring layer and electrically connected to the Cu wiring layer; and a second insulating layer covering these layers. And an opening reaching the pad metal layer from the surface of the second insulating layer.
[0008]
Further, in the semiconductor device according to the present invention, the Cu wiring layer is not formed immediately below the opening of the pad metal layer.
[0009]
The semiconductor device according to the present invention is characterized in that the second insulating layer is formed via a SiN layer.
[0010]
Further, in the semiconductor device according to the present invention, the second insulating layer is formed on the Cu wiring layer via the pad metal layer.
[0011]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0012]
(Embodiment 1)
FIG. 1 shows the structure of the semiconductor device according to the first embodiment. On a semiconductor substrate 1 on which an element region is formed, Cu wirings 2 and 2 ′ of a predetermined pattern are buried and formed in a TEOS interlayer film (first insulating layer) 4 via a liner barrier metal layer 3, A barrier metal layer 5 having a predetermined pattern and a pad metal layer 6 made of an Al alloy are formed in a part of the upper layer including the metal layer 2. In the uppermost layer, a passivation film 8 (second insulating layer) is formed via a SiN layer 7, and a bonding pad opening 9 reaching a predetermined region of the pad metal layer 6 is provided.
[0013]
Such a semiconductor device is formed as follows. First, as shown in FIG. 2A, a groove having a predetermined pattern is formed in the TEOS interlayer film 4, the liner barrier metal layer 3 is sputtered, and then Cu wirings 2, 2 'are formed in the groove by plating. As shown in (b), the Cu and the liner barrier metal other than the groove portions are removed by the CMP method, the TEOS interlayer film is further polished, the entire surface is flattened, and the Cu wirings 2 and 2 ′, the liner barrier metal layer 3 and the TEOS An interlayer film 4 is formed. As shown in (c), a barrier metal 5 and a pad metal 6 are sequentially sputtered thereon, and as shown in (d), the photoresist 10 is processed into a predetermined pattern by a lithography technique.
[0014]
Then, as shown in FIG. 3A, a barrier metal layer 5 / pad metal layer 6 having a predetermined pattern is formed by RIE technique, and as shown in FIG. 3B, for preventing oxidation of the exposed Cu wiring 2 '. After the SiN layer 7 and the passivation film 8 are sequentially deposited by CVD, the photoresist 10 'is patterned as shown in FIG. At this time, a resist pattern is formed on the Cu wirings 2 and 2 'without forming an opening. Then, a bonding pad opening 9 reaching the pad metal layer 6 is formed in the passivation film 8 and the SiN layer 7 by RIE technology, and the photoresist 10 'is removed to form a semiconductor device as shown in FIG.
[0015]
In the semiconductor device formed in this manner, since it is not necessary to form a via, electromigration failure is suppressed, and the bonding pad opening 9 is not formed on the Cu wirings 2 and 2 ′. High reliability and yield can be obtained without being affected by probing.
[0016]
(Embodiment 2)
FIG. 4 shows the structure of the semiconductor device according to the second embodiment. A Cu wiring 12 wider than that of the first embodiment having a predetermined pattern is embedded in the TEOS interlayer film 14 via a liner barrier metal layer 13, and a barrier metal layer 15 of a predetermined pattern and a pad metal made of an Al alloy are formed thereon. A layer 16 has been formed. A passivation film 18 is formed on the uppermost layer via a SiN layer 17, and a bonding pad opening 19 is provided to reach a region of the pad metal layer 16 including the area above the Cu wiring 12. Such a semiconductor device has a different pattern, but is formed in the same manner as in the first embodiment.
[0017]
In the semiconductor device according to the present embodiment, by making the bonding pad opening 19 wide, the exposed pad metal layer 16 can be provided with the bonding region 16a and the probing region 16b. That is, by setting the exposed region of the pad metal layer 16 on the Cu wiring 12 as the bonding region 16a and the region other than on the Cu wiring 12 as the probing region 16b, even if the probing is performed in the probing region 16b, the bonding can be performed. Since the bonding is performed in the bonding region 16a, the bonding strength does not deteriorate due to Cu oxidation. At this time, the bonding region 16a and the probing region 16b need to be formed in the same pad metal layer, but the openings are not necessarily continuous and may be separated by the passivation film 18.
[0018]
(Embodiment 3)
FIG. 5 shows the structure of the semiconductor device according to the third embodiment. Predetermined patterns of Cu wirings 22 and 22 ′ are buried in the TEOS interlayer film 24 via a liner barrier metal layer 23, and have a predetermined pattern of barrier metal layers 25 and 25 so as to cover all the Cu wirings 22 and 22 ′. ', Pad metal layers 26 and 26' made of an Al alloy are formed. A passivation film 28 is formed on the uppermost layer without interposing the SiN layer, and a bonding pad opening 29 reaching a predetermined region of the pad metal layer 26 is provided. In the present embodiment, unlike Embodiments 1 and 2, a barrier metal layer 25 'and a pad metal layer 26' are also formed on the Cu wiring 22 'where the bonding pad opening 29 is not formed. Such a semiconductor device is formed in the same manner as the first embodiment, except that the pattern and the SiN layer are not formed.
[0019]
In the semiconductor device according to the present embodiment, since the Cu wiring 22 'is not exposed during the patterning of the barrier metal layer 25 and the pad metal layer 26, there is no need to form a SiN layer for preventing oxidation. Further, there is no concern that the wiring resistance is increased due to over-etching during the patterning and substantial decrease in the thickness of the Cu wiring. Therefore, the number of steps for forming the SiN layer can be reduced, and the reliability and the characteristic stability can be improved.
[0020]
In this embodiment, the bonding pad opening is not formed on the Cu wiring, but a bonding region and a probing region may be formed as in the second embodiment.
[0021]
In these embodiments, an Al alloy is used for the pad metal layer, but an alloy such as AlCu or AlSiCu, or Al alone can also be used. In addition, a laminated film of Ta / TaN, Ti / TiN, Ta / TaN / Ti / TiN, or the like can be used for the barrier metal layer. Then, a similar laminated film such as TaN / Ta can be used for the liner barrier metal.
[0022]
【The invention's effect】
According to the present invention, it is possible to provide a semiconductor device having high reliability and high yield while suppressing a decrease in bonding strength.
[Brief description of the drawings]
FIG. 1 is a diagram showing a structure of a semiconductor device according to a first embodiment of the present invention.
FIG. 2 is a diagram showing a manufacturing process of the semiconductor device of the present invention.
FIG. 3 is a view showing a manufacturing process of the semiconductor device of the present invention.
FIG. 4 is a diagram showing a structure of a semiconductor device according to a second embodiment of the present invention.
FIG. 5 is a view showing a structure of a semiconductor device according to a third embodiment of the present invention.
FIG. 6 illustrates a structure of a conventional semiconductor device.
FIG. 7 illustrates a problem of a conventional semiconductor device.
FIG. 8 illustrates a structure of a conventional semiconductor device.
[Explanation of symbols]
1 Semiconductor substrate 2, 2 ', 12, 22, 22', 32, 42 on which element regions are formed Cu wirings 3, 13, 23, 33, 43 Liner barrier metal layers 4, 14, 24, 34, 34 ', 44, 44 'TEOS interlayer film 5, 15, 25, 25', 35, 45 Barrier metal layer 6, 16, 26, 26 ', 36, 46 Pad metal layer 16a Bonding region 16b Probing region 7, 17, 37, 47 SiN layers 8, 18, 28, 38, 48 Passivation films 9, 19, 29, 39, 49 Bonding pad openings 10, 10 'photoresist 40 Probe 50 Via

Claims (4)

半導体基板上に形成された第１の絶縁層と、この第１の絶縁層中に、上面が実質的に同一平面となるよう埋め込まれた所定パターンのＣｕ配線層と、前記第１の絶縁層及び前記Ｃｕ配線層の上面上に形成され、前記Ｃｕ配線層と電気的に接続された所定パターンのパッドメタル層と、これら各層を被覆する第２の絶縁層を備え、この第２の絶縁層表面より前記パッドメタル層に達する開口部を有することを特徴とする半導体装置。A first insulating layer formed on a semiconductor substrate, a Cu wiring layer having a predetermined pattern embedded in the first insulating layer so that an upper surface thereof is substantially flush with the first insulating layer; And a pad metal layer of a predetermined pattern formed on the upper surface of the Cu wiring layer and electrically connected to the Cu wiring layer, and a second insulating layer covering each of these layers. A semiconductor device having an opening reaching a pad metal layer from a surface. 前記パッドメタル層の前記開口部直下には、前記Ｃｕ配線層が形成されていないことを特徴とする請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein the Cu wiring layer is not formed immediately below the opening of the pad metal layer. 前記第２の絶縁層は、ＳｉＮ層を介して形成されることを特徴とする請求項１又は２記載の半導体装置。3. The semiconductor device according to claim 1, wherein the second insulating layer is formed via a SiN layer. 前記Ｃｕ配線層上には、前記パッドメタル層を介して前記第２の絶縁層が形成されていることを特徴とする請求項１乃至３記載の半導体装置。4. The semiconductor device according to claim 1, wherein the second insulating layer is formed on the Cu wiring layer via the pad metal layer.
JP2003102842A 2003-04-07 2003-04-07 Semiconductor device Pending JP2004311697A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013136388A1 (en) * 2012-03-14 2013-09-19 パナソニック株式会社 Semiconductor device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013136388A1 (en) * 2012-03-14 2013-09-19 パナソニック株式会社 Semiconductor device
CN103650131A (en) * 2012-03-14 2014-03-19 松下电器产业株式会社 Semiconductor device
US8766418B2 (en) 2012-03-14 2014-07-01 Panasonic Corporation Semiconductor device
JPWO2013136388A1 (en) * 2012-03-14 2015-07-30 パナソニック株式会社 Semiconductor device
CN103650131B (en) * 2012-03-14 2016-12-21 松下电器产业株式会社 Semiconductor device

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