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JP2004140093A - Bonding pad and method for forming the same - Google Patents

Bonding pad and method for forming the same Download PDF

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Publication number
JP2004140093A
JP2004140093A JP2002301989A JP2002301989A JP2004140093A JP 2004140093 A JP2004140093 A JP 2004140093A JP 2002301989 A JP2002301989 A JP 2002301989A JP 2002301989 A JP2002301989 A JP 2002301989A JP 2004140093 A JP2004140093 A JP 2004140093A
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metal
metal layer
insulating layer
layer
forming
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JP3970150B2 (en
Inventor
Shinya Mori
森　真也
Junji Yamada
山田　順治
Yutaka Yamada
山田　裕
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Sanyo Electric Co Ltd
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Sanyo Electric Co Ltd
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To improve bonding wire adhesion to a multilayer metal bonding pad. <P>SOLUTION: A recess 9a present in tungsten 9 imbedded in a second via 8 results in a recess 10a in a third metal layer 10 formed on the second via 8. Consequently, a irregularity is formed on the third metal layer 10, and this enlarges the surface area and improves bonding wire adhesion. Providing a plurality of second vias 8 designed as such enlarges the surface areas of recesses 9a and increases corrugations on the third metal layer 10, and this further improves bonding wire adhesion. <P>COPYRIGHT: (C)2004,JPO

Description

【０００１】
【発明の属する技術分野】
本発明は、多層メタルから成るボンディングパッド及びその形成方法に関する。
【０００２】
【従来の技術】
近年、半導体集積回路の高集積化のために多層メタル配線が広く用いられている。図５は、２層メタル配線の半導体集積回路のボンディングパッド構造を示す断面図である。半導体基板１００の表面には、内部回路（不図示）に接続された第１のＡｌ層１０１が形成されている。また、第１のＡｌ層１０１上にはシリコン窒化膜やＳｉＯ２膜等の絶縁膜１０２が形成され、この絶縁層１０２にビア１０３が形成され、この開口部１０３を介して上層の第２のＡｌ層１０４と下層の第１のＡｌ層１０１とが電気的に接続されている。そして、ビア１０３で露出された第２のＡｌ層１０４の表面に、ボンディングマシンにより、Ａｕ等から成るボンディングワイヤー（不図示）が圧着される。
【０００３】
図５では、絶縁層１０２に１つのビア１０３が形成されているが、以下の特許文献１には、絶縁層に複数のビアを形成して、これらの複数のビアを介して上層と下層の金属層を電気的に接続する技術が記載されている。
【０００４】
【特許文献１】
特開昭６１−５９８５５号公報
【０００５】
【発明が解決しようとする課題】
しかしながら、図５に示した構造では、第２のＡｌ層１０４の表面がほぼ平坦（ビア１０３のエッジ部を除く）であるために、ボンディングワイヤーとの密着性が悪く、接触不良が生じる場合があった。また、絶縁層に形成される大きなビアを１つ形成した構造では、ビア１０３のエッジ部で第２のＡｌ層１０４の段差が大きくなり、第２のＡｌ層１０４のパターニングが難しくなる。これは段差があるために、レジスト露光時に焦点深度の差が生じるためである。図５には２層メタルのボンディングパッド構造を示したが３層メタル以上のボンディングパッド構造では更に上層のメタルの段差が大きくなり、メタルのパターニングが益々難しくなる。
【０００６】
【課題を解決するための手段】
そこで本発明は、下層の金属層上に絶縁層を形成し、この絶縁層にビアを形成し、このビアの上部に凹部が形成されるようにビアの深さの途中まで金属を埋め込み、上層の金属層を形成して、上層の配線層と下層の配線層とをビアに埋め込まれた金属を通して電気的に接続するようにした。
【０００７】
本発明によれば、ビアに埋め込まれた金属には凹部があるので、このビア上に形成された上層の金属層にはこの凹部を反映して凹部が形成される。これにより、
上層の金属層の表面には凹凸が形成され、この上層の金属層にボンディングを行えば、ボンディングワイヤーの密着性が向上する。
【０００８】
そして、そのようなビアを複数設けることで、ビアに埋め込まれた金属の凹部の面積が増加して、上層の金属層の凹凸が増加するため、その表面積が増大し、ボンディングワイヤーの密着性は更に向上する。
【０００９】
また、ビアを複数設ける代わりに、そのようなビアをストライプパターンに形成しても、同様に凹部の面積が増加して、上層の金属層の凹凸が増加するため、ボンディングワイヤーの密着性は更に向上する。
【００１０】
【発明の実施の形態】
次に、本発明の実施形態について図面を参照しながら詳細に説明する。図１は第１の実施形態に係るボンディングパッドを説明する図であり、図１（Ａ）は平面図であり、図１（Ｂ）は図１（Ａ）のＸ−Ｘ線に沿った断面図である。
【００１１】
例えばＳｉ基板等の半導体基板１上に第１の金属層２が形成されている。この第１の金属層２は、半導体基板１上に形成された半導体集積回路の内部回路（不図示）、例えば入力回路や出力回路に接続されている。図１（Ｂ）において第１の金属層２は半導体基板１上に直接形成されているが、通常はシリコン酸化層等の絶縁層上に形成される。
【００１２】
この第１の金属層２上には複数の第１のビア４を有する第１の絶縁層３が形成され、この複数の第１のビア４に高融点金属、例えばタングステン（Ｗ）５が埋め込まれている。このタングステン５がビア４の深さの途中まで埋め込まれ、タングステン５は第１のビア４の上部に凹部５ａを有している。
【００１３】
そして、第１の絶縁層３上には第２の金属層６が形成されている。この第２の金属層６はスパッタで形成され、タングステン５の凹部５ａを反映して、表面に凹部６ａが形成されている。
【００１４】
更に、この第２の金属層６上には複数のビア８を有する第２の絶縁層７が形成され、この複数の第２のビア８に高融点金属、例えばタングステン（Ｗ）９が埋め込まれている。このタングステン９が第２のビア８の深さの途中まで埋め込まれ、タングステン９は第２のビア８の上部に凹部９ａを有している。
【００１５】
そして、第２の絶縁層７上には第３の金属層１０が形成されている。この第３の金属層１０はスパッタで形成され、タングステン６，９の凹部６ａ，９ａを反映して、凹部１０ａを有している。更に、最上層の第３の絶縁層１０が形成されている。この第３の絶縁層１１には、第３の金属層１０を露出するための開口部１２が設けられている。
【００１６】
このように、第３の絶縁層１１の開口部１２によって露出された第３の金属層１０の表面には凹凸が形成されるため、その表面積が増大し、この第３の金属層１０の表面に圧着されボンディングワイヤーの密着性が向上する。
【００１７】
次に、図１に示したボンディングパッドの形成方法について図２、図３を参照しながら説明する。
【００１８】
まず、図２（Ａ）に示すように、半導体基板１上にＡｌ、Ａｌ−Ｓｉ合金、Ａｌ−Ｓｉ−Ｃｕ合金等の金属をスパッタし、これを選択的にエッチングすることにより第１の金属層２を形成する。第１の金属層２の厚さは例えば１μｍ程度である。そして、ＣＶＤ法によりＳｉＯ２のような絶縁物を全面に例えば、８００ｎｍの厚さに堆積し、第１の絶縁層３を形成する。
【００１９】
次に図２（Ｂ）に示すように、ドライエッチング法を用いて第１の絶縁層３に複数の第１のビア４を形成する。ここで、第１のビア４の開口径はデザインルールによるが、例えば０．５μｍである。
【００２０】
次に図２（Ｃ）に示すように、ＣＶＤ法によりタングステン５を全面に堆積させる。すると、複数の第１のビア４はタングステン５によって埋め込まれる。ここで、複数の第１のビア４内に埋め込まれたタングステン５にはその上面に凹部５ａが形成される。
【００２１】
そして、図２（Ｄ）に示すように、全面に堆積されたタングステン５を第１の絶縁層３の表面までエッチバックすることにより、複数の第１のビア４内にのみタングステン５を残存させる。このエッチバックに用いられるエッチングガスは例えばＳＦ６ガスとＡｒガスの混合ガスである。
【００２２】
ここで、堆積時に複数の第１のビア４内のタングステン５の上面には凹部が形成されているので、この形状が上層に反映される。この結果、タングステン５はビア４の深さの途中まで埋め込まれ、タングステン５は第１のビア４の上部に、その上面に凹部５ａを有することになる。そして、更にエッチバックを続け、オーバーエッチすることでさらに凹部５ａの深さを大きくできる。
【００２３】
ここで、第１のビア４の開口径が０．５μｍ、第１の絶縁層３の厚さが８００ｎｍの場合には、タングステン５の凹部５ａの深さ（第１の絶縁層３の表面から凹部５ａの最も窪んだ部分までの距離ｈ１）は１００ｎｍ〜２００ｎｍとなる。
【００２４】
次に図３（Ａ）に示すように、Ａｌ、Ａｌ−Ｓｉ合金、Ａｌ−Ｓｉ−Ｃｕ合金等の金属をスパッタし、これを選択的にエッチングすることにより第２の金属層６を形成する。第２の金属層６の厚さは例えば１μｍ程度である。第２の金属層６の表面には、タングステン５の凹部５ａを反映して、凹部６ａが形成されている。
【００２５】
そして、図３（Ｂ）に示すように、ＣＶＤ法によりＳｉＯ２のような絶縁物を全面に例えば、８００ｎｍの厚さに堆積し、第２の絶縁層７を形成する。その後、第２の絶縁層に複数の第２のビア８を形成し、上記と同様の方法（タングステンの全面ＣＶＤ＋タングステンのエッチバック）により、この複数の第２のビア８にタングステン９を、第２のビア８の深さの途中まで埋め込む。こうして、タングステン９は第２のビア８の上部に、その上面に凹部９ａを有するように加工される。
【００２６】
ここで、第２のビア８の開口径が０．５μｍ、第２の絶縁層７の厚さが８００ｎｍの場合には、タングステン９の凹部９ａの深さ（第２の絶縁層７の表面から凹部９ａの最も窪んだ部分までの距離ｈ２）は１００ｎｍ〜２００ｎｍとなる。
【００２７】
次に図３（Ｃ）に示すように、Ａｌ、Ａｌ−Ｓｉ合金、Ａｌ−Ｓｉ−Ｃｕ合金等の金属をスパッタし、これを選択的にエッチングすることにより最上層の第３の金属層１０を形成する。この第３の金属層１０は、タングステン６，９の凹部６ａ，９ａを反映して、その表面に多数の凹部１０ａを有している。
【００２８】
そして、図１（Ｂ）に示すように、全面にシリコン窒化膜等をＣＶＤ法により堆積し、このシリコン窒化膜を選択的にエッチングすることにより、第３の金属層１０を露出するための開口部１２を有する第３の絶縁層１１を形成する。
【００２９】
このように、第３の絶縁層１１の開口部１２によって露出された第３の金属層１０の表面には多数の凹凸が形成されるため、その表面積が増大し、この第３の金属層１０の表面に圧着されボンディングワイヤーの密着性が向上する。
【００３０】
また、本実施形態において、第１のビア４と第２のビア８の数を増やすことにより、第３の金属層１０の表面には、より多くの凹凸が形成され、その分ボンディングワイヤーの密着性が向上し、しかも第２の金属層６、第３の金属層１０を平坦化することができる。
【００３１】
また、図１のように、第１のビア４と第２のビア８の形成位置をずらすことで、第３の金属層１０の表面には、タングステン６の凹部６ａとタングステン９の凹部９ａを反映した多くの凹凸が形成され、ボンディングワイヤーの密着性が更に向上する。
【００３２】
なお、本実施形態では、３層メタルのボンディングパッドを例として説明したが、同様の構造を繰り返し積み上げることで４層以上の多層メタルのボンディングパッドについても形成することができる。また、２層メタルのボンディングパッドについても同様に適用できる。この場合は、第１の金属層２、第１の絶縁層３、第１のビア４、タングステン５、第２の金属層６を上記と同様に形成し、最上層の絶縁層（不図示）を形成し、この絶縁層に第２の金属層６を露出するための開口部（不図示）を形成すればよい。
【００３３】
また、本実施形態では、第１の絶縁層３に形成された第１のビア４にタングステン５を第１のビア４の深さの途中まで埋め込み、タングステン５の上面に凹部５ａを形成しているが、本発明は、この第１のビア４については、タングステン５を第１のビア４を完全に充填するように埋め込み、タングステン５の上面が平坦になっているものも含む。つまり、第２の絶縁層７に形成された第２のビア８に、埋め込まれたタングステン９がその上面に凹部９ａを有していれば、その凹部９ａを反映して最上層の第３の金属層１０に凹凸は形成される。この点は、以下に説明する第２の実施形態についても同様である。
【００３４】
次に、本発明の第２の実施形態について図面を参照しながら詳細に説明する。図４は第２の実施形態に係るボンディングパッドを説明する図であり、図４（Ａ）は平面図であり、図４（Ｂ）は図４（Ａ）のＸ−Ｘ線に沿った断面図である。
【００３５】
本実施形態では、第１のビア４、第２のビア８のパターン形状に特徴がある。すなわち、第１のビア４は図４（Ａ）に示すように、１つのストライプパターンの形状を呈している。また、第２のビア８も、１つのストライプパターンの形状を呈している。これらの第１のビア４と第２のビア８は、平面的に見ると、互いにずらして配置されている。
【００３６】
本実施形態においても、第１の実施形態と同様に、例えば第２のビア８については、タングステン９が第２のビア８の深さの途中まで埋め込まれ、タングステン９の上面には凹部９ａが形成されている。このため、最上層の第３の金属層９の表面には多数の凹凸が形成される。特に、本実施形態によれば、ビアをストライプパターン形状にしたので、第１の実施形態に比して、タングステン５の凹部５ａ、タングステン９の凹部９の深さｈ１，ｈ２がより深くなる。これは、タングステン５，９をＣＶＤ法により堆積する際に、ストライプパターンのビアが比較的埋まりにくいためである。このため、最上層の第３の金属層９の表面にはより大きな凹凸が形成され、その表面積がより増大し、ボンディングワイヤーの密着性をより高めることが可能になる。
【００３７】
【発明の効果】
本発明によれば、ビアの深さの途中まで金属を埋め込み、その上部に凹部を形成するようにしたので、このビア上に形成された上層の金属層にはこの凹部を反映して凹部が形成される。これにより、上層の金属層の表面には凹凸が形成され、その表面積が増大するので、この上層の金属層にボンディングを行えば、ボンディングワイヤーの密着性が向上する。そして、ビアを複数設けることで、金属層を平坦化し、金属層のパターニングに伴う問題を解消することができる。
【図面の簡単な説明】
【図１】本発明の第１の実施形態に係るボンディングパッド及びその形成方法を説明する図である。
【図２】本発明の第１の実施形態に係るボンディングパッドの形成方法を説明する断面図である。
【図３】本発明の第１の実施形態に係るボンディングパッドの形成方法を説明する断面図である。
【図４】本発明の第２の実施形態に係るボンディングパッド及びその形成方法を説明する図である。
【図５】従来例のボンディングパッドを説明する断面図である。[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a bonding pad made of a multilayer metal and a method for forming the same.
[0002]
[Prior art]
2. Description of the Related Art In recent years, multilayer metal wiring has been widely used for high integration of semiconductor integrated circuits. FIG. 5 is a sectional view showing a bonding pad structure of a semiconductor integrated circuit having two-layer metal wiring. On the surface of the semiconductor substrate 100, a first Al layer 101 connected to an internal circuit (not shown) is formed. An insulating film 102 such as a silicon nitride film or a SiO 2 film is formed on the first Al layer 101, a via 103 is formed in the insulating layer 102, and an upper second Al layer is formed through the opening 103. The layer 104 and the lower first Al layer 101 are electrically connected. Then, a bonding wire (not shown) made of Au or the like is pressure-bonded to the surface of the second Al layer 104 exposed by the via 103 by a bonding machine.
[0003]
In FIG. 5, one via 103 is formed in the insulating layer 102. However, in Patent Document 1 below, a plurality of vias are formed in the insulating layer, and upper and lower layers are formed through the plurality of vias. A technique for electrically connecting metal layers is described.
[0004]
[Patent Document 1]
JP-A-61-59855 [0005]
[Problems to be solved by the invention]
However, in the structure shown in FIG. 5, since the surface of the second Al layer 104 is almost flat (excluding the edge of the via 103), the adhesion to the bonding wire is poor, and a contact failure may occur. there were. Further, in the structure in which one large via formed in the insulating layer is formed, the step of the second Al layer 104 is large at the edge of the via 103, and it is difficult to pattern the second Al layer 104. This is because there is a step, which causes a difference in the depth of focus during resist exposure. FIG. 5 shows a bonding pad structure of a two-layer metal. However, in a bonding pad structure of a three-layer metal or more, the step of the metal in the upper layer is further increased, and patterning of the metal becomes more difficult.
[0006]
[Means for Solving the Problems]
Accordingly, the present invention provides an insulating layer formed on a lower metal layer, a via formed in the insulating layer, and a metal buried halfway in the depth of the via so that a recess is formed in an upper portion of the via, and an upper layer is formed. The upper wiring layer and the lower wiring layer are electrically connected to each other through the metal embedded in the via.
[0007]
According to the present invention, since the metal embedded in the via has a concave portion, the concave portion is formed in the upper metal layer formed on the via reflecting the concave portion. This allows
Irregularities are formed on the surface of the upper metal layer, and bonding to the upper metal layer improves the adhesion of the bonding wire.
[0008]
By providing a plurality of such vias, the area of the concave portion of the metal embedded in the via increases, and the unevenness of the upper metal layer increases, so that the surface area increases, and the adhesion of the bonding wire increases. Further improve.
[0009]
Also, instead of providing a plurality of vias, even if such vias are formed in a stripe pattern, the area of the concave portion similarly increases, and the unevenness of the upper metal layer increases. improves.
[0010]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a view for explaining a bonding pad according to a first embodiment, FIG. 1A is a plan view, and FIG. 1B is a cross section taken along line XX of FIG. 1A. FIG.
[0011]
For example, a first metal layer 2 is formed on a semiconductor substrate 1 such as a Si substrate. The first metal layer 2 is connected to an internal circuit (not shown) of the semiconductor integrated circuit formed on the semiconductor substrate 1, for example, an input circuit and an output circuit. In FIG. 1B, the first metal layer 2 is formed directly on the semiconductor substrate 1, but is usually formed on an insulating layer such as a silicon oxide layer.
[0012]
A first insulating layer 3 having a plurality of first vias 4 is formed on the first metal layer 2, and a refractory metal, for example, tungsten (W) 5 is embedded in the plurality of first vias 4. Have been. This tungsten 5 is buried halfway through the depth of the via 4, and the tungsten 5 has a recess 5 a above the first via 4.
[0013]
Then, a second metal layer 6 is formed on the first insulating layer 3. The second metal layer 6 is formed by sputtering, and a concave portion 6a is formed on the surface reflecting the concave portion 5a of the tungsten 5.
[0014]
Further, a second insulating layer 7 having a plurality of vias 8 is formed on the second metal layer 6, and a high melting point metal, for example, tungsten (W) 9 is embedded in the plurality of second vias 8. ing. The tungsten 9 is buried halfway in the depth of the second via 8, and the tungsten 9 has a concave portion 9 a above the second via 8.
[0015]
Then, a third metal layer 10 is formed on the second insulating layer 7. The third metal layer 10 is formed by sputtering, and has a concave portion 10a reflecting the concave portions 6a and 9a of tungsten 6,9. Further, an uppermost third insulating layer 10 is formed. An opening 12 for exposing the third metal layer 10 is provided in the third insulating layer 11.
[0016]
As described above, since the surface of the third metal layer 10 exposed by the opening 12 of the third insulating layer 11 has irregularities, the surface area increases, and the surface of the third metal layer 10 increases. To improve the adhesion of the bonding wire.
[0017]
Next, a method for forming the bonding pad shown in FIG. 1 will be described with reference to FIGS.
[0018]
First, as shown in FIG. 2A, a metal such as Al, an Al—Si alloy, or an Al—Si—Cu alloy is sputtered on a semiconductor substrate 1 and selectively etched to form a first metal. The layer 2 is formed. The thickness of the first metal layer 2 is, for example, about 1 μm. Then, an insulator such as SiO 2 is deposited on the entire surface to a thickness of, for example, 800 nm by a CVD method to form the first insulating layer 3.
[0019]
Next, as shown in FIG. 2B, a plurality of first vias 4 are formed in the first insulating layer 3 by using a dry etching method. Here, the opening diameter of the first via 4 depends on the design rule, but is, for example, 0.5 μm.
[0020]
Next, as shown in FIG. 2C, tungsten 5 is deposited on the entire surface by a CVD method. Then, the plurality of first vias 4 are filled with tungsten 5. Here, a recess 5 a is formed on the upper surface of the tungsten 5 embedded in the plurality of first vias 4.
[0021]
Then, as shown in FIG. 2D, the tungsten 5 deposited on the entire surface is etched back to the surface of the first insulating layer 3 so that the tungsten 5 remains only in the plurality of first vias 4. . The etching gas used for this etch back is, for example, a mixed gas of SF 6 gas and Ar gas.
[0022]
Here, since a concave portion is formed on the upper surface of the tungsten 5 in the plurality of first vias 4 at the time of deposition, this shape is reflected on the upper layer. As a result, the tungsten 5 is buried halfway through the depth of the via 4, and the tungsten 5 has a concave portion 5 a on the upper surface of the first via 4. The depth of the concave portion 5a can be further increased by continuing the etch back and performing the overetch.
[0023]
Here, when the opening diameter of the first via 4 is 0.5 μm and the thickness of the first insulating layer 3 is 800 nm, the depth of the concave portion 5 a of the tungsten 5 (from the surface of the first insulating layer 3). The distance h1) to the most concave portion of the concave portion 5a is 100 nm to 200 nm.
[0024]
Next, as shown in FIG. 3A, a metal such as Al, an Al-Si alloy, or an Al-Si-Cu alloy is sputtered, and the second metal layer 6 is formed by selectively etching the metal. . The thickness of the second metal layer 6 is, for example, about 1 μm. A concave portion 6a is formed on the surface of the second metal layer 6, reflecting the concave portion 5a of the tungsten 5.
[0025]
Then, as shown in FIG. 3B, an insulator such as SiO2 is deposited on the entire surface to a thickness of, for example, 800 nm by a CVD method, and a second insulating layer 7 is formed. Thereafter, a plurality of second vias 8 are formed in the second insulating layer, and tungsten 9 is formed in the plurality of second vias 8 by the same method as described above (entire CVD of tungsten + etch back of tungsten). 2 is buried halfway through the depth of the via 8. Thus, the tungsten 9 is processed so as to have a concave portion 9a on the upper surface of the second via 8 and on the upper surface thereof.
[0026]
Here, when the opening diameter of the second via 8 is 0.5 μm and the thickness of the second insulating layer 7 is 800 nm, the depth of the concave portion 9a of the tungsten 9 (from the surface of the second insulating layer 7) The distance h2) to the most depressed portion of the recess 9a is 100 nm to 200 nm.
[0027]
Next, as shown in FIG. 3C, a metal such as Al, an Al-Si alloy, or an Al-Si-Cu alloy is sputtered and selectively etched to thereby form the uppermost third metal layer 10. To form The third metal layer 10 has a large number of concave portions 10a on its surface, reflecting the concave portions 6a, 9a of tungsten 6,9.
[0028]
Then, as shown in FIG. 1B, a silicon nitride film or the like is deposited on the entire surface by a CVD method, and the silicon nitride film is selectively etched to form an opening for exposing the third metal layer 10. The third insulating layer 11 having the portion 12 is formed.
[0029]
As described above, since a large number of irregularities are formed on the surface of the third metal layer 10 exposed by the openings 12 of the third insulating layer 11, the surface area increases, and the third metal layer 10 Is pressed against the surface of the substrate to improve the adhesion of the bonding wire.
[0030]
In the present embodiment, by increasing the number of the first vias 4 and the second vias 8, more irregularities are formed on the surface of the third metal layer 10, and the adhesion of the bonding wires is correspondingly increased. Thus, the second metal layer 6 and the third metal layer 10 can be flattened.
[0031]
Also, as shown in FIG. 1, the positions of the first via 4 and the second via 8 are shifted to form a concave portion 6 a of tungsten 6 and a concave portion 9 a of tungsten 9 on the surface of the third metal layer 10. Many reflected irregularities are formed, and the adhesion of the bonding wire is further improved.
[0032]
In the present embodiment, a three-layer metal bonding pad has been described as an example, but a similar structure can be repeatedly stacked to form a four-layer or more multi-layer metal bonding pad. Further, the present invention can be similarly applied to a two-layer metal bonding pad. In this case, the first metal layer 2, the first insulating layer 3, the first via 4, the tungsten 5, and the second metal layer 6 are formed in the same manner as described above, and the uppermost insulating layer (not shown) And an opening (not shown) for exposing the second metal layer 6 may be formed in the insulating layer.
[0033]
Further, in the present embodiment, tungsten 5 is buried in the first via 4 formed in the first insulating layer 3 to the middle of the depth of the first via 4, and a concave portion 5 a is formed on the upper surface of the tungsten 5. However, the present invention includes a case where the first via 4 is filled with tungsten 5 so as to completely fill the first via 4 and the upper surface of the tungsten 5 is flat. In other words, if the tungsten 9 buried in the second via 8 formed in the second insulating layer 7 has the concave portion 9a on the upper surface, the third via of the uppermost layer is reflected by reflecting the concave portion 9a. The unevenness is formed on the metal layer 10. This is the same for the second embodiment described below.
[0034]
Next, a second embodiment of the present invention will be described in detail with reference to the drawings. 4A and 4B are views for explaining a bonding pad according to the second embodiment, FIG. 4A is a plan view, and FIG. 4B is a cross section taken along line XX of FIG. 4A. FIG.
[0035]
The present embodiment is characterized by the pattern shapes of the first via 4 and the second via 8. That is, the first via 4 has a shape of one stripe pattern as shown in FIG. The second via 8 also has the shape of one stripe pattern. The first via 4 and the second via 8 are arranged to be shifted from each other when viewed in a plan view.
[0036]
In the present embodiment, similarly to the first embodiment, for example, in the second via 8, the tungsten 9 is buried halfway in the depth of the second via 8, and a recess 9 a is formed on the upper surface of the tungsten 9. Is formed. For this reason, many irregularities are formed on the surface of the uppermost third metal layer 9. In particular, according to the present embodiment, the vias are formed in a stripe pattern, so that the depths h1 and h2 of the concave portions 5a of the tungsten 5 and the concave portions 9 of the tungsten 9 are larger than those of the first embodiment. This is because when the tungsten 5, 9 is deposited by the CVD method, the via of the stripe pattern is relatively difficult to fill. For this reason, larger irregularities are formed on the surface of the third metal layer 9 as the uppermost layer, the surface area thereof is further increased, and the adhesion of the bonding wire can be further enhanced.
[0037]
【The invention's effect】
According to the present invention, the metal is buried halfway through the depth of the via, and a recess is formed on the via. Therefore, the recess reflecting the recess is formed in the upper metal layer formed on the via. It is formed. As a result, irregularities are formed on the surface of the upper metal layer, and the surface area increases. Therefore, if bonding is performed on the upper metal layer, the adhesion of the bonding wire is improved. By providing a plurality of vias, the metal layer can be flattened, and problems associated with patterning the metal layer can be solved.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating a bonding pad and a method for forming the bonding pad according to a first embodiment of the present invention.
FIG. 2 is a sectional view illustrating a method for forming a bonding pad according to the first embodiment of the present invention.
FIG. 3 is a cross-sectional view illustrating a method for forming a bonding pad according to the first embodiment of the present invention.
FIG. 4 is a diagram illustrating a bonding pad and a method for forming the same according to a second embodiment of the present invention.
FIG. 5 is a cross-sectional view illustrating a conventional bonding pad.

Claims (16)

基板上に複数の金属層と複数の絶縁層が交互に積層され、
前記絶縁層に形成されたビアに埋め込まれた金属を通して前記金属層と前記絶縁層とが電気的に接続され、かつ最上層の金属層上に、この金属層を露出する開口部を有した最上層の絶縁層を有するボンディングパッドであって、前記金属は前記ビアの上部に凹部を有するように前記ビアの深さの途中まで埋め込まれ、前記最上層の金属層の表面が前記金属の凹部を反映して、凹凸を有することを特徴とするボンディングパッド。A plurality of metal layers and a plurality of insulating layers are alternately stacked on the substrate,
The metal layer and the insulating layer are electrically connected to each other through a metal embedded in a via formed in the insulating layer, and the uppermost metal layer has an opening exposing the metal layer. A bonding pad having an upper insulating layer, wherein the metal is buried halfway down the depth of the via so as to have a recess at the top of the via, and the surface of the uppermost metal layer covers the recess of the metal. A bonding pad characterized by having irregularities in reflection. 前記絶縁層は複数のビアを有することをすることを特徴とする請求項１記載のボンディングパッド。The bonding pad according to claim 1, wherein the insulating layer has a plurality of vias. 前記絶縁層はストライプパターンのビアを有することを特徴とする請求項１記載のボンディングパッド。The bonding pad according to claim 1, wherein the insulating layer has a via of a stripe pattern. 基板上に第１の金属層を形成する工程と、
前記第１の金属層上に第１の絶縁層を形成する工程と、
前記第１の絶縁層にビアを形成し、このビアを通して前記第１の金属層を露出する工程と、
前記ビアの上部に凹部が形成されるようにこのビアの深さの途中まで金属を埋め込む工程と、
前記第１の絶縁層上に第２の金属層を形成し、この第２の金属層を前記ビアに埋め込まれた金属を介して前記第１の金属層と電気的に接続する工程と、
前記第２の金属層を露出する開口部を有する第２の絶縁層を形成する工程と、を具備することを特徴とするボンディングパッドの形成方法。Forming a first metal layer on the substrate;
Forming a first insulating layer on the first metal layer;
Forming a via in the first insulating layer and exposing the first metal layer through the via;
Burying metal partway through the depth of the via so that a recess is formed at the top of the via;
Forming a second metal layer on the first insulating layer, and electrically connecting the second metal layer to the first metal layer via a metal embedded in the via;
Forming a second insulating layer having an opening exposing the second metal layer. 前記第１の絶縁層に複数のビアを形成することを特徴とする請求項４記載のボンディングパッドの形成方法。5. The method according to claim 4, wherein a plurality of vias are formed in the first insulating layer. 前記第１の絶縁層にストライプパターンのビアを形成することを特徴とする請求項４記載のボンディングパッドの形成方法。5. The method according to claim 4, wherein a via having a stripe pattern is formed in the first insulating layer. 前記ビアの上部に凹部が形成されるように金属を埋め込む工程は、前記ビアが形成された第１の絶縁層上に高融点金属層をＣＶＤ法により形成する工程と、この高融点金属層をエッチバックする工程とを含むことを特徴とする請求項４記載のボンディングパッドの形成方法。The step of embedding a metal so as to form a concave portion above the via includes a step of forming a refractory metal layer on the first insulating layer in which the via is formed by a CVD method, and a step of depositing the refractory metal layer. 5. The method for forming a bonding pad according to claim 4, further comprising a step of etching back. 基板上に第１の金属層を形成する工程と、
前記第１の金属層上に第１の絶縁層を形成する工程と、
前記第１の絶縁層にビアを形成し、これらの第１のビアを通して前記第１の金属層を露出する工程と、
前記第１のビアの上部に凹部が形成されるように金属をこの第１のビアの深さの途中まで埋め込む工程と、
前記第１の絶縁層上に第２の金属層を形成し、この第２の金属層を前記第１のビアに埋め込まれた金属を介して前記第１の金属層と電気的に接続する工程と、
前記第２の金属層上に第２の絶縁層を形成する工程と、
前記第２の絶縁層に第２のビアを形成し、これらの第２のビアを通して前記第２の金属層を露出する工程と、
前記第２のビアの上部に凹部が形成されるように金属を第２のビアの深さの途中まで埋め込む工程と、
前記第２の絶縁層上に第３の金属層を形成し、この第３の金属層を前記第２のビアに埋め込まれた金属を介して前記第２の金属層と電気的に接続する工程と、
前記第３の金属を露出する開口部を有する第３の絶縁層を形成する工程と、
を具備することを特徴とするボンディングパッドの形成方法。Forming a first metal layer on the substrate;
Forming a first insulating layer on the first metal layer;
Forming vias in said first insulating layer and exposing said first metal layer through said first vias;
Embedding a metal partway into the depth of the first via so that a recess is formed in the upper part of the first via;
Forming a second metal layer on the first insulating layer, and electrically connecting the second metal layer to the first metal layer via a metal embedded in the first via When,
Forming a second insulating layer on the second metal layer;
Forming second vias in said second insulating layer and exposing said second metal layer through said second vias;
Embedding a metal partway in the depth of the second via so that a recess is formed in the upper part of the second via;
Forming a third metal layer on the second insulating layer, and electrically connecting the third metal layer to the second metal layer via a metal embedded in the second via When,
Forming a third insulating layer having an opening exposing the third metal;
A method for forming a bonding pad, comprising: 前記第１の絶縁層に複数の第１のビアを形成し、前記第２の絶縁層に複数の第２のビアを形成することを特徴とする請求項８記載のボンディングパッドの形成方法。The method according to claim 8, wherein a plurality of first vias are formed in the first insulating layer, and a plurality of second vias are formed in the second insulating layer. 前記第１の絶縁層にストライプパターンの第１のビアを形成し、前記第２の絶縁層にストライプパターンの第２のビアを形成することを特徴とする請求項８記載のボンディングパッドの形成方法。9. The method according to claim 8, wherein a first via having a stripe pattern is formed in the first insulating layer, and a second via having a stripe pattern is formed in the second insulating layer. . 前記第１のビアの上部に凹部が形成されるように金属をこの第２のビアの深さの途中まで埋め込む工程は、前記第１のビアが形成された第１の絶縁層上に高融点金属層をＣＶＤ法により形成する工程と、この高融点金属層をエッチバックする工程とを含むことを特徴とする請求項８記載のボンディングパッドの形成方法。The step of embedding a metal partway in the depth of the second via so that a recess is formed in the upper part of the first via may include forming a metal having a high melting point on the first insulating layer in which the first via is formed. 9. The method according to claim 8, further comprising the steps of: forming a metal layer by a CVD method; and etching back the high melting point metal layer. 前記第２のビアの上部に凹部が形成されるように金属をこの第２のビアの深さの途中まで埋め込む工程は、前記第２のビアが形成された第２の絶縁層上に高融点金属層をＣＶＤ法により形成する工程と、この高融点金属層をエッチバックする工程とを含むことを特徴とする請求項８記載のボンディングパッドの形成方法。The step of embedding a metal partway into the depth of the second via so that a recess is formed in the upper part of the second via may include forming a metal having a high melting point on the second insulating layer in which the second via is formed. 9. The method according to claim 8, further comprising the steps of: forming a metal layer by a CVD method; and etching back the high melting point metal layer. 基板上に金属層と絶縁層とを交互にそれぞれ複数の層に積層し、それぞれの絶縁層にビアを形成して、最上層の金属層上に、この金属層を露出する開口部を有した最上層の絶縁層を形成するボンディングパッドの形成方法であって、前記ビアの上部に凹部が形成されるように金属をこのビアの深さの途中まで埋め込む工程を含み、このビアに埋め込まれた金属を通して金属層間を電気的に接続したことを特徴とするボンディングパッドの形成方法。A metal layer and an insulating layer were alternately stacked on a substrate in a plurality of layers, vias were formed in each of the insulating layers, and an opening was formed on the uppermost metal layer to expose the metal layer. A method of forming a bonding pad for forming an uppermost insulating layer, the method including a step of burying a metal partway in the depth of the via so that a recess is formed in the upper part of the via, A method for forming a bonding pad, wherein a metal layer is electrically connected through a metal. 前記絶縁層のそれぞれに複数のビアを形成することを特徴とする請求項１３記載のボンディングパッドの形成方法。14. The method of claim 13, wherein a plurality of vias are formed in each of the insulating layers. 前記絶縁層のそれぞれに、ストライプパターンのビアを形成することを特徴とする請求項１３記載のボンディングパッドの形成方法。14. The method according to claim 13, wherein a via of a stripe pattern is formed in each of the insulating layers. 前記ビアの上部に凹部が形成されるように金属をこのビアの深さの途中まで埋め込む工程は、前記ビアが形成された絶縁層上に高融点金属層をＣＶＤ法により形成する工程と、この高融点金属層をエッチバックする工程とを含むことを特徴とする請求項１３記載のボンディングパッドの形成方法。The step of embedding a metal partway in the depth of the via so that a recess is formed in the upper part of the via includes a step of forming a high melting point metal layer on the insulating layer in which the via is formed by a CVD method. 14. The method for forming a bonding pad according to claim 13, further comprising a step of etching back the refractory metal layer.
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