JP2004311587A - Dummy wiring creation method and dummy wiring creation apparatus - Google Patents

Abstract

An object of the present invention is to provide a dummy wiring creating method capable of effectively and efficiently generating a dummy wiring.
A plurality of dummy patterns (41) are arranged in a substantially well shape in a dummy generation area (36) estimated in a layout area (31). The dummy wiring patterns 42 having a fixed wiring width are formed by connecting the wirings.
[Selection diagram] FIG.

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a dummy wiring forming method and a dummy wiring forming apparatus.
2. Description of the Related Art In recent years, in a semiconductor device (LSI), lamination of metal wiring has been increasingly promoted with high integration and miniaturization. At the same time, flattening techniques such as CMP are further advanced. In general, in the LSI manufacturing process, a dummy wiring pattern is generated for each wiring layer for the purpose of pattern flattening and the like, and the ratio of the wiring area to the chip area (wiring area) Density) to meet certain criteria. There is a demand for a method of effectively and efficiently generating a dummy wiring pattern for satisfying such a wiring density standard.
[0002]
[Prior art]
Conventionally, as a method for generating a dummy wiring pattern, for example, there is the following method.
[0003]
First method: a first dummy wiring pattern is formed so as to overlap with a power supply wiring formed in an upper layer and not to overlap with a signal wiring, and furthermore, both a power supply wiring and a signal wiring are formed. A second dummy wiring pattern is formed in a non-wiring area that does not exist (see Patent Document 1). According to this method, since the dummy wiring pattern can be formed by effectively utilizing the area where no wiring exists, the wiring density can be made uniform in each wiring layer.
[0004]
Second method: A rectangular dummy wiring pattern formed with a predetermined threshold size is arranged in a matrix in a dummy generation area in a chip (see Patent Document 2). In this method, a dummy wiring pattern smaller than the threshold size is not generated, so that the dummy wiring pattern is prevented from being partially missing.
[0005]
[Patent Document 1]
JP-A-11-040672
[Patent Document 2]
JP 2000-338646 A
[0006]
[Problems to be solved by the invention]
However, the conventional techniques as described above have the following problems.
In Patent Literature 1, for example, when a signal wiring has a diagonal wiring, a dummy wiring pattern is formed along the diagonal wiring, so that a dummy wiring having an acute angle is generated. Such a dummy wiring pattern has a problem that the resist pattern formed on the substrate surface at the time of generation thereof is easily peeled off, and is not suitable for manufacturing. Further, since the width of the dummy wiring cannot be controlled by this method, a dummy wiring pattern can be generated by applying this method to a process having a limited wiring width, such as a generation process using copper wiring. There was a problem that could not be done.
[0007]
In Patent Document 2, since the dummy wiring pattern is generated while maintaining a certain threshold size, the above-described problem such as the resist peeling does not occur when the dummy wiring is generated. However, in this method, since the dummy wiring pattern is formed in a rectangular shape, when a dummy wiring pattern for the purpose of reinforcing the capacity between wirings and power supply is to be generated, it must be performed manually, and the operation is complicated. . Therefore, there is a problem that the number of man-hours and the verification time increase.
[0008]
The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a dummy wiring creation method and a dummy wiring creation device capable of effectively and efficiently generating dummy wirings. To provide.
[0009]
[Means for Solving the Problems]
In order to achieve the above object, according to the first and fifth aspects of the present invention, a plurality of dummy patterns are arranged in a substantially well shape in a dummy generation area estimated in a layout area, and each dummy pattern included in the dummy generation area is provided. By connecting the dummy patterns which are not missing in the figure, a dummy wiring having a constant wiring width value is created. With this method, it is possible to prevent the formation of a dummy wiring that is not suitable for manufacturing, such as an acute angle or a narrow width.
[0010]
According to the second aspect of the present invention, first, a plurality of dummy patterns are arranged in a matrix in the dummy generation area estimated in the layout area, and the dummy patterns which are not missing in the figure among the dummy patterns included in the dummy generation area. Are undersized by the minimum dummy wiring width value and deleted from the dummy generation area, and a first dummy wiring is formed on the outer peripheral portion of the resulting dummy generation area. Next, the plurality of dummy patterns are arranged in a substantially well-shape in the dummy generation region, and among the dummy patterns included in the dummy generation region, dummy patterns that are not missing in the figure are connected to each other to form a fixed wiring width value. A second dummy wiring having the same is created. Then, a dummy wiring is prepared by synthesizing the first dummy wiring and the second dummy wiring. According to this method, it is possible to prevent a dummy wiring having an acute angle, a narrow width, or the like, which is not suitable for manufacturing, from being formed, and to increase a wiring density in an outer peripheral portion of the dummy generation region.
[0011]
According to the third aspect of the present invention, the dummy generation area is estimated based on a predefined interval definition between the dummy wiring and the active wiring arranged in the layout area. According to this method, in the same layer, the influence of the capacitance between wirings generated between the dummy wiring and the active wiring can be reduced to form the dummy wiring.
[0012]
According to the invention described in claim 4, according to the node definition in which the node of the dummy wiring is defined for each wiring layer, a port is created for each of the dummy wiring and the active wiring having the same node in the layout region, The connection between ports was made. In this method, the power supply can be reinforced by connecting the dummy wiring and the active wiring of the power supply system.
[0013]
BEST MODE FOR CARRYING OUT THE INVENTION
An embodiment of the present invention will be described below with reference to FIGS.
FIG. 1 is a schematic configuration diagram of a dummy wiring forming apparatus.
[0014]
The dummy wiring creating device 11 is a general CAD (Computer Aided Design) device, and includes a central processing unit (hereinafter, CPU) 12, a memory 13, a magnetic disk device 14, a CRT 15 as a display device, and a keyboard as an input device. 16 and an external storage device 17, which are interconnected via a bus 18.
[0015]
The magnetic disk device 14 stores program data (hereinafter, referred to as a program) and various data necessary for the dummy wiring creation processing. The programs and various data are provided on the external recording medium 19.
[0016]
The CPU 12 executes a program stored in the magnetic disk device 14 using the memory 13, and temporarily stores processing data generated during the processing operation in the memory 13.
[0017]
On the CRT 15, the contents of the dummy wiring creation processing by the CPU 12 or the processing results are sequentially displayed according to the process. The keyboard 16 is used when an operator performs a required input operation during the dummy wiring creation processing.
[0018]
The external storage device 17 is controlled by the CPU 12 to read programs and various data from the external recording medium 19 and store them in the magnetic disk device 14. As the external recording medium 19, any recording medium such as a memory card, a flexible disk, an optical disk (CD-ROM, DVD-ROM,...), A magneto-optical disk (MO, MD,. It includes a medium recording a program uploaded or downloaded via a communication medium, and a disk device.
[0019]
FIG. 2 and FIG. 3 are flowcharts showing the outline of the dummy wiring creation processing. The layout data storage unit 21, interval definition storage unit 22, dummy area storage unit 23, node definition storage unit 24, wiring layer connection condition storage unit 25, extraction information storage unit 26, and contact generation rule storage unit 27 shown in each figure are: Each is stored in the magnetic disk device 14 as a data file.
[0020]
In the layout data storage unit 21, wiring figures such as active wiring (power supply wiring and signal wiring) and dummy wiring for each wiring layer are stored together with text information to which node names are assigned.
[0021]
In the interval definition storage unit 22, the wiring interval between the active wiring and the dummy wiring is defined for each wiring type of the active wiring and stored for each node. The wiring interval is defined for an active wiring in the same layer as the dummy wiring or an active wiring in a different layer from the dummy wiring. For example, the wiring interval between the high-speed signal active wiring and the dummy wiring is set to a value larger than other wiring intervals in consideration of the influence of the parasitic capacitance (inter-wire capacitance).
[0022]
The dummy area storage unit 23 is used for temporarily storing a dummy wiring generation area calculated during the dummy wiring creation processing operation.
The node definition storage unit 24 stores node names of dummy wirings defined for each wiring layer. For example, in the case of a four-layer wiring, one-layer dummy wiring is defined as GND (ground), two-layer dummy wiring is defined as VCC, three-layer dummy wiring is defined as GND, four-layer dummy wiring is defined as VCC, and the like.
[0023]
The wiring layer connection condition storage unit 25 stores information indicating the connection relationship of each wiring for each wiring layer.
The extraction information storage unit 26 is used when extracting the wiring information of the active wiring from the layout data storage unit 21 and temporarily storing the extracted wiring information during the dummy wiring creation processing operation.
[0024]
In the contact generation rule storage unit 27, connection contacts between wiring layers generated at the time of the dummy wiring creation processing operation are defined and stored for each combination of wiring layers. For example, in the case of a four-layer wiring, the generation rules for the connection contacts of the first and second layers, the connection contacts of the second and third layers, and the connection contacts of the third and fourth layers are stored.
[0025]
Next, the processing operation (dummy wiring creation processing) of the dummy wiring creating apparatus 11 configured as described above will be described.
As shown in FIG. 2, at the start of the dummy wiring creation processing, the CPU 12 first reads the active wiring to be arranged in the layout area from the layout data storage unit 21 and generates a dummy wiring for the wiring figure (dummy generating area). ) Is estimated for each wiring layer based on the interval definition storage unit 22 (step 1).
[0026]
More specifically, a necessary interval between the active wiring and the dummy wiring is added to the active wiring read from the layout data storage unit 21, and an area obtained by erasing the area from the layout area is set as a dummy generation area. It is stored in the dummy area storage unit 23.
[0027]
Next, the CPU 12 reads the dummy area storage unit 23, and determines an area to be subjected to dummy wiring creation processing among the dummy occurrence areas obtained in Step 1 (Step 2).
[0028]
More specifically, if the number of the dummy occurrence area obtained in step 1 is one, the CPU 12 determines that area as a target of the dummy wiring creation processing. If there are two or more dummy generation areas obtained in the step 1, the CPU 12 compares the areas of the respective dummy wiring areas, and determines the area having the largest area as a target of the dummy wiring creation processing. To be determined.
[0029]
Next, the CPU 12 generates a predetermined dummy wiring (dummy wiring pattern) in the dummy generation area determined in Step 2 (Step 3).
As a method of creating a dummy wiring in step 3, as will be described later, there are two methods, a first dummy wiring creating method shown in FIG. 5 or a second dummy wiring creating method shown in FIGS. 6 and 7. is there. The CPU 12 creates a dummy wiring by one of these methods, and performs a joining process (merge) in the layout data storage unit 21 so that the dummy wiring can be identified from the active wiring.
[0030]
Next, the CPU 12 reads the node definition of the dummy wiring created in step 3 from the node definition storage unit 24 for each wiring layer. Then, in each layer, a wiring pattern (active wiring) of the same node as the dummy wiring is extracted from the layout data storage unit 21 according to the wiring layer connection condition storage unit 25, and the node names, positions, wiring layers, and shapes of the active wirings are extracted. It is temporarily stored in the storage unit 26 (step 4).
[0031]
Next, the CPU 12 creates a port for each of the dummy wiring created in Step 3 and the active wiring having the same node as the dummy wiring (Step 5). A method for creating this port will be described later with reference to FIG.
[0032]
Next, the CPU 12 connects between the dummy wiring created in step 5 and the port of the active wiring according to the wiring layer connection condition storage unit 25 (step 6).
By this processing, for example, when the node of the dummy wiring is set as the power supply node, the dummy wiring is connected to the active wiring of the power supply wiring, so that the active wiring of the power supply wiring is reinforced with the dummy wiring. Thus, the effect of suppressing voltage fluctuation can be obtained.
[0033]
Next, as shown in FIG. 3, the CPU 12 executes the steps 1 and 2 including the dummy wiring generated in the step 3 and the wiring connecting the dummy wiring and the active wiring created in the step 6. By performing the same processing, the area where the dummy wiring is to be generated is estimated again (step 7).
[0034]
Then, the CPU 12 determines whether or not a dummy occurrence area exists (step 8). If the dummy occurrence area exists, the CPU 12 returns to step 2 and repeats the processing of steps 2 to 7.
[0035]
That is, the CPU 12 repeats the processing of Steps 2 to 7 until there is no area in which the dummy wiring is to be generated in the layout area 31, and then proceeds to Step 9 to perform the same processing as in Step 4 described above.
[0036]
Next, for all nodes set as dummy wirings, the CPU 12 reads wiring patterns (active wirings and dummy wirings) of the same node from the layout data storage unit 21 based on the extracted information storage unit 26, and reads the upper and lower wiring wirings. A coordinate value indicating a portion where the dummy wiring of the same node overlaps between the layers is obtained (step 10).
[0037]
This coordinate value is obtained for each combination of the upper and lower wiring layers having an overlapping portion and for each node. For example, in the case of a four-layer wiring, a dummy is provided for each combination of one layer, two layers, one layer, three layers, one layer, four layers, two layers, three layers, two layers, four layers, and three layers, four layers. Coordinate values indicating portions where wirings overlap are extracted for each node.
[0038]
Next, the CPU 12 checks whether or not the wiring of the other node is sandwiched between the upper and lower wiring layers at the portion where the dummy wiring of the same node is overlapped. The value is corrected (step 11).
[0039]
Specifically, the portion where the wiring of the other node is sandwiched is subtracted from the portion where the dummy wiring of the same node overlaps between the upper and lower wiring layers by a value oversized by the wiring interval, and the coordinate value corresponding to the area portion is subtracted. Then, the coordinate value obtained in step 10 is changed. That is, only the part where the wiring of the other node is not sandwiched between the upper and lower wiring layers where the dummy wiring of the same node overlaps is extracted.
[0040]
For example, in the case of a four-layer wiring as described above, a two-layer wiring of another node may be sandwiched between the first and third layers where the dummy wiring of the same node overlaps. Therefore, the CPU 12 reads the wiring pattern (active wiring and dummy wiring) of the two-layer portion from the layout data storage unit 21, subtracts the wiring pattern by a value oversized by the wiring interval, and changes the coordinate value to the corresponding coordinate value. .
[0041]
Then, according to the contact generation rule storage unit 27, the CPU 12 arranges the contact in a portion where the dummy wiring of the same node obtained in step 11 overlaps (step 12).
[0042]
Next, the specific processing of steps 1 and 2 (calculation of a dummy generation area and determination of a processing target area) in the dummy wiring creation processing will be described with reference to FIG.
As shown in FIG. 4, in the layout area 31, for example, a first-layer wiring 32, a second-layer wiring 33, and first and second block areas 34 and 35 (BLOCK1 and BLOCK2 in the figure) are arranged as active wirings. You. The first and second block regions 34 and 35 are regions in which wiring of functional blocks having a hierarchical structure is regarded as one wiring figure.
[0043]
In step 1 described above, based on the wiring intervals stored in the interval definition storage unit 22, the active wirings are oversized by a necessary distance from the dummy wirings and erased from the layout area 31. The figure (region) left in the region 31 is estimated as a dummy occurrence region. In the figure, two dummy generation areas 36 and 37 are created in the layout area 31.
[0044]
In step 2 described above, the areas of the dummy generation areas 36 and 37 are compared, and among them, the dummy generation area 36 having the larger area is determined as the dummy wiring creation processing target area. It should be noted that the two-layer wiring 33 indicated by the arrow A in FIG. 4 indicates a wiring type in which the wiring interval with the one-layer dummy wiring is not limited.
[0045]
Next, a specific process of step 3 (generation of a dummy wiring pattern) in the dummy wiring forming process will be described with reference to FIGS. The same components as those in FIG. 4 will be described with the same reference numerals.
[0046]
FIG. 5 is an explanatory diagram illustrating a processing procedure of the first dummy wiring creation method.
In this method, first, a plurality of dummy patterns 41 are arranged in a substantially well-like matrix in the layout area 31 (step 21). The dummy pattern 41 is set so that the pattern width d1 has the size of the dummy wiring width to be created. In the present embodiment, the dummy pattern 41 is formed in a square shape of, for example, 1 μm × 1 μm.
[0047]
An interval d2 between adjacent dummy patterns 41 (hereinafter, pattern interval) is set to a value smaller than a minimum required interval between dummy wirings to be created (hereinafter, minimum interval between dummy wirings). It is set to 0.5 μm. The distance d3 between the dummy patterns 41 that are not adjacent to each other (the hollow portion in the figure in the figure) is set to a value equal to or larger than the minimum dummy wiring distance. The interval value (2 μm) is set.
[0048]
Next, a logical product (AND) of each dummy pattern 41 arranged in the layout area 31 and the dummy generation area 36 is calculated (step 22).
Next, each of the patterns 41 is undersized to a size that can maintain the area of the dummy pattern 41 in the dummy generation region 36 (a threshold size that can represent the dummy pattern 41 as a graphic), and then oversized with the same value ( Step 23). Here, for example, the threshold size of the dummy pattern 41 is set to 0.002 μm × 0.002 μm, and each of the dummy patterns 41 is undersized by 0.499 μm in a direction from each side toward the center, and then oversized by the same value. To size.
[0049]
As a result, of the dummy patterns 41 in the dummy generation region 36, a pattern with a missing part in the figure is deleted. That is, by performing the processing in step 23, the dummy pattern 41 that is not suitable for manufacturing, such as an acute angle and a narrow width, can be deleted.
[0050]
Next, each dummy pattern 41 is oversized until the pattern interval d2 is eliminated, and then undersized with the same value (step 24). Here, the dummy patterns 41 are each oversized by 0.25 μm and then undersized by the same value.
[0051]
As a result, the adjacent dummy patterns 41 are connected to each other, and a line-shaped dummy wiring pattern 42 is formed. That is, in the first dummy wiring forming method, the dummy wiring pattern 42 in which the dummy wiring width is fixed to a constant value can be formed.
[0052]
6 and 7 are explanatory diagrams showing the processing procedure of the second dummy wiring creation method.
In this method, as shown in FIG. 6, after the dummy generation area 36 is undersized with a value of 1/2 of the predetermined minimum dummy wiring width (step 31), the area 36a obtained by the processing is set to the same value. To oversize (step 32).
[0053]
As a result, a dummy generation area 36b is created in which the area of the dummy generation area 36 which does not satisfy the minimum dummy wiring width (for example, a protruding area surrounded by a broken line in the dummy generation area 36 shown in FIG. 6) is created.
[0054]
Next, the dummy patterns 43 are arranged in a matrix in the dummy generation region 36b (step 33). This dummy pattern 43 is, for example, formed in a square shape with a pattern width d1 = 1 μm and the pattern interval d2 = 0.5 μm, similarly to the dummy pattern 41 described above.
[0055]
Next, a logical product (AND) of the dummy patterns 43 arranged in a matrix and the dummy generation region 36b is calculated, and each of the dummy patterns 43 in the dummy generation region 36b is undersized by 0.499 μm, and then the same value is set. Oversize. Further, each dummy pattern 43 in the dummy generation region 36b obtained by the process is oversized by 0.25 μm and then undersized by the same value (step 34).
[0056]
As a result, of the dummy patterns 43 in the dummy generation area 36b, after a pattern with a missing part in the figure is deleted, the dummy patterns 43 in the dummy generation area 36b are connected to each other to form an area 44. Is done.
[0057]
Next, after the area 44 is undersized by the value of the minimum dummy wiring width (step 35), the area 44a obtained by the processing is deleted from the dummy generation area 36b (step 36). As a result, a dummy wiring pattern 45 in which an area satisfying the minimum dummy wiring width is secured is formed around the dummy generating area 36b.
[0058]
Next, as shown in FIG. 7, a line-shaped dummy wiring pattern 46 is formed in the dummy generation region 36b by the same processing procedure as the first dummy wiring forming method (see FIG. 5) (step 37). . Then, the dummy wiring pattern 46 and the dummy wiring pattern 45 obtained by the processing in the step 36 are combined to create a dummy wiring pattern 47 (step 38).
[0059]
Next, the synthesized dummy wiring pattern 47 is oversized with a value smaller than the minimum dummy wiring interval (specifically, the minimum dummy wiring interval−0.001 μm), and then undersized with the same value (step). 39).
[0060]
As a result, in the dummy wiring pattern 47, a pattern is formed between the wirings that are equal to or smaller than the minimum dummy wiring interval, and a dummy wiring pattern 48 that satisfies the minimum dummy wiring interval is created. That is, in the second dummy wiring forming method, the wiring density at the outer peripheral portion of the dummy generation region 36b can be improved.
[0061]
Next, a specific process of step 5 (port creation) in the dummy wire creation process will be described with reference to FIG. The same components as those in FIGS. 4 to 7 will be described with the same reference numerals.
[0062]
As shown in FIG. 8, in the dummy generation area 36 of the layout area 31, a dummy wiring pattern 48 (see FIG. 7) created by, for example, the second dummy wiring creating method is arranged.
[0063]
In the above step 5, first, a perpendicular line is extended from the outer side of the dummy wiring pattern 48 in a direction indicated by an arrow in the drawing, and whether or not the perpendicular line intersects the active wiring pattern of the power supply system having the same node as the dummy wiring pattern 48 is determined. Check. Then, when there is an active wiring pattern (for example, the single-layer wiring 32 in the figure) of the power supply system that intersects, ports 51 and 52 are created on the sides of the dummy wiring pattern 48 and the active wiring pattern, respectively.
[0064]
As described above, the present embodiment has the following advantages.
(1) In the first dummy wiring creation method, a predetermined pattern processing is performed after a pattern having a small part of a pattern is deleted from the dummy patterns 41 arranged in a substantially well shape in the dummy generation area 36. Then, a line-shaped dummy wiring pattern 42 is created. According to this method, the dummy wiring width is fixed to a fixed value, and it is prevented that a dummy wiring having an acute angle, a narrow width, or the like that is not suitable for manufacturing is created.
[0065]
(2) In the second dummy wiring creating method, first, among the dummy patterns 43 arranged in a matrix in the dummy generation area 36b, a pattern with a slight chip in the figure is deleted, and then a predetermined figure processing is performed. Thus, a dummy wiring pattern 45 is formed on the outer peripheral portion of the dummy generation region 36b. Then, the dummy wiring pattern 45 and the line-shaped dummy wiring pattern 46 formed by the same processing procedure as the above-described first dummy wiring forming method are combined to form a dummy wiring pattern 48. According to this method, it is possible to prevent the formation of a dummy wiring that is not suitable for manufacturing such as an acute angle and a narrow width, and it is possible to increase the wiring density in the outer peripheral portion of the dummy generation region 36b.
[0066]
(3) The wiring interval between the dummy wiring and the active wiring in the same layer is defined for each wiring type of each active wiring, and the dummy generation regions 36 and 37 are estimated based on the definition of the spacing. Therefore, the dummy wiring can be created in consideration of the effect of the inter-wiring capacitance (parasitic capacitance) generated between the active wiring and the dummy wiring.
[0067]
(4) The active wiring having the same node as the dummy wiring is extracted according to the node definition storage unit 24, stored as the extracted information storage unit 26, and the dummy wiring is arranged based on the extracted information storage unit 26. As a result, dummy wirings are arranged so that opposing power supply nodes are alternately stacked, and the wiring layers of the same upper and lower nodes sandwiching the wiring layers of different nodes are connected via contacts. (Capacity between power supplies) can be configured to stabilize the power supply.
[0068]
(5) Based on the extracted information storage unit 26, a port is generated for each of the dummy wiring of the same node and the active wiring of the power supply system, and the ports are connected to each other, so that the power supply can be reinforced by the dummy wiring. .
[0069]
(6) In the present embodiment, not only dummy wiring can be created for the purpose of flattening a pattern, but also it can be used for the purpose of inter-power supply capacity and power supply reinforcement. Can be created. Therefore, it is possible to reduce the number of work steps, thereby reducing the TAT and the manufacturing cost.
[0070]
The above embodiment may be implemented in the following modes.
The dummy pattern 41 is not limited to a square pattern, but may be a rectangular pattern (for example, a rectangular pattern).
[0071]
In the first dummy wiring forming method, the distance d3 between the dummy patterns 41 (the hollow portion in FIG. 5) may be the value of (pattern width d1 + pattern distance d2).
[0072]
The features of the above embodiment are summarized as follows.
(Supplementary Note 1) A plurality of dummy patterns are arranged in a substantially well shape in the dummy generation area estimated in the layout area, and the dummy patterns of the dummy generation areas included in the dummy generation area are connected to each other and are fixed to each other. Forming a dummy wiring having a wiring width of:
(Supplementary Note 2) A plurality of dummy patterns are arranged in a matrix in the dummy generation area estimated in the layout area, and an area generated by connecting dummy patterns having no missing parts in the figures among the dummy patterns included in the dummy generation area is defined. Undersize with the value of the minimum dummy wiring width and delete from the dummy generation area, create a first dummy wiring on the outer periphery of the dummy generation area obtained by the deletion,
The second dummy pattern having a certain wiring width by arranging the plurality of dummy patterns in a substantially well shape in the dummy generating region and connecting the dummy patterns of the dummy patterns included in the dummy generating region that are not missing in the figure. Create dummy wiring,
A dummy wiring forming method, comprising: forming a dummy wiring obtained by combining the first dummy wiring and the second dummy wiring.
(Supplementary note 3) The supplementary note 1 or 2, wherein the dummy generation area is estimated based on a predefined interval definition between the dummy wiring and the active wiring arranged in the layout area. Dummy wiring creation method.
(Supplementary Note 4) A node of the dummy wiring is defined for each wiring layer, and a port is created in each of the dummy wiring and the active wiring having the same node in the layout area, and each port is connected. 4. The method for creating a dummy wiring according to any one of supplementary notes 1 to 3, wherein
(Supplementary Note 5) It is determined whether or not the wiring of the other node is sandwiched between the upper and lower wiring layers where the dummy wiring of the same node overlaps, and the upper and lower wiring layers are separated at the portion where the wiring of the other node is not sandwiched. 4. The method according to claim 4, wherein the connection is established via a contact.
(Supplementary Note 6) A recording medium which records a program for executing a dummy wiring creation process for creating a dummy wiring in a layout area,
6. The recording medium according to claim 1, wherein the program includes a step of executing a process according to the dummy wiring creation method according to any one of Supplementary Notes 1 to 5.
(Supplementary Note 7) A means for estimating a dummy generation area for generating a dummy wiring in the layout area,
A plurality of dummy patterns are arranged in a substantially well shape in the dummy generation region, and dummy patterns having a constant wiring width are created by connecting, among the dummy patterns included in the dummy generation region, dummy patterns that are not missing in the figure. Means to
A dummy wiring creating apparatus, comprising:
(Supplementary Note 8) A means for estimating a dummy generation area for generating a dummy wiring in the layout area,
A plurality of dummy patterns are arranged in a matrix in the dummy generation area, and an area generated by connecting dummy patterns which are not missing in the figure among the dummy patterns included in the dummy generation area is undersized with a value of a minimum dummy wiring width. Means for removing from the dummy generation area and creating a first dummy wiring on an outer peripheral portion of the dummy generation area obtained by the deletion;
The second dummy pattern having a certain wiring width by arranging the plurality of dummy patterns in a substantially well shape in the dummy generating region and connecting the dummy patterns of the dummy patterns included in the dummy generating region that are not missing in the figure. Means for creating dummy wiring;
Means for creating a dummy wiring by combining the first dummy wiring and the second dummy wiring;
A dummy wiring creating apparatus, comprising:
(Supplementary Note 9) The apparatus further includes means for defining a node of the dummy wiring for each wiring layer, creating ports for the dummy wiring and the active wiring having the same node in the layout area, and connecting the respective ports. 7. The dummy wiring creating apparatus according to claim 7 or 8, wherein:
(Supplementary Note 10) It is determined whether the wiring of the other node is not sandwiched between the upper and lower wiring layers where the dummy wiring of the same node overlaps, and the upper and lower wiring layers are not sandwiched in the portion where the wiring of the other node is not sandwiched. The dummy wiring creating apparatus according to claim 9, further comprising: means for connecting via a contact.
[0073]
【The invention's effect】
As described in detail above, according to the present invention, there is provided a dummy wiring creating method and a dummy wiring creating apparatus capable of efficiently generating a dummy wiring that can be effectively used as a pseudo capacitance and a power supply reinforcing wiring. be able to.
[Brief description of the drawings]
FIG. 1 is a schematic configuration diagram showing a dummy wiring forming apparatus.
FIG. 2 is a flowchart illustrating an outline of a dummy wiring creation process.
FIG. 3 is a flowchart illustrating an outline of a dummy wiring creation process.
FIG. 4 is an explanatory diagram showing a dummy generation area.
FIG. 5 is an explanatory diagram showing a processing procedure of a first dummy wiring creation method.
FIG. 6 is an explanatory diagram showing a processing procedure of a second dummy wiring creation method.
FIG. 7 is an explanatory diagram showing a processing procedure of a second dummy wiring creating method.
FIG. 8 is an explanatory diagram showing ports.
[Explanation of symbols]
11 Dummy wiring creation device
22 Interval definition storage as interval definition
31 Layout area
32 to 35 1-layer wiring as active wiring, 2-layer wiring, first and second block regions
36, 36b, 37 Dummy generation area
41, 43 dummy pattern
42, 48 Dummy wiring pattern as dummy wiring
45 Dummy Wiring Pattern as First Dummy Wiring
46 Dummy wiring pattern as second dummy wiring
51, 52 ports

Claims (5)

A plurality of dummy patterns are arranged in a substantially well shape in the dummy generation area estimated in the layout area, and among the dummy patterns included in the dummy generation area, dummy patterns that are not missing in the figure are connected to each other to have a certain wiring width. A dummy wiring creating method, characterized by creating a dummy wiring having the same. A plurality of dummy patterns are arranged in a matrix in a dummy generating area estimated in a layout area, and a region generated by connecting dummy patterns having no missing parts in a figure among the dummy patterns included in the dummy generating area is a minimum dummy wiring width. Undersize with the value of and delete from the dummy generation area, create a first dummy wiring on the outer periphery of the dummy generation area obtained by the deletion,
The second dummy pattern having a certain wiring width by arranging the plurality of dummy patterns in a substantially well shape in the dummy generating region and connecting the dummy patterns of the dummy patterns included in the dummy generating region that are not missing in the figure. Create dummy wiring,
A dummy wiring forming method, comprising: forming a dummy wiring obtained by combining the first dummy wiring and the second dummy wiring. 3. The dummy wiring generation according to claim 1, wherein the dummy generation area is estimated based on a predefined interval definition between the dummy wiring and an active wiring arranged in the layout area. Method. The node of the dummy wiring is defined for each wiring layer, and a port is created for each of the dummy wiring and the active wiring having the same node in the layout area, and the ports are connected to each other. Item 4. The method for creating a dummy wiring according to any one of Items 1 to 3. Means for estimating a dummy generation area for generating a dummy wiring in the layout area;
A plurality of dummy patterns are arranged in a substantially well shape in the dummy generation region, and dummy patterns having a constant wiring width are created by connecting, among the dummy patterns included in the dummy generation region, dummy patterns that are not missing in the figure. A dummy wiring creating apparatus.

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