JP2004280754A - Radio communication ic reader and writer, radio communication ic information processing system using the same, and radio communication ic - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a radio communication IC information processing system for easily performing a communication error detection processing, and detecting multiple kinds of errors, and also to provide a radio communication IC. <P>SOLUTION: A radio communication IC reader/writer includes: a receiving means for dividing a frame into a plurality of sub-frames with a prescribed number of bytes, so as to receive data a plurality of times; a determining means for determining whether a communication error exists or not in each unit of received sub-frame; and a reception stop means for stopping reception from the radio communication IC when the existence of the communication error is determined as the result of determination by the determining means. The determining means detects a plurality of kinds of communication errors. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a wireless communication IC reader / writer and a wireless communication IC information processing system using the same, and more particularly, to a non-contact type IC card or a stamp-type non-contact type memory medium, or a storage medium such as an IC tag or an electronic key. And an information processing device such as a computer equipped with a reader for exchanging data with this storage medium in a non-contact manner, and a traffic gate for exchanging data with the IC card in a non-contact state and confirming the validity of the IC card In devices and systems such as entry / exit devices, entry / exit management devices, product management systems, and electronic commerce that use information media such as electronic keys, etc., communication error detection processing is easy, and various types of error detection can be performed. A possible wireless communication IC reader / writer is improved.
It should be noted that the reader / writer in the specification and the claims includes those that perform communication processing with a non-contact medium as a transceiver / receiver.
[0002]
[Prior art]
A non-contact type IC card transmits and receives information to and from a reader / writer by electromagnetic induction or electromagnetic coupling. Conventionally, a non-contact type IC card itself has a built-in battery. However, recently, a non-contact type IC card in which IC driving power is reduced, power is supplied by radio waves, and transmission / reception is implemented has been put to practical use. (Patent Documents 1 and 2).
[0003]
[Patent Document 1]
JP-A-8-330840 [Patent Document 2]
Japanese Patent Application No. 2000-172793
Furthermore, recently, using an electroforming technique or the like, a coil having a width of several tens of μm is formed on a chip of several mm square with an insulating layer interposed therebetween, and this chip is attached to an IC card or an IC. It is built in and used as a tag. This type of IC is one of non-contact type information media, and a wireless communication IC (or IC tag, other IC type non-contact information media, hereinafter including these, wireless communication in this specification and claims) IC).
A data transfer system using a non-contact medium, including such a wireless communication IC, is a contact type (a distance of about 0 to 2 mm to a non-contact type IC card or an IC tag) or a proximity type (a distance of about 2 mm to about 10 cm). -Send and receive data by bringing the non-contact information medium into close contact with or close to the writer. Then, the power supply of the wireless communication IC is performed in such a manner that a radio wave of a non-modulated and constant amplitude is transmitted to the non-contact information medium side for a certain period in ASK or FSK, and the non-contact information medium operates with the power and responds to the device side. I do. As response communication at this time, there is a wireless communication IC side in which data transmission is performed by a load modulation method.
[0005]
By the way, a reader / writer that exchanges data with a wireless communication IC normally transmits and receives data in a frame unit of about 128 bytes to 256 bytes, similarly to a recording unit such as an FD or a hard disk. The transmission / reception protocol corresponds to SOF (start-of-frame) or SOT (start-of-text), EOF (end-of-frame), or EOT (start-of-text), as is performed in normal communication since the other party is specified. A command or response code and data are transmitted with such a code interposed at the beginning and end, and a check code such as CRC is added at the end.
[0006]
[Problems to be solved by the invention]
However, when receiving data from such a wireless communication IC, various communication errors occur. For example, various errors such as a communication error caused by a wireless communication IC being insufficiently attached to a reader / writer or being not attached, a bit missing error, a CRC error, and an insufficient output of a carrier radio wave. There is something. However, when a communication error is detected in response to these errors, the processing load of the reader / writer increases. Moreover, the processing correspondence on the host data processing device (host computer) side differs depending on each communication error. For example, if the wireless communication IC is not properly attached to the reader / writer or a communication error occurs because the wireless communication IC is not attached to the reader / writer, a corresponding message is required, and a bit missing error, a bit detection error, a CRC check error, etc. In such a case, a retry process is required, and sometimes a process such as enhancement of the carrier radio wave output is also required.
On the other hand, for example, there is a demand for faster reader / writer processing such as a shift from the USB 1.1 standard to a faster USB 2.0 standard. In addition, miniaturization of a stick type or the like is required. For this reason, it is necessary to efficiently detect various types of errors in the reader / writer, but it is difficult to meet the demand for high-speed and miniaturization.
An object of the present invention is to solve such a problem of the related art, and provides a wireless communication IC information processing system and a wireless communication IC that can easily detect a communication error and detect various types of errors. Is to do.
Another object of the present invention is to provide a wireless communication IC information processing system and a wireless communication IC capable of easily detecting a communication error and detecting various types of errors.
[0007]
[Means for Solving the Problems]
The wireless communication IC reader / writer of the present invention, a wireless communication IC information processing system using the same, and a wireless communication IC using the same are characterized by a non-contact type information storage medium incorporating a wireless communication IC, A wireless communication IC reader that supplies power to a contact-type information storage medium, reads data stored in a memory built in the wireless communication IC in units of frames (transmission frames) of a predetermined capacity, and transfers the data to a higher-level information processing device In the writer,
A receiving unit that divides a frame into a plurality of sub-frames of a predetermined number of bytes (a divided frame obtained by dividing a frame having a predetermined capacity into a plurality of pieces) and receives data a plurality of times; And a reception stopping means for stopping reception from the wireless communication IC when it is determined that there is a communication error as a result of the determination by the determination means. The means detects a plurality of types of communication errors.
[0008]
BEST MODE FOR CARRYING OUT THE INVENTION
As described above, in the present invention, a frame is divided into a plurality of subframes having a predetermined number of bytes, and various communication errors are determined in subframe units. Also, it is possible to reduce the size and speed of the determining means (determining circuit and the like).
As a result, it is possible to easily realize a wireless communication IC information processing system and a wireless communication IC that can easily perform communication error detection processing capable of detecting various types of errors and perform high-speed error detection processing.
[0009]
【Example】
FIG. 1 is a block diagram of a wireless communication IC information processing system using a wireless communication IC reader / writer to which the present invention is applied, FIG. 2 is an explanatory diagram of a format of a data transmission protocol using a wireless communication medium, and FIG. And FIG. 4 is an explanatory diagram of the communication error code.
In FIG. 1, 1 is a wireless communication IC information processing system, 2 is its host computer, 3 is a wireless communication medium reader / writer with a built-in wireless communication IC, and has a microprocessor interface (hereinafter, microcomputer I / F). ) 30 to the host computer 2. The wireless communication medium reader / writer 3 includes a microcomputer I / F 30, a control circuit (CNT) 31, a transmission / reception circuit 32 having a modulation circuit (MOD) 32a and a demodulation circuit (DEM) 32b, a transmission / reception buffer memory 33, a communication error determination circuit. The transmission / reception circuit 32 is controlled by the control circuit 31 to transmit / receive data via the transmission / reception buffer memory 33. Note that the communication error determination circuit 35 is provided with an 8-bit error register 35a.
On the other hand, the control circuit 31 and the microcomputer interface (IF) 30 transmit and receive data to and from the host computer 1 when the wireless communication medium reader / writer 3 (and the host computer 1) is in an active state. 2 and receives a response to it.
[0010]
The control circuit 31 receives data from the host computer 2 via the microcomputer I / F 30, temporarily stores the data in the transmission / reception buffer memory 33, sends the transmission data TD to the transmission / reception circuit 32, and receives the reception data RD output from the transmission / reception circuit 32. In response, the data is temporarily stored in the transmission / reception buffer memory 33 and transferred to the host computer 2 via the microcomputer I / F 30.
The transmission / reception circuit 32 includes an encoder (ENC), a transmission unit including a modulation circuit (MOD) 32a and a transmission circuit, and a reception unit including a demodulation circuit (DEM) 32b and a decoder (DEC). , Are connected to the loop antenna 36, respectively. 36a is a matching circuit.
The encoder (ENC) receives the transmission data, converts it into an MFM signal, and sends it to the modulation circuit (MOD) 32a. The modulation circuit (MOD) 32a performs, for example, ASK modulation on the data received from the host computer 2 and supplies the data to the loop antenna 36 via the transmission circuit.
[0011]
Reference numeral 20 denotes a wireless communication medium having a built-in wireless communication IC, which has a loop antenna 21 and an IC 22 therein. The loop antenna 21 is stacked on a chip via an insulating layer. The IC 22 incorporates a power generation circuit such as a capacitor for storing power and a detection circuit in addition to a microprocessor (MPU) and a memory.
On the other hand, the host computer 2 is provided with a controller (MPU) 1a, a memory 1b, and an application program 1c partially including a process of reading data from the wireless communication medium 20 stored in the memory 1b.
[0012]
When the program part of the card reading process is called in the host computer 2, the MPU 1a of the host computer 2 executes the program, and first, the MPU 1a sends an access request signal (REQ) to the wireless communication medium 20 to the wireless communication medium reader.・ Send to the writer 3, the microcomputer I / F 30 receives it, and controls the control circuit 31. The control circuit 31 turns on the transmission / reception buffer memory 33, starts power supply to the transmission / reception circuit 32, and to start. Then, it waits for a response to the data received from the wireless communication medium 20.
[0013]
The wireless communication medium 20 is detected based on the response information from the wireless communication medium 20, and the process enters an actual data communication process with the wireless communication medium 20, and a reading process is performed in the data communication process. At this time, the communication error determination circuit 35 detects a communication error in the reception state with respect to the wireless communication medium 20 based on whether there is a response carrier, whether or not read data is being received, and the like. Further, a 128-byte transmission frame 4 is received by dividing predetermined transmission data from the wireless communication medium 20 into sub-frames 5a to 5n. Then, the control circuit 31 reads and stores the data of each of the sub-frames 5 a to 5 n received from the wireless communication medium 20 in the transmission / reception buffer memory 33. When this is completed, the communication error determination circuit 35 sequentially records the received data of each of the sub-frames 5a to 5n in the transmission / reception buffer memory 33, and when one sub-frame is stored, starts the CRC error, the bit omission error, etc. A communication error is detected for the received data. Each detection error is stored in the area of the communication error information 7c (see FIG. 3) of the subframes 5a to 5n stored in the transmission / reception buffer memory 33.
Then, when a communication error is detected at this time, the communication error determination circuit 35 sends an error detection signal to the control circuit 31. Thereby, the control circuit 31 performs a process of stopping the reception process from the wireless communication medium 20.
This means that the control circuit 31 resets the internal flip-flop, thereby stopping various control signals and turning off the transmission / reception buffer memory 33. As a result, power supply to the transmission / reception circuit 32 is stopped.
[0014]
FIG. 2 to FIG. 4 are explanatory diagrams of the reception processing of the subframe and the communication error of the communication error determination circuit 35.
FIG. 2 is an explanatory diagram of the format of a data reception protocol using a wireless communication medium. The wireless communication medium 20 includes an SOF column 6a at the beginning of the transmission data 6, a 1-byte response code column 6b, and an 8-byte sub-code. It consists of a frame transmission data column 6c, a CRC check code column 6d, and finally an EOF column 6e.
As shown in FIG. 3, the wireless communication medium reader / writer 3 that receives data transmitted in this format first detects an error such as whether or not a transmission carrier is present during reception by the communication error determination circuit 35. , And sequentially stores the received data in the transmission / reception buffer memory 33 in correspondence with the reception of each subframe.
[0015]
FIG. 3 shows the storage contents of the response corresponding to the subframe in the transmission / reception buffer memory 33. The response code column 7a, the 8-byte reception data column 7b divided into actual subframes, and the communication error information column 7c. The received data divided into 16 pieces is sequentially stored.
At this time, the communication error information column 7c is stored at the position of the CRC check code column 6d of the transmission data 6, replacing the communication error information column 7c.
When a communication error occurs in the communication error information column 7c, the reception is stopped by the control circuit 31, and the transmission data of the subframe is not stored in the transmission / reception buffer memory 33.
The error content determined by the communication error determination circuit 35 in this case is shown in FIG. 4, and the communication error data is composed of a 1-byte error flag, and when a corresponding error occurs, the bit at the corresponding digit position is set to “1”. "Remains set. That is, all of the 8 bits of the error flag except the LSB are set to the error detection state of “1” in the initial state, and are reset to “0” when it is determined that there is no error. The LSB is set to “0” in the initial state, and is set to “1” when an error occurs.
[0016]
Hereinafter, the error flag at each digit position will be described in order from the LSB. LSB (= b0) is a carrier error flag, and indicates an error indicating that the carrier of the transmission signal has been stopped. It becomes. The next second digit (= b1) becomes “1” when the received byte number error flag and the total received byte number are different. The next third digit (= b2) is a status error flag, which becomes “1” when a status confirmation notification is not received from the wireless communication medium 20.
The next fourth digit (= b3) becomes “1” when a signal reception error or a reception signal is not detected from the wireless communication medium 20.
The fifth digit (= b4) is a bit detection error. When the signal received from the wireless communication medium 20 is not at the bit detection position, the bit signal is detected. 1 ".
The next sixth digit (= b5) becomes “1” when a bit undetected error occurs and the signal received from the wireless communication medium 20 is not a bit-corresponding signal when it is at a bit detection position.
The seventh digit (= b6) is a CRC error flag, which becomes "1" when the result of the CRC check of the data received from the wireless communication medium 20 is different from the CRC code transmitted.
The last MSB (8th digit = b7) is a flag indicating the presence or absence of a communication error, and is set to “1” when any of b0 to b6 has an error flag “1”.
[0017]
The communication error stored in the communication error information column 7c of each subframe is ORed for each bit, and the 8 bits of the OR are stored in the 8-bit error register 35a.
When there is a communication error on the way according to the detection signal from the communication error determination circuit 35, the control circuit 31 receives all of the 16 subframes 5a to 5n even if the reception is terminated. At the timing, the communication error flag data of the logical sum of the error register 35a is transmitted to the host computer 2 via the microcomputer I / F30.
[0018]
The above description focuses on reading data from the non-contact type wireless communication medium 20. However, when writing data to the wireless communication medium 20, power is supplied in the same process as described above, and data is written. Write.
[0019]
As described above, in the embodiment, the communication error bit is set to 8 bits, but this may be a plurality of bits, and is not limited to 8 bits.
Although the communication error determination circuit of the embodiment is described as a hardware circuit, it is needless to say that the communication error determination circuit may be processed by a program or a gate array of firmware, and may be a determination unit in this sense.
Further, the reader / writer of the non-contact information storage medium in the embodiment only needs to have a reader function of reading data, and may be a so-called reader. The reader / writer or the reader of the non-contact information storage medium may be built in the host computer or external.
[0020]
【The invention's effect】
As described above, according to the present invention, a frame is divided into a plurality of subframes having a predetermined number of bytes, and various communication errors are determined in subframe units. Even if the number increases, the size and speed of the determination means (determination circuit and the like) can be reduced.
As a result, it is possible to easily realize a wireless communication IC information processing system and a wireless communication IC that can easily perform communication error detection processing capable of detecting various types of errors and perform high-speed error detection processing.
[Brief description of the drawings]
FIG. 1 is a block diagram of a wireless communication IC information processing system using a wireless communication IC reader / writer to which the present invention is applied.
FIG. 2 is an explanatory diagram of a format of a data transmission protocol using a wireless communication medium.
FIG. 3 is an explanatory diagram of subframe reception data in a transmission / reception buffer memory;
FIG. 4 is an explanatory diagram of the communication error code.
[Explanation of symbols]
1. Non-contact type information storage medium wireless communication IC information processing system,
2. Host computer, 3. Non-contact wireless communication medium reader / writer,
4 ... transmission frame,
5: encoder (ENC), 6: modulation circuit (MOD),
7 transmission circuit, 8 detection circuit, 9 demodulation circuit (DEM),
10 ... decoder, 20 ... wireless communication medium,
21: loop antenna, 22: IC,
30 ... microcomputer IF, 31 ... control circuit,
32 transmission / reception circuit, 33 transmission / reception buffer memory,
35: communication error determination circuit, 35a: 8-bit error register,
36 ... Loop antenna.

Claims (5)

A non-contact information storage medium having a built-in wireless communication IC, and data stored in a memory built in the wireless communication IC by supplying power to the non-contact information storage medium in units of frames having a predetermined capacity. In a wireless communication IC reader / writer for reading and transferring to a higher-level information processing device,
A receiving unit that divides the frame into a plurality of subframes having a predetermined number of bytes and receives data a plurality of times;
Determining means for determining whether there is a communication error for each of the received subframe units,
And a reception stop unit for stopping reception from the wireless communication IC when it is determined that the communication error exists, as a result of the determination by the determination unit,
A wireless communication IC reader / writer for detecting a plurality of types of communication errors; The judging means is a judging circuit, wherein the subframe is stored in a receiving memory as data to which the error code is added, and the plurality of types of communication error results are communicated in place of the error code at the position of the error code. 2. The wireless communication IC reader / writer according to claim 1, wherein the wireless communication IC reader / writer is stored as error information, and sends the communication error result to the upper data processing device in synchronization with a timing at which the frame is received. The communication error result is composed of a plurality of bits corresponding to the plurality of types of communication errors, and assigns each bit position to a communication error having a different content to detect a communication error, and detects data of the frame. 3. The wireless communication IC reader / writer according to claim 2, wherein a plurality of bits of the logical sum of the communication error result are sent to the upper data processing device. A wireless communication IC information processing system comprising the wireless communication IC reader / writer according to claim 1 and the upper data processing device. A wireless communication IC that divides the frame into the subframes and transmits data to the wireless communication IC reader / writer according to claim 1.

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