JP2004279849A - Reciprocating deflection circuit and image display device having the same - Google Patents

Abstract

Provided is a reciprocating deflection circuit capable of sufficiently suppressing an amplitude fluctuation component of a horizontal deflection current due to a disturbance during a vertical flyback period with a non-adjustable and easy configuration.
A horizontal deflection circuit includes a voltage generation circuit, a pulse generation circuit, a resonance circuit, and a resonance frequency adjustment circuit. Further, resonance circuit 60K includes horizontal deflection coil 60 and resonance capacitor 61, and resonance frequency adjustment circuit 80 includes transistor 81 and adjustment capacitor 82. In the resonance circuit 60K, the horizontal deflection coil 60 and the resonance capacitor 61 resonate by applying a rectangular voltage. The resonance frequency adjustment circuit 80 connects the adjustment capacitor 82 in parallel with the resonance capacitor 61 during the vertical flyback period, and disconnects the adjustment capacitor 82 from the resonance capacitor 81 during the vertical effective scanning period. As a result, the resonance frequency changes between the vertical blanking period and the vertical effective scanning period.
[Selection] Fig. 2

Description

【００６７】
Ｌ１は共振回路６０Ｋにおける水平偏向コイル６０のインダクタンス成分を示し、Ｃ１は共振コンデンサ６１の容量値を示す。また、上式（１）において、垂直帰線期間ＲＴの共振周波数ｆｂは次式により表される。
【００６８】
【数２】

【００６９】
Ｃ２は調整コンデンサ８２の容量値を示し、Ｌ１は水平偏向コイル６０のインダクタンス成分を示し、Ｃ１は共振コンデンサ６１の容量値を示す。
【００７０】
以上より本例では、調整コンデンサ８２の容量値Ｃ２は上式（１）を満足する値に設定される。
【００７１】
図６は、共振回路６０Ｋにおける垂直有効走査期間ＳＴの共振周波数ｆｏと垂直帰線期間ＲＴの共振周波数ｆｂとを説明するための波形図である。図６（ａ）に垂直有効走査期間ＳＴの水平偏向電流Ａ２が示され、図６（ｂ）に垂直帰線期間ＲＴの水平偏向電流Ａ２が示されている。
【００７２】
図６（ａ）に示すように、垂直有効走査期間ＳＴにおける水平偏向電流Ａ２の周期は１／ｆｏで表される。なお、本実施の形態に係る映像表示装置１００において、電子ビームの偏向動作は往路と復路とでそれぞれ１走査線を形成するので、水平走査周期は１／２ｆｏとなる。
【００７３】
一方、図６（ｂ）に示すように、垂直帰線期間ＲＴにおける水平偏向電流Ａ２の周期は１／ｆｂで表される。
【００７４】
以下に、映像に現れるリンギングについての実験結果を説明する。図７は垂直有効走査期間ＳＴの共振周波数ｆｏに対する垂直帰線期間ＲＴの共振周波数ｆｂの比率とリンギングとの関係の測定結果を示すグラフであり、図８は垂直有効走査期間ＳＴの共振周波数ｆｏに対する垂直帰線期間ＲＴの共振周波数ｆｂの比率に応じた画面の左上の部分での映像に現れるリンギングを示す模式図である。
【００７５】
図７において、横軸は数式（１）により算出される垂直帰線期間ＲＴの共振周波数ｆｂと垂直有効走査期間ＳＴの共振周波数ｆｏとの比率Ｒであり、縦軸は図５（ａ）に示す変動成分の最大振幅値αおよび図５（ｂ）に示す垂直方向の画素の乱れの持続距離Ｒβが画面の垂直方向の長さに占める割合である。
【００７６】
曲線Ｔｒは、図５（ａ）に示す変動成分Ａ２−Ａ１の最大振幅値αと比率Ｒとの関係を示す。曲線Ｔｒによれば、比率Ｒが０．９０の場合に最大振幅値αが約１０ｍＡ程度であり、比率Ｒが０．９２の場合に最大振幅値αが約１５ｍＡ程度であり、比率Ｒが０．９４の場合に最大振幅値αが約４５ｍＡ程度である。また、比率Ｒが０．９６の場合に最大振幅値αが約９０ｍＡ程度であり、比率αが０．９８の場合に最大振幅値αが約３５０ｍＡ程度である。
【００７７】
以上の実験結果によれば、比率Ｒが０．９６以下の場合には、比率Ｒが０．９８の場合に比べて最大振幅値αが３分の１以下となり、リンギングの水平方向成分が低減される。また、比率Ｒが０．９４以下の場合には、比率Ｒが０．９８の場合に比べて最大振幅値αが５分の１以下となり、リンギングの水平方向成分が大幅に低減される。さらに、比率Ｒが０．９２以下の場合には、比率Ｒが０．９８の場合に比べて最大振幅値αが１０分の１以下となり、リンギングの水平方向成分が、さらに大幅に低減される。そして、比率Ｒが０．９０以下になると、最大振幅値αがほとんど０に近づき、リンギングの水平方向成分がほとんどなくなる。
【００７８】
一方、曲線Ｊｉは、図５（ｂ）の持続距離Ｒβの画面の垂直方向に占める割合と比率Ｒとの関係を示す。
【００７９】
曲線Ｊｉによれば、比率Ｒが０．９０の場合に持続距離の割合が０であり、比率Ｒが０．９２の場合に持続距離の割合が約０．０５であり、比率Ｒが０．９４の場合に持続距離の割合が約０．１５である。また、比率Ｒが０．９６の場合に持続距離の割合が約０．５であり、比率Ｒが０．９８の場合に持続距離の割合が約１．０である。
【００８０】
以上の実験結果によれば、比率Ｒが０．９６以下の場合には、比率Ｒが０．９８の場合に比べて持続距離の割合が半分以下となり、比率Ｒが０．９４以下の場合には、比率Ｒが０．９８の場合に比べて持続距離の割合が５分の１以下となる。また、比率Ｒが０．９２以下の場合には、比率Ｒが０．９８の場合に比べて持続距離の割合が１０分の１以下となり、比率Ｒが０．９０になると、持続距離の割合がほぼ０となる。
【００８１】
ここで、比率Ｒが０．９である場合のＣＲＴ７上に現れるリンギングが図８（ａ）に示されている。図８（ａ）によれば、比率Ｒが０．９の場合にＣＲＴ７上に示される映像にはほとんどリンギングは認められない。
【００８２】
続いて、比率Ｒが０．９２である場合のＣＲＴ７上に現れるリンギングが図８（ｂ）に示されている。図８（ｂ）によれば、比率Ｒが０．９２の場合にＣＲＴ７上に示される映像には、水平方向に小さな振幅でリンギングが認められ、垂直方向に短い範囲でリンギングが認められる。
【００８３】
また、比率Ｒが０．９４である場合のＣＲＴ７上に現れるリンギングが図８（ｃ）に示されている。図８（ｃ）によれば、比率Ｒが０．９４の場合にＣＲＴ７上に示される映像には、水平方向にやや小さな振幅でリンギングが認められ、垂直方向にやや短い範囲でリンギングが認められる。
【００８４】
さらに、比率Ｒが０．９６である場合のＣＲＴ７上に現れるリンギングが図８（ｄ）に示されている。図８（ｄ）によれば、比率Ｒが０．９６の場合にＣＲＴ７上に示される映像には、水平方向にやや大きい振幅でリンギングが認められ、垂直方向のほぼ全体に渡りリンギングが認められる。
【００８５】
最後に、比率Ｒが０．９８である場合のＣＲＴ７上に現れるリンギングが図８（ｅ）に示されている。図８（ｅ）によれば、比率Ｒが０．９８の場合にＣＲＴ７上に示される映像には、水平方向に非常に大きい振幅でリンギングが認められ、垂直方向の全体に渡りリンギングが認められる。
【００８６】
以上に示す実験結果から、比率Ｒを０．９６以下に設定することが好ましく、０．９４以下に設定することがより好ましいことがわかる。また、比率Ｒを０．９２以下に設定することがさらに好ましく、０．９０以下に設定することが最も好ましいことがわかる。
【００８７】
したがって、比率Ｒが０．９６以下となるように調整コンデンサ８２の容量値Ｃ２を設定することが好ましく、比率Ｒが０．９４以下となるように調整コンデンサ８２の容量値Ｃ２を設定することがより好ましいことがわかる。また、比率Ｒが０．９２以下となるように調整コンデンサ８２の容量値Ｃ２を設定することがさらに好ましく、Ｒが０．９０以下となるように調整コンデンサ８２の容量値Ｃ２を設定することが最も好ましいことがわかる。
【００８８】
なお、垂直帰線期間ＲＴにおいては、垂直有効走査期間ＳＴに比べて水平走査周期が大きくなるが、垂直帰線期間ＲＴには画面上に映像が表示されないので不都合が生じない。
【００８９】
続いて、本発明の実施の形態に係る水平偏向回路６の具体的な構成例および動作について図９に基づき説明する。図９は、本実施の形態に係る水平偏向回路６の具体的な構成例を示す回路図である。
【００９０】
図９の水平偏向回路６は、パルス生成回路１０、電圧発生回路２０、カレントトランス３３、垂直走査期間検出回路４０、共振回路６０Ｋ、振幅変動補正回路７０および共振周波数調整回路８０から構成される。なお、垂直走査期間検出回路４０は図２のパルス生成回路３０に相当する。
【００９１】
共振回路６０Ｋは水平偏向コイル６０および共振コンデンサ６１を含む。さらに、水平偏向コイル６０はインダクタンスＬＨおよび抵抗成分ＲＨを有する。共振周波数調整回路８０は、トランジスタ８１および調整コンデンサ８２を備える。カレントトランス３３は、１次側コイルＰおよび２次側コイルＳを含む。
【００９２】
電圧発生回路２０は、位相比較器２１、ローパスフィルタ（以下、ＬＰＦと略記する。）回路２２、パルス幅制御部２３、スイッチング回路２４およびコンパレータ２６を備える。ここで、電圧発生回路２０のスイッチング回路２４は、トランジスタ２４ａ，２４ｂおよびダイオード（整流素子）２４ｃ，２４ｄを備える。
【００９３】
振幅変動補正回路７０は、コンパレータ７１、位相比較器７２、ＬＰＦ回路７３、減衰器７４、パワーアンプ７５および抵抗７６を備える。ここで、振幅変動補正回路７０のパワーアンプ７５は、オペアンプ７５ｂおよび抵抗７５ａ，７５ｃから構成される。
【００９４】
ここで、水平偏向コイル６０を流れる水平偏向電流は、水平偏向コイル６０が有する抵抗成分ＲＨの影響により歪を生じる。カレントトランス３３および振幅変動補正回路７０は、抵抗成分ＲＨの水平偏向電流に与える影響をなくすために用いられており、抵抗成分ＲＨを打ち消す負抵抗成分の役割を果たしている。
【００９５】
パルス生成回路１０には図１の同期信号分離回路３より水平同期信号ＨＳが与えられる。パルス生成回路１０は、入力された水平同期信号ＨＳより電子ビームを水平方向に往復偏向させるためのタイミングおよび偏向方向を示す往復タイミングパルスＳＤならびに表示画面上における電子ビームの理想的な中心位置を示すラインセンターパルスＬＣを生成する。パルス生成回路１０は、生成した往復タイミングパルスＳＤを電圧発生回路２０に与え、生成したラインセンターパルスＬＣを振幅変動補正回路７０に与える。
【００９６】
一方、垂直走査期間検出回路４０には図１の同期信号分離回路３より垂直同期信号ＶＳが与えられる。垂直走査期間検出回路４０は、垂直同期信号ＶＳに応答して垂直帰線期間ＲＴおよび垂直有効走査期間ＳＴを検出する。そして、垂直帰線期間ＲＴに調整コンデンサ８２を共振コンデンサ６１に並列に接続し、垂直有効走査期間ＳＴに調整コンデンサ８２を共振コンデンサ６１から切り離すためのパルス信号ＶＢを共振周波数調整回路８０に与える。なお、このパルス信号ＶＢは、上述の図２においてブランキング期間検出信号ＶＢに相当する。
【００９７】
ここで、電圧発生回路２０の動作について図９および図１０に基づき説明する。図１０は、電圧発生回路２０の内部で発生する各種信号および電流の例を示す波形図である。図１０においては、往路および復路の切替タイミングが一点鎖線Ｔｉにより示されている。なお、ここでは理解を容易にするため水平偏向電流の波形は三角波形とする。
【００９８】
電圧発生回路２０において、パルス生成回路１０より与えられた往復タイミングパルスＳＤは位相比較器２１に入力される。図１０（ａ）に位相比較器２１に入力される往復タイミングパルスＳＤの波形の一例を示す。図１０（ａ）によれば、例えば、往復タイミングパルスＳＤは、論理ハイのときに電子ビームを往方向（画面の左から右の方向）に偏向することを示し、論理ローのときに電子ビームを復方向（画面の右から左の方向）に偏向することを示す。そして、電圧発生回路２０の内部では、往復タイミングパルスＳＤに基づいて、以下に示すように、水平偏向電流のフィードバック制御が行われる。
【００９９】
パルス幅制御部２３においては、後述の制御電圧ＰＶの電圧のレベルに基づいてパルス信号ＴＳ，ＲＳが生成される。パルス信号ＴＳ，ＲＳは、図１０（ｂ），（ｃ）に示すように、互いに逆位相となっている。パルス幅制御部２３は、生成したパルス信号ＴＳ，ＲＳをスイッチング回路２４に与える。
【０１００】
スイッチング回路２４においては、トランジスタ２４ａのベースにパルス幅制御部２３からのパルス信号ＴＳが与えられ、コレクタは電源端子２４ｅに接続され、エミッタはノードＮ１に接続されている。また、トランジスタ２４ｂのベースにパルス幅制御部２３からのパルス信号ＲＳが与えられ、コレクタはノードＮ１に接続され、エミッタは接地端子に接続されている。ダイオード２４ｃのアノードはノードＮ１に接続され、カソードは電源端子２４ｅに接続されている。ダイオード２４ｄのアノードは接地端子に接続され、カソードはノードＮ１に接続されている。
【０１０１】
パルス信号ＴＳが論理ハイになり、パルス信号ＲＳが論理ローになると、トランジスタ２４ａがオンし、トランジスタ２４ｂがオフする。それにより、電源端子２４ｅからトランジスタ２４ａを通して共振コンデンサ６１または調整コンデンサ８２に電流が流れる。パルス信号ＴＳが論理ローになり、パルス信号ＲＳが論理ハイになると、トランジスタ２４ａがオフし、トランジスタ２４ｂがオンする。それにより、共振コンデンサ６１または調整コンデンサ８２からトランジスタ２４ｂを通して接地端子に電流が流れる。このようにして、図１０（ｄ）に示すように、水平偏向コイル６０に水平偏向電流ＡＬが流れる。このとき、ノードＮ１には矩形電圧が発生する。この場合の水平偏向電流ＡＬは往復タイミングにずれを生じている。
【０１０２】
一方、コンパレータ２６には、ノードＮ１に発生する矩形電圧および基準電圧Ｖ_ｒｅｆが入力されている。
【０１０３】
コンパレータ２６は、ノードＮ１の矩形電圧と基準電圧Ｖ_ｒｅｆとを比較する。例えば、コンパレータ２６は、ノードＮ１の矩形電圧が基準電圧Ｖ_ｒｅｆより高い場合に論理ハイの位相比較パルスＣＤを位相比較器２１に出力し、矩形電圧が基準電圧Ｖ_ｒｅｆよりも低い場合に論理ローの位相比較パルスＣＤを位相比較器２１に出力する。図１０（ｅ）に、コンパレータ２６から出力される位相比較パルスＣＤの波形の一例を示す。
【０１０４】
位相比較器２１は、パルス生成回路１０より与えられる往復タイミングパルスＳＤとコンパレータ２６より与えられる位相比較パルスＣＤとの位相比較を行う。この位相比較は、往復タイミングパルスＳＤおよび位相比較パルスＣＤのそれぞれの立ち上がりタイミングまたは立下りタイミングに基づき行われる。位相比較により得られた位相差成分は位相差信号ＰＤとしてＬＰＦ回路２２へ出力される。図１０（ｆ）に、位相比較器２１により出力される位相差信号ＰＤの波形の一例を示す。
【０１０５】
ＬＰＦ回路２２は、入力される位相差信号ＰＤを積分し、制御電圧ＰＶを生成する。図１０（ｇ）に、ＬＰＦ回路２２により生成される制御電圧ＰＶの一例を示す。パルス幅制御部２３は、制御電圧ＰＶに基づいて、上記のパルス信号ＴＳ，ＲＳを発生する。
【０１０６】
このようにして、図１０（ｈ）に示すように水平偏向電流ＡＬの往路および復路の切替タイミングが正確に制御される。
【０１０７】
続いて、共振周波数調整回路８０および振幅変動補正回路７０の動作について図９および図１１に基づき説明する。
【０１０８】
図１１は、本実施の形態に係る振幅振動補正回路７０により発生する各種信号および電流の例を示す波形図である。図６においては、往路および復路の切替タイミングが一点鎖線Ｔｉにより示されている。なお、図１０と同様、水平偏向電流の波形は三角波形とする。
【０１０９】
図９の共振周波数調整回路８０において、トランジスタ８１には図３に示す垂直帰線期間ＲＴに論理ハイのパルス信号ＶＢが与えられ、図３に示す垂直有効走査期間ＳＴに論理ローのパルス信号ＶＢが与えられる。
【０１１０】
トランジスタ８１のベースには垂直走査期間検出回路４０からパルス信号ＶＢが与えられ、コレクタは調整コンデンサ８２に接続され、エミッタはノードＮ１に接続されている。
【０１１１】
パルス信号ＶＢが論理ハイになると、トランジスタ８１がオンする。それにより、調整コンデンサ８２が共振コンデンサ６１と並列に接続される。パルス信号ＶＢが論理ローになると、トランジスタ８１がオフする。それにより、調整コンデンサ８２が共振コンデンサ６１から切り離される。
【０１１２】
このように、共振周波数調整回路８０のトランジスタ８１は、垂直帰線期間ＲＴに調整コンデンサ８２を共振コンデンサ６１と並列に接続し、垂直有効走査期間ＳＴに調整コンデンサ８２を共振コンデンサ６１から切り離す。
【０１１３】
パルス生成回路１０より与えられたラインセンターパルスＬＣは位相比較器７２に入力される。位相比較器７２に入力されるラインセンターパルスＬＣの波形の一例を図１１（ａ）に示す。図１１（ａ）において、ラインセンターパルスＬＣは、その立上りタイミングおよび立下りタイミングにより往路の走査および復路の走査における理想的な中心タイミングを示す。
【０１１４】
一方、水平偏向コイル６０に直列にカレントトランス３３の一次巻線Ｐが接続されている。二次巻線Ｓの一端は接地端子に接続され、他端はノードＶ７に接続されている。ノードＶ７は抵抗７６を介して接地端子に接続されている。カレントトランス３３の一次巻線Ｐには図１０（ｈ）に示す水平偏向電流ＡＬが流れ、二次巻線Ｓには水平偏向電流ＡＬに基づく二次電流が流れる。図１１（ｂ）に、二次巻線Ｓに流れる二次電流ＡＬ２の波形の一例を示す。
【０１１５】
二次電流ＡＬ２が抵抗７６を流れることによりノードＶ７に電圧が発生する。ノードＶ７の電圧はコンパレータ７１および減衰器７４に供給される。
【０１１６】
コンパレータ７１は、ノードＶ７の電圧と接地電位とを比較し、ゼロクロスパルスＣＤ２を出力する。例えば、コンパレータ７１は、ノードＶ７の電圧が接地電位より高い場合に論理ハイのゼロクロスパルスＣＤ２を位相比較器７２に出力し、ノードＶ７の電圧が接地電位より低い場合に論理ローのゼロクロスパルスＣＤ２を位相比較器７２に出力する。図１１（ｃ）にコンパレータ７１から出力されるゼロクロスパルスＣＤ２の波形の一例を示す。ゼロクロスパルスＣＤ２の立ち上がりタイミングおよび立ち下がりタイミングは、水平偏向電流ＡＬが電流値０のレベルを交差するタイミング（ゼロクロス点）に相当する。
【０１１７】
位相比較器７２は、パルス生成回路１０より与えられるラインセンターパルスＬＣとコンパレータ７１より与えられるゼロクロスパルスＣＤ２との位相比較を行う。この位相比較は、ラインセンターパルスＬＣおよびゼロクロスパルスＣＤ２のそれぞれの立上りタイミングおよび立下りタイミングに基づき行われる。位相比較により得られた位相差成分は位相差信号ＰＤ２としてＬＰＦ回路７３へ出力される。図１１（ｄ）に、位相比較器７２により出力される位相差信号ＰＤ２の波形の一例を示す。
【０１１８】
ＬＰＦ回路７３は、入力される位相差信号ＰＤ２を積分し、制御電圧ＰＶ２を生成する。ＬＰＦ回路７３により生成された制御電圧ＰＶ２は減衰器７４へ与えられる。図１１（ｅ）に、ＬＰＦ回路７３により生成される制御電圧ＰＶ２の波形の一例を示す。
【０１１９】
減衰器７４の入力端子には、ノードＶ７の電圧が与えられる。減衰器７４は、ノードＶ７の電圧を制御電圧ＰＶ２に基づいて減衰させ、減衰された電圧を振幅変動補正信号としてパワーアンプ７５に与える。
【０１２０】
パワーアンプ７５は、減衰器７４より与えられる振幅変動補正信号を反転増幅し、一次巻線Ｐの一端のノードＶ８に与える。それにより、ノードＶ８の電圧が上昇し、水平偏向電流ＡＬが減少する。その結果、一次巻線Ｐに流れる水平偏向電流ＡＬが図１１（ｆ）に示すように補正される。このようにして、水平偏向コイル６０には、抵抗成分ＲＨによる歪がない理想的な水平偏向電流ＡＬが流れることとなる。すなわち、振幅変動補正回路７０は、負性抵抗成分として機能する。
【０１２１】
以上に示す水平偏向回路６においては、垂直帰線期間ＲＴに共振周波数調整回路８０の共振コンデンサ８２が共振コンデンサ６１と並列に接続される。これにより、調整コンデンサ８１の容量値を上述の式（１）が満たされるように設定することにより、共振回路６０Ｋにおいて外乱ＧＶの影響を受けにくい共振周波数を得ることができる。その結果、無調整かつ簡単な構成で外乱ＧＶにより水平偏向電流に発生する振幅変動成分を十分に抑制することが可能となる。
【０１２２】
本実施の形態において、図９の振幅変動補正回路７０は水平偏向コイル６０の抵抗成分ＲＨの影響を低減するために用いているが、抵抗成分ＲＨの水平偏向電流に対する影響が少なく無視できる程のものであれば、特に必要となるものではない。
【０１２３】
本実施の形態において、共振コンデンサ６１が共振容量に相当し、電圧発生回路２０がパルス電圧印加手段に相当し、垂直有効走査期間ＳＴにおける共振回路６０Ｋの共振周波数ｆｏが第１の値に相当し、垂直帰線期間ＲＴの共振周波数ｆｂが第２の値に相当する。また、共振周波数調整回路８０が共振周波数切替手段に相当し、調整コンデンサ８２が調整用容量に相当し、トランジスタ８１がスイッチ手段に相当し、垂直帰線期間ＲＴの共振周波数ｆｂと垂直有効走査期間ＳＴの共振周波数ｆｏとの比率が第１の値に対する第２の値に相当し、振幅変動補正回路７０が負性抵抗成分発生手段に相当する。さらに、水平偏向回路６が往復偏向回路に相当し、垂直偏向回路５が垂直偏向回路に相当する。
【０１２４】
【発明の効果】
本発明に係る往復偏向回路においては、パルス電圧印加手段により水平偏向コイルに水平走査周期の２倍の周期で変化するパルス電圧が印加される。さらに、共振周波数切替手段により垂直有効走査期間において共振回路の共振周波数が第１の値に設定され、垂直帰線期間において共振回路の共振周波数が第１の値と異なる第２の値に設定される。
【０１２５】
このように、共振回路の共振周波数を垂直帰線期間において外乱の影響を受けにくい値に切替えることにより、外乱の影響により発生する水平偏向電流の振幅変動成分が十分に低減される。さらに、上記共振周波数の切替えは、共振周波数切替手段により行われる。したがって、共振周波数切替手段を設けることで無調整かつ簡単な構成で外乱の影響が低減される。
【図面の簡単な説明】
【図１】本実施の形態に係る映像表示装置の構成を示すブロック図
【図２】本実施の形態に係る水平偏向回路の動作を説明するための回路図
【図３】図２の水平偏向回路の動作を示す波形図
【図４】図２のトランジスタが常にオフとなっていると仮定した場合の垂直同期信号および垂直偏向電流の測定結果を模式的に示した図および水平偏向電流の包絡線の一部Ｒｎを拡大した図
【図５】水平偏向電流の変動成分がＣＲＴに表示される映像に与える影響を説明するための説明図
【図６】共振回路における垂直有効走査期間の共振周波数と垂直帰線期間の共振周波数とを説明するための波形図
【図７】垂直有効走査期間の共振周波数と垂直帰線期間の共振周波数との比率とリンギングとの関係の測定結果を示すグラフ
【図８】垂直有効走査期間の共振周波数と垂直帰線期間の共振周波数との比率に応じた画面の左上の部分での映像に現れるリンギングを示す模式図
【図９】本実施の形態に係る水平偏向回路の具体的な構成例を示す回路図
【図１０】電圧発生回路の内部で発生する各種信号および電流の例を示す波形図
【図１１】本実施の形態に係る振幅振動補正回路により発生する各種信号および電流の例を示す波形図
【図１２】自励式の発振回路を備えるサイン波偏向回路を示す概略図
【図１３】図１２のサイン波偏向回路の偏向コイルに印加される電圧および電流の経時的変化の一例を示す波形図
【図１４】水平偏向コイルに与えられる外乱の影響を説明するための図
【図１５】外乱電圧による水平偏向電流の変動成分を十分に低減可能な振幅補正回路の一例を示す模式図
【図１６】外乱により発生する水平偏向電流の変動成分の低減方法を説明するための波形図
【符号の説明】
５ 垂直偏向回路
６ 水平偏向回路
２０ 電圧発生回路
３０ パルス生成回路
６０Ｋ 共振回路
６１ 共振コンデンサ
７０ 振幅変動補正回路
８０ 共振周波数調整回路
８１ トランジスタ
８２ 調整コンデンサ
ｆｂ 共振周波数
ｆｈ 水平走査周波数
ｆｏ 共振周波数
ＳＴ 垂直有効走査期間
ＲＴ 垂直帰線期間[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a reciprocating deflection circuit for reciprocally scanning an electron beam in a horizontal direction of a display screen, and a video display device including the same.
[0002]
[Prior art]
In the field of video display devices such as a cathode ray tube (hereinafter, referred to as CRT) display device, use of a reciprocating deflection circuit suitable for displaying a high-definition image has been proposed. As such a reciprocating deflection circuit, there has been proposed a sine wave deflection circuit that reciprocally deflects an electron beam by supplying a sine waveform horizontal deflection current to a horizontal deflection coil (see Patent Document 1).
[0003]
FIG. 12 is a schematic diagram showing a sine wave deflection circuit including a self-excited oscillation circuit. FIG. 13 is a waveform diagram showing an example of a temporal change of the voltage and the current applied to the deflection coil 95 of the sine wave deflection circuit of FIG.
[0004]
The sine wave deflection circuit 90 in FIG. 12 includes a pulse output circuit 91, a coil 92, a resonance capacitor 93, a waveform correction capacitor 94, a deflection coil 95, a waveform shaping circuit 96, and a drive circuit 97.
[0005]
The pulse output circuit 91 supplies a pulse voltage to a resonance circuit including a resonance capacitor 93, a waveform correction capacitor 94, and a deflection coil 95 via a coil 92. The potential at node 90D between the waveform correcting capacitor 94 and the deflection coil 95 is supplied to the waveform shaping circuit 96. The waveform shaping circuit 96 shapes the potential of the node 90. The output signal of the waveform shaping circuit 96 is provided to the pulse output circuit 91 via the drive circuit 97.
[0006]
As described above, in the sine wave deflecting circuit 90, the voltage between both ends of the deflecting coil 95 is shaped and fed back to the drive circuit 97, so that self-excited oscillation is performed.
[0007]
FIG. 13A is a waveform diagram showing a voltage across the deflection coil 95 in FIG. 12, and FIG. 13B is a waveform diagram showing a horizontal deflection current flowing in the deflection coil 95 in FIG.
[0008]
A voltage represented by a solid line V95 in FIG. 13A is applied to both ends of the deflection coil 95. As a result, a horizontal deflection current having an ideal sine waveform represented by a solid line A95 in FIG.
[0009]
According to the sine wave deflecting circuit 90 having the above configuration, by forming a resonance circuit including the deflecting coil 95, power consumption can be extremely reduced, and a stable operation is performed with the phase relationship between energy supply and resonance always constant. be able to.
[0010]
By the way, in the horizontal deflection coil for deflecting the electron beam reciprocally in the horizontal direction, for example, the ideal current waveform of the horizontal deflection current shown in FIG. I can't get it.
[0011]
Hereinafter, the influence of the disturbance generated in the vertical flyback period on the horizontal deflection coil will be described with reference to FIG. 12 and FIGS. In the following description, the deflection coil 95 in FIG. 12 is a horizontal deflection coil.
[0012]
FIG. 14 is a diagram for explaining the influence of disturbance on the horizontal deflection current. In FIG. 12, when the pulse voltage V1 of FIG. 14A is output from the pulse output circuit 91, a horizontal deflection current A1 having a sine waveform as shown in FIG.
[0013]
Here, when the deflection coil 95 in FIG. 12 is affected by the disturbance GV generated in the vertical flyback period, FIG. 14C shows each of the vertical scanning periods VT including the vertical effective scanning period and the vertical flyback period. A disturbance voltage V2 is generated. Then, the current flowing through the deflection coil 95 in FIG. 12 is disturbed by being affected by the disturbance voltage V2. In this case, assuming that the current flowing through the deflection coil 95 is the horizontal deflection current A2, the horizontal deflection current A2 has, for example, a waveform shown in FIG.
[0014]
Thereby, the disturbance of the horizontal deflection current flowing through the deflection coil 95 is represented as a fluctuation component A2-A1. FIG. 14E shows an example of the fluctuation component A2-A1 of the horizontal deflection current. According to FIG. 14E, the disturbance of the current occurs every vertical scanning period VT together with the generation of the disturbance voltage V2.
[0015]
Here, the inventor has devised an amplitude correction circuit to sufficiently reduce the fluctuation component of the horizontal deflection current due to the disturbance voltage as described above (see Patent Document 2).
[0016]
FIG. 15 is a schematic diagram illustrating an example of an amplitude correction circuit capable of sufficiently reducing a fluctuation component of a horizontal deflection current due to a disturbance voltage. FIG. 16 is a waveform chart for explaining a method of reducing the fluctuation component of the horizontal deflection current generated by disturbance.
[0017]
According to FIG. 15, the amplitude correction circuit 900 includes a rectangular voltage generation circuit 901, a power supply voltage modulation circuit 902, a pulse generation circuit 903, and a resonance circuit 920. Note that the resonance circuit 920 includes a horizontal deflection coil Lj and a capacitor Cj.
[0018]
In the amplitude correction circuit 900 shown in FIG. 15, a pulse generation circuit 903 generates a pulse voltage S1 shown in FIG. 16A for each vertical scanning period VT, and supplies it to a power supply voltage modulation circuit 902.
[0019]
The power supply voltage VX is supplied to the power supply voltage modulation circuit 902 together with the pulse voltage S1. In power supply voltage modulation circuit 902, power supply voltage VX is modulated based on pulse voltage S 1, and modulated power supply voltage VC is applied to rectangular voltage generation circuit 901. The waveform of the power supply voltage VC is as shown in FIG.
[0020]
In the rectangular voltage generation circuit 901, a pulse voltage V 1 shown in FIG. 16C is generated using the supplied power supply voltage VC, and applied to the resonance circuit 920.
[0021]
In this case, the level of the pulse voltage V1 applied to the resonance circuit 920 during the vertical blanking period is lower than the pulse voltage V1 applied to the resonance circuit 920 during the vertical effective scanning period. As a result, the fluctuation component of the horizontal deflection current is reduced every vertical scanning period VT in which the disturbance voltage V2 occurs, and the ideal current waveform A1 shown in FIG. 16D can be continuously obtained.
[0022]
[Patent Document 1]
JP-A-3-70369
[Patent Document 2]
JP 2001-36347 A
[0023]
[Problems to be solved by the invention]
According to the amplitude correction circuit 900, the correction of the amplitude fluctuation of the horizontal deflection current is performed by generating the pulse voltage S1 in synchronization with the disturbance voltage V2. Therefore, the amplitude correction circuit 900 requires the pulse generation circuit 903, and has a complicated configuration.
[0024]
Further, in the amplitude correction circuit 900, it is necessary to adjust the pulse voltage S1 so that the amplitude fluctuation component of the horizontal deflection current due to the disturbance voltage V2 is minimized. In this case, the amplitude fluctuation component of the horizontal deflection current due to the disturbance voltage V2 must be measured using a measuring device. As described above, a step of adjusting the pulse voltage S1 is required at the time of manufacturing the amplitude correction circuit 900.
[0025]
SUMMARY OF THE INVENTION An object of the present invention is to provide a reciprocating deflection circuit capable of sufficiently suppressing an amplitude fluctuation component of a horizontal deflection current due to a disturbance during a vertical flyback period with a non-adjustable and easy configuration, and a video display device including the same. .
[0026]
[Means for Solving the Problems]
A reciprocating deflection circuit according to a first aspect of the present invention is a reciprocating deflection circuit for reciprocally deflecting an electron beam in a horizontal direction. The reciprocating deflection circuit includes a resonance circuit including a horizontal deflection coil and a resonance capacitor. Pulse voltage applying means for applying a pulse voltage that changes at a double cycle; a resonance frequency of the resonance circuit set to a first value during a vertical effective scanning period; and a resonance frequency of the resonance circuit set to a first value during a vertical flyback period. Resonance frequency switching means for setting a second value different from the value.
[0027]
In the reciprocating deflection circuit according to the first aspect of the invention, a pulse voltage that changes at twice the horizontal scanning period is applied to the horizontal deflection coil by the pulse voltage applying means. Further, the resonance frequency switching means sets the resonance frequency of the resonance circuit to a first value during the vertical effective scanning period, and sets the resonance frequency of the resonance circuit to a second value different from the first value during the vertical flyback period. You.
[0028]
As described above, by switching the resonance frequency of the resonance circuit to a value that is hardly affected by disturbance during the vertical flyback period, the amplitude fluctuation component of the horizontal deflection current generated by the influence of disturbance is sufficiently reduced. Further, the switching of the resonance frequency is performed by a resonance frequency switching unit. Therefore, by providing the resonance frequency switching means, the influence of disturbance is reduced with no adjustment and a simple configuration.
[0029]
The resonance frequency switching unit may include an adjustment capacitor and a switch unit that separates the adjustment capacitor from the resonance capacitor during the vertical effective scanning period and connects the adjustment capacitor to the resonance capacitor during the vertical blanking period.
[0030]
In this case, in the resonance frequency switching unit, the adjustment capacitor is disconnected from the resonance capacitor during the vertical effective scanning period by the switch unit, and the adjustment capacitor is connected to the resonance capacitor during the vertical blanking period. Thereby, the resonance frequency in the vertical blanking period is switched so as to be different from the resonance frequency in the vertical effective scanning period. In addition, since the switching operation of the resonance frequency is performed by the adjusting capacitor and the switch unit provided in the resonance frequency switching unit, the influence of disturbance is reduced with a simple and unadjusted configuration.
[0031]
The switch means may connect the adjustment capacitor in parallel with the resonance capacitor during the vertical flyback period. In this case, the adjusting capacitor is connected in parallel to the resonance capacitor during the vertical flyback period by the switch means. As a result, the resonance frequency in the vertical flyback period is switched so as to be lower than the resonance frequency in the vertical effective scanning period. In addition, since the switching operation of the resonance frequency is performed by the adjusting capacitor and the switch unit provided in the resonance frequency switching unit, the influence of disturbance is reduced with a simple and unadjusted configuration.
[0032]
The ratio of the second value to the first value may be 0.96 or less. Thereby, the horizontal component of the distortion appearing in the image is significantly reduced due to the influence of the disturbance, and the sustaining distance of the vertical distortion is significantly reduced.
[0033]
The ratio of the second value to the first value may be 0.90 or less. As a result, due to the influence of the disturbance, the horizontal component of the distortion appearing in the video is almost eliminated, and the sustaining distance of the vertical distortion is almost eliminated.
[0034]
The horizontal deflection coil may further include a negative resistance component generating unit that has an inductance component and a resistance component and generates a negative resistance component for canceling the resistance component of the horizontal deflection coil.
[0035]
In this case, the negative resistance component generating means generates a negative resistance component for canceling the resistance component of the horizontal deflection coil. Thereby, distortion of the horizontal deflection current generated by the resistance component of the horizontal deflection coil is prevented. Therefore, an ideal horizontal deflection current can be obtained, so that disturbance of pixels that should be arranged vertically is prevented.
[0036]
A video display device according to a second aspect of the present invention is a cathode ray tube, a reciprocating deflection circuit for horizontally reciprocating an electron beam in the cathode ray tube, and a vertical deflection circuit for deflecting the electron beam in the cathode ray tube in a vertical direction. A reciprocating deflection circuit includes a resonance circuit including a horizontal deflection coil and a resonance capacitor; a pulse voltage application unit configured to apply a pulse voltage that changes in a cycle twice as long as the horizontal scanning cycle to the horizontal deflection coil; Resonance frequency switching means for setting the resonance frequency of the resonance circuit to a first value during the period and setting the resonance frequency of the resonance circuit to a second value different from the first value during the vertical flyback period. is there.
[0037]
In the video display device according to the second aspect of the invention, the electron beam in the cathode ray tube is reciprocated in the horizontal direction by the reciprocating deflection circuit, and the electron beam in the cathode ray tube is deflected in the vertical direction by the vertical deflection circuit. Further, in the reciprocating deflection circuit, a pulse voltage which changes in a cycle twice as long as the horizontal scanning cycle is applied to the horizontal deflection coil by the pulse voltage applying means. Further, the resonance frequency switching means sets the resonance frequency of the resonance circuit to a first value during the vertical effective scanning period, and sets the resonance frequency of the resonance circuit to a second value different from the first value during the vertical flyback period. You.
[0038]
In this way, by switching the resonance frequency of the resonance circuit in the reciprocating deflection circuit to a value that is less affected by disturbance during the vertical flyback period, the amplitude variation component of the horizontal deflection current generated by the influence of disturbance is sufficiently reduced. You. Further, the switching of the resonance frequency in the reciprocating deflection circuit is performed by a resonance frequency switching unit. Therefore, by providing the resonance frequency switching means, the influence of disturbance is reduced with no adjustment and a simple configuration.
[0039]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, a reciprocating deflection circuit according to the present embodiment and a video display device including the same will be described with reference to FIGS.
[0040]
FIG. 1 is a block diagram showing a configuration of the video display device according to the present embodiment.
1 includes a video signal processing circuit 1, a color signal processing circuit 2, a synchronization signal separation circuit 3, a vertical deflection circuit 5, a horizontal deflection circuit 6, and a cathode ray tube (hereinafter referred to as CRT) 7. A vertical deflection coil 50 of the vertical deflection circuit 5 and a horizontal deflection coil 60 of the horizontal deflection circuit 6 are attached to the CRT 7.
[0041]
The video signal TV is supplied to the video signal processing circuit 1 and the synchronization signal separation circuit 3 in FIG.
[0042]
The synchronization signal separation circuit 3 separates a vertical synchronization signal VS and a horizontal synchronization signal HS from the supplied video signal TV. Then, the synchronization signal separation circuit 3 supplies the separated vertical synchronization signal VS to the video signal processing circuit 1, the vertical deflection circuit 5 and the horizontal deflection circuit 6, and supplies the separated horizontal synchronization signal HS to the video signal processing circuit 1 and the horizontal deflection circuit. Give to 6.
[0043]
The video signal processing circuit 1 extracts a color difference signal (I, Q) and a luminance signal Y from the supplied video signal TV in response to the vertical synchronization signal VS and the horizontal synchronization signal HS supplied from the synchronization signal separation circuit 3. To the color signal processing circuit 2. The color signal processing circuit 2 reproduces the primary color signal DS based on the color difference signals (I, Q) and the luminance signal Y, and outputs the primary color signal DS to the CRT 7.
[0044]
The vertical deflection circuit 5 supplies a vertical deflection current to a vertical deflection coil 50 attached to the CRT 7 using the vertical synchronization signal VS given from the synchronization signal separation circuit 3.
[0045]
The horizontal deflection circuit 6 supplies a horizontal deflection current to a horizontal deflection coil 60 attached to the CRT 7 using the vertical synchronization signal VS and the horizontal synchronization signal HS given from the synchronization signal separation circuit 3. In the present embodiment, the horizontal deflection current has a sine waveform having a period twice as long as the horizontal scanning period.
[0046]
In the CRT 7, the electron beam is deflected by the operation of the vertical deflection coil 50 of the vertical deflection circuit 5 and the horizontal deflection coil 60 of the horizontal deflection circuit 6, and an image based on the primary color signal DS given from the color signal processing circuit 2 is displayed. .
[0047]
Next, the horizontal deflection circuit 6 according to the embodiment of the present invention will be described. FIG. 2 is a circuit diagram for explaining the operation of the horizontal deflection circuit according to the present embodiment. FIG. 3 is a waveform chart showing the operation of the horizontal deflection circuit of FIG.
[0048]
2, the horizontal deflection circuit 6 includes a voltage generation circuit 20, a pulse generation circuit 30, a resonance circuit 60K, and a resonance frequency adjustment circuit 80. Further, resonance circuit 60K includes horizontal deflection coil 60 and resonance capacitor 61, and resonance frequency adjustment circuit 80 includes transistor 81 and adjustment capacitor 82.
[0049]
The reciprocating timing pulse SD generated based on the horizontal synchronizing signal HS is input to the voltage generating circuit 20. The voltage generation circuit 20 generates a rectangular voltage V1 shown in FIG. 3A based on the input reciprocating timing pulse SD, and applies it to the resonance circuit 60K.
[0050]
In the resonance circuit 60K, when the rectangular voltage V1 is applied, the horizontal deflection coil 60 and the resonance capacitor 61 resonate. As a result, a horizontal deflection current flows through the horizontal deflection coil 60, a horizontal deflection magnetic field is generated, and the electron beam is deflected in the horizontal direction. FIG. 3B shows an ideal current waveform of the horizontal deflection current A1.
[0051]
Incidentally, in the horizontal deflection coil 60, a disturbance voltage is generated due to the influence of the disturbance GV generated during the vertical flyback period, and the horizontal deflection current A1 fluctuates. FIG. 3C shows a disturbance voltage V2 generated by the disturbance GV during the vertical flyback period RT. In this example, the disturbance GV generated during the vertical blanking period RT is a flyback pulse generated during the vertical blanking period RT of the vertical deflection current.
[0052]
On the other hand, a blanking period detection signal VB generated based on the vertical synchronization signal VS is input to the pulse generation circuit 30. The pulse generation circuit 30 generates a control pulse CP for controlling the operation of the resonance frequency adjustment circuit 80 described below based on the input blanking period detection signal VB, and supplies the control pulse CP to the resonance frequency adjustment circuit 80. In this example, the control pulse CP becomes logic low during the vertical effective scanning period ST, and becomes logic high during the vertical blanking period RT.
[0053]
In the resonance frequency adjusting circuit 80, the control pulse CP given from the pulse generating circuit 30 is given to the base of the transistor 81. Thereby, when the control pulse CP becomes logic high, the transistor 81 is turned on, and the adjustment capacitor 82 is connected in parallel to the resonance capacitor 61. When the control pulse CP becomes logic low, the transistor 81 is turned off, and the adjustment capacitor 82 is disconnected from the resonance capacitor 81. As a result, the resonance capacitance value in the vertical blanking period RT differs from the resonance capacitance value in the vertical effective scanning period ST, and the resonance frequency changes.
[0054]
Here, assuming that the transistor 81 is always off, a horizontal deflection current A2 shown in FIG. The horizontal deflection current A2 is disturbed by the disturbance voltage V2 in each vertical scanning period VT including the vertical effective scanning period ST and the vertical blanking period RT. FIG. 3E shows the waveform of the fluctuation component A2-A1 of the horizontal deflection current due to the influence of the disturbance voltage V2. The fluctuation component A2-A1 of the horizontal deflection current is largest immediately after the vertical retrace period RT and gradually decreases. Such a fluctuation component A2-A1 of the horizontal deflection current appears as distortion in the image displayed on the CRT 7 in FIG.
[0055]
FIG. 4A is a diagram schematically illustrating a measurement result of the vertical synchronization signal VS and the vertical deflection current A2 when it is assumed that the transistor 81 in FIG. 2 is always off. FIG. 4B is an enlarged view of a part Rn of the envelope of the horizontal deflection current shown in FIG.
[0056]
In FIG. 4A, the horizontal deflection current A2 has a sine waveform having a period twice as long as the horizontal scanning period throughout the vertical effective scanning period ST and the vertical retrace period RT. The shape of the envelope (solid line M) in the vertical effective scanning period ST is adjusted according to the structure of the CRT 7 or the like.
[0057]
According to FIG. 4B, the solid line M, which is the envelope of the horizontal deflection current A2, has an amplitude fluctuation immediately after the vertical blanking period RT. In FIG. 4B, the dashed-dotted line N indicates an ideal comprehensive line of the horizontal deflection current having no amplitude fluctuation. In this case, assuming that the displacement of the solid line M with respect to the alternate long and short dash line N is Q, the change over time of the displacement Q corresponds to the fluctuation component A2-A1 of the horizontal deflection current in FIG. Therefore, the displacement Q of the solid line M with respect to the alternate long and short dash line N becomes maximum immediately after the vertical flyback period RT as shown in FIG. 4A, and gradually decreases thereafter.
[0058]
FIG. 5 is an explanatory diagram for explaining the effect of the fluctuation component A2-A1 of the horizontal deflection current on the image displayed on the CRT 7.
[0059]
FIG. 5A shows a temporal change of the fluctuation component A2-A1 of the horizontal deflection current. The fluctuation component A2-A1 of the horizontal deflection current has a maximum amplitude value α and a fluctuation period β.
[0060]
FIG. 5B is a schematic diagram showing image distortion affected by the fluctuation component A2-A1 of the horizontal deflection current. The dashed line S in FIG. 5B indicates a scanning line on the CRT 7, and the solid line Hi indicates a set of pixels that should be arranged vertically on the CRT 7.
[0061]
In FIG. 5B, the disturbance (shift) Rα of the pixel in the horizontal direction changes according to the maximum amplitude value α in FIG. 5A. That is, as the maximum amplitude value α of the horizontal deflection current increases, the disturbance Rα of the pixels in the horizontal direction displayed on the CRT 7 increases. In FIG. 5B, the distance (persistence distance) Rβ at which the pixel disturbance appears in the vertical direction changes according to the fluctuation period β in FIG. 5A. That is, the longer the fluctuation period β of the fluctuation component of the horizontal deflection current, the longer the pixel disturbance duration Rβ in the vertical direction on the CRT 7. Such disturbance of the pixels on the CRT 7 is called ringing.
[0062]
When the transistor 81 in FIG. 2 is always off, ringing is significantly generated due to the influence of the disturbance GV. In the horizontal deflection circuit 6 according to the present embodiment, when the transistor 81 is turned on during the vertical blanking period RT, the resonance capacitance value of the resonance circuit 60K in FIG. 2 changes, and the resonance frequency changes. Thus, the resonance circuit 60K is hardly affected by the disturbance GV, and the ringing is reduced. The resonance frequency of the resonance circuit 60K during the vertical blanking period RT is adjusted by the capacitance value of the adjustment capacitor 82. As a result, a resonance frequency that is hardly affected by the disturbance GV is set.
[0063]
Hereinafter, a method of setting the capacitance value of the adjustment capacitor 82 in FIG. 2 will be described.
The capacitance value of the adjustment capacitor 82 is determined based on the resonance frequency unique to the resonance circuit 60K and the deflection frequency of the horizontal deflection current A2.
[0064]
Here, the resonance frequency (deflection frequency) of the resonance circuit 60K in the vertical effective scanning period ST in which the adjustment capacitor 82 is separated from the resonance capacitor 61 is fo. Further, the resonance frequency of the resonance circuit 60K in the vertical retrace period RT in which the adjustment capacitor 82 is connected in parallel with the resonance capacitor 61 is represented by fb. If the horizontal scanning frequency in the vertical effective scanning period ST is fh, the resonance frequency fo is ２ of the horizontal scanning frequency fh. In this case, in order to make the horizontal deflection circuit 6 less susceptible to the disturbance GV, it is preferable to set the resonance frequency fb in the vertical blanking period RT so as to satisfy the following relationship.
[0065]
fb / fo ≦ 0.9 (1)
The relationship of the above equation (1) is obtained from the experimental results described later. The resonance frequency fo in the vertical effective scanning period ST is represented by the following equation.
[0066]
(Equation 1)

[0067]
L1 indicates an inductance component of the horizontal deflection coil 60 in the resonance circuit 60K, and C1 indicates a capacitance value of the resonance capacitor 61. In the above equation (1), the resonance frequency fb during the vertical blanking period RT is expressed by the following equation.
[0068]
(Equation 2)

[0069]
C2 indicates the capacitance value of the adjustment capacitor 82, L1 indicates the inductance component of the horizontal deflection coil 60, and C1 indicates the capacitance value of the resonance capacitor 61.
[0070]
As described above, in this example, the capacitance value C2 of the adjustment capacitor 82 is set to a value that satisfies the above equation (1).
[0071]
FIG. 6 is a waveform diagram for explaining the resonance frequency fo in the vertical effective scanning period ST and the resonance frequency fb in the vertical blanking period RT in the resonance circuit 60K. FIG. 6A shows the horizontal deflection current A2 in the vertical effective scanning period ST, and FIG. 6B shows the horizontal deflection current A2 in the vertical blanking period RT.
[0072]
As shown in FIG. 6A, the cycle of the horizontal deflection current A2 in the vertical effective scanning period ST is represented by 1 / fo. In the video display device 100 according to the present embodiment, since the electron beam deflecting operation forms one scanning line in each of the forward path and the backward path, the horizontal scanning cycle is 1/2 fo.
[0073]
On the other hand, as shown in FIG. 6B, the cycle of the horizontal deflection current A2 in the vertical flyback period RT is represented by 1 / fb.
[0074]
Hereinafter, an experimental result on ringing appearing in a video will be described. FIG. 7 is a graph showing a measurement result of a relationship between a ratio of a resonance frequency fb of the vertical retrace period RT to a resonance frequency fo of the vertical effective scanning period ST and ringing, and FIG. 8 is a graph showing a resonance frequency fo of the vertical effective scanning period ST. FIG. 7 is a schematic diagram showing ringing appearing in an image in an upper left portion of a screen according to a ratio of a resonance frequency fb in a vertical retrace period RT with respect to FIG.
[0075]
In FIG. 7, the horizontal axis is the ratio R between the resonance frequency fb of the vertical retrace period RT and the resonance frequency fo of the vertical effective scanning period ST calculated by the equation (1), and the vertical axis is shown in FIG. This is the ratio of the maximum amplitude value α of the variation component shown and the vertical pixel disturbance duration Rβ shown in FIG. 5B to the vertical length of the screen.
[0076]
The curve Tr shows the relationship between the maximum amplitude value α of the fluctuation component A2-A1 and the ratio R shown in FIG. According to the curve Tr, the maximum amplitude value α is about 10 mA when the ratio R is 0.90, the maximum amplitude value α is about 15 mA when the ratio R is 0.92, and the ratio R is 0. .94, the maximum amplitude value α is about 45 mA. When the ratio R is 0.96, the maximum amplitude value α is about 90 mA, and when the ratio α is 0.98, the maximum amplitude value α is about 350 mA.
[0077]
According to the above experimental results, when the ratio R is 0.96 or less, the maximum amplitude value α becomes 1/3 or less as compared with the case where the ratio R is 0.98, and the horizontal component of ringing is reduced. Is done. When the ratio R is 0.94 or less, the maximum amplitude value α becomes 1/5 or less as compared with the case where the ratio R is 0.98, and the horizontal component of ringing is greatly reduced. Further, when the ratio R is 0.92 or less, the maximum amplitude value α becomes 1/10 or less as compared with the case where the ratio R is 0.98, and the horizontal component of the ringing is further greatly reduced. . When the ratio R becomes 0.90 or less, the maximum amplitude value α almost approaches 0, and the horizontal component of ringing is almost eliminated.
[0078]
On the other hand, the curve Ji shows the relationship between the ratio of the sustained distance Rβ in FIG. 5B in the vertical direction of the screen and the ratio R.
[0079]
According to the curve Ji, when the ratio R is 0.90, the ratio of the sustained distance is 0, and when the ratio R is 0.92, the ratio of the sustained distance is approximately 0.05. In the case of 94, the ratio of the sustained distance is about 0.15. When the ratio R is 0.96, the ratio of the sustained distance is about 0.5, and when the ratio R is 0.98, the ratio of the sustained distance is about 1.0.
[0080]
According to the above experimental results, when the ratio R is 0.96 or less, the ratio of the sustained distance is less than half as compared with the case where the ratio R is 0.98, and when the ratio R is 0.94 or less. The ratio of the sustained distance becomes 1/5 or less as compared with the case where the ratio R is 0.98. When the ratio R is 0.92 or less, the ratio of the sustained distance is 1/10 or less as compared with the case where the ratio R is 0.98. Becomes almost zero.
[0081]
Here, the ringing appearing on the CRT 7 when the ratio R is 0.9 is shown in FIG. According to FIG. 8A, when the ratio R is 0.9, almost no ringing is recognized in the image displayed on the CRT 7.
[0082]
Subsequently, the ringing appearing on the CRT 7 when the ratio R is 0.92 is shown in FIG. According to FIG. 8 (b), when the ratio R is 0.92, the video displayed on the CRT 7 has ringing with a small amplitude in the horizontal direction and ringing in a short range in the vertical direction.
[0083]
FIG. 8C shows ringing that appears on the CRT 7 when the ratio R is 0.94. According to FIG. 8 (c), when the ratio R is 0.94, in the image shown on the CRT 7, ringing is recognized with a slightly smaller amplitude in the horizontal direction, and ringing is recognized in a slightly shorter range in the vertical direction. .
[0084]
Further, the ringing appearing on the CRT 7 when the ratio R is 0.96 is shown in FIG. According to FIG. 8D, when the ratio R is 0.96, ringing is recognized in the video displayed on the CRT 7 with a relatively large amplitude in the horizontal direction, and ringing is recognized in almost the entire vertical direction. .
[0085]
Finally, the ringing that appears on the CRT 7 when the ratio R is 0.98 is shown in FIG. According to FIG. 8E, when the ratio R is 0.98, in the image displayed on the CRT 7, ringing is recognized with a very large amplitude in the horizontal direction, and ringing is recognized in the entire vertical direction. .
[0086]
From the experimental results described above, it is understood that the ratio R is preferably set to 0.96 or less, and more preferably set to 0.94 or less. It is also found that the ratio R is more preferably set to 0.92 or less, and most preferably set to 0.90 or less.
[0087]
Therefore, it is preferable to set the capacitance value C2 of the adjustment capacitor 82 so that the ratio R becomes 0.96 or less, and it is preferable to set the capacitance value C2 of the adjustment capacitor 82 so that the ratio R becomes 0.94 or less. It turns out that it is more preferable. Further, it is more preferable to set the capacitance value C2 of the adjustment capacitor 82 so that the ratio R becomes 0.92 or less, and it is preferable to set the capacitance value C2 of the adjustment capacitor 82 so that R becomes 0.90 or less. It turns out that it is the most preferable.
[0088]
In the vertical blanking period RT, the horizontal scanning period is longer than in the vertical effective scanning period ST. However, no inconvenience occurs because no image is displayed on the screen in the vertical blanking period RT.
[0089]
Next, a specific configuration example and operation of the horizontal deflection circuit 6 according to the embodiment of the present invention will be described with reference to FIG. FIG. 9 is a circuit diagram showing a specific configuration example of the horizontal deflection circuit 6 according to the present embodiment.
[0090]
The horizontal deflection circuit 6 in FIG. 9 includes a pulse generation circuit 10, a voltage generation circuit 20, a current transformer 33, a vertical scanning period detection circuit 40, a resonance circuit 60K, an amplitude fluctuation correction circuit 70, and a resonance frequency adjustment circuit 80. Note that the vertical scanning period detection circuit 40 corresponds to the pulse generation circuit 30 in FIG.
[0091]
The resonance circuit 60K includes a horizontal deflection coil 60 and a resonance capacitor 61. Further, the horizontal deflection coil 60 has an inductance LH and a resistance component RH. The resonance frequency adjustment circuit 80 includes a transistor 81 and an adjustment capacitor 82. The current transformer 33 includes a primary coil P and a secondary coil S.
[0092]
The voltage generation circuit 20 includes a phase comparator 21, a low-pass filter (hereinafter abbreviated as LPF) circuit 22, a pulse width control unit 23, a switching circuit 24, and a comparator 26. Here, the switching circuit 24 of the voltage generation circuit 20 includes transistors 24a and 24b and diodes (rectifying elements) 24c and 24d.
[0093]
The amplitude fluctuation correction circuit 70 includes a comparator 71, a phase comparator 72, an LPF circuit 73, an attenuator 74, a power amplifier 75, and a resistor 76. Here, the power amplifier 75 of the amplitude fluctuation correction circuit 70 includes an operational amplifier 75b and resistors 75a and 75c.
[0094]
Here, the horizontal deflection current flowing through the horizontal deflection coil 60 is distorted due to the influence of the resistance component RH of the horizontal deflection coil 60. The current transformer 33 and the amplitude fluctuation correction circuit 70 are used to eliminate the influence of the resistance component RH on the horizontal deflection current, and play a role of a negative resistance component for canceling the resistance component RH.
[0095]
The horizontal synchronizing signal HS is supplied to the pulse generating circuit 10 from the synchronizing signal separating circuit 3 in FIG. The pulse generation circuit 10 indicates a timing for reciprocating the electron beam in the horizontal direction from the input horizontal synchronizing signal HS and a reciprocating timing pulse SD indicating a deflection direction and an ideal center position of the electron beam on the display screen. A line center pulse LC is generated. The pulse generation circuit 10 supplies the generated reciprocating timing pulse SD to the voltage generation circuit 20 and supplies the generated line center pulse LC to the amplitude fluctuation correction circuit 70.
[0096]
On the other hand, the vertical scanning period detection circuit 40 is supplied with the vertical synchronization signal VS from the synchronization signal separation circuit 3 in FIG. The vertical scanning period detection circuit 40 detects a vertical blanking period RT and a vertical effective scanning period ST in response to the vertical synchronization signal VS. Then, the adjustment capacitor 82 is connected in parallel to the resonance capacitor 61 during the vertical retrace period RT, and a pulse signal VB for separating the adjustment capacitor 82 from the resonance capacitor 61 is supplied to the resonance frequency adjustment circuit 80 during the vertical effective scanning period ST. The pulse signal VB corresponds to the blanking period detection signal VB in FIG.
[0097]
Here, the operation of the voltage generation circuit 20 will be described with reference to FIGS. FIG. 10 is a waveform diagram showing an example of various signals and currents generated inside the voltage generation circuit 20. In FIG. 10, the switching timing of the forward path and the return path is indicated by a chain line Ti. Here, the waveform of the horizontal deflection current is a triangular waveform for easy understanding.
[0098]
In the voltage generation circuit 20, the reciprocating timing pulse SD given from the pulse generation circuit 10 is input to the phase comparator 21. FIG. 10A shows an example of the waveform of the reciprocating timing pulse SD input to the phase comparator 21. According to FIG. 10A, for example, the reciprocating timing pulse SD indicates that the electron beam is deflected in the forward direction (from left to right on the screen) when it is logic high, and the electron beam is deflected when it is logic low. In the backward direction (from right to left of the screen). Then, inside the voltage generating circuit 20, feedback control of the horizontal deflection current is performed based on the reciprocating timing pulse SD as described below.
[0099]
In the pulse width control unit 23, pulse signals TS and RS are generated based on a voltage level of a control voltage PV described later. The pulse signals TS and RS have opposite phases as shown in FIGS. 10B and 10C. The pulse width control unit 23 supplies the generated pulse signals TS and RS to the switching circuit 24.
[0100]
In the switching circuit 24, the pulse signal TS from the pulse width control unit 23 is applied to the base of the transistor 24a, the collector is connected to the power supply terminal 24e, and the emitter is connected to the node N1. The pulse signal RS from the pulse width control unit 23 is applied to the base of the transistor 24b, the collector is connected to the node N1, and the emitter is connected to the ground terminal. The anode of the diode 24c is connected to the node N1, and the cathode is connected to the power supply terminal 24e. The anode of the diode 24d is connected to the ground terminal, and the cathode is connected to the node N1.
[0101]
When the pulse signal TS becomes logic high and the pulse signal RS becomes logic low, the transistor 24a turns on and the transistor 24b turns off. As a result, current flows from the power supply terminal 24e to the resonance capacitor 61 or the adjustment capacitor 82 through the transistor 24a. When the pulse signal TS becomes logic low and the pulse signal RS becomes logic high, the transistor 24a turns off and the transistor 24b turns on. As a result, a current flows from the resonance capacitor 61 or the adjustment capacitor 82 to the ground terminal through the transistor 24b. Thus, the horizontal deflection current AL flows through the horizontal deflection coil 60 as shown in FIG. At this time, a rectangular voltage is generated at the node N1. In this case, the horizontal deflection current AL has a shift in the reciprocating timing.
[0102]
On the other hand, the rectangular voltage generated at the node N1 and the reference voltage V _ref Is entered.
[0103]
The comparator 26 calculates the rectangular voltage of the node N1 and the reference voltage V _ref Compare with For example, the comparator 26 determines that the rectangular voltage at the node N1 is equal to the reference voltage V _ref If it is higher, a logic high phase comparison pulse CD is output to the phase comparator 21 so that the rectangular voltage is equal to the reference voltage V. _ref If it is lower than the threshold value, a phase comparison pulse CD of a logic low is output to the phase comparator 21. FIG. 10E shows an example of the waveform of the phase comparison pulse CD output from the comparator 26.
[0104]
The phase comparator 21 compares the phase of the reciprocating timing pulse SD given from the pulse generation circuit 10 with the phase comparison pulse CD given from the comparator 26. This phase comparison is performed based on the rising timing or falling timing of each of the round-trip timing pulse SD and the phase comparison pulse CD. The phase difference component obtained by the phase comparison is output to the LPF circuit 22 as a phase difference signal PD. FIG. 10F shows an example of the waveform of the phase difference signal PD output from the phase comparator 21.
[0105]
The LPF circuit 22 integrates the input phase difference signal PD and generates a control voltage PV. FIG. 10G shows an example of the control voltage PV generated by the LPF circuit 22. The pulse width control unit 23 generates the above-described pulse signals TS and RS based on the control voltage PV.
[0106]
In this way, as shown in FIG. 10 (h), the switching timing of the forward and backward paths of the horizontal deflection current AL is accurately controlled.
[0107]
Next, the operations of the resonance frequency adjustment circuit 80 and the amplitude fluctuation correction circuit 70 will be described with reference to FIGS.
[0108]
FIG. 11 is a waveform diagram showing an example of various signals and currents generated by the amplitude vibration correction circuit 70 according to the present embodiment. In FIG. 6, the timing of switching between the forward path and the return path is indicated by a chain line Ti. Note that, similarly to FIG. 10, the waveform of the horizontal deflection current is a triangular waveform.
[0109]
In the resonance frequency adjusting circuit 80 shown in FIG. 9, a pulse signal VB of logic high is given to the transistor 81 in the vertical blanking period RT shown in FIG. 3, and a pulse signal VB of logic low in the vertical effective scanning period ST shown in FIG. Is given.
[0110]
The pulse signal VB is applied to the base of the transistor 81 from the vertical scanning period detection circuit 40, the collector is connected to the adjustment capacitor 82, and the emitter is connected to the node N1.
[0111]
When the pulse signal VB becomes logic high, the transistor 81 turns on. Thereby, the adjustment capacitor 82 is connected in parallel with the resonance capacitor 61. When the pulse signal VB becomes logic low, the transistor 81 turns off. Thereby, the adjustment capacitor 82 is separated from the resonance capacitor 61.
[0112]
As described above, the transistor 81 of the resonance frequency adjustment circuit 80 connects the adjustment capacitor 82 in parallel with the resonance capacitor 61 during the vertical blanking period RT, and disconnects the adjustment capacitor 82 from the resonance capacitor 61 during the vertical effective scanning period ST.
[0113]
The line center pulse LC given from the pulse generation circuit 10 is input to the phase comparator 72. An example of the waveform of the line center pulse LC input to the phase comparator 72 is shown in FIG. In FIG. 11A, the line center pulse LC indicates the ideal center timing in the forward scan and the backward scan based on the rising timing and the falling timing.
[0114]
On the other hand, the primary winding P of the current transformer 33 is connected to the horizontal deflection coil 60 in series. One end of the secondary winding S is connected to the ground terminal, and the other end is connected to the node V7. The node V7 is connected to the ground terminal via the resistor 76. The horizontal deflection current AL shown in FIG. 10H flows through the primary winding P of the current transformer 33, and a secondary current based on the horizontal deflection current AL flows through the secondary winding S. FIG. 11B shows an example of the waveform of the secondary current AL2 flowing through the secondary winding S.
[0115]
When the secondary current AL2 flows through the resistor 76, a voltage is generated at the node V7. The voltage at the node V7 is supplied to the comparator 71 and the attenuator 74.
[0116]
The comparator 71 compares the voltage of the node V7 with the ground potential and outputs a zero cross pulse CD2. For example, the comparator 71 outputs a logic high zero-cross pulse CD2 to the phase comparator 72 when the voltage of the node V7 is higher than the ground potential, and outputs a logic low zero-cross pulse CD2 when the voltage of the node V7 is lower than the ground potential. Output to the phase comparator 72. FIG. 11C shows an example of the waveform of the zero-cross pulse CD2 output from the comparator 71. The rising timing and falling timing of the zero-cross pulse CD2 correspond to the timing (zero-cross point) at which the horizontal deflection current AL crosses the level of the current value 0.
[0117]
The phase comparator 72 compares the phase of the line center pulse LC supplied from the pulse generation circuit 10 with the zero cross pulse CD2 supplied from the comparator 71. This phase comparison is performed based on the rising timing and falling timing of the line center pulse LC and the zero cross pulse CD2, respectively. The phase difference component obtained by the phase comparison is output to the LPF circuit 73 as a phase difference signal PD2. FIG. 11D shows an example of the waveform of the phase difference signal PD2 output from the phase comparator 72.
[0118]
LPF circuit 73 integrates input phase difference signal PD2 to generate control voltage PV2. The control voltage PV2 generated by the LPF circuit 73 is provided to the attenuator 74. FIG. 11E shows an example of a waveform of the control voltage PV2 generated by the LPF circuit 73.
[0119]
The input terminal of the attenuator 74 is supplied with the voltage of the node V7. The attenuator 74 attenuates the voltage of the node V7 based on the control voltage PV2, and supplies the attenuated voltage to the power amplifier 75 as an amplitude fluctuation correction signal.
[0120]
The power amplifier 75 inverts and amplifies the amplitude fluctuation correction signal supplied from the attenuator 74, and supplies the signal to the node V8 at one end of the primary winding P. As a result, the voltage of the node V8 increases, and the horizontal deflection current AL decreases. As a result, the horizontal deflection current AL flowing through the primary winding P is corrected as shown in FIG. In this way, the ideal horizontal deflection current AL without distortion due to the resistance component RH flows through the horizontal deflection coil 60. That is, the amplitude fluctuation correction circuit 70 functions as a negative resistance component.
[0121]
In the horizontal deflection circuit 6 described above, the resonance capacitor 82 of the resonance frequency adjustment circuit 80 is connected in parallel with the resonance capacitor 61 during the vertical blanking period RT. Accordingly, by setting the capacitance value of the adjustment capacitor 81 so as to satisfy the above expression (1), it is possible to obtain a resonance frequency that is not easily affected by the disturbance GV in the resonance circuit 60K. As a result, it is possible to sufficiently suppress the amplitude fluctuation component generated in the horizontal deflection current due to the disturbance GV with a simple configuration without adjustment.
[0122]
In the present embodiment, the amplitude variation correction circuit 70 in FIG. 9 is used to reduce the influence of the resistance component RH of the horizontal deflection coil 60, but the resistance component RH has a small effect on the horizontal deflection current and can be ignored. If it is, it is not particularly necessary.
[0123]
In the present embodiment, the resonance capacitor 61 corresponds to the resonance capacitance, the voltage generation circuit 20 corresponds to the pulse voltage application unit, and the resonance frequency fo of the resonance circuit 60K during the vertical effective scanning period ST corresponds to the first value. , The resonance frequency fb in the vertical flyback period RT corresponds to the second value. Further, the resonance frequency adjustment circuit 80 corresponds to the resonance frequency switching means, the adjustment capacitor 82 corresponds to the adjustment capacitor, the transistor 81 corresponds to the switch means, and the resonance frequency fb of the vertical blanking period RT and the vertical effective scanning period The ratio of ST to the resonance frequency fo corresponds to a second value with respect to the first value, and the amplitude fluctuation correction circuit 70 corresponds to a negative resistance component generating means. Further, the horizontal deflection circuit 6 corresponds to a reciprocating deflection circuit, and the vertical deflection circuit 5 corresponds to a vertical deflection circuit.
[0124]
【The invention's effect】
In the reciprocating deflection circuit according to the present invention, a pulse voltage that changes in a cycle twice the horizontal scanning cycle is applied to the horizontal deflection coil by the pulse voltage applying means. Further, the resonance frequency switching means sets the resonance frequency of the resonance circuit to a first value during the vertical effective scanning period, and sets the resonance frequency of the resonance circuit to a second value different from the first value during the vertical flyback period. You.
[0125]
As described above, by switching the resonance frequency of the resonance circuit to a value that is hardly affected by disturbance during the vertical flyback period, the amplitude fluctuation component of the horizontal deflection current generated by the influence of disturbance is sufficiently reduced. Further, the switching of the resonance frequency is performed by a resonance frequency switching unit. Therefore, by providing the resonance frequency switching means, the influence of disturbance is reduced with no adjustment and a simple configuration.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a video display device according to the present embodiment.
FIG. 2 is a circuit diagram for explaining the operation of the horizontal deflection circuit according to the embodiment;
FIG. 3 is a waveform chart showing the operation of the horizontal deflection circuit of FIG. 2;
FIG. 4 is a diagram schematically showing a measurement result of a vertical synchronization signal and a vertical deflection current when it is assumed that the transistor in FIG. 2 is always turned off, and a part Rn of an envelope of the horizontal deflection current is enlarged; Figure
FIG. 5 is an explanatory diagram for explaining an effect of a fluctuation component of a horizontal deflection current on an image displayed on a CRT.
FIG. 6 is a waveform chart for explaining a resonance frequency in a vertical effective scanning period and a resonance frequency in a vertical blanking period in a resonance circuit.
FIG. 7 is a graph showing a measurement result of a relationship between a ratio between a resonance frequency in a vertical effective scanning period and a resonance frequency in a vertical blanking period and ringing.
FIG. 8 is a schematic diagram showing ringing appearing in an image in an upper left portion of a screen according to a ratio between a resonance frequency in a vertical effective scanning period and a resonance frequency in a vertical flyback period.
FIG. 9 is a circuit diagram showing a specific configuration example of a horizontal deflection circuit according to the present embodiment.
FIG. 10 is a waveform diagram showing an example of various signals and currents generated inside the voltage generation circuit.
FIG. 11 is a waveform chart showing an example of various signals and currents generated by the amplitude vibration correction circuit according to the present embodiment.
FIG. 12 is a schematic diagram showing a sine wave deflection circuit including a self-excited oscillation circuit.
FIG. 13 is a waveform chart showing an example of a temporal change of a voltage and a current applied to a deflection coil of the sine wave deflection circuit of FIG.
FIG. 14 is a diagram for explaining the influence of disturbance applied to a horizontal deflection coil.
FIG. 15 is a schematic diagram showing an example of an amplitude correction circuit capable of sufficiently reducing a fluctuation component of a horizontal deflection current due to a disturbance voltage.
FIG. 16 is a waveform chart for explaining a method of reducing a fluctuation component of a horizontal deflection current generated by a disturbance.
[Explanation of symbols]
5. Vertical deflection circuit
6. Horizontal deflection circuit
20 Voltage generation circuit
30 pulse generation circuit
60K resonance circuit
61 Resonant capacitor
70 Amplitude fluctuation correction circuit
80 Resonance frequency adjustment circuit
81 transistors
82 adjustment capacitor
fb resonance frequency
fh Horizontal scanning frequency
fo resonance frequency
ST Vertical effective scanning period
RT Vertical flyback period

Claims (7)

A reciprocating deflection circuit for reciprocally deflecting the electron beam in a horizontal direction,
A resonance circuit comprising a horizontal deflection coil and a resonance capacitor;
Pulse voltage applying means for applying a pulse voltage that changes in a cycle twice as long as a horizontal scanning cycle to the horizontal deflection coil;
Resonance frequency switching means for setting a resonance frequency of the resonance circuit to a first value during a vertical effective scanning period and setting a resonance frequency of the resonance circuit to a second value different from the first value during a vertical flyback period And a reciprocating deflection circuit comprising: The resonance frequency switching means,
Adjustment capacity,
2. A reciprocating deflection circuit according to claim 1, further comprising switch means for separating said adjusting capacitor from said resonance capacitor during a vertical effective scanning period and connecting said adjusting capacitor to said resonance capacitor during a vertical blanking period. . The switch means,
3. The reciprocating deflection circuit according to claim 2, wherein the adjusting capacitor is connected in parallel to the resonance capacitor during a vertical blanking period. 4. The reciprocating deflection circuit according to claim 1, wherein a ratio of the second value to the first value is 0.96 or less. The reciprocating deflection circuit according to any one of claims 1 to 4, wherein a ratio of the second value to the first value is 0.90 or less. The horizontal deflection coil,
Having an inductance component and a resistance component,
6. The reciprocating deflection circuit according to claim 1, further comprising a negative resistance component generating means for generating a negative resistance component for canceling a resistance component of the horizontal deflection coil. A cathode ray tube,
A reciprocating deflection circuit for horizontally reciprocating the electron beam in the cathode ray tube,
A vertical deflection circuit for vertically deflecting the electron beam in the cathode ray tube,
The reciprocating deflection circuit,
A resonance circuit comprising a horizontal deflection coil and a resonance capacitor;
Pulse voltage applying means for applying a pulse voltage that changes in a cycle twice as long as a horizontal scanning cycle to the horizontal deflection coil;
Resonance frequency switching means for setting a resonance frequency of the resonance circuit to a first value during a vertical effective scanning period and setting a resonance frequency of the resonance circuit to a second value different from the first value during a vertical flyback period A video display device comprising:

Images