JPH11146223A - Horizontal deflector - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow a safe and stable switching operation of a deflection circuit without an overcurrent in a PWM circuit when an input frequency changes or the like. SOLUTION: When a frequency of a horizontal synchronizing signal changes, a discriminating signal showing the point of the change is delayed by a delay circuit 113, and during this operation, until a horizontal oscillating pulse synchronized with the horizontal synchronizing signal outputted from an oscillation circuit 104 is stabilized, the capacitances of S-shaped correction capacitors 107, 108 and 109 remain large so that a deflecting current from a horizontal output circuit 103 can be reduced and no overcurrent flows to a PWM circuit 101. Besides, corresponding to the discriminating signal delayed by the delay circuit 113, a control circuit 14 performs switching to the S-shaped correction capacitor for performing the optimum distortion correction after the stabilization of the horizontal oscillating pulse so that no overcurrent flows to the PWM circuit 101 and switching operation is performed stably and safely.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a horizontal deflecting device for performing a display corresponding to a multi-scan on a personal computer monitor or the like, and for stably and safely controlling the switching of a deflecting circuit when an input frequency changes. About.

[0002]

2. Description of the Related Art A conventional horizontal deflection device is disclosed in, for example, Japanese Patent Application Laid-Open No. 4-29471.

FIG. 14 is a block diagram of the conventional horizontal deflection device. In FIG. 14, F / V (F
The (requency / Voltage) conversion circuit 1 is a circuit that converts an input synchronization signal (horizontal synchronization signal) SYNC having a waveform as shown in FIG. 15A into a voltage having a waveform as shown in FIG. The PWM (Pulse Width Modulation) circuit 11
The input synchronizing signal SYN is determined by the output voltage of the F / V
This is a circuit that outputs a control pulse synchronized with C.

The transistor 12 is a circuit for converting the output pulse of the PWM circuit 11 into a desired drive voltage, and the smoothing circuit 13 is a voltage V obtained by smoothing and rectifying the drive voltage.
a is a circuit that supplies a as a power source of the horizontal deflection circuit 4 via the choke coil 5.

The horizontal deflection circuit 4 includes a deflection coil 6 and an S-shaped correction capacitor 7 connected in series between the choke coil 5 and the ground, a resonance capacitor 8 and a damper diode 9 connected between the choke coil 5 and the ground. When,
A PWM drive transistor 12 having a collector terminal connected to the choke coil 5 and an emitter terminal connected to the ground
It is comprised including.

In the conventional horizontal deflection device configured as described above, when the frequency changes due to the F / V converted voltage, the pulse width of the driving pulse of the PWM circuit 11 is controlled, and the horizontal deflection circuit 4 is controlled. By changing the input voltage at the input frequency, the current flowing through the deflection coil 6 is kept constant, and the display amplitude is controlled to be constant even when the frequency changes.

[0007]

However, in a configuration such as the above-mentioned conventional horizontal deflection device, when the frequency changes, the S-shaped correction capacitor is switched to correct horizontal non-linear distortion of the screen. In the case of such a horizontal deflection device, an overcurrent flows through the PWM circuit 11 as shown in FIG. 15C at a frequency switching point indicated by reference numeral 151 in FIG. 15A, and in the worst case, the driving transistor is destroyed. Will do.

In the high-voltage output circuit, a circuit for keeping the anode voltage constant using a PWM circuit is used similarly to the horizontal output circuit 4 in order to keep the anode voltage constant regardless of the input frequency. As in the case described above, an overcurrent flows through the PWM circuit when the frequency changes.

The present invention provides a horizontal deflecting device capable of performing stable and safe switching control of a deflection circuit unit without overcurrent flowing in a PWM circuit at the time of switching control of the deflection circuit unit when the input frequency changes. The purpose is to provide.

[0010]

Means for Solving the Problems The present invention has the following arrangement to solve the above-mentioned problems.

According to the first aspect of the present invention, a PWM means for generating a power supply voltage necessary to obtain a desired horizontal amplitude synchronized with a horizontal synchronization signal, and an oscillation means for outputting a horizontal oscillation pulse synchronized with the horizontal synchronization signal Means for generating a deflection current for deflecting the electron beam in the horizontal direction from the power supply voltage in synchronization with the horizontal oscillation pulse, and the deflection current being supplied via a deflection coil, A plurality of S-shaped correction capacitors for performing the distortion correction, frequency determining means for determining the frequency of the horizontal synchronization signal, delay means for delaying the determination signal from the frequency determining means, Control means for switching to the S-shaped correction capacitor for performing optimal distortion correction in response to the change.

With this configuration, when the frequency (input frequency) of the horizontal synchronizing signal changes, the determination signal indicating the change point is delayed by the delay means, and during this time, it is synchronized with the horizontal synchronizing signal output from the oscillating means. Until the horizontal oscillation pulse becomes stable, the deflection current becomes small because the capacitance of the S-correction capacitor remains large.
An overcurrent does not flow through the M means, and the control means switches to an S-shaped correction capacitor for performing optimal distortion correction in accordance with the discrimination signal delayed by the delay means. After the stabilization, the switching operation can be performed stably and safely without overcurrent flowing through the PWM means.

According to a second aspect of the present invention, in the horizontal deflection device according to the first aspect, the delay means includes a step of, when the determination signal from the frequency determination means indicates that the frequency has changed from a low frequency to a high frequency. The discrimination signal is delayed by a time during which the horizontal oscillation pulse is stabilized, and the control means switches to an S-shaped correction capacitor for performing optimal distortion correction in synchronization with the discrimination signal from the delay means.

According to this configuration, when the input frequency changes from a low frequency to a high frequency, after the horizontal output is stabilized, the control means switches to the S-shaped correction capacitor for performing optimum distortion correction. The switching operation can be performed stably and safely without causing an overcurrent to flow.

According to a third aspect of the present invention, in the horizontal deflecting device of the first aspect, the delay means includes: when the discrimination signal from the frequency discrimination means indicates a change from a high frequency to a low frequency, The discrimination signal is output at the same timing as it is, and the control means switches to an S-shaped correction capacitor for performing optimal distortion correction in synchronization with the discrimination signal from the delay means.

According to this configuration, when the input frequency changes from a high frequency to a low frequency, the S-shaped correction capacitor is switched at the same time as the input frequency is changed, so that the S-shaped correction is increased, thereby reducing the deflection current. P
The switching operation can be performed stably and safely without overcurrent flowing in the WM circuit.

According to a fourth aspect of the present invention, there is provided a PWM means for generating a power supply voltage necessary for obtaining a desired horizontal amplitude synchronized with a horizontal synchronization signal, and an oscillator for outputting a horizontal oscillation pulse synchronized with the horizontal synchronization signal. Means for generating a deflection current for deflecting the electron beam in the horizontal direction from the power supply voltage in synchronization with the horizontal oscillation pulse, and outputting a divided voltage pulse obtained by dividing the voltage at the time of the generation; A plurality of S-shaped correction capacitors to which the deflection current is supplied via a deflection coil to correct the distortion of the electron beam; frequency determination means for determining the frequency of the horizontal synchronization signal; and determination from the frequency determination means. A delay means for delaying a signal, a peak voltage detecting means for detecting a peak point of the voltage of the divided pulse, and an optimum signal according to the discrimination signal from the peak point and the delay means. Has a configuration comprising a control means for switching to the S-correction capacitor that performs only correction, the.

With this configuration, in addition to the function of the first aspect,
Since the S-shaped correction capacitor is switched at the peak point, the deflection current is zero, so that no overcurrent flows to the PWM means, and the switching control can be performed more safely.

According to a fifth aspect of the present invention, in the horizontal deflecting device of the fourth aspect, the delay means indicates that the discrimination signal from the frequency discrimination means has changed from a low frequency to a high frequency. The determination signal is delayed by a time during which the horizontal oscillation pulse is stabilized, and the control unit controls the
In synchronization with the discrimination signal from the delay means, the configuration is such that an S-shaped correction capacitor for performing optimal distortion correction is switched.

With this configuration, when the input frequency changes from a low frequency to a high frequency, the horizontal oscillation pulse is stabilized, and when the deflection current is zero, the capacitor is switched to an S-shaped correction capacitor for performing optimal distortion correction. Switching control can be performed safely.

According to a sixth aspect of the present invention, in the horizontal deflecting device of the fourth aspect, the delay means, when the determination signal from the frequency determination means indicates that the frequency has changed from a high frequency to a low frequency, The determination signal is output at the same timing as it is, and the control means performs optimal distortion correction at the peak point in synchronization with the determination signal from the delay means.
It is configured to switch to a character correction capacitor.

With this configuration, even when the input frequency changes from a low frequency to a high frequency, when the deflection current is zero, the switching to the S-shaped correction capacitor for performing the optimum distortion correction can be performed. Can be.

According to a seventh aspect of the present invention, there is provided a PWM means for generating a power supply voltage necessary for obtaining a desired anode voltage synchronized with a horizontal synchronizing signal, and a voltage required for generating an anode voltage from the power supply voltage. High-voltage output means for generating a waveform, a flyback transformer for boosting and rectifying the output voltage of the high-voltage output means to generate a desired anode voltage, frequency determination means for determining the frequency of the horizontal synchronization signal, Delay means for delaying a determination signal from the determination means, and switching means for switching such that the signal frequency of the output voltage of the high-voltage output means synchronized with the horizontal synchronizing signal is doubled in accordance with the determination signal from the delay means When,
Was provided.

According to this configuration, the delay means delays the output voltage of the PWM means so as to compensate for the delay in following the output voltage, thereby preventing the overvoltage from being applied to the high-voltage output means, thereby preventing the overcurrent from flowing through the PWM means. Thus, the switching operation can be performed stably and safely.

According to an eighth aspect of the present invention, in the horizontal deflecting device according to the seventh aspect, when the discrimination signal from the frequency discrimination means indicates that the frequency has changed from a high frequency to a low frequency, The determination signal is delayed by a time during which the power supply voltage output from the PWM means is stabilized, and the switching means doubles the signal frequency of the output voltage of the high voltage output means in synchronization with the determination signal from the delay means. The switching is performed as follows.

With this configuration, when the input frequency changes from a high frequency to a low frequency, switching is performed after the power supply voltage output from the PWM means has stabilized, so that an overcurrent does not flow through the PWM means. The switching operation can be performed stably and safely.

According to a ninth aspect of the present invention, in the horizontal deflecting device of the seventh aspect, the delay means, when the determination signal from the frequency determination means indicates that the frequency has changed from a low frequency to a high frequency, The determination signal is output at the same timing as it is, and the switching means switches in synchronization with the determination signal from the delay means so that the signal frequency of the output voltage of the high-voltage output means is doubled.

With this configuration, when the input frequency is switched from a low frequency to a high frequency, the voltage applied to the high voltage output means switches from a low voltage to a high voltage, so that no overcurrent flows through the PWM means. By PW
The switching operation can be performed stably and safely so that an overcurrent does not flow to the M means.

According to a tenth aspect of the present invention, a PWM means for generating a power supply voltage required to obtain a desired anode voltage synchronized with a horizontal synchronization signal, and a voltage required for generating an anode voltage from the power supply voltage High-voltage output means for generating a waveform, a flyback transformer for boosting and rectifying the output voltage of the high-voltage output means to generate a desired anode voltage, frequency determination means for determining the frequency of the horizontal synchronization signal, Delay means for delaying a determination signal from the determination means, peak voltage detection means for detecting a peak point of a voltage obtained by dividing the output voltage of the high-voltage output circuit, and a determination signal from the peak point and the delay means. Switching means for switching so that the signal frequency of the output voltage of the high-voltage output means is doubled in synchronization.

With this configuration, in addition to the function of claim 7,
Since the switching is performed when the deflection current is zero at the peak point, the switching operation can be performed more stably and safely so that an overcurrent does not flow through the PWM means.

The invention according to claim 11 is the same as the invention according to claim 1.
0, the delay unit, when the determination signal from the frequency determination unit indicates that the frequency has changed from a high frequency to a low frequency, the power supply voltage output from the PWM unit stabilizes the determination signal. Delayed by a time, the switching means switches so that the signal frequency of the output voltage of the high-voltage output means is doubled at the peak point in synchronization with the determination signal from the delay means.

With this configuration, when the input frequency changes from a high frequency to a low frequency, the power supply voltage output from the PWM means is stabilized, and the switching is performed when the deflection current is zero at the peak point. The switching operation can be performed more stably and safely so that an overcurrent does not flow through the means.

The invention according to claim 12 is the first invention.
0, the delay unit outputs the determination signal at the same timing when the determination signal from the frequency determination unit indicates that the frequency has changed from a low frequency to a high frequency. At the peak point, in synchronization with the discrimination signal from the delay means, the switching is performed so that the signal frequency of the output voltage of the high voltage output means is doubled.

With this configuration, even when the input frequency changes from a low frequency to a high frequency, the switching is performed when the deflection current is zero at the peak point, so that the PWM means is more stable and more stable so that the overcurrent does not flow. The switching operation can be performed safely.

[0035]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the horizontal deflection device of the present invention will be specifically described below with reference to the drawings.

(Embodiment 1) FIG. 1 is a block diagram of a horizontal deflection apparatus according to Embodiment 1 of the present invention.

The horizontal deflection device shown in FIG. 1 has an input terminal 100 to which a horizontal synchronizing signal is supplied, a PWM circuit 101,
Choke coil 102, horizontal output circuit 103, oscillation circuit 104, oscillation control circuit 105, horizontal deflection coil 106, S-shaped correction capacitors 107, 108 and 10
9, FETs 110 and 111, and frequency discrimination circuit 11
2, a delay circuit 113, and a control circuit 114.

In FIG. 1, a PWM circuit 101 generates a voltage control pulse (PWM current) synchronized with a horizontal synchronization signal supplied to an input terminal 100, rectifies the voltage control pulse, and supplies it to a horizontal output circuit 103 through a choke coil 102. By controlling the width of the voltage control pulse, control is performed to keep the horizontal amplitude constant even when the frequency (input frequency) of the horizontal synchronization signal input to the input terminal 100 changes.

The oscillation circuit 104 outputs a horizontal oscillation pulse synchronized with a horizontal synchronization signal in accordance with a control voltage output from the oscillation control circuit 105.

The horizontal output circuit 103 generates a waveform (deflection current) for deflecting the electron beam in the horizontal direction from the horizontal oscillation pulse output from the oscillation circuit 104, and the generated waveform is used for horizontal deflection. The electric current is supplied to the coil 106, whereby the sawtooth current flows through the horizontal deflection coil 106, and the electron beam is deflected in the horizontal direction.

The S-shaped correction capacitors 107 to 109 are for correcting non-linearity in the horizontal direction on the display screen.

The FETs 110 and 111 have S-shaped correction capacitors 1 so that the nonlinearity is optimally corrected at the input frequency.
08 and 109 are switched.

The frequency discriminating circuit 112 discriminates the frequency of the horizontal synchronizing signal, and outputs a discrimination signal when the frequency is switched. The delay circuit 113 delays the output determination signal of the frequency determination circuit 112.

The control circuit 114 controls the S-correction capacitor 1 via the FETs 110 and 111 so that the S-correction is optimized at an input frequency synchronized with the output signal of the delay circuit 113.
08 and 109 are switched.

FIG. 2 shows an S-shaped correction capacitor 108 when the input frequency changes from a low frequency to a high frequency.
10 and 10 show a switching timing chart.

FIG. 2A shows a horizontal synchronizing signal, and the input frequency is switched at point A.

FIG. 2B shows an oscillation frequency control voltage waveform output from the oscillation control circuit 105. The control voltage is for generating a horizontal oscillation pulse output from the oscillation circuit 104 to the horizontal output circuit 103 when the input frequency is switched, and gradually increases from a low voltage to a high voltage as illustrated. Changes to

FIG. 2C shows the frequency change detection pulse P1 output from the frequency determination circuit 112. The pulse P1 is generated by the frequency discrimination circuit 112 performing F / V conversion on the horizontal synchronization signal and detecting that the input frequency has changed from a low frequency to a high frequency based on a change in voltage.

FIG. 2D shows that the frequency change detection pulse P1 output from the frequency
5 shows the delay frequency change detection pulse P2 delayed by the above. The delay circuit 113 detects the rise of the frequency change detection pulse P1 and outputs a pulse P2 delayed by Δt from this detection point.

FIG. 2E shows an output waveform of a control signal for switching the S-shaped correction capacitors 108 and 109 output from the control circuit 114. The control circuit 114 outputs a control signal by detecting the rise of the output pulse P2 of the delay circuit 113.

FIG. 2F shows a PWM current waveform output from the PWM circuit 101, and the current flowing changes according to a change in the input frequency.

FIG. 3 shows an S-shaped correction capacitor 108 when the input frequency changes from a high frequency to a low frequency.
10 and 10 show a switching timing chart.

FIG. 3A shows a horizontal synchronizing signal. The input frequency is switched at point B.

FIG. 3B shows an oscillation frequency control voltage waveform output from the oscillation control circuit 105. The control voltage is for generating a horizontal oscillation pulse output from the oscillation circuit 104 to the horizontal output circuit 103 when the input frequency is switched, and gradually increases from a high voltage to a low voltage as illustrated. Change.

FIG. 3C shows a frequency change detection pulse P3 output from the frequency discriminating circuit 112. The pulse P3 is generated by the frequency discrimination circuit 112 performing F / V conversion on the horizontal synchronization signal and detecting that the input frequency has changed from a higher frequency to a lower frequency based on a change in voltage.

FIG. 3D shows that the frequency change detection pulse P 3 output from the frequency discriminating circuit 112 is
5 shows the delay frequency change detection pulse P4 delayed by the above. The delay circuit 113 detects the falling of the frequency change detection pulse P3, and outputs a pulse P4 at this detection point.

FIG. 3E shows an output waveform of a control signal for switching the S-shaped correction capacitors 108 and 109 output from the control circuit 114. The control circuit 114 outputs a control signal by detecting the rise of the output pulse P4 of the delay circuit 113.

FIG. 3F shows a PWM current waveform output from the PWM circuit 101, and the current flowing varies according to the change in the input frequency.

Next, the operation of the horizontal deflection device according to the first embodiment configured as described above will be described.

First, when the input frequency changes from a low frequency to a high frequency, the horizontal oscillation pulse input to the horizontal output circuit 103 changes according to the control voltage output from the oscillation control circuit 105.

As a result, the deflection current pulse output from the horizontal output circuit 103 gradually becomes equal to the input frequency. The frequency discrimination circuit 112 outputs a positive frequency change detection pulse when the input changes from a low frequency to a high frequency, as shown in FIG.

The delay circuit 113 includes the frequency discriminating circuit 1
From the input timing of the twelve output pulses, a pulse delayed by Δt at which the frequency of the output pulse of the horizontal output circuit 103 is stabilized is output to the control circuit 114.

The control circuit 114 performs control for switching the S-shaped correction capacitors 108 and 109 to a capacitor capacity that is optimal at the input frequency when the output pulse of the delay circuit 113 rises.

Here, since the capacitance of the S-shaped correction capacitor changes from a low frequency to a high frequency, the capacitance value changes from a large capacitance value to a small capacitance value in order to perform optimal nonlinearity correction at that frequency.

Therefore, if the capacitance of the S-shaped correction capacitor is changed while the frequency of the pulse of the deflection current is low, the capacitance of the S-shaped correction capacitor is reduced, and the deflection current is increased as shown by the broken line in FIG. Sometimes PWM
An overcurrent flows through the circuit 101.

However, when the control shown in FIG. 2 is performed, the capacitance of the S-shaped correction capacitor remains large until the frequency of the horizontal output is stabilized as shown in FIG.
As shown in FIG. 5B, the deflection current i2 is smaller than i1 and i3 shown in FIGS. 5A and 5B.
As shown in (f), the PWM circuit 10 at the time of frequency switching
1 can be suppressed.

Then, after the frequency of the horizontal output is stabilized,
By switching the S-shaped correction capacitors 108 and 109 to the optimum capacity, the deflection current i3 is reduced as shown in FIG.
The current value is returned to the same value as in FIG.

Next, a case where the input frequency changes from a high frequency to a low frequency will be described.

When the frequency changes from a high frequency to a low frequency, as shown in FIG. 3C, the frequency discriminating circuit 112 outputs a negative pulse P3 when the frequency is switched. The delay circuit 113 outputs a pulse P4 obtained by inverting the output of the frequency discrimination circuit 112, as shown in FIG.

The control circuit 114 adjusts the S-shaped correction capacitor 108 so that the S-shaped correction capacitor has the optimum capacitance at the input frequency simultaneously with the rise of the output of the delay circuit 113.
And 109 are switched.

As described above, the S-shaped correction capacitor is switched to the low-frequency capacitor at the same time as the input frequency, so that the S-shaped correction is increased, and the S-shaped correction capacitor is changed in the same manner as when the frequency is changed from the low frequency to the high frequency. Since the capacitance is large, the S-shaped correction is effective and the deflection current is reduced. As a result, as shown in FIG. 3 (f), the PWM current also decreases and then changes to an optimum PWM current waveform, so that no overcurrent flows.

As described above, according to the first embodiment, when the input frequency changes from a low frequency to a high frequency,
After the horizontal output is stabilized, the S-shaped correction capacitors 108 and 109 are switched so as to obtain the optimum non-linearity correction. When the frequency changes from a high frequency to a low frequency, the S-shaped correction capacitors 108 and 109 are simultaneously changed with the input frequency. By switching the switching circuit 109, an overcurrent does not flow through the PWM circuit 101, and the switching operation can be performed stably and safely.

(Embodiment 2) FIG. 6 is a block diagram showing a horizontal deflection apparatus according to Embodiment 2 of the present invention. In FIG. 6, portions corresponding to the respective portions of the first embodiment shown in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.

In FIG. 6, a horizontal output circuit 601 receives a horizontal oscillation pulse output from an oscillation circuit 104 synchronized with a horizontal synchronization signal, and thereby receives a deflection current pulse for deflecting an electron beam in the horizontal direction. And outputs a waveform obtained by dividing the pulse of the deflection current. The waveform of the output voltage division pulse is supplied to the horizontal deflection coil 106, whereby a saw-tooth current flows through the deflection coil 106, and the electron beam is deflected in the horizontal direction.

The peak voltage detection circuit 602 detects the peak voltage of the divided pulse divided by the horizontal output circuit 601 and inputs the detected voltage to the control circuit 603.

The control circuit 603 uses the frequency change detection pulse output from the frequency discrimination circuit 112 delayed via the delay circuit 113 and the detection voltage output from the peak voltage detection circuit 602 to control the S-shaped correction capacitor 108 and FETs 110 and 111 for switching 109 are controlled.

FIG. 7 is a timing chart for switching the S-shaped correction capacitor. However, in FIG. 7, portions corresponding to the respective portions in FIG. 2 are denoted by the same reference numerals, and description thereof will be omitted.

FIG. 7E shows a pulse obtained by dividing the divided pulse output from the horizontal output circuit 601.

FIG. 7F shows a peak voltage detection circuit 602.
5 shows the waveform of the detected voltage detected in step (a), and outputs a pulse at the peak voltage of the divided pulse.

FIG. 7G shows a control signal output from the control circuit 603, which is generated by a delay frequency change detection pulse output from the delay circuit 113 and a pulse output from the peak voltage detection circuit 602. Is what is done.

FIG. 8 is a waveform diagram of the horizontal output circuit 601.

FIG. 8A shows the waveform of the horizontal synchronizing signal.
FIG. 8B shows a collector current waveform of the driving transistor.
8C shows the current waveform of the diode, FIG. 8D shows the current waveform during the retrace period, FIG. 8E shows the deflection current waveform, and FIG. 8F shows the voltage division of the horizontal output circuit 601. FIG.
(G) shows a PWM current waveform.

Next, the operation of the horizontal deflection device configured as described above will be described.

First, according to the control voltage output from the oscillation control circuit 105, the oscillation circuit 104
The horizontal oscillation pulse output to 01 changes. Thus, the deflection current pulse output from the horizontal output circuit 601 gradually becomes equal to the input frequency.

The frequency discriminating circuit 112 outputs a positive pulse when the input frequency changes from a low frequency to a high frequency. In this case, the delay circuit 113 delays the frequency change detection pulse output from the frequency determination circuit 112 by Δt at which the frequency of the pulse output from the horizontal output circuit 601 is stabilized, and controls the delay frequency change detection pulse. Output to the circuit 603.

The peak voltage detection circuit 602 detects the peak voltage of the divided pulse output from the horizontal output circuit 601 and outputs a pulse waveform as shown in FIG.

The control circuit 603 determines that the output pulse of the delay circuit 113 is at “H” level and the peak voltage detection circuit 60
At the rise of 2, the S-shaped correction capacitors 108 and 109 are switched via FETs 110 and 111 to a capacitor capacity that is optimal at the input frequency.

In this case, the switching of the capacitance of the S-shaped correction capacitor is performed when the frequency of the horizontal oscillation pulse is stable and the switching of the S-shaped correction capacitor is performed.
As shown in (h), the S-shaped correction capacitors 108 and 109 are switched during the period when the current of the PWM circuit 101 is zero, so that no overcurrent flows.

As shown in FIG. 8B, the current flows from the PWM circuit 101 to the horizontal output circuit 601 only during the scanning period, and the deflection current in the other portion (return period) is the horizontal output. This is because the voltage is supplied from the resonance capacitor included in the circuit 601.

Therefore, if the S-shaped correction capacitors 108 and 109 are switched at the peak point of the divided voltage pulse generated during the retrace period as shown in FIG. 8F, the PWM current is zero and the PWM circuit 101 No overcurrent flows.

In this description, the case where the frequency is switched from the low frequency to the high frequency is described. However, the reverse is also true, and the S-shaped correction capacitors 108 and 109 are switched when the PWM current is zero.

As described above, according to the second embodiment, the peak voltage of the deflection current pulse is detected, and when the frequency change is stabilized and the deflection current is zero, the S-shaped correction capacitor 108 is detected.
And 109, the switching control can be performed more safely than in the first embodiment.

(Embodiment 3) FIG. 9 is a block diagram showing a horizontal deflection apparatus according to Embodiment 3 of the present invention. In FIG. 9, portions corresponding to the respective portions of the first embodiment shown in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.

In FIG. 9, the PWM circuit 101 generates a voltage control pulse synchronized with the horizontal synchronization signal supplied to the input terminal 100, rectifies the voltage control pulse, and supplies it to the high voltage output circuit 303 through the choke coil 102. By controlling the pulse width of the PWM circuit,
Even when the frequency of the synchronization signal input to the input terminal 100 changes, the anode output voltage output from the FBT (Flyback Transformer) 304 is kept constant.

The high voltage output circuit 303 generates a voltage pulse for emitting an electron beam to the screen side.
This output waveform is supplied to the FBT 304, and the output voltage of the high voltage output circuit 303 is boosted and rectified to generate an anode voltage.

The 2fh switching circuit 308 includes a delay circuit 113
The horizontal synchronizing signal is switched to a double frequency in accordance with the input frequency in synchronism with the output of the delay frequency change detection pulse output from.

FIG. 10 is a circuit diagram of the high-voltage output circuit 303 when the input frequency changes from a high frequency to a low frequency.
The fh drive switching timing chart is shown.

FIG. 10A shows a horizontal synchronizing signal, and the input frequency is switched at point A.

FIG. 10B shows a frequency change detection pulse P1 output from the frequency determination circuit 112.

FIG. 10 (c) shows that the frequency change detection pulse P1 output from the frequency
3 shows a delay frequency change detection pulse P2 delayed by 3. The frequency change detection pulse P1 is output from the delay circuit 113.
Is detected, and a pulse P2 delayed by Δt from this detection point is output.

In FIG. 10D, the 2fh switching circuit 308 switches the voltage pulse output from the high voltage output circuit 303 to twice the frequency in synchronization with the output of the delay circuit.

FIG. 10 (e) shows the current waveform of the PWM circuit, and the current flowing changes due to a change in the input frequency or the like.

FIG. 11 shows the relationship between the input frequency and the PWM output voltage.

Next, the third embodiment configured as described above
The operation of the horizontal deflection device will be described.

The high voltage output circuit 303 has substantially the same circuit configuration as the horizontal output circuit 103 shown in FIG. 1, but the voltage pulse generated by the high voltage output circuit 303 is boosted by the FBT 304.
This is a circuit that rectifies and generates a DC voltage pulse of about 30 KV.

For this reason, although it is necessary to synchronize with the horizontal synchronizing signal, since it is not necessary to drive at the same frequency as the input frequency, the control range of the PWM circuit 101 is narrowed, the output voltage at a low frequency is increased, and the current consumption is increased. Is driven at twice the frequency of the input frequency to reduce the frequency. This control is performed at the following timing.

The horizontal synchronizing signal changes at a point A shown in FIG. The frequency discriminating circuit 112 outputs a positive pulse P1 when the frequency changes. Delay circuit 113
Is higher than the rising of the pulse P1.
3 to output a pulse P2 delayed by Δt at which the synchronization signal is stabilized.

The 2fh switching circuit doubles the frequency of the voltage pulse output from high voltage output circuit 303 in synchronization with the rise of pulse P2 output from delay circuit 113.

The advantage of delaying 2fh switching with respect to an input signal when switching from a high frequency to a low frequency will be described with reference to FIG.

If the 2fh switching is performed at the point A where the input frequency is switched, the voltage pulse output from the high voltage output circuit 303 is switched to a double frequency by the 2fh switching circuit 308.

However, the output voltage of the PWM circuit 101 is
Since the DC voltage (voltage pulse) is created by rectifying the high-voltage pulse, the voltage becomes a desired voltage slightly later than the switching of the frequency. For this reason, when the frequency is switched to a lower frequency, it is the same as the case where the hatched voltage is input although the actually required voltage is the solid line shown in FIG.
03 is overvoltaged. For this reason, an overcurrent flows through the PWM circuit 101, and the PWM circuit 101 is broken.

This is converted into a PWM signal by using a delay circuit 113.
By delaying the output voltage of the circuit 101 to compensate for the delay, the overvoltage is prevented from being applied to the high-voltage output circuit 303, so that the overcurrent can be prevented from flowing through the PWM circuit 101.

When the input frequency changes from a low frequency to a high frequency, similarly to the first embodiment, a negative pulse P3 {see FIG. 3C} is output from the frequency discriminating circuit 112, and the delay circuit 113 The same positive pulse P4 as in FIG.
(D) Reference｝ is output, and the high-frequency output circuit 30 is output by the 2fh switching circuit 308 by the output pulse P4 of the delay circuit 113.
The frequency of the drive pulse input to 3 is switched from twice the frequency to the same frequency (fh) as the input frequency.

As described above, when switching from the low frequency to the high frequency, the voltage applied to the high voltage output circuit 303 switches from the low voltage to the high voltage, so that the PWM
No overcurrent flows through the circuit 101.

As described above, according to the first embodiment, when the input frequency changes from a high frequency to a low frequency, the PWM voltage input to high voltage output circuit 303 is stabilized and then output from high voltage output circuit 303. Two voltage pulses
The frequency is doubled by the fh switching circuit 308,
When the frequency changes from the low frequency to the high frequency, the voltage pulse output from the high voltage output circuit 303 is switched from twice the frequency to the same frequency as the input synchronization signal simultaneously with the change of the input frequency, so that the overcurrent is supplied to the PWM circuit 101. Does not flow, and the switching operation can be performed stably and safely.

(Embodiment 4) FIG. 12 is a block diagram showing a horizontal deflection apparatus according to Embodiment 4 of the present invention. This figure 1
In FIG. 2, portions corresponding to the respective portions of the third embodiment shown in FIG. 9 are denoted by the same reference numerals, and description thereof will be omitted.

In FIG. 12, high voltage output circuit 1201
Generates a high-voltage pulse input to the FBT 304 as shown in FIG. 13D and outputs a divided voltage pulse obtained by dividing the high-voltage pulse.

The peak voltage detection circuit 1202 detects the peak voltage of the divided voltage pulse output from the high voltage output circuit 1201 and outputs a detection pulse having a waveform as shown in FIG.

The 2fh switching circuit 1203 is connected to the delay circuit 11
3 is a circuit that switches the divided voltage pulse output from the high voltage output circuit 1201 to a double frequency in accordance with the output signal of the third signal and the output pulse of the peak detection circuit 1202.

The operation of the horizontal deflection device according to the fourth embodiment configured as described above will be described below.

The frequency discrimination circuit 112 outputs a positive pulse P1 when the input changes from a high frequency to a low frequency, as indicated by the symbol A in FIG. From the output pulse P1 of the frequency determination circuit 112, the delay circuit 1
Reference numeral 13 outputs to the control circuit a pulse P2 delayed by a time Δt at which the output voltage of the PWM circuit 101 is stabilized.

The peak voltage detecting circuit 1202 detects the peak voltage of the divided pulse output from the high voltage output circuit 1201 and outputs a frequency switching control waveform as shown in FIG.

The 2fh switching circuit 1203 is connected to the delay circuit 11
3 is "H" and the peak voltage detection circuit 1
At the rise of 202, 2fh switching is performed, and the divided voltage pulse output from the high voltage output circuit 1201 is switched to twice the frequency.

By such an operation, the PWM circuit 10
This is because 2fh switching is performed during a period in which the output voltage of the PWM circuit 101 is stable and the current of the PWM circuit 101 is zero as shown in FIG. An overcurrent does not flow through the PWM circuit 101.

In the above, the case where the frequency is switched from the high frequency to the low frequency has been described. However, the opposite is also true, and the switching is performed at 2 fh when the PWM current is zero.

As described above, according to the fourth embodiment, the peak voltage of the high-voltage output pulse is detected, and when the PWM voltage is stable and the deflection current is zero, the driving frequency input to the high-voltage output circuit is doubled. By performing the switching, the switching control can be performed more safely than in the third embodiment.

[0127]

As is apparent from the above description, the switching timing of the S-shaped correction capacitor for correcting the non-linear distortion of the screen in the horizontal output means is switched at an optimum point, so that the PWM means is switched to the horizontal output circuit. The current to be supplied does not become an overcurrent, and the timing of switching the driving pulse (horizontal oscillation pulse) for generating the high-voltage output voltage in the high-voltage output means is switched at an optimum point, so that the PWM means is switched to the high-voltage output means The switching control can be performed stably and safely without the supplied current becoming an overcurrent.

[Brief description of the drawings]

FIG. 1 is a block diagram of a horizontal deflection device according to a first embodiment of the present invention.

FIG. 2 is an operation waveform diagram at the time of a frequency change (from low to high) in the embodiment.

FIG. 3 is an operation waveform diagram when a frequency changes (from high to low) in the embodiment.

FIG. 4 is an S-shaped correction capacitor capacitance and a current waveform diagram according to the embodiment.

FIG. 5 is a change diagram of a current waveform according to the embodiment.

FIG. 6 is a block diagram of a horizontal deflection device according to a second embodiment of the present invention.

FIG. 7 is an operation waveform diagram of the embodiment.

FIG. 8 is an operation waveform diagram of the horizontal output unit of the embodiment.

FIG. 9 is a block diagram of a horizontal deflection device according to a third embodiment of the present invention.

FIG. 10 is an operation waveform diagram of the embodiment.

FIG. 11 is a diagram illustrating a relationship between an input frequency and a PWM output voltage in the embodiment.

FIG. 12 is a block diagram of a horizontal deflection device according to a fourth embodiment of the present invention.

FIG. 13 is an operation waveform diagram of the embodiment.

FIG. 14 is a block diagram of a conventional horizontal deflection device.

FIG. 15 is an operation waveform diagram of the conventional example.

[Description of Signs] 101 PWM circuit 102 choke coil 103 horizontal output circuit 104 oscillation circuit 106 deflection coil 107, 108, 109 S-shaped correction capacitor 112 frequency discrimination circuit 113 delay circuit 114 control circuit

Claims (12)

[Claims] 1. PWM means for generating a power supply voltage necessary to obtain a desired horizontal amplitude synchronized with a horizontal synchronization signal;
An oscillating unit that outputs a horizontal oscillation pulse synchronized with the horizontal synchronization signal; a horizontal output unit that generates a deflection current for synchronizing with the horizontal oscillation pulse and deflecting the electron beam in a horizontal direction from the power supply voltage; A deflection current is supplied via a deflection coil, a plurality of S-shaped correction capacitors for correcting distortion of the electron beam, frequency determination means for determining the frequency of the horizontal synchronization signal, and a determination signal from the frequency determination means. A horizontal deflecting device comprising: delay means for delaying; and control means for switching to the S-shaped correction capacitor for performing optimal distortion correction in accordance with a determination signal from the delay means. 2. The delay means, when the determination signal from the frequency determination means indicates that the frequency has changed from a low frequency to a high frequency, delays the determination signal by a time during which a horizontal oscillation pulse is stabilized. 2. The horizontal deflecting device according to claim 1, wherein the S-shaped correction capacitor is switched to an S-shaped correction capacitor for performing optimum distortion correction in synchronization with a determination signal from the delay unit. 3. The delay unit outputs the determination signal at the same timing when the determination signal from the frequency determination unit indicates that the frequency has changed from a high frequency to a low frequency. 3. The horizontal deflecting device according to claim 1, wherein the horizontal deflection device is switched to an S-shaped correction capacitor for performing optimal distortion correction in synchronization with a discrimination signal from the control unit. 4. A PWM means for generating a power supply voltage necessary to obtain a desired horizontal amplitude synchronized with a horizontal synchronization signal;
An oscillating means for outputting a horizontal oscillation pulse synchronized with the horizontal synchronization signal; and a deflection current for synchronizing with the horizontal oscillation pulse and deflecting the electron beam in the horizontal direction from the power supply voltage. Horizontal output means for outputting a divided voltage pulse obtained by dividing the voltage, a plurality of S-shaped correction capacitors for supplying the deflection current through a deflection coil, for correcting distortion of the electron beam, and a frequency of the horizontal synchronization signal. Frequency discriminating means for discriminating, delay means for delaying a discrimination signal from the frequency discriminating means, peak voltage detecting means for detecting a peak point of the voltage of the divided voltage pulse, discrimination from the peak point and the delay means Control means for switching to the S-shaped correction capacitor for performing optimal distortion correction according to a signal. 5. The delay means, when the discrimination signal from the frequency discrimination means indicates that the frequency has changed from a low frequency to a high frequency, delays the discrimination signal by a time during which a horizontal oscillation pulse is stabilized. And switching to an S-shaped correction capacitor for performing optimal distortion correction at a peak point in synchronization with the discrimination signal from the delay means.
The horizontal deflection device as described in the above. 6. The delay means, when the determination signal from the frequency determination means indicates that the frequency has changed from a high frequency to a low frequency, outputs the determination signal at the same timing. 6. The horizontal deflection apparatus according to claim 4, wherein the apparatus is switched to an S-shaped correction capacitor for performing optimal distortion correction in synchronization with a determination signal from the delay unit. 7. A PWM means for generating a power supply voltage necessary to obtain a desired anode voltage synchronized with a horizontal synchronizing signal, and a high-voltage output for generating a voltage waveform necessary for generating an anode voltage from said power supply voltage Means, a flyback transformer for boosting and rectifying the output voltage of the high voltage output means to generate a desired anode voltage, frequency discriminating means for discriminating the frequency of the horizontal synchronizing signal, and discriminating signals from the frequency discriminating means. And switching means for switching so that the signal frequency of the output voltage of the high-voltage output means synchronized with the horizontal synchronizing signal is doubled in accordance with the determination signal from the delay means. A horizontal deflection device. 8. The delay means, when the determination signal from the frequency determination means indicates a change from a high frequency to a low frequency, delays the determination signal by a time during which a power supply voltage output from the PWM means is stabilized. 8. The horizontal deflecting device according to claim 7, wherein the switching means switches the signal frequency of the output voltage of the high voltage output means to be doubled in synchronization with the determination signal from the delay means. 9. The delay means outputs the determination signal as it is when the determination signal from the frequency determination means has changed from a low frequency to a high frequency. 9. The horizontal deflecting device according to claim 7, wherein the switching is performed such that the signal frequency of the output voltage of the high-voltage output means is doubled in synchronization with the determination signal from the controller. 10. A PWM means for generating a power supply voltage necessary to obtain a desired anode voltage synchronized with a horizontal synchronizing signal, and a high voltage output for generating a voltage waveform necessary for generating an anode voltage from said power supply voltage Means, a flyback transformer for boosting and rectifying the output voltage of the high voltage output means to generate a desired anode voltage, frequency discriminating means for discriminating the frequency of the horizontal synchronizing signal, and discriminating signals from the frequency discriminating means. Delay means, a peak voltage detecting means for detecting a peak point of a voltage obtained by dividing the output voltage of the high voltage output circuit, and the high voltage output in synchronization with the peak point and a discrimination signal from the delay means. Switching means for switching so that the signal frequency of the output voltage of the means is doubled. 11. The delay means delays the determination signal when the power supply voltage output from the PWM means is stabilized, when the determination signal from the frequency determination means indicates that the frequency has changed from a high frequency to a low frequency. 11. The horizontal switching device according to claim 10, wherein the switching unit switches at a peak point in synchronization with the determination signal from the delay unit so that the signal frequency of the output voltage of the high-voltage output unit is doubled. Deflection device. 12. The delay unit outputs the determination signal at the same timing when the determination signal from the frequency determination unit indicates that the frequency has changed from a low frequency to a high frequency. 12. The horizontal deflection device according to claim 10, wherein switching is performed so that the signal frequency of the output voltage of the high voltage output unit is doubled in synchronization with the determination signal from the delay unit.