JP2004274077A - Semiconductor integrated circuit device and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device, such as a high-performance semiconductor integrated circuit device whose soft errors of a SRAM(static random access memory) are reduced. <P>SOLUTION: The SRAM memory cell includes a pair of n-channel type MISFETs(metal insulator semiconductor field effect transistor), in whch a pair of the gate electrode and the drain are cross-connected, and the surface of a wiring MD2 of the cross-connected portion protrudes from the surface of a silicon oxide film 21, and a silicon nitride film 23 of a capacitive dielectric film and an upper electrode 24 are formed on the wiring MD2. The capacitance C can be formed of the wiring MD2, the silicon nitride film 23 and upper electrode 24, and the soft errors due to α rays can be reduced. Moreover, since the capacitance can be formed on the the sidewalls of the wiring MD2 too, increase in the capacitance can be attained. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

  The present invention relates to a semiconductor integrated circuit device and a manufacturing technique thereof, and more particularly to a technique effective when applied to a semiconductor integrated circuit device having an SRAM (Static Random Access Memory).

  SRAM is used as a cache memory for personal computers and workstations.

  The SRAM includes a flip-flop circuit that stores 1-bit information and two MISFETs (Metal Insulator Semiconductor Field Effect Transistors) for information transfer. The flip-flop circuit includes, for example, a pair of driving MISFETs and a pair of driving MISFETs. And the load MISFET.

  For such a memory cell, a soft error due to α rays has become a problem. A soft error due to α-rays means that α-rays contained in external cosmic rays and α-rays emitted from radioactive atoms contained in LSI package material enter a memory cell and are stored in the memory cell. It is a phenomenon that destroys information.

  As a countermeasure against α rays, a method of increasing the capacity of the information storage unit by adding a capacity to the information storage unit (input / output unit of the flip-flop circuit) in the memory cell is being studied.

  For example, Japanese Patent Application Laid-Open No. H11-17027 (Patent Document 1) discloses that a polycrystalline silicon 10 connected to drain regions of FETs Qp ′ and Qnd ′ and a polycrystalline silicon 11 connected to drain regions of FETs Qp and Qnd. A technique for improving soft error resistance by forming a capacitor by using the method is described.

Japanese Patent Application Laid-Open No. 10-163440 (Patent Document 2) discloses that a local wiring L1, L2 cross-connecting input / output terminals of a flip-flop circuit for storing information and a thin insulating film interposed between the local wirings L1, L2. A technique is described in which C is configured to increase the capacity of a storage node of a memory cell and prevent a decrease in α-ray soft error resistance.
JP-A-11-17027 JP-A-10-163440

  However, as the miniaturization of memory cells progresses with higher integration, the area where a capacitor can be formed also becomes smaller. Therefore, there is a limit in increasing the capacity of the information storage unit.

  On the other hand, the target value of the capacity is also increasing according to the purpose of use of the product. FIG. 48 is a diagram showing the relationship between the incident energy of α rays (MeV) and the amount of noise charge (C) for products whose power supply voltage (Vcc) is 1.2 V and 1.5 V. As shown in FIG. 48, when the information storage unit is irradiated with α rays, electric charges (noise) are stored in the information storage unit. The maximum value of this charge is 6.2 fC in a 1.2 V product. Since the critical charge of this product is 4.3 fC, it is necessary to add a capacity that can store a charge of 1.9 (= 6.2-4.3) fC or more to each node. is there. In a 1.5 V product, the maximum value of this charge is 6.1 fC, and the critical charge amount is 3.4 fC, so that 2.7 (= 6.1-3) is applied to each node. .4) It is necessary to add a capacitor capable of storing the charge amount of fC. Note that the critical charge amount is a charge amount that inverts information (1 or 0) held in the information storage unit.

  As described above, the required capacitance has been increased in spite of the fact that the area where the capacitance can be formed has been reduced due to miniaturization.

  An object of the present invention is to provide a technique capable of reducing a soft error due to α rays by securing a capacity of an information storage unit of a memory cell of a semiconductor integrated circuit device, for example, an SRAM.

  It is another object of the present invention to provide a semiconductor integrated circuit device, for example, a high-performance semiconductor integrated circuit device in which soft errors in a memory cell of an SRAM are reduced.

  The above objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  (1) A semiconductor integrated circuit device according to the present invention is a semiconductor integrated circuit device having a memory cell including a pair of n-channel MISFETs each having a gate electrode and a drain cross-connected, the n-channel MISFET being a component. A conductive layer connecting the gate electrode and the drain formed on the type MISFET, and formed in a connection hole extending from the gate electrode to the drain; A conductive layer having a protruding protrusion; a capacitor insulating film formed on the conductive layer and along a side wall of the protrusion; and an upper electrode formed on the capacitor insulating film. According to such a means, since a capacitance can be formed by the conductive layer, the capacitance insulating film, and the upper electrode, a soft error due to α rays can be reduced. Further, since a capacitance can be formed also on the side wall of the protruding portion of the conductive layer, the capacitance can be increased.

  (2) The semiconductor integrated circuit device according to the present invention is a semiconductor integrated circuit device having a memory cell including a pair of n-channel MISFETs each having a gate electrode and a drain cross-connected to each other. A conductive layer for connecting the gate electrode and the drain, the conductive layer being formed in a connection hole extending from the gate electrode to the drain, and the conductive layer , A lower electrode formed on the lower electrode, a capacitor insulating film formed on the lower electrode, and an upper electrode formed on the capacitor insulating film. According to such a means, since a capacitance can be formed by the lower electrode, the capacitor insulating film, and the upper electrode, a soft error due to α rays can be reduced. Further, when the formation region of the lower electrode is made larger than the formation region of the conductive layer, the capacitance can be increased.

  (3) The semiconductor integrated circuit device according to the present invention is a semiconductor integrated circuit device having a memory cell including a pair of n-channel MISFETs each having a gate electrode and a drain cross-connected, wherein the n-channel MISFET is a component. A conductive layer connecting the gate electrode and the drain formed on the type MISFET, and formed in a connection hole extending from the gate electrode to the drain; A conductive layer having a protruding protrusion, a lower electrode formed along the upper side of the conductive layer and a side wall of the protrusion, a capacitor insulating film formed on the lower electrode, and And an upper electrode formed. According to such a means, a capacitance connected to the conductive layer can be formed by the lower electrode, the capacitor insulating film, and the upper electrode, so that a soft error due to α rays can be reduced. Further, when the formation region of the lower electrode is made larger than the formation region of the conductive layer, the capacitance can be increased, and the capacitance can be formed on the lower electrode formed along the side wall of the protrusion of the conductive layer. Can be formed, so that the capacity can be increased.

  (4) The semiconductor integrated circuit device according to the present invention is a semiconductor integrated circuit device having a memory cell including a pair of n-channel MISFETs each having a gate electrode and a drain cross-connected, the n-channel MISFET being a component. A conductive layer for connecting the gate electrode and the drain, the conductive layer being formed in a connection hole extending from the gate electrode to the drain, and having a recess on the surface thereof. A capacitive insulating film formed on the conductive layer including the inside of the concave portion, and an upper electrode formed on the capacitive insulating film. According to such a means, since a capacitance can be formed by the conductive layer, the capacitance insulating film, and the upper electrode, a soft error due to α rays can be reduced. In addition, since a capacitance can be formed also on the concave portion of the conductive layer, the capacitance can be increased.

  (5) A method for manufacturing a semiconductor integrated circuit device according to the present invention is a method for manufacturing a semiconductor integrated circuit device having a memory cell including a pair of n-channel MISFETs each having a gate electrode and a drain cross-connected. A step of forming the n-channel MISFET; a step of forming an interlayer insulating film on the n-channel MISFET; and forming a connection hole extending from a gate electrode of the n-channel MISFET to a drain. A step of depositing a conductive film on the interlayer insulating film including the inside of the connection hole, and embedding the conductive film in the connection hole by polishing until the surface of the interlayer insulating film is exposed. Forming a conductive layer, and further etching the exposed surface of the interlayer insulating film to expose an upper portion of a sidewall of the conductive layer. And a step, a step of forming a capacitor insulating film along the top and the exposed sidewall of the conductive layer, and forming an upper electrode on the capacitive insulating film. According to such a means, it is possible to form a semiconductor integrated circuit device in which soft errors are reduced by the capacitance constituted by the conductive layer, the capacitor insulating film and the upper electrode. The capacitance can be increased by further etching the surface of the interlayer insulating film and exposing the upper part of the side wall of the conductive layer.

  (6) The method for manufacturing a semiconductor integrated circuit device according to the present invention is a method for manufacturing a semiconductor integrated circuit device having a memory cell including a pair of n-channel MISFETs whose gate electrodes and drains are cross-connected. A step of forming the n-channel MISFET; a step of forming an interlayer insulating film on the n-channel MISFET; and a step of extending to one gate electrode or the other drain of the pair of n-channel MISFETs. Forming an existing connection hole, depositing a conductive film on the interlayer insulating film including the inside of the connection hole, forming a lower electrode on the conductive layer, and forming a lower electrode on the lower electrode. Forming a capacitive insulating film; and forming an upper electrode on the capacitive insulating film. According to such a means, it is possible to form a semiconductor integrated circuit device in which soft errors are reduced by the capacitance constituted by the lower electrode, the capacitor insulating film, and the upper electrode. Further, when the formation region of the lower electrode is made larger than the formation region of the conductive layer, the capacitance can be increased.

  (7) A method for manufacturing a semiconductor integrated circuit device according to the present invention is a method for manufacturing a semiconductor integrated circuit device having a memory cell including a pair of n-channel MISFETs each having a gate electrode and a drain cross-connected. A step of forming the n-channel MISFET; a step of forming an interlayer insulating film on the n-channel MISFET; and a step of extending from one gate electrode of the pair of n-channel MISFETs to the other drain. Forming an existing connection hole, depositing a conductive film on the interlayer insulating film including the inside of the connection hole, and polishing the conductive film until the surface of the interlayer insulating film is exposed. Forming a conductive layer embedded in the connection hole, and further etching the exposed surface of the interlayer insulating film to form the conductive layer Exposing an upper part of the side wall, forming a lower electrode along the upper part of the conductive layer and the exposed side wall, forming a capacitive insulating film on the lower electrode, and forming an upper part on the capacitive insulating film. Forming an electrode. According to such a means, it is possible to form a semiconductor integrated circuit device in which soft errors are reduced by the capacitance constituted by the lower electrode, the capacitor insulating film, and the upper electrode. Further, when the formation region of the lower electrode is made larger than the formation region of the conductive layer, the capacitance can be increased. In addition, since a capacitance can be formed on the lower electrode formed along the exposed side wall of the conductive layer, the capacitance can be increased.

  (8) The method for manufacturing a semiconductor integrated circuit device according to the present invention is a method for manufacturing a semiconductor integrated circuit device having a memory cell including a pair of n-channel MISFETs whose gate electrodes and drains are cross-connected. A step of forming the n-channel MISFET; a step of forming an interlayer insulating film on the n-channel MISFET; and forming a connection hole extending from a gate electrode of the n-channel MISFET to a drain. A step of depositing a conductive film on the interlayer insulating film including the inside of the connection hole, wherein a step of depositing a conductive film having a thickness smaller than the radius of the connection hole; Forming a conductive layer buried in the connection hole by polishing until the surface of the interlayer insulating film is exposed and having a concave portion thereon; And a step of forming a capacitor insulating film on the top, and forming an upper electrode on the capacitive insulating film. According to such a means, it is possible to form a semiconductor integrated circuit device in which soft errors are reduced by the capacitance constituted by the conductive layer, the capacitor insulating film and the upper electrode. In addition, since a capacitance can be formed also on the concave portion of the conductive layer, the capacitance can be increased.

  The effects obtained by typical aspects of the invention disclosed in the present application will be briefly described as follows.

  (1) A capacitance insulating film (silicon nitride film) is formed on the cross-connecting wirings (MD1, MD2) of an SRAM memory cell having a pair of n-channel MISFETs (Qd1, Qd2) whose gate electrodes and drains are cross-connected. Since 23) and the upper electrode 24 are formed, a capacitance can be formed by the wiring, the capacitor insulating film, and the upper electrode. As a result, soft errors due to α rays can be reduced.

  Further, since the surface of the wiring is formed so as to protrude from the surface of the interlayer insulating film (silicon nitride film 17, PSG film 20, and silicon oxide film 21), a capacitance can be formed on the side wall of this protruding portion. The capacity can be increased.

  (2) In the SRAM memory cell having a pair of n-channel MISFETs in which each gate electrode and drain are cross-connected, the lower electrode 22 and the capacitor insulating film (silicon nitride film) are formed on the cross-connecting wires (MD1, MD2). 23) and the upper electrode 24 are formed, so that a capacitor composed of the lower electrode, the capacitor insulating film and the upper electrode can be formed on this wiring. As a result, soft errors due to α rays can be reduced. In addition, when the formation region of the lower electrode is made larger than the formation region of the wiring, the capacitance can be increased.

  (3) The surface of the cross-connecting wiring (MD1, MD2) of the SRAM memory cell having a pair of n-channel MISFETs whose gate electrodes and drains are cross-connected is formed so as to protrude from the surface of the interlayer insulating film. Since the capacitor including the lower electrode, the capacitor insulating film, and the upper electrode is formed on the wiring, soft errors due to α rays can be reduced, and the capacitance can be increased.

  (4) Since the recess a is formed on the surface of the cross connection wirings (MD1, MD2) of the SRAM memory cell having a pair of n-channel MISFETs in which the gate electrode and the drain are cross connected, the recess a is also formed on the recess. Since the capacitance can be formed, the capacitance can be increased.

  (5) A high-performance SRAM memory cell in which soft errors due to α rays are reduced can be manufactured.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for describing the embodiments, the same members are denoted by the same reference numerals in principle, and the repeated description thereof will be omitted.

(Embodiment 1)
FIG. 1 is an equivalent circuit diagram showing a memory cell of the SRAM according to the first embodiment. As shown, this memory cell MC is arranged at the intersection of a pair of complementary data lines (data line DL, data line / (bar) DL) and a word line WL, and a pair of driving MISFETs Qd1, Qd2, It is constituted by a pair of load MISFETs Qp1 and Qp2 and a pair of transfer MISFETs Qt1 and Qt2. The drive MISFETs Qd1 and Qd2 and the transfer MISFETs Qt1 and Qt2 are formed of n-channel MISFETs, and the load MISFETs Qp1 and Qp2 are formed of p-channel MISFETs.

  Of the six MISFETs constituting the memory cell MC, the driving MISFET Qd1 and the load MISFET Qp1 constitute a CMOS inverter INV1, and the driving MISFET Qd2 and the load MISFET Qp2 constitute a CMOS inverter INV2. The input / output terminals (storage nodes A and B) of the pair of CMOS inverters INV1 and INV2 are cross-coupled to form a flip-flop circuit as an information storage unit for storing 1-bit information. One input / output terminal (storage node A) of the flip-flop circuit is connected to one of the source and drain regions of the transfer MISFET Qt1, and the other input / output terminal (storage node B) is connected to the source of the transfer MISFET Qt2. , And one of the drain regions.

  Further, the other of the source and drain regions of the transfer MISFET Qt1 is connected to the data line DL, and the other of the source and drain regions of the transfer MISFET Qt2 is connected to the data line / DL. One end (the source regions of the load MISFETs Qp1 and Qp2) of the flip-flop circuit is connected to the power supply voltage (Vcc), and the other end (the source regions of the drive MISFETs Qd1 and Qd2) is connected to the reference voltage (Vss). ing.

  The operation of the above circuit will be described. When the storage node A of one CMOS inverter INV1 is at a high potential ("H"), the driving MISFET Qd2 is turned on, and the storage node B of the other CMOS inverter INV2 is at a low potential. (“L”). Therefore, the driving MISFET Qd1 is turned off, and the high potential (“H”) of the storage node A is held. That is, the state of the mutual storage nodes A and B is held by a latch circuit in which a pair of CMOS inverters INV1 and INV2 are cross-coupled, and information is stored while the power supply voltage is applied.

  A word line WL is connected to each gate electrode of the transfer MISFETs Qt1 and Qt2, and the conduction and non-conduction of the transfer MISFETs Qt1 and Qt2 are controlled by the word line WL. That is, when the word line WL is at a high potential ("H"), the transfer MISFETs Qt1 and Qt2 are turned on, and the flip-flop circuit is electrically connected to the complementary data lines (data lines DL and / DL). Therefore, the potential states (“H” or “L”) of the storage nodes A and B appear on the data lines DL and / DL, and are read as information of the memory cells MC.

  To write information into the memory cell MC, the word line WL is set to the "H" potential level, the transfer MISFETs Qt1, Qt2 are turned on, and the information on the data lines DL, / DL is transmitted to the storage nodes A, B.

  Next, a method for manufacturing the SRAM of the present embodiment will be described with reference to FIGS.

  First, as shown in FIGS. 2 and 3, an element isolation 2 is formed in a semiconductor substrate 1. FIG. 3 is a plan view of a semiconductor substrate showing a region for about one memory cell, and FIG. 2 is a cross-sectional view of FIG. 3, which corresponds to a cross section taken along line AA of FIG. This element isolation 2 is formed as follows. For example, an element isolation groove having a depth of about 250 nm is formed by etching a semiconductor substrate 1 made of p-type single crystal silicon having a specific resistance of about 1 to 10 Ωcm.

  Thereafter, the semiconductor substrate 1 is thermally oxidized at about 1000 ° C. to form a thin silicon oxide film (not shown) having a thickness of about 10 nm on the inner wall of the groove. This silicon oxide film is used to recover the damage of the dry etching generated on the inner wall of the groove and to relieve the stress generated at the interface between the silicon oxide film 5 and the semiconductor substrate 1 embedded in the groove in the next step. Form.

  Next, a silicon oxide film 5 having a film thickness of about 450 to 500 nm is deposited on the semiconductor substrate 1 including the inside of the groove by a CVD (Chemical Vapor deposition) method, and the groove is formed by a chemical mechanical polishing (CMP) method. Is polished and the surface thereof is flattened.

  Next, a p-type impurity (boron) and an n-type impurity (for example, phosphorus) are ion-implanted into the semiconductor substrate 1, and then the impurities are diffused by a heat treatment at about 1000 ° C., so that the p-type well 3 and the An n-type well 4 is formed. As shown in FIG. 3, active regions An1, An2, Ap1, and Ap2, which are main surfaces of two p-type wells 3 and two n-type wells 4, are formed in the semiconductor substrate 1, and these active regions are oxidized. It is surrounded by an element isolation 2 in which a silicon film 5 is embedded.

  Further, as will be described later in detail, among the six MISFETs (Qt1, Qt2, Qd1, Qd2, Qp1, Qp2) constituting the memory cell MC, the n-channel type MISFET (Qt1, Qd1) has an active region Ap1 ( The n-channel MISFET (Qt2, Qd2) is formed on the p-type well 3), and is formed on the active region Ap2 (p-type well 3). The p-channel MISFET (Qp2) is formed on the active region An1 (n-type well 4), and the p-channel MISFET (Qp1) is formed on the active region An2 (n-type well 4).

  Next, an n-channel MISFET (Qt1, Qd1, Qt2, Qd2) and a p-channel MISFET (Qp1, Qp2) are formed on the main surface of the semiconductor substrate 1.

  First, the surface of the semiconductor substrate 1 (p-type well 3 and n-type well 4) is wet-cleaned using a hydrofluoric acid-based cleaning solution, and then, as shown in FIG. Then, a clean gate oxide film 8 having a thickness of about 6 nm is formed on each surface of the n-type well 4.

  Next, a gate electrode G is formed on the gate oxide film 8. FIG. 5 is a plan view of a semiconductor substrate showing a region for about one memory cell, and FIG. 4 corresponds to a cross section taken along line AA of FIG. This gate electrode G is formed as follows. First, a low-resistance polycrystalline silicon film 9 having a thickness of about 100 nm is deposited on the gate oxide film 8 by a CVD method.

  Next, the gate electrode G made of the polycrystalline silicon film 9 is formed by dry-etching the polycrystalline silicon film 9 using a photoresist film (not shown) as a mask. As shown in FIG. 5, a gate electrode G of the transfer MISFET Qt1 and a gate electrode G of the drive MISFET Qd1 are formed on the active region Ap1, and a gate electrode G of the transfer MISFET Qt2 is formed on the active region Ap2. The gate electrode G of the driving MISFET Qd2 is formed. The gate electrode G of the load MISFET Qp2 is formed on the active region An1, and the gate electrode G of the load MISFET Qp1 is formed on the active region An2. These gate electrodes are formed in a direction orthogonal to AA in the figure, and the gate electrode G of the load MISFET Qp1 and the gate electrode of the drive MISFET Qd1 are common, and the gate electrodes of the load MISFET Qp2 and It is common to the gate electrode of the driving MISFET Qd2.

Next, an n ⁻ -type semiconductor region is formed by implanting n-type impurities (phosphorus) on both sides of the gate electrode G on the p-type well 3, and a p-type impurity (arsenic) is formed on the n-type well 4. The p ⁻ type semiconductor region 14 is formed by the implantation.

  Next, a silicon nitride film having a thickness of about 40 nm is deposited on the semiconductor substrate 1 by the CVD method, and is etched anisotropically to form a sidewall spacer 16 on the side wall of the gate electrode G.

Next, an n ⁺ -type semiconductor region (source, drain) is formed by ion-implanting an n-type impurity (phosphor or arsenic) into the p-type well 3, and a p-type impurity (boron) is ion-implanted into the n-type well 4. By doing so, ap ⁺ type semiconductor region 18 (source, drain) is formed.

  Through the steps so far, six MISFETs (driving MISFETs Qd1 and Qd2, transfer MISFETs Qt1 and Qt2, and load MISFETs Qp1 and Qp2) constituting the memory cell MC are completed.

Subsequently, after cleaning the surface of the semiconductor substrate 1, a Co film and a Ti film are sequentially deposited on the semiconductor substrate 1 by a sputtering method. Next, as shown in FIG. 6, a heat treatment is performed at 600 ° C. for 1 minute, so that a CoSi ₂ layer 19 is formed on the exposed portions (the n ⁺ type semiconductor region and the p ⁺ type semiconductor region 18) of the semiconductor substrate 1 and the gate electrode G. To form

Next, after the unreacted Co film and Ti film are removed by etching, a heat treatment is performed at 700 to 800 ° C. for about 1 minute to lower the resistance of the CoSi ₂ layer 19.

  Next, as shown in FIG. 7, a silicon nitride film 17 having a thickness of about 50 nm is deposited on the semiconductor substrate 1 by the CVD method. The silicon nitride film 17 functions as an etching stopper when forming a contact hole C1 and the like described later.

  Subsequently, a PSG (Phosphor Silicate Glass) film 20 may be applied on the silicon nitride film 17, heat-treated, flattened, and then a silicon oxide film 21 may be deposited. The silicon oxide film 21 is formed by using, for example, tetraethoxysilane as a raw material by a plasma CVD method. The PSG film 20, the silicon oxide film 21, and the silicon nitride film 17 serve as an interlayer insulating film between the gate electrode G and the first layer wiring M1. After a silicon oxide film 21 having a thickness of about 700 nm to 800 nm is deposited on the silicon nitride film 17 by a CVD method, the surface of the silicon oxide film 21 is polished by a CMP (Chemical Mechanical Polishing) method to flatten the surface. It may be.

Next, as shown in FIGS. 8 and 9, the silicon oxide film 21 and the PSG film 20 are dry-etched by dry etching using a photoresist film (not shown) as a mask, and then the silicon nitride film 17 is dry-etched. Thereby, a contact hole C1 and a wiring groove HM are formed on the n ⁺ type semiconductor region (source and drain) and the p ⁺ type semiconductor region 18 (source and drain). Further, a contact hole C1 is formed on the gate electrodes G of the transfer MISFETs Qt1 and Qt2. One of the two wiring grooves HM in FIG. 9 extends from above the drain of the driving MISFET Qd1 to above the gate electrode of the driving MISFET Qd2 via above the drain of the load MISFET Qp1. The other wiring groove HM extends from above the drain of the driving MISFET Qd2 to above the gate electrode of the driving MISFET Qd1 via the drain of the load MISFET Qp2 (FIG. 9).

  Next, a plug P1 and wirings MD1, MD2 (conductive layers) are formed by embedding a conductive film in the contact hole C1 and the wiring groove HM. First, a Ti film (not shown) having a film thickness of about 10 nm and a TiN film having a film thickness of about 50 nm are sequentially formed on the silicon oxide film 21 including the inside of the contact hole C1 and the wiring groove HM by sputtering. Heat treatment at 1 ° C. for 1 minute. Next, a W film is deposited by a CVD method, etch back or CMP is performed until the surface of the silicon oxide film 21 is exposed, and the Ti film, TiN film and W film outside the contact hole C1 and the wiring groove HM are removed. The plug P1 is formed in the contact hole C1, and the wirings MD1 and MD2 are formed in the wiring groove HM. At this time, the surface of the silicon oxide film 21 and the surfaces of the plug P1 and the wirings MD1 and MD2 are almost the same.

  Next, as shown in FIG. 10, the surface of the silicon oxide film 21 is further etched. At this time, the upper portions of the side walls of the plug P1 and the wirings MD1, MD2 are exposed. When the PSG film 20 is formed, it is necessary to adjust the thickness of the silicon oxide film 21 so that the surface of the PSG film 20 is not exposed.

  Next, as shown in FIG. 11, a silicon nitride film 23 is formed on the silicon oxide film 21, the plug P1, and the wiring MD2. The silicon nitride film 23 is formed between the wirings MD1 and MD2 serving as lower electrodes and an upper electrode 24 described later, and serves as a capacitance insulating film.

  Next, a TiN film is deposited on the silicon nitride film 23 by a sputtering method and patterned to form an upper electrode 24 extending on the wirings MD1 and MD2 and on the plug P1 on the sources of the load MISFETs Qp1 and Qp2. (FIG. 12). The upper electrode 24 is patterned so as not to extend over the plug P1 on one end (the side connected to the data line) of the transfer MISFETs Qt1 and Qt2 and the plug P1 on the sources of the drive MISFETs Qd1 and Qd2.

  Through the above steps, the capacitance C composed of the wirings MD1 and MD2 serving as lower electrodes, the silicon nitride film 23, and the upper electrode 24 can be formed.

  As described above, according to the present embodiment, since the capacitance C connected to the wirings MD1 and MD2 is formed, it is possible to reduce soft errors due to α rays incident on the memory cells of the SRAM. After the wirings MD1 and MD2 are formed, the surface of the silicon oxide film 21 is further etched, so that the upper portions of the side walls of the wirings MD1 and MD2 are exposed, and the silicon nitride film 23 serving as a capacitive insulating film is formed along the side walls. Since it can be formed, the capacity can be increased.

  FIG. 18 is a diagram showing the relationship between the amount of etching of the surface of the silicon oxide film 21, the thickness of the silicon nitride film 23, and the amount of increase in memory cell capacity (fF). Graphs (a), (b) and (c) show the increase in capacitance when the etching amount of the surface of the silicon oxide film 21 is 200 nm, 100 nm and 0 nm, respectively. As shown in FIG. 18, for example, when the etching amount of the surface of the silicon oxide film 21 is 200 nm and the thickness of the silicon nitride film 23 is 10 nm, the capacitance can be increased by about 6 fF. When the etching amount of the surface of the silicon oxide film 21 is 100 nm and the thickness of the silicon nitride film is 10 nm, the capacitance can be increased by about 4 fF.

  After that, a first layer wiring M1 and a second layer wiring M2 are formed on the upper electrode 24 via an interlayer insulating film. Subsequently, the steps of forming these wirings will be described.

  First, as shown in FIGS. 13 and 14, a silicon oxide film 25 is deposited on the upper electrode 24 by a CVD method. Next, a contact hole C2 is formed by removing the silicon oxide film 25 on the plug P1 by etching. Here, since the silicon nitride film 23 exists on the plug P1 on the source of the load MISFETs Qp1 and Qp2, the upper electrode 24 and the silicon nitride film 23 as well as the silicon oxide film 25 are removed by etching.

  Next, a plug P2 is formed by embedding a conductive film in the contact hole C2. First, a Ti film (not shown) having a thickness of about 10 nm and a TiN film having a thickness of about 50 nm are sequentially formed on the upper part of the silicon oxide film 25 including the inside of the contact hole C2 by a sputtering method. Heat treatment is performed. Next, a W film is deposited by the CVD method, etched back or CMP is performed until the surface of the silicon oxide film 25 is exposed, and the Ti film, the TiN film and the W film outside the contact hole C2 are removed to form the plug P2. . Note that, in the plan view of FIG. 14, the illustration of the gate electrode G, the active region An1, and the like is omitted.

  Subsequently, as shown in FIGS. 15 and 16, a first layer wiring M1 is formed on the silicon oxide film 25 and the plug P2. A Ti film (not shown) having a thickness of about 10 nm and a TiN film having a thickness of about 50 nm are sequentially formed by a sputtering method, and heat-treated at 500 to 700 ° C. for 1 minute. Next, a first film M1 is formed by depositing and patterning a W film by the CVD method. In the first layer wiring M1, the first layer wiring M1 connecting the gate electrodes G of the transfer MISFETs Qt1 and Qt2 via the plug P1 becomes the word line WL.

  Next, as shown in FIG. 17, a silicon oxide film 27 (not shown in FIG. 17) is deposited on the first layer wiring M1 and the silicon oxide film 25 by the CVD method, and then the first layer wiring M1 is formed. The contact hole C3 is formed by removing the upper silicon oxide film 27 by etching.

  Next, a plug P3 is formed by embedding a conductive film in the contact hole C3. This plug P3 is formed similarly to the plug P2.

  Subsequently, a second layer wiring M2 is formed on the silicon oxide film 27 and the plug P3. First, a Ti film (not shown) having a thickness of about 10 nm and a TiN film having a thickness of about 50 nm are sequentially formed by a sputtering method, and heat-treated at 500 to 700 ° C. for 1 minute. Next, a second film M2 is formed by depositing and patterning a W film by the CVD method. A reference potential (Vss) is supplied to the sources of the driving MISFETs Qd1 and Qd2 via the second layer wiring M2.

  The power supply potential (Vcc) is supplied to the sources of the load MISFETs Qp1 and Qp2 via the second-layer wiring M2. Therefore, as shown in FIG. 13, since the upper electrode 24 is in contact with the side wall of the plug P2 connected to the sources of the load MISFETs Qp1 and Qp2, the upper electrode 24 is supplied with the power supply potential (Vcc). You. As a result, the above-mentioned capacitance C becomes a capacitance connected between the storage node A or B in FIG. 1 and the power supply potential (Vcc).

  In addition, the second layer wiring connected to one end of the driving MISFETs Qd1 and Qd2 becomes a data line (DL, / DL).

  Through the above steps, the SRAM memory cell described with reference to FIG. 1 is almost completed.

(Embodiment 2)
A method of manufacturing the SRAM of the present embodiment will be described with reference to FIGS. Note that the steps up to the step of forming the plug P1 and the wirings MD1 and MD2 described with reference to FIGS.

  First, the semiconductor substrate 1 shown in FIGS. 8 and 9 described in the first embodiment is prepared, and as shown in FIG. 19, a TiN film is deposited on the silicon oxide film 21, the plug P1, and the wiring MD2 by a sputtering method. Then, the lower electrode 22 is formed on the wirings MD1 and MD2 by patterning. The region where the lower electrode 22 is formed is larger than the region where the wirings MD1 and MD2 are formed (FIG. 20).

  Next, as shown in FIGS. 21 and 22, a silicon nitride film 23 is formed on the lower electrode 22 and the silicon oxide film 21. The silicon nitride film 23 is formed between the lower electrode 22 and an upper electrode 24 described later, and serves as a capacitance insulating film.

  Next, a TiN film is deposited on the silicon nitride film 23 by a sputtering method and patterned to form an upper electrode 24 extending on the lower electrode 22 and the plug P1 on the sources of the load MISFETs Qp1 and Qp2. I do. The upper electrode 24 is patterned so as not to extend over the plug P1 on one end (the side connected to the data line) of the transfer MISFETs Qt1 and Qt2 and the plug P1 on the sources of the drive MISFETs Qd1 and Qd2.

  Through the above steps, the capacitor C including the lower electrode 22, the silicon nitride film 23, and the upper electrode 24 can be formed.

  As described above, according to the present embodiment, since the capacitance C connected to the wirings MD1 and MD2 is formed, it is possible to reduce soft errors due to α rays incident on the memory cells of the SRAM. Further, since the lower electrode 22 formation region is made larger than the wiring MD1 and MD2 formation regions, the capacitance can be increased.

  Next, after a silicon oxide film 25 is deposited on the upper electrode 24 by a CVD method, a first layer wiring M1 and a second layer wiring M2 are formed. For the formation steps, see FIGS. The description is omitted because it is the same as that of the first embodiment described above.

(Embodiment 3)
The method of manufacturing the SRAM according to the present embodiment will be described with reference to FIGS. Note that the steps up to the step of etching the surface of the silicon oxide film 21 described with reference to FIGS. 2 to 10 are the same as those in the first embodiment, and thus description thereof will be omitted.

  First, the semiconductor substrate 1 shown in FIG. 10 described in the first embodiment is prepared, and as shown in FIG. 23, a TiN film is deposited on the silicon oxide film 21, the plug P1, and the wiring MD2 by a sputtering method, and is patterned. Thereby, the lower electrode 22 is formed on the wirings MD1 and MD2. At this time, since a step is formed between the surfaces of the wirings MD1 and MD2 and the surface of the silicon oxide film 21, a step corresponding to the step is also formed on the surface of the lower electrode 22. The formation region of the lower electrode 22 is larger than the formation regions of the wirings MD1 and MD2 (similar to FIG. 20).

  Next, as shown in FIG. 24, a silicon nitride film 23 is formed on the lower electrode 22, the silicon oxide film 21, and the plug P1. The silicon nitride film 23 is formed between the lower electrode 22 and an upper electrode 24 described later, and serves as a capacitance insulating film.

  Next, a TiN film is deposited on the silicon nitride film 23 by a sputtering method and patterned to form an upper electrode 24 extending on the wirings MD1 and MD2 and on the plug P1 on the sources of the load MISFETs Qp1 and Qp2. It is formed (similar to FIG. 22). The upper electrode 24 is patterned so as not to extend over the plug P1 on one end (the side connected to the data line) of the transfer MISFETs Qt1 and Qt2 and the plug P1 on the sources of the drive MISFETs Qd1 and Qd2.

  Through the above steps, the capacitor C including the lower electrode 22, the silicon nitride film 23, and the upper electrode 24 can be formed.

  As described above, according to the present embodiment, since the capacitance C connected to the wirings MD1 and MD2 is formed, it is possible to reduce soft errors due to α rays incident on the memory cells of the SRAM. At this time, since a step corresponding to the step between the surfaces of the wirings MD1 and MD2 and the surface of the silicon oxide film 21 is formed on the surface of the lower electrode 22, the lower electrode 22 and the capacitor are formed along the step. The silicon nitride film 23 serving as an insulating film can be formed, and the capacitance can be increased. Further, since the lower electrode 22 formation region is made larger than the wiring MD1 and MD2 formation regions, the capacitance can be increased.

  Next, after a silicon oxide film 25 is deposited on the upper electrode 24 by a CVD method, a first layer wiring M1 and a second layer wiring M2 are formed. For the formation steps, see FIGS. The description is omitted because it is the same as that of the first embodiment described above.

(Embodiment 4)
The method of manufacturing the SRAM according to the present embodiment will be described with reference to FIGS. Note that the steps up to the step of forming the silicon oxide film 21 described with reference to FIGS. 2 to 7 are the same as in the case of the first embodiment, and a description thereof will be omitted.

First, the semiconductor substrate 1 shown in FIG. 7 described in the first embodiment is prepared, and as shown in FIG. 25, the silicon oxide film 21 and the PSG film 20 are dry-etched using a photoresist film (not shown) as a mask. Is dry-etched, and then the silicon nitride film 17 is dry-etched to form a contact hole C1 and a wiring groove HM on the n ⁺ type semiconductor region (source, drain) and the p ⁺ type semiconductor region 18 (source, drain). Form. Further, a contact hole C1 is formed on the gate electrode G (same as FIG. 9). Of the two wiring grooves in the drawing, one wiring groove HM extends from above the drain of the driving MISFET Qd1 to above the gate electrode of the driving MISFET Qd2 via above the drain of the load MISFET Qp1. The other wiring groove HM extends from above the drain of the driving MISFET Qd2 to above the gate electrode of the driving MISFET Qd1 via the drain of the load MISFET Qp2.

  Next, a Ti film (not shown) having a thickness of about 10 nm and a TiN film having a thickness of about 50 nm are sequentially formed on the upper portion of the silicon oxide film 21 including the inside of the contact hole C1 and the wiring groove HM by a sputtering method. Heat treatment at 1 ° C. for 1 minute. Next, a W film is deposited by a CVD method. At this time, the thickness of the W film is made smaller than the radius of the contact hole C1. Next, the Ti film, the TiN film, and the W film are etched back or CMP until the surface of the silicon oxide film 21 is exposed, and the Ti film, the TiN film, and the W film outside the contact hole C1 and the wiring groove HM are removed. As a result, the plugs P1 embedded in the contact holes C1 and the wirings MD1 and MD2 having the concave portions a thereon are formed.

  Next, as shown in FIG. 26, a silicon nitride film 23 is formed on the silicon oxide film 21, the plug P1, and the wiring MD2. The silicon nitride film 23 is formed between the wirings MD1 and MD2 serving as lower electrodes and an upper electrode 24 described later, and serves as a capacitance insulating film.

  Next, a TiN film is deposited on the silicon nitride film 23 by a sputtering method and patterned to form an upper electrode 24 extending on the wirings MD1 and MD2 and on the plug P1 on the sources of the load MISFETs Qp1 and Qp2. It is formed (similar to FIG. 22). The upper electrode 24 is patterned so as not to extend over the plug P1 on one end (the side connected to the data line) of the transfer MISFETs Qt1 and Qt2 and the plug P1 on the sources of the drive MISFETs Qd1 and Qd2.

  Through the above steps, the capacitance C composed of the wirings MD1 and MD2 serving as lower electrodes, the silicon nitride film 23, and the upper electrode 24 can be formed.

  As described above, according to the present embodiment, since the capacitance C connected to the wirings MD1 and MD2 is formed, it is possible to reduce soft errors due to α rays incident on the memory cells of the SRAM. Further, since the wirings MD1 and MD2 are formed using a W film having a thickness smaller than the radius of the contact hole C1, a concave portion a is formed above the wiring MD1 and MD2, and a capacitance insulating film is formed along the concave portion a. Since the silicon nitride film 23 can be formed, the capacity can be increased.

  Next, after a silicon oxide film 25 is deposited on the upper electrode 24 by a CVD method, a first layer wiring M1 and a second layer wiring M2 are formed. For the formation steps, see FIGS. The description is omitted because it is the same as that of the first embodiment described above.

  In the present embodiment, the silicon nitride film 23 may be formed after the surface of the silicon oxide film 21 is etched as in the first embodiment after the plug P1 and the wirings MD1 and MD2 are formed. In this case, since the silicon nitride film 23 is formed along the side walls of the wirings MD1 and MD2 exposed by the etching, the capacitance can be further increased.

  Further, in order to increase the capacitance, the silicon nitride film 23 may be formed after the lower electrodes 22 are formed on these wirings as in Embodiment 2 after forming the wirings MD1 and MD2. After the formation of the plug P1 and the wirings MD1 and MD2, the surface of the silicon oxide film 21 may be etched to form the lower electrode 22 and then the silicon nitride film 23 as in the third embodiment.

(Embodiment 5)
In the fifth embodiment (the same applies to the second to fourth embodiments), the power supply potential (Vcc) is connected to the upper electrode 24 via the side wall of the plug P2 (connected to the sources of the load MISFETs Qp1 and Qp2). ), The power supply potential (Vcc) can be supplied via the bottom surface of the plug P2.

  The method of manufacturing the SRAM according to the present embodiment will be described with reference to FIGS. Note that the steps up to the step of etching the surface of the silicon oxide film 21 described with reference to FIGS. 2 to 10 are the same as those in the first embodiment, and thus description thereof will be omitted.

  First, the semiconductor substrate 1 shown in FIG. 10 described in the first embodiment is prepared, and as shown in FIG. 27, a silicon nitride film 23 is formed on the silicon oxide film 21, the plug P1, and the wiring MD2. The silicon nitride film 23 is formed between the wirings MD1 and MD2 serving as lower electrodes and an upper electrode 24 described later, and serves as a capacitance insulating film.

  Next, as shown in FIGS. 28 and 29, the silicon nitride film 23 on the plug P1 on the source of the load MISFET is removed, and an opening OP1 is formed.

  Next, as shown in FIGS. 30 and 31, a TiN film is deposited on the silicon nitride film 23 including the inside of the opening OP1 by a sputtering method, and is patterned to form the wiring MISFETs Qp1 and Qp2 on the wirings MD1 and MD2. The upper electrode 24 extending above the plug P1 on the source of FIG. The upper electrode 24 is patterned so as not to extend over the plug P1 on one end (the side connected to the data line) of the transfer MISFETs Qt1 and Qt2 and the plug P1 on the sources of the drive MISFETs Qd1 and Qd2.

  Through the above steps, the capacitance C composed of the wirings MD1 and MD2 serving as lower electrodes, the silicon nitride film 23, and the upper electrode 24 can be formed.

  Next, as shown in FIG. 32, a silicon oxide film 25 is deposited on the upper electrode 24 by a CVD method. Next, the contact hole C2 is formed by removing the silicon oxide film 25 on the plug P1 by etching.

  As described above, in the present embodiment, since the silicon nitride film 23 of the plug P1 on the sources of the load MISFETs Qp1 and Qp2 is removed in advance, only the silicon oxide film 25 on the plug P1 needs to be removed. The contact hole C2 on the plug P1 can be easily formed.

  Further, even if misalignment occurs between the plug P1 and the contact hole C2, the plug P1 and the plug P2 formed in the contact hole C2 are connected via the upper electrode 24. The conduction failure can be reduced. In addition, a margin for a short circuit between the gate electrode G and the plug P2 can be secured.

  Next, a first layer wiring M1 and a second layer wiring M2 are formed on the silicon oxide film 25. These wiring forming steps are the same as those of the first embodiment described with reference to FIGS. The description is omitted because it is the same as the case.

  In the second to fourth embodiments, similarly, after removing the silicon nitride film 23 of the plug P1 on the sources of the load MISFETs Qp1 and Qp2 to form the opening OP1, the upper electrode 24 and the plug P2 , The above-described effects can be obtained.

(Embodiment 6)
In the sixth embodiment (the same applies to the second to fourth embodiments), a region for about one memory cell has been described. However, a case in which the present invention is applied to a memory cell array will be described.

  As shown in FIG. 33, the memory cells MC are arranged in a matrix at the intersections of the data line pairs (DL, / DL) and the word lines WL. In the memory cell array, memory cells for redundancy repair are formed in addition to normal memory cells. This memory cell for redundancy repair is also arranged at the intersection of the data line pair (DL, / DL) and the word line WL. If a defect occurs in a normal memory cell, the same data line (DL) is used. , / DL) is replaced with a redundancy relief memory cell column by cutting a fuse (FUSE). FIG. 34 shows a layout of a memory cell array arranged on a chip. As shown in FIG. 34, the memory cell array includes a plurality of memory mats. An input buffer (input Buf.), An output circuit, and peripheral circuits such as FUSE are arranged around the memory cell array. Note that the above-described memory cell row for redundancy repair need not be formed in all memory mats.

  FIG. 35 is a main-portion plan view of the semiconductor substrate showing the SRAM of the present embodiment. In the figure, two memory cells MC11, MC12, MC21, MC22 are arranged vertically and horizontally. The memory cells MC11 and MC21 have the same configuration as the memory cell of the first embodiment described with reference to FIGS. Further, the memory cells MC21 and MC22 have a structure corresponding to the memory cells MC11 and MC12 with respect to BB in the figure. Although not shown, memory cells MC11 and MC12 and a target memory cell are arranged with respect to CC in the figure, and memory cells MC21 and MC22 and a target memory cell with respect to CC in the figure are arranged. Be placed.

  Here, the upper electrodes 24 of the memory cells MC11 and MC12 are connected. The upper electrodes 24 of the memory cells MC21 and MC22 are also connected. Further, the upper electrode 24 of the memory cell (MC11, MC12) connected to a pair of data line pairs (DL, / DL) and the memory cell (MC21, MC21, The upper electrode 24 of the MC 22) is independent (not connected).

  As described above, if the upper electrode 24 is divided for each data line pair (DL, / DL), redundancy repair for each memory cell column connected to the same data line pair (DL, / DL) can be easily performed. It can be carried out.

  Also in the second to fourth embodiments, if the upper electrode 24 is similarly divided for each data line pair (DL, / DL), the upper electrode 24 is connected to the same data line pair (DL, / DL). The redundancy relief for each memory cell column can be easily performed.

  Also, when performing redundancy relief for each memory cell row connected to the same word line pair (WL), the upper electrode 24 may be divided for each word line (WL). In addition, when performing redundancy repair for each memory cell (for each bit), the upper electrode 24 may be divided for each memory cell.

(Embodiment 7)
In the seventh embodiment (the same applies to the second to fourth embodiments), the power supply potential (Vcc) is supplied to the upper electrode 24, and the potential of the storage node A or B in FIG. Although the capacitor C is formed between them, a capacitor can be formed between the storage nodes AB in FIG.

  The method of manufacturing the SRAM of the present embodiment will be described with reference to FIGS. Note that the steps up to the step of etching the surface of the silicon oxide film 21 described with reference to FIGS. 2 to 10 are the same as those in the first embodiment, and thus description thereof will be omitted.

  First, the semiconductor substrate 1 shown in FIG. 10 described in the first embodiment is prepared, and as shown in FIGS. 36, 37, and 38, a silicon nitride film is formed on the silicon oxide film 21, the plug P1, and the wirings MD1, MD2. 23 are formed. The silicon nitride film 23 is formed between the wirings MD1 and MD2 serving as lower electrodes and an upper electrode 24 described later, and serves as a capacitance insulating film. FIG. 38 is a main-portion plan view of the substrate, illustrating the method for manufacturing the SRAM of the present embodiment. FIGS. 36 and 37 correspond to the AA cross section and the DD cross section in FIG. 38, respectively.

  Next, the silicon nitride film 23 on the wiring MD1 is removed, and an opening OP2 is formed.

  Next, as shown in FIGS. 39 and 40, a TiN film is deposited by sputtering on the silicon nitride film 23 including the inside of the opening OP2, and is patterned to form an upper portion extending above the wirings MD1 and MD2. An electrode 24 is formed. The upper electrode 24 is connected to the wiring MD1 via the opening OP2.

  Through the above steps, a capacitor C composed of the wiring MD2 serving as a lower electrode and the upper electrode 24 connected to the silicon nitride film 23 and the wiring MD1 can be formed. This capacitance C is a capacitance connected between the storage nodes AB in FIG.

  As described above, according to the present embodiment, since the capacitance C is formed by the wiring MD2 serving as the lower electrode and the upper electrode 24 connected to the silicon nitride film 23 and the wiring MD1, the capacitance C enters the SRAM memory cell. Soft errors due to α rays can be reduced. When a capacitor is formed between the storage nodes AB in FIG. 1 as in the present embodiment, the capacitor C is formed between the storage node A or B in FIG. 1 and the power supply potential (Vcc). As compared with the case, the critical charge amount (C) increases.

  FIG. 47 shows a simulation result of a critical charge amount at which data held in the storage node is inverted when a noise (current) pulse is applied to the storage node (A or B). The horizontal axis of the graph indicates the pulse width (s), and the vertical axis indicates the critical charge (C). As shown in FIG. 47, when the capacitance C is not formed (a), when the capacitance (2fF) is formed between the storage nodes AB (c), and when the storage node A (B) and the power supply potential (Vcc) Although the critical charge is increased in both cases where a capacitance (2fF) is formed between the storage node A and the power supply potential Vcc, the critical charge increases in both cases. When the capacitance is formed between the storage nodes AB, the critical charge amount is larger in the case (c). For example, when the pulse width is 20 nm, the capacitance in the case (b) is 2.4 fC larger than that in the case (a), whereas the capacitance in the case (c) is 3.5 fC larger than that in the case (a). , About 1.5 times as effective.

  Next, after a silicon oxide film is deposited on the upper electrode 24 by a CVD method, a first layer wiring M1 and a second layer wiring M2 are formed. These steps are performed with reference to FIGS. The description is omitted because it is similar to that of the first embodiment described above. As shown in FIG. 40, since upper electrode 24 does not extend over the sources of load MISFETs Qp1 and Qp2, plugs P1 and P2 on the sources of load MISFETs Qp1 and Qp2 are not connected to upper electrode 24. .

  In the case of the fourth embodiment (when the lower electrode 22 is not formed), similarly, after the silicon nitride film 23 on the wiring MD1 is removed and the opening OP2 is formed, the inside of the opening OP2 is also included. By forming the upper electrode 24 on the silicon nitride film 23, a capacitance can be formed between the storage nodes AB in FIG.

  The case of the second and third embodiments having the lower electrode 22 will be described below.

  First, the semiconductor substrate 1 shown in FIG. 8 described in the first embodiment is prepared, and as shown in FIGS. 41 and 42, a TiN film is formed on the silicon oxide film 21, the plug P1, and the wirings MD1 and MD2 by sputtering. Are deposited and patterned to form lower electrodes 22a and 22b on the wirings MD1 and MD2. The regions where the lower electrodes 22a and 22b are formed are larger than the regions where the wirings MD1 and MD2 are formed, respectively. FIG. 42 is a main-portion plan view of the substrate, illustrating the method for manufacturing the SRAM of the present embodiment. FIG. 41 corresponds to a section taken along line DD in FIG.

  Next, a silicon nitride film 23 is formed on the lower electrodes 22 a and 22 b and the silicon oxide film 21. The silicon nitride film 23 is formed between the lower electrodes 22a and 22b and an upper electrode 24 described later, and serves as a capacitance insulating film.

  Next, as shown in FIGS. 43 and 44, the silicon nitride film 23 on the wiring MD1 is removed to form an opening OP2.

  Next, as shown in FIGS. 45 and 46, a TiN film is deposited by sputtering on the silicon nitride film 23 including the inside of the opening OP2, and is patterned to form an upper portion extending over the wirings MD1 and MD2. An electrode 24 is formed. The upper electrode 24 is connected to the lower electrode 22a on the wiring MD1 via the opening OP2.

  Through the above steps, a capacitor C composed of the lower electrode 22b, the silicon nitride film 23, and the upper electrode 24 connected to the wiring MD1 can be formed. This capacitance C is a capacitance connected between the storage nodes AB in FIG.

  Similarly, in the case of the third embodiment, the silicon nitride film 23 on the lower electrode 22a among the lower electrodes 22a and 22b on the wirings MD1 and MD2 is removed to form an opening OP2. By forming the upper electrode 24 on the silicon nitride film 23 including the inside of OP2, a capacitance can be formed between the storage nodes AB in FIG. The same applies to the case where the lower electrode 22 of the fourth embodiment is formed.

  As described above, the invention made by the inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the gist of the invention. Needless to say.

  INDUSTRIAL APPLICABILITY As described above, the present invention is particularly effective when applied to a semiconductor integrated circuit device mounted on a mobile communication device such as a mobile phone, a memory card, an IC card, and the like, including a cache memory for a personal computer or a workstation. It is.

FIG. 2 is an equivalent circuit diagram showing a memory cell of the SRAM according to the first embodiment of the present invention; FIG. 3 is a cross-sectional view of a main part of the substrate, illustrating the method for manufacturing the SRAM according to the first embodiment of the present invention; FIG. 3 is a plan view of a main portion of the substrate, illustrating the method for manufacturing the SRAM according to the first embodiment of the present invention; FIG. 4 is a cross-sectional view of a principal part of the substrate, illustrating the method for manufacturing the SRAM according to the first embodiment of the present invention; FIG. 3 is a plan view of a main portion of the substrate, illustrating the method for manufacturing the SRAM according to the first embodiment of the present invention; FIG. 4 is a cross-sectional view of a principal part of the substrate, illustrating the method for manufacturing the SRAM according to the first embodiment of the present invention; FIG. 4 is a cross-sectional view of a principal part of the substrate, illustrating the method for manufacturing the SRAM according to the first embodiment of the present invention; FIG. 4 is a cross-sectional view of a principal part of the substrate, illustrating the method for manufacturing the SRAM according to the first embodiment of the present invention; FIG. 3 is a plan view of a main portion of the substrate, illustrating the method for manufacturing the SRAM according to the first embodiment of the present invention; FIG. 3 is a cross-sectional view of a main part of the substrate, illustrating the method for manufacturing the SRAM according to the first embodiment of the present invention; FIG. 3 is a cross-sectional view of a main part of the substrate, illustrating the method for manufacturing the SRAM according to the first embodiment of the present invention; FIG. 3 is a plan view of a main portion of the substrate, illustrating the method for manufacturing the SRAM according to the first embodiment of the present invention; FIG. 3 is a cross-sectional view of a main part of the substrate, illustrating the method for manufacturing the SRAM according to the first embodiment of the present invention; FIG. 3 is a plan view of a main portion of the substrate, illustrating the method for manufacturing the SRAM according to the first embodiment of the present invention; FIG. 3 is a cross-sectional view of a main part of the substrate, illustrating the method for manufacturing the SRAM according to the first embodiment of the present invention; FIG. 3 is a plan view of a main portion of the substrate, illustrating the method for manufacturing the SRAM according to the first embodiment of the present invention; FIG. 3 is a plan view of a main portion of the substrate, illustrating the method for manufacturing the SRAM according to the first embodiment of the present invention; It is a figure for explaining an effect of the present invention. FIG. 14 is a cross-sectional view of a main part of a substrate, illustrating a method of manufacturing an SRAM according to a second embodiment of the present invention; FIG. 13 is a plan view of a main portion of a substrate, illustrating a method of manufacturing an SRAM according to a second embodiment of the present invention; FIG. 14 is a cross-sectional view of a main part of a substrate, illustrating a method of manufacturing an SRAM according to a second embodiment of the present invention; FIG. 13 is a plan view of a main portion of a substrate, illustrating a method of manufacturing an SRAM according to a second embodiment of the present invention; FIG. 13 is a cross-sectional view of a main part of a substrate, illustrating a method of manufacturing an SRAM according to a third embodiment of the present invention; FIG. 13 is a cross-sectional view of a main part of a substrate, illustrating a method of manufacturing an SRAM according to a third embodiment of the present invention; FIG. 21 is a cross-sectional view of a principal part of a substrate, illustrating a method for manufacturing an SRAM according to a fourth embodiment of the present invention; FIG. 21 is a cross-sectional view of a principal part of a substrate, illustrating a method for manufacturing an SRAM according to a fourth embodiment of the present invention; FIG. 35 is a cross-sectional view of a principal part of a substrate, illustrating a method of manufacturing an SRAM according to a fifth embodiment of the present invention; FIG. 35 is a cross-sectional view of a principal part of a substrate, illustrating a method of manufacturing an SRAM according to a fifth embodiment of the present invention; FIG. 35 is a plan view of a principal part of a substrate, illustrating a method of manufacturing an SRAM according to a fifth embodiment of the present invention; FIG. 35 is a cross-sectional view of a principal part of a substrate, illustrating a method of manufacturing an SRAM according to a fifth embodiment of the present invention; FIG. 35 is a plan view of a principal part of a substrate, illustrating a method of manufacturing an SRAM according to a fifth embodiment of the present invention; FIG. 35 is a cross-sectional view of a principal part of a substrate, illustrating a method of manufacturing an SRAM according to a fifth embodiment of the present invention; FIG. 15 is a diagram showing an arrangement of a memory cell of an SRAM according to a sixth embodiment of the present invention; FIG. 15 is a diagram showing an arrangement of a memory cell array of an SRAM according to a sixth embodiment of the present invention; FIG. 39 is a plan view of a main portion of a substrate, illustrating a method of manufacturing an SRAM according to a sixth embodiment of the present invention; FIG. 39 is a cross-sectional view of a principal part of a substrate, illustrating a method of manufacturing an SRAM according to a seventh embodiment of the present invention; FIG. 39 is a cross-sectional view of a principal part of a substrate, illustrating a method of manufacturing an SRAM according to a seventh embodiment of the present invention; FIG. 39 is a plan view of a principal part of a substrate, illustrating a method of manufacturing an SRAM according to a seventh embodiment of the present invention; FIG. 39 is a cross-sectional view of a principal part of a substrate, illustrating a method of manufacturing an SRAM according to a seventh embodiment of the present invention; FIG. 39 is a plan view of a principal part of a substrate, illustrating a method of manufacturing an SRAM according to a seventh embodiment of the present invention; FIG. 39 is a cross-sectional view of a principal part of a substrate, illustrating a method of manufacturing an SRAM according to a seventh embodiment of the present invention; FIG. 39 is a plan view of a principal part of a substrate, illustrating a method of manufacturing an SRAM according to a seventh embodiment of the present invention; FIG. 39 is a cross-sectional view of a principal part of a substrate, illustrating a method of manufacturing an SRAM according to a seventh embodiment of the present invention; FIG. 39 is a plan view of a principal part of a substrate, illustrating a method of manufacturing an SRAM according to a seventh embodiment of the present invention; FIG. 39 is a cross-sectional view of a principal part of a substrate, illustrating a method of manufacturing an SRAM according to a seventh embodiment of the present invention; FIG. 39 is a plan view of a principal part of a substrate, illustrating a method of manufacturing an SRAM according to a seventh embodiment of the present invention; It is a figure for explaining an effect of the present invention. It is a figure for explaining a subject of the present invention.

Explanation of reference numerals

Reference Signs List 1 semiconductor substrate 2 element isolation 3 p-type well 4 n-type well 5 silicon oxide film 8 gate oxide film 9 polycrystalline silicon film 14 p ^- type semiconductor region 16 sidewall spacer 17 silicon nitride film 18 p ⁺ type semiconductor region 19 CoSi ₂ Layer 20 PSG film 21 Silicon oxide film 22 Lower electrode 22a Lower electrode 22b Lower electrode 23 Silicon nitride film 24 Upper electrode 25 Silicon oxide film 27 Silicon oxide film A Storage node B Storage node An1 Active area An2 Active area Ap1 Active area Ap2 Active area C capacitance C1 contact hole C2 contact hole C3 contact hole DL, / DL data line G gate electrode HM wiring trench INV1 CMOS inverter INV2 CMOS inverter M1 first layer wiring M2 second layer wiring MC memory cells MC11, MC 12 Memory cell MC21, MC22 Memory cell MD1 Wiring MD2 Wiring OP1 Opening OP2 Opening P1 Plug P2 Plug P3 Plug Qd1 Driving MISFET
Qd2 driving MISFET
Qp1 Load MISFET
Qp2 Load MISFET
Qt1 transfer MISFET
Qt2 transfer MISFET
WL Word line a Recess Vcc Power supply voltage Vss Reference voltage

Claims (15)

A semiconductor integrated circuit device having a memory cell including a pair of n-channel MISFETs in which respective gate electrodes and drains are cross-connected,
An interlayer insulating film formed on the n-channel MISFET;
A conductive layer that connects the gate electrode and the drain, the conductive layer being formed in a connection hole extending from the gate electrode to the drain, and having a recess on the surface thereof;
A capacitance insulating film formed on the conductive layer including the inside of the concave portion,
An upper electrode formed on the capacitive insulating film,
A semiconductor integrated circuit device comprising:   2. The semiconductor integrated circuit device according to claim 1, wherein a thickness of said capacitance insulating film is smaller than a depth of said recess.   2. The semiconductor integrated circuit according to claim 1, wherein the memory cell includes a pair of transfer n-channel MISFETs and a pair of load p-channel MISFETs in addition to the pair of n-channel MISFETs. apparatus.   2. The semiconductor integrated circuit device according to claim 1, wherein a power supply voltage is supplied to said upper electrode. A memory cell having a pair of inverters composed of a pair of driving MISFETs and a pair of load MISFETs, and a pair of transfer MISFETs, wherein a gate electrode and a drain of each of the pair of driving MISFETs are cross-connected. A semiconductor integrated circuit device having
An interlayer insulating film formed on the driving MISFET;
A first conductive layer that connects the gate electrode and the drain, the first conductive layer being formed in a connection hole extending from the gate electrode to the drain, and having a concave portion on a surface thereof;
A capacitance insulating film formed on the conductive layer including the inside of the concave portion,
An upper electrode formed on the capacitive insulating film,
A second conductive layer electrically connected to a source of the load MISFET, wherein the second conductive layer is connected to the upper electrode at a side wall thereof;
A semiconductor integrated circuit device comprising: A memory cell having a pair of inverters composed of a pair of driving MISFETs and a pair of load MISFETs, and a pair of transfer MISFETs, wherein a gate electrode and a drain of each of the pair of driving MISFETs are cross-connected. A semiconductor integrated circuit device having
An interlayer insulating film formed on the driving MISFET;
A first conductive layer that connects the gate electrode and the drain, the first conductive layer being formed in a connection hole extending from the gate electrode to the drain, and having a concave portion on a surface thereof;
A second conductive layer electrically connected to a source of the load MISFET;
A capacitor insulating film formed on the first conductive layer including the inside of the concave portion, the capacitor insulating film having an opening on the second conductive layer;
An upper electrode formed on the capacitor insulating film and the opening, wherein the second conductive layer is connected at a side wall thereof;
A third conductive layer formed on the upper electrode and electrically connected to the second conductive layer;
A semiconductor integrated circuit device comprising: A semiconductor integrated circuit device having a memory cell including a pair of n-channel MISFETs in which respective gate electrodes and drains are cross-connected,
An interlayer insulating film formed on the pair of n-channel MISFETs;
A pair of conductive layers cross-connecting each gate electrode and drain of the pair of n-channel MISFETs, each conductive layer being formed in a connection hole extending from the gate electrode to the drain; A conductive layer having a concave portion on the surface,
A capacitor insulating film formed on the conductive layer including the inside of the concave portion, the capacitor insulating film having an opening on the pair of conductive layers,
An upper electrode formed on the capacitive insulating film and the opening;
A semiconductor integrated circuit device comprising: In the semiconductor integrated circuit device, the memory cell may include a plurality of wirings connected to the cross-connecting section via another n-channel MISFET in a first extending direction and a second direction orthogonal to the first direction. Having an arranged memory cell array,
2. The semiconductor integrated circuit device according to claim 1, wherein the upper electrode is connected along the first direction, but is divided for each memory cell arranged in the second direction. A method of manufacturing a semiconductor integrated circuit device having a memory cell including a pair of n-channel MISFETs in which respective gate electrodes and drains are cross-connected,
Forming the n-channel MISFET;
Forming an interlayer insulating film on the n-channel MISFET;
Forming a connection hole extending from above the gate electrode to the drain of the n-channel MISFET;
Depositing a conductive film on the interlayer insulating film including the inside of the connection hole, and depositing a conductive film having a thickness smaller than a radius of the connection hole;
Forming a conductive layer embedded in the connection hole by polishing the conductive film until the surface of the interlayer insulating film is exposed, and having a concave portion on the upper portion thereof;
Forming a capacitive insulating film on the conductive layer,
Forming an upper electrode on the capacitive insulating film;
A method for manufacturing a semiconductor integrated circuit device, comprising:   10. The method according to claim 9, wherein the thickness of the capacitance insulating film is smaller than the depth of the recess. The memory cell includes, in addition to the pair of n-channel MISFETs, a pair of transfer n-channel MISFETs and a pair of p-channel load MISFETs,
10. The semiconductor integrated circuit device according to claim 9, wherein the conductive layer extends over a drain of one of the pair of p-channel load MISFETs. Production method. The method for manufacturing a semiconductor integrated circuit further includes:
Forming another interlayer insulating film on the upper electrode;
Forming another connection hole by selectively removing the other interlayer insulating film and the upper electrode;
A step of forming a plug by embedding a conductive material in the other connection hole;
10. The method for manufacturing a semiconductor integrated circuit device according to claim 9, comprising: The method for manufacturing a semiconductor integrated circuit,
After forming the capacitive insulating film and before forming the upper electrode, a step of forming an opening by selectively removing the capacitive insulating film;
Forming an upper electrode on the capacitive insulating film including the inside of the opening;
Forming another interlayer insulating film on the upper electrode;
Forming another connection hole by selectively removing the other interlayer insulating film;
A step of forming a plug by embedding a conductive material in the other connection hole;
10. The method for manufacturing a semiconductor integrated circuit device according to claim 9, comprising: A method of manufacturing a semiconductor integrated circuit device having a memory cell including a pair of n-channel MISFETs in which respective gate electrodes and drains are cross-connected,
Forming an interlayer insulating film on the pair of n-channel MISFETs;
A first connection hole extending from the gate electrode of one n-channel MISFET of the pair of n-channel MISFETs to the drain of the other n-channel MISFET; and from the gate electrode of the other n-channel MISFET. Forming a second connection hole extending to the drain of one of the n-channel MISFETs;
Depositing a conductive film having a thickness smaller than a radius of the connection hole on the interlayer insulating film including inside the first and second connection holes;
First and second conductive layers buried in the first and second connection holes by polishing the conductive film until the surface of the interlayer insulating film is exposed, and a concave portion on each of the first and second conductive layers; Forming first and second conductive layers having:
Forming a capacitive insulating film on each of the first and second conductive layers;
Forming an opening by selectively removing a capacitive insulating film on the first conductive layer;
Forming an upper electrode on the capacitive insulating film including the inside of the opening;
A method for manufacturing a semiconductor integrated circuit device, comprising: In the semiconductor integrated circuit device, a plurality of the memory cells are arranged in a first direction extending in a first direction and a second direction orthogonal to the wiring, the wiring being connected to the cross connection portion via another n-channel MISFET. Having a memory cell array,
10. The semiconductor integrated circuit device according to claim 9, wherein the upper electrode is connected along the first direction, but is divided for each memory cell arranged in the second direction. Production method.

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