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JP2004253821A - Hybrid integrated circuit device - Google Patents

Hybrid integrated circuit device Download PDF

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Publication number
JP2004253821A
JP2004253821A JP2004170999A JP2004170999A JP2004253821A JP 2004253821 A JP2004253821 A JP 2004253821A JP 2004170999 A JP2004170999 A JP 2004170999A JP 2004170999 A JP2004170999 A JP 2004170999A JP 2004253821 A JP2004253821 A JP 2004253821A
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Prior art keywords
wiring board
multilayer wiring
wiring
multilayer
interconnection board
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Inventor
Masahito Numanami
雅仁 沼波
Katsuji Tsuchiya
勝治 土屋
Tsuneo Endo
恒雄 遠藤
Yasuhiro Nunokawa
康弘 布川
Iwamichi Kamishiro
岩道 神代
Tetsuaki Adachi
徹朗 安達
Kazuo Sudo
一雄 須藤
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Renesas Technology Corp
Renesas Eastern Japan Semiconductor Inc
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Renesas Technology Corp
Renesas Eastern Japan Semiconductor Inc
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Application filed by Renesas Technology Corp, Renesas Eastern Japan Semiconductor Inc filed Critical Renesas Technology Corp
Priority to JP2004170999A priority Critical patent/JP2004253821A/en
Publication of JP2004253821A publication Critical patent/JP2004253821A/en
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4911Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49175Parallel arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19105Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3011Impedance
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L2924/301Electrical effects
    • H01L2924/3025Electromagnetic shielding

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  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a small-size radiofrequency power module which can reduce a packaging area. <P>SOLUTION: Hybrid integrated circuit device has a cryogenic calcination multilayer interconnection board, at least one or more active components(FET chip) and passive components which are loaded on major faces of the multilayer interconnection board, a conductive wire for connecting an electrode of the active components with a wiring(Ag-Pt) of the multilayer interconnection board, a cap fixed to the multilayer interconnection board so as to cover the major faces of the multilayer interconnection board, and plural multilayer-interconnected electrode terminals which are mounted on a rear face of the multilayer interconnection board. A lower part of the multilayer interconnection board has a strip line structure, and an upper part of the multilayer interconnection board has a microstrip line structure. A ground wiring has a network structure. A semiconductor chip is fixed to a hollow provided on the major faces of the multilayer interconnection board, and the height of the electrode surface of the semiconductor chip is set to be almost the same as the height of the wiring surface of the multilayer interconnection board. A thermal via is provided under the semiconductor chip. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

本発明は低温焼成多層配線基板を用いた混成集積回路装置に関し、特にセルラー電話機等の送信部に用いる小型の高周波電力増幅装置(高周波パワーモジュール:RFパワーモジュール)に適用して有効な技術に関する。   The present invention relates to a hybrid integrated circuit device using a low-temperature fired multilayer wiring board, and more particularly to a technique which is effective when applied to a small high-frequency power amplifier (high-frequency power module: RF power module) used for a transmission unit of a cellular telephone or the like.

自動車電話,携帯電話等の移動通信機器無線部に使用されるRFパワーモジュールは、金属製のフランジとキャップとによってパッケージが形成されている。また、前記パッケージの一側面から信号端子等の電極端子を突出させるとともに、パッケージの両端下部からグランド電極を兼ねた取付用フィンを突出させる構造となっている。   2. Description of the Related Art An RF power module used in a wireless communication section of a mobile communication device such as a mobile phone or a mobile phone has a package formed by a metal flange and a cap. In addition, electrode terminals such as signal terminals protrude from one side surface of the package, and mounting fins also serving as ground electrodes protrude from lower portions of both ends of the package.

また、前記パッケージ内において、前記フランジ上には両面に導体を有する配線基板が固定されている。この配線基板は、誘電体基板の表面に回路パターンを設け、裏面にグランド(GND)パターンを設けた所謂マイクロストリップライン構造となっている。また、前記配線基板は、部分的に穴が設けられている。そして、前記穴底のフランジ部分には熱伝導性の良好なヒートシンクが固定されている。前記ヒートシンクには電界効果トランジスタからなる半導体チップが固定されている。   In the package, a wiring board having conductors on both sides is fixed on the flange. This wiring board has a so-called microstrip line structure in which a circuit pattern is provided on the front surface of a dielectric substrate and a ground (GND) pattern is provided on the back surface. The wiring board is partially provided with a hole. A heat sink having good thermal conductivity is fixed to the flange at the bottom of the hole. A semiconductor chip made of a field effect transistor is fixed to the heat sink.

高周波パワーモジュール(高周波電力増幅用MOS・パワーモジュール)の寸法の一例を挙げると、E型と呼称される高周波パワーモジュールは、幅22mm,奥行き12mm,高さ3.7mmとなっている(例えば、非特許文献1)。   As an example of the dimensions of a high-frequency power module (MOS / power module for high-frequency power amplification), a high-frequency power module called an E type has a width of 22 mm, a depth of 12 mm, and a height of 3.7 mm (for example, Non-patent document 1).

日立評論社発行「日立評論」1993年第4号、同年4月25日発行、P12〜P26"Hitachi Review" Issued by Hitachi Hyoronsha, No. 4, 1993, April 25, pp. 12-26

従来の高周波パワーモジュールは、大別すると、金属製のフランジ(ヘッダ)と、このフランジ上に固定される配線基板と、前記配線基板に設けた穴を利用しかつ前記フランジに固定したヒートシンク上に固定される半導体チップと、前記フランジに固定され前記配線基板を覆うキャップと、前記配線基板に固定され先端を前記キャップの外に突出させる電極端子(リード)とからなっている。また、前記フランジの両端は部分的にキャップの外側に突出してグランド電極を兼ねた取付用フィンを構成している。   Conventional high-frequency power modules are roughly classified into a metal flange (header), a wiring board fixed on the flange, and a heat sink fixed to the flange using holes provided in the wiring board. It comprises a semiconductor chip to be fixed, a cap fixed to the flange to cover the wiring board, and an electrode terminal (lead) fixed to the wiring board and having a tip protruding out of the cap. Both ends of the flange partially protrude outside the cap to form mounting fins that also serve as ground electrodes.

なお、前記配線基板の表面にはコンデンサ,抵抗,ツェナーダイオード等の電子部品が搭載されている。また、配線基板の表面の配線と前記半導体チップの電極とは導電性のワイヤで接続されている。   Electronic components such as capacitors, resistors and zener diodes are mounted on the surface of the wiring board. Further, the wiring on the surface of the wiring board and the electrode of the semiconductor chip are connected by a conductive wire.

従来の高周波パワーモジュールの小型化,高性能化,低コスト化等を検討した結果、以下の事項が小型化,高機能化,低コスト化等を妨げるということが判明した。   As a result of studying the miniaturization, high performance, and low cost of the conventional high-frequency power module, it was found that the following matters hindered miniaturization, high functionality, low cost, and the like.

(1)配線基板は、誘電体基板の表面に信号配線や電源配線等の回路パターンを設け、裏面にグランド(GND)パターンを設けたマイクロストリップライン構造となっている。これは、配線基板の作製後、抵抗をトリミングしたり、線路幅の調整を行って特性の調整を行うためである。しかし、誘電体基板の一面に信号配線を形成するマイクロストリップライン構造では、所望の電気特性を得るために、信号配線の引き回し長さが長いことから、配線基板が大型化し、この配線基板を内蔵するパッケージが大きくなり、高周波パワーモジュールの小型化が妨げられている。   (1) The wiring board has a microstrip line structure in which circuit patterns such as signal wiring and power supply wiring are provided on the front surface of a dielectric substrate, and a ground (GND) pattern is provided on the back surface. This is for adjusting the characteristics by trimming the resistance or adjusting the line width after the wiring board is manufactured. However, in the microstrip line structure in which the signal wiring is formed on one surface of the dielectric substrate, the wiring length of the signal wiring is long in order to obtain desired electrical characteristics. This increases the size of the package, which hinders miniaturization of the high-frequency power module.

(2)フランジ上に配線基板を固定し、さらにキャップで覆う構造となるため、パッケージの高さが大きくなり、高周波パワーモジュールの小型化が妨げられている。   (2) Since the wiring board is fixed on the flange and further covered with the cap, the height of the package is increased, and miniaturization of the high-frequency power module is hindered.

(3)フランジの両端の一部は、キャップの外側に突出してグランド電極を兼ねた取付用フィンを構成することから高周波パワーモジュールが大型化する。したがって、実装面積も大きくなる。   (3) Since a part of both ends of the flange protrudes outside the cap to form a mounting fin that also serves as a ground electrode, the size of the high-frequency power module increases. Therefore, the mounting area also increases.

(4)パッケージ(キャップ)の一側面から長くリードを突出させることから高周波パワーモジュールが大型化する。したがって、実装面積も大きくなる。   (4) Since the leads protrude long from one side of the package (cap), the high-frequency power module becomes large. Therefore, the mounting area also increases.

(5)半導体チップの表面と、配線基板の配線面の高さが異なるため、半導体チップの電極と配線を接続するワイヤが長くなる。また、半導体チップは、配線基板に設けた穴の底部分のフランジに固定されたヒートシンク上に固定されるため、半導体チップの電極と配線との間隔が長くなり、ワイヤが長くなる。ワイヤが長くなると抵抗が増大し高周波特性が低くなる。例えば出力ゲインが小さくなる。   (5) Since the height of the surface of the semiconductor chip is different from the height of the wiring surface of the wiring board, the wire connecting the electrode of the semiconductor chip and the wiring becomes longer. Further, since the semiconductor chip is fixed on the heat sink fixed to the flange at the bottom of the hole provided in the wiring board, the distance between the electrode of the semiconductor chip and the wiring becomes longer, and the wire becomes longer. The longer the wire, the higher the resistance and the lower the high frequency characteristics. For example, the output gain decreases.

(6)配線基板は誘電体基板で形成されているため、発熱量の大きい半導体チップを直接配線基板に搭載することができないため、配線基板に穴を設け、この穴底の金属製のフランジ部分に熱伝導性の良好なヒートシンクを固定し、このヒートシンクに半導体チップを固定する構造となるため、部品点数の増大と、組立工数の増大から高周波パワーモジュールのコストの高騰を招いている。   (6) Since the wiring substrate is formed of a dielectric substrate, it is not possible to directly mount a semiconductor chip generating a large amount of heat on the wiring substrate. Therefore, a hole is formed in the wiring substrate, and a metal flange at the bottom of the hole is provided. Since a heat sink having good heat conductivity is fixed to the heat sink and the semiconductor chip is fixed to the heat sink, the cost of the high-frequency power module is increased due to an increase in the number of components and an increase in the number of assembly steps.

(7)支持部材,放熱部材,グランド電極を兼ねるフランジを配線基板に固定する構造となっていることから、部品点数が増大する。   (7) Since the support member, the heat radiation member, and the flange serving also as the ground electrode are fixed to the wiring board, the number of components is increased.

(8)高周波パワーモジュールの実装のため、フランジの一部を成形して取付用フィンを形成しているが、成形のため各取付用フィンの実装面高さがばらつきやすくなり、実装の信頼性を損なうこともある。   (8) For mounting the high-frequency power module, a part of the flange is formed to form the mounting fins. However, the mounting surface height of each mounting fin tends to vary due to the forming, and the reliability of mounting is increased. May be impaired.

本発明の目的は、実装面積の縮小化が図れる小型の混成集積回路装置を提供することにある。
本発明の他の目的は、高性能な混成集積回路装置を提供することにある。
本発明の他の目的は、製造コストの低減が達成できる混成集積回路装置を提供することにある。
本発明の前記ならびにそのほかの目的と新規な特徴は、本明細書の記述および添付図面からあきらかになるであろう。
An object of the present invention is to provide a small-sized hybrid integrated circuit device capable of reducing a mounting area.
It is another object of the present invention to provide a high-performance hybrid integrated circuit device.
Another object of the present invention is to provide a hybrid integrated circuit device that can achieve a reduction in manufacturing cost.
The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

本願において開示される発明のうち代表的なものの概要を簡単に説明すれば、下記のとおりである。   The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows.

(1)混成集積回路装置は以下の構造となっている。
(a)多層配線基板と、前記多層配線基板の主面に搭載される少なくとも一つ以上の能動部品および受動部品と、前記能動部品の電極と前記多層配線基板の配線とを接続する導電性のワイヤと、前記多層配線基板の主面を覆うように多層配線基板に固定されるキャップと、前記多層配線基板の裏面に設けられた前記多層配線の複数の電極端子とを有する。
(1) The hybrid integrated circuit device has the following structure.
(A) a multilayer wiring board, at least one or more active components and passive components mounted on a main surface of the multilayer wiring board, and a conductive property for connecting an electrode of the active component and a wiring of the multilayer wiring board. The multilayer wiring board includes a wire, a cap fixed to the multilayer wiring board so as to cover a main surface of the multilayer wiring board, and a plurality of electrode terminals of the multilayer wiring provided on a back surface of the multilayer wiring board.

(b)前記多層配線基板には電界効果トランジスタを構成する半導体チップが多段に接続配置されて高周波パワーモジュールを構成している。   (B) On the multilayer wiring board, semiconductor chips constituting field effect transistors are connected and arranged in multiple stages to constitute a high-frequency power module.

(c)前記多層配線基板は配線を介在させて誘電体層を多段に積み重ねた構造となるとともに、前記誘電体層間に設けられた信号配線はその上下を誘電体層を介してグランド配線で挟まれるストリップライン構造となっている。また、多層配線基板の上部分はマイクロストリップライン構造となっている。   (C) The multilayer wiring board has a structure in which dielectric layers are stacked in multiple stages with wirings interposed therebetween, and the signal wiring provided between the dielectric layers is sandwiched above and below the ground wiring via the dielectric layer. Strip line structure. The upper part of the multilayer wiring board has a microstrip line structure.

(d)前記グランド配線は編み目構造となっている。   (D) The ground wiring has a stitch structure.

(e)前記能動部品において半導体チップは前記多層配線基板の主面に設けられた窪みに固定され、前記半導体チップの電極面と前記多層配線基板の配線面の高さは略同一高さとなり、前記半導体チップの電極と前記配線を接続する前記ワイヤは略直線状に延在している。   (E) In the active component, a semiconductor chip is fixed to a depression provided on a main surface of the multilayer wiring board, and an electrode surface of the semiconductor chip and a wiring surface of the multilayer wiring board have substantially the same height; The wire connecting the electrode of the semiconductor chip and the wiring extends substantially linearly.

(f)前記多層配線基板の所望部分には、所望の誘電体層から最下層の誘電体層まで貫通延在するサーマルビィアが設けられている。   (F) A thermal via is provided at a desired portion of the multilayer wiring board so as to extend from a desired dielectric layer to a lowermost dielectric layer.

(g)前記サーマルビィアの上には半導体チップが位置している。   (G) A semiconductor chip is located on the thermal via.

(h)前記多層配線基板の裏面の電極端子において、グランド電極端子はその表面が実装用接合材に濡れないレジスト膜で部分的に覆われて相互に独立した複数の電極端子となっている。   (H) Among the electrode terminals on the rear surface of the multilayer wiring board, the ground electrode terminals are partially covered with a resist film which does not wet the bonding material for mounting, and are a plurality of electrode terminals independent of each other.

(i)前記多層配線基板の裏面の電極端子の配列間隔は同一ピッチとなっている。   (I) The arrangement intervals of the electrode terminals on the back surface of the multilayer wiring board are the same.

(j)前記多層配線基板の裏面の電極端子のうち、少なくともグランド電極以外の電極端子は多層配線基板の側面の上下に延在する端面スルーホール端子を介して各層の配線に接続されている。   (J) Among the electrode terminals on the back surface of the multilayer wiring board, at least the electrode terminals other than the ground electrode are connected to the wiring of each layer via end face through-hole terminals extending vertically on the side surface of the multilayer wiring board.

(k)前記多層配線基板は低温焼成多層セラミック基板となり、配線は銀系金属からなる高導電性金属で形成されている。   (K) The multilayer wiring substrate is a low-temperature fired multilayer ceramic substrate, and the wiring is formed of a highly conductive metal made of a silver-based metal.

(2)前記手段(1)の構成において、前記キャップは多層配線基板に設けた窪みにフックを介して着脱自在に取り付けられている。   (2) In the configuration of the means (1), the cap is removably attached to a recess provided in the multilayer wiring board via a hook.

本願において開示される発明のうち代表的なものによって得られる効果を簡単に説明すれば、下記のとおりである。
前記(1)の手段によれば、(a)高周波パワーモジュールは、電界効果トランジスタ等の能動部品や受動部品を主面に搭載した多層配線基板と、この多層配線基板の主面側に固定されたキャップとによって形成された矩形体構造となっていることから、従来のようにパッケージからリードを突出させたり、取付用フィンを突出させないため小型となる。
The effects obtained by the typical inventions among the inventions disclosed in the present application will be briefly described as follows.
According to the means (1), (a) the high-frequency power module is a multilayer wiring board having active components and passive components such as a field effect transistor mounted on a main surface thereof, and is fixed to the main surface side of the multilayer wiring substrate. Since the rectangular structure is formed by the cap and the cap, the lead is not protruded from the package and the mounting fin is not protruded as in the related art, so that the size is reduced.

(b)前記多層配線基板はストリップライン構造にマイクロストリップライン構造を積み重ねた構造となるため、伝送線路(信号配線等)の長さを長くとっても、伝送線路は2段に設けられるため、多層配線基板の大きさは小さくでき、高周波パワーモジュールの小型化が達成できる。   (B) Since the multilayer wiring board has a structure in which a microstrip line structure is stacked on a strip line structure, even if the length of a transmission line (such as a signal wiring) is long, the transmission lines are provided in two stages. The size of the substrate can be reduced, and downsizing of the high-frequency power module can be achieved.

(c)誘電体層間に設けられた信号配線はその上下を誘電体層を介してグランド配線で挟まれる構造となることから、電気・電磁的シールドがなされ、高周波特性が安定する。   (C) Since the signal wiring provided between the dielectric layers has a structure in which the signal wiring is sandwiched above and below by the ground wiring via the dielectric layer, an electric / electromagnetic shield is provided and the high-frequency characteristics are stabilized.

(d)前記グランド配線は編み目構造となっていることから、編み目部分には誘電体層が入り込み、グランド配線の上下の誘電体層の接合強度が高くなり、剥がれ難い多層配線基板となる。したがって、耐湿性に優れた高周波パワーモジュールとなる。   (D) Since the ground wiring has a stitch structure, a dielectric layer enters the stitch portion, the bonding strength between the dielectric layers above and below the ground wiring is increased, and a multilayer wiring board that is difficult to peel off is obtained. Therefore, a high-frequency power module having excellent moisture resistance is obtained.

(e)前記能動部品において半導体チップは前記多層配線基板の主面に設けられた窪みに固定され、前記半導体チップの電極面と前記多層配線基板の配線面の高さは略同一高さとなり、前記半導体チップの電極と前記配線を接続する前記ワイヤは略直線状に延在している。したがって、ワイヤが短くなり、抵抗が軽減されて高周波特性が良好となる。例えば出力ゲインが大きくなる。   (E) In the active component, a semiconductor chip is fixed to a depression provided on a main surface of the multilayer wiring board, and an electrode surface of the semiconductor chip and a wiring surface of the multilayer wiring board have substantially the same height; The wire connecting the electrode of the semiconductor chip and the wiring extends substantially linearly. Therefore, the wire is shortened, the resistance is reduced, and the high-frequency characteristics are improved. For example, the output gain increases.

(f)前記多層配線基板の所望部分には、所望の誘電体層から最下層の誘電体層まで貫通延在するサーマルビィアが設けられている。したがって、熱放散性が高くなり、安定した電気特性が得られる。   (F) A thermal via is provided at a desired portion of the multilayer wiring board so as to extend from a desired dielectric layer to a lowermost dielectric layer. Therefore, heat dissipation is enhanced, and stable electric characteristics can be obtained.

(g)前記サーマルビィアの上には半導体チップが位置している。したがって、半導体チップで発熱した熱は速やかに外部に放散され、電界効果トランジスタが安定動作する。   (G) A semiconductor chip is located on the thermal via. Therefore, the heat generated by the semiconductor chip is quickly dissipated to the outside, and the field effect transistor operates stably.

(h)前記多層配線基板の裏面の電極端子において、グランド電極端子はその表面が実装用接合材に濡れないレジスト膜で部分的に覆われて相互に独立した複数の電極端子となっている。したがって、各電極端子に均一に実装用接合材が濡れるため、各電極端子は確実に実装用接合材を介して実装基板に固定される。   (H) Among the electrode terminals on the rear surface of the multilayer wiring board, the ground electrode terminals are partially covered with a resist film which does not wet the bonding material for mounting, and are a plurality of electrode terminals independent of each other. Accordingly, since the bonding material for mounting is uniformly wetted on each electrode terminal, each electrode terminal is securely fixed to the mounting board via the bonding material for mounting.

(i)前記多層配線基板の裏面の電極端子の配列間隔は同一ピッチとなっている。したがって、各電極端子は実装用接合材の片寄りもなく実装用接合材のブリッジ等の不良も発生しなくなる。また、実装のセルフアライン化も可能となる。   (I) The arrangement intervals of the electrode terminals on the back surface of the multilayer wiring board are the same. Therefore, each electrode terminal does not have a bias of the bonding material for mounting, and does not generate a defect such as a bridge of the bonding material for mounting. In addition, self-alignment of mounting becomes possible.

(j)前記多層配線基板の裏面の電極端子のうち、少なくともグランド電極以外の電極端子は多層配線基板の側面の上下に延在する端面スルーホール端子を介して各層の配線に接続されている。すなわち、高周波パワーモジュールはLCC(リードレス・チップ・キャリア)構造となり、小型化が達成できる。   (J) Among the electrode terminals on the back surface of the multilayer wiring board, at least the electrode terminals other than the ground electrode are connected to the wiring of each layer via end face through-hole terminals extending vertically on the side surface of the multilayer wiring board. That is, the high-frequency power module has an LCC (leadless chip carrier) structure, and can be reduced in size.

(k)前記多層配線基板は低温焼成多層セラミック基板となることから、配線は融点の低い銀系金属(Ag−Pt)からなる高導電性金属で形成できるため、抵抗の低減から高周波特性が良好となる。すなわち、出力ゲインの向上を図ることができる。   (K) Since the multilayer wiring board is a multilayer ceramic substrate fired at a low temperature, the wiring can be formed of a highly conductive metal made of a silver-based metal (Ag-Pt) having a low melting point, so that high-frequency characteristics are good due to reduction in resistance. It becomes. That is, the output gain can be improved.

前記(2)の手段によれば、キャップは多層配線基板に設けた窪みにフックを介して着脱自在に取り付けられていることから、多層配線基板へのキャップの着脱が容易である。 前記(1)及び(2)から、高周波パワーモジュールは、LCC構造となるため小型となる。また、配線基板は多層配線基板となるため、信号配線は各段に形成できるため所定の長さを得ることができ、配線基板の大きさも小さくでき、パッケージの大きさを小さくできる。これらによって高周波パワーモジュールの小型化,実装面積の縮小化が達成できる。   According to the means (2), since the cap is detachably attached to the recess provided in the multilayer wiring board via the hook, the cap can be easily attached to and detached from the multilayer wiring board. From the above (1) and (2), the high-frequency power module has a small size because it has an LCC structure. Further, since the wiring board is a multilayer wiring board, the signal wiring can be formed in each stage, so that a predetermined length can be obtained, the size of the wiring board can be reduced, and the size of the package can be reduced. With these, the miniaturization and mounting area of the high-frequency power module can be reduced.

前記(1)及び(2)から、高周波パワーモジュールは低温焼成多層配線基板を使用するため、高導電性金属で配線を形成できること、内層の信号配線はストリップライン構造となることから電気・電磁的にシールドされること、半導体チップで発生した熱はサーマルビィアによって速やかにパッケージ外に放熱されること等によって高周波特性の向上が達成できる。   From the above (1) and (2), since the high-frequency power module uses the low-temperature fired multilayer wiring board, the wiring can be formed by a highly conductive metal, and the signal wiring in the inner layer has a stripline structure, so that the electric / electromagnetic is obtained. In addition, the heat generated in the semiconductor chip is quickly radiated out of the package by the thermal via, thereby improving the high frequency characteristics.

前記(1)及び(2)から、多層配線基板の裏面に電極端子を設けるとともに、多層配線基板をキャップで覆うことによって高周波パワーモジュールを形成していることから、部品点数が少なくなり、組立工数の低減,材料費の低減から製造コストの低減が達成できる。   From the above (1) and (2), since the high frequency power module is formed by providing the electrode terminals on the back surface of the multilayer wiring board and covering the multilayer wiring board with the cap, the number of parts is reduced and the number of assembly steps is reduced. It is possible to achieve a reduction in manufacturing costs due to a reduction in cost and material costs.

以下、図面を参照して本発明の実施の形態を詳細に説明する。なお、発明の実施の形態を説明するための全図において、同一機能を有するものは同一符号を付け、その繰り返しの説明は省略する。   Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for describing the embodiments of the present invention, components having the same functions are denoted by the same reference numerals, and their repeated description will be omitted.

図1乃至図9は本発明の一実施例(実施例1)である高周波パワーモジュールに係わる図であり、図1は高周波パワーモジュールの外観を示す斜視図、図2は高周波パワーモジュールの断面図、図3はキャップを取り外した高周波パワーモジュールを示す平面図、図4は高周波パワーモジュールを構成する多層配線基板の構造を示す一部の斜視図、図5は前記多層配線基板の表面、すなわち上段誘電体層の露出面に形成される配線パターン(第1層配線)を示す平面図、図6は前記多層配線基板の上段誘電体層と中段誘電体層との間に形成される配線パターン(第2層配線)を示す平面図、図7は前記多層配線基板の中段誘電体層と下段誘電体層との間に形成される配線パターン(第3層配線)を示す平面図、図8は前記多層配線基板の裏面、すなわち下段誘電体層の露出面に形成される配線パターン(第4層配線)を示す底面図、図9は前記多層配線基板におけるグランド配線となる第2層配線および第4層配線の一部を示す平面図である。   1 to 9 are views relating to a high-frequency power module according to an embodiment (Example 1) of the present invention. FIG. 1 is a perspective view showing the appearance of the high-frequency power module, and FIG. 2 is a cross-sectional view of the high-frequency power module. , FIG. 3 is a plan view showing the high-frequency power module with the cap removed, FIG. 4 is a partial perspective view showing the structure of the multilayer wiring board constituting the high-frequency power module, and FIG. FIG. 6 is a plan view showing a wiring pattern (first-layer wiring) formed on the exposed surface of the dielectric layer. FIG. 6 is a plan view showing a wiring pattern (first-layer wiring) formed between the upper dielectric layer and the middle dielectric layer of the multilayer wiring board. FIG. 7 is a plan view showing a second-layer wiring, FIG. 7 is a plan view showing a wiring pattern (third-layer wiring) formed between a middle dielectric layer and a lower dielectric layer of the multilayer wiring board, and FIG. Back side of the multilayer wiring board That is, a bottom view showing a wiring pattern (fourth layer wiring) formed on the exposed surface of the lower dielectric layer. FIG. 9 shows a part of the second layer wiring and a part of the fourth layer wiring serving as ground wiring in the multilayer wiring board. FIG.

本実施例1の混成集積回路装置(高周波パワーモジュール)1は、図1に示すように、板状の多層配線基板2と、この多層配線基板2の主面(上面)に被せるように半田3(例えば、Pb/Sn=95/5の高温半田)を介して固定されたキャップ4とからなり、外観的には、偏平な矩形体となっている。高周波パワーモジュール1は、例えば、幅8mm,長さ12.3mm,高さ2.5mmとなり、従来のE型の高周波パワーモジュールの幅22mm,奥行き12mm,高さ3.7mmに比較して大幅に小型となる。   As shown in FIG. 1, a hybrid integrated circuit device (high-frequency power module) 1 according to the first embodiment includes a plate-shaped multilayer wiring board 2 and solder 3 so as to cover the main surface (upper surface) of the multilayer wiring board 2. (For example, a high-temperature solder of Pb / Sn = 95/5), and the cap 4 is fixed through the cap 4, and has a flat rectangular shape in appearance. The high-frequency power module 1 has, for example, a width of 8 mm, a length of 12.3 mm, and a height of 2.5 mm, which is significantly larger than the conventional E-type high-frequency power module having a width of 22 mm, a depth of 12 mm, and a height of 3.7 mm. It becomes small.

また、図8の多層配線基板2の底面図に示すように、前記多層配線基板2の裏面には、複数の電極端子(外部端子)5が設けられている。電極端子5は多層配線基板2の両側にそれぞれ設けられ、多層配線基板2の長手方向に沿って一定ピッチで並び、一側(図中上側)では左から右に向かって入力端子(Pin)6,グランド端子(GND)7,グランド端子(GND)8,ゲインコントロール端子(Vapc)9となる。また、他側(図中下側)では左から右に向かって出力端子(Pout)10,グランド端子(GND)11,グランド端子(GND)12,電源端子(Vdd)13となる。 Further, as shown in the bottom view of the multilayer wiring board 2 in FIG. 8, a plurality of electrode terminals (external terminals) 5 are provided on the back surface of the multilayer wiring board 2. The electrode terminals 5 are provided on both sides of the multilayer wiring board 2, respectively, and are arranged at a constant pitch along the longitudinal direction of the multilayer wiring board 2. On one side (upper side in the figure), input terminals (P in ) are from left to right. 6, a ground terminal (GND) 7, a ground terminal (GND) 8, and a gain control terminal (V apc ) 9. On the other side (lower side in the figure), an output terminal (P out ) 10, a ground terminal (GND) 11, a ground terminal (GND) 12, and a power supply terminal (V dd ) 13 are arranged from left to right.

前記入力端子6,ゲインコントロール端子9,出力端子10,電源端子13に対応する多層配線基板2の側面には、多層配線基板2の表面から裏面に至る部分に端面スルーホールが設けられている。これは、高周波パワーモジュール1を実装基板に実装する際、各電極端子が多層配線基板2の裏面の電極部分と側面の端面スルーホール20部分で接続されて実装されることになり、確実な実装が行える。   On the side surface of the multilayer wiring board 2 corresponding to the input terminal 6, the gain control terminal 9, the output terminal 10, and the power supply terminal 13, an end face through hole is provided in a portion from the front surface to the back surface of the multilayer wiring substrate 2. That is, when the high-frequency power module 1 is mounted on the mounting board, each electrode terminal is connected and mounted at the electrode portion on the back surface of the multilayer wiring board 2 and the through-hole 20 on the side surface of the multilayer wiring board 2, thereby ensuring reliable mounting. Can be performed.

以上のことから、本実施例1の高周波パワーモジュール1は、混成集積回路装置ではあるが、単体の半導体チップをパッケージ内に組み込んだLCC構造となり、製品の小型化が達成できる。   As described above, although the high-frequency power module 1 of the first embodiment is a hybrid integrated circuit device, it has an LCC structure in which a single semiconductor chip is incorporated in a package, and the product can be downsized.

一方、図8において4つのグランド端子(GND)7,8,11,12を区画するように延在するハッチング部分は、高周波パワーモジュール1を実装基板に実装する際使用される実装用接合材に濡れない材料で形成されたレジスト膜14である。例えば、高周波パワーモジュール1は半田によって実装基板に実装されることから、前記レジスト膜14は厚さ20μm前後のソルダーレジスト膜となる。   On the other hand, in FIG. 8, the hatched portions extending so as to partition the four ground terminals (GND) 7, 8, 11, and 12 are used as mounting bonding materials used when mounting the high-frequency power module 1 on a mounting board. The resist film 14 is formed of a non-wetting material. For example, since the high-frequency power module 1 is mounted on a mounting board by soldering, the resist film 14 is a solder resist film having a thickness of about 20 μm.

前記レジスト膜14はグランド配線を覆うように設けられている。したがって、多層配線基板2の裏面には、前記4つのグランド端子(GND)7,8,11,12が延在する領域と、レジスト膜14とによって覆われる領域に亘って一体となるグランド(GND)配線15が延在することになる。これは、後述するが、信号配線および電源配線等を上下で誘電体層を介してグランド配線で挟む所謂ストリップライン構造とし、電気・電磁的なシールドを行うためである。   The resist film 14 is provided so as to cover the ground wiring. Therefore, on the back surface of the multilayer wiring board 2, a ground (GND) integrated over a region where the four ground terminals (GND) 7, 8, 11, 12 extend and a region covered with the resist film 14. ) The wiring 15 extends. This is because, as will be described later, a so-called strip line structure in which signal wiring, power supply wiring, and the like are sandwiched between ground wirings via dielectric layers on the upper and lower sides to provide electric and electromagnetic shielding.

また、前記一体のグランド配線15をレジスト膜14で部分的に覆い、独立した複数のグランド端子7,8,11,12とすることは、各電極端子の面積差を余り大きくしないことにある。すなわち、高周波パワーモジュール1を半田実装した場合、各電極端子の面積差が極端に大きいと、半田の表面張力によって広い面積部分での高周波パワーモジュール1の浮き上がり高さが大きくなり、四方に設けられた小面積部分では、一部で接合不良が発生するおそれがある。そこで、本実施例1では、各電極端子の面積比率は最大でも2倍程度としてある。   The reason why the integral ground wiring 15 is partially covered with the resist film 14 to form a plurality of independent ground terminals 7, 8, 11, and 12 is that the area difference between the electrode terminals is not so large. That is, when the high-frequency power module 1 is mounted by soldering, if the area difference between the electrode terminals is extremely large, the floating height of the high-frequency power module 1 in a wide area is increased due to the surface tension of the solder, and the electrode terminals are provided on all sides. In the small area portion, there is a possibility that a joining failure occurs in a part. Therefore, in the first embodiment, the area ratio of each electrode terminal is set to about twice at the maximum.

また、一列に並ぶ電極端子において各電極端子を等しいピッチで配列することによって、セルフアライメントを促進する。また、半田ブリッジ等の実装不良も防止できる。   In addition, self-alignment is promoted by arranging the electrode terminals at an equal pitch in the electrode terminals arranged in a line. Further, it is possible to prevent a mounting failure such as a solder bridge.

また、図8において示す小丸は、高周波パワーモジュール1内で発生した熱を外部に伝達するサーマルビィア16であり、同図では一部のみを示してある。サーマルビィア16は、サーマルビィアホールに熱伝導性の良好な金属を充填した構造となっている。サーマルビィア16は、例えば発熱量の大きい能動部品である半導体チップの下部に設けられている。   The small circles shown in FIG. 8 are thermal vias 16 for transmitting the heat generated in the high-frequency power module 1 to the outside, and only a part is shown in FIG. The thermal via 16 has a structure in which a thermal via hole is filled with a metal having good thermal conductivity. The thermal via 16 is provided, for example, below a semiconductor chip that is an active component that generates a large amount of heat.

高周波パワーモジュール1を構成するキャップ4は、例えば金属板を成形して周壁を形成した構造となり、両端の端面壁21で多層配線基板2の両端を覆い、両側の側壁22から突出する接続片23で多層配線基板2の側面と重なり、半田3を介して多層配線基板2に固定されている。また、側壁22の一部は開口されている。キャップ4は厚さ0.1mmとなり、例えばメッキレスの洋白、あるいはニッケルメッキを施したリン青銅で形成されている。   The cap 4 constituting the high-frequency power module 1 has a structure in which, for example, a metal plate is formed to form a peripheral wall, and both ends of the multilayer wiring board 2 are covered with end walls 21 on both ends, and connection pieces 23 projecting from the side walls 22 on both sides. , And is fixed to the multilayer wiring board 2 via the solder 3. Further, a part of the side wall 22 is opened. The cap 4 has a thickness of 0.1 mm and is made of, for example, plating-free nickel-white or nickel-plated phosphor bronze.

多層配線基板2は、図2および図4に示すように、上段誘電体層(上段誘電体板)25,中段誘電体層(中段誘電体板)26,下段誘電体層(下段誘電体板)27と誘電体層(誘電体板)を3段に重ねた構造となっている。   As shown in FIGS. 2 and 4, the multilayer wiring board 2 includes an upper dielectric layer (upper dielectric plate) 25, a middle dielectric layer (middle dielectric plate) 26, and a lower dielectric layer (lower dielectric plate). 27 and a dielectric layer (dielectric plate) in three layers.

また、上段誘電体層25の上面(露出面)には、図5に示すような配線パターン(第1層配線30)が設けられている。また、前記上段誘電体層25と中段誘電体層26との間には図6に示すような配線パターン(第2層配線31)が設けられ、前記中段誘電体層26と下段誘電体層27との間には図7に示すような配線パターン(第3層配線32)が設けられ、下段誘電体層27の裏面(露出面)には図8に示すような配線パターン(第4層配線33)が設けられている。   On the upper surface (exposed surface) of the upper dielectric layer 25, a wiring pattern (first-layer wiring 30) as shown in FIG. 5 is provided. A wiring pattern (second wiring 31) as shown in FIG. 6 is provided between the upper dielectric layer 25 and the middle dielectric layer 26, and the middle dielectric layer 26 and the lower dielectric layer 27 are provided. 7, a wiring pattern (third layer wiring 32) as shown in FIG. 7 is provided, and on the back surface (exposed surface) of the lower dielectric layer 27, a wiring pattern (third layer wiring 32) as shown in FIG. 33) is provided.

多層配線基板2は、例えば、ガラスセラミックスを積層させた低温焼成多層配線基板からなり、配線は高導電性金属、例えば銀系金属を使用している。すなわち、外層配線はAg−Ptを使用し、内装配線はAgを使用している。低温焼成は600℃程度となり、融点の低いAgの使用が可能となる。Agは抵抗値が低い高導電性金属となるため、高周波特性の向上が達成できる。   The multilayer wiring board 2 is composed of, for example, a low-temperature fired multilayer wiring board in which glass ceramics are laminated, and the wiring uses a highly conductive metal, for example, a silver-based metal. That is, the outer wiring uses Ag-Pt, and the interior wiring uses Ag. The low temperature firing is about 600 ° C., which makes it possible to use Ag having a low melting point. Since Ag is a highly conductive metal having a low resistance value, improvement in high frequency characteristics can be achieved.

図5乃至図8において、35は信号配線、36は電源配線、15はグランド配線である。これにより、中段誘電体層26と下段誘電体層27との間の第3層配線32は、中段誘電体層26上の第2層配線31と下段誘電体層27の下の第4層配線33がいずれもグランド配線15となることから、ストリップライン構造となる。また、上段誘電体層25上の第1層配線30は上段誘電体層25の下面にグランド配線15となる第2層配線31が設けられていることから、マイクロストリップライン構造となる。
内層の信号配線は上下を誘電体層を介して挟まれることから、電気・電磁的シールドが可能となり、高周波特性が安定する。
5 to 8, 35 is a signal wiring, 36 is a power supply wiring, and 15 is a ground wiring. As a result, the third-layer wiring 32 between the middle dielectric layer 26 and the lower dielectric layer 27 becomes the second wiring 31 on the middle dielectric layer 26 and the fourth wiring below the lower dielectric layer 27. Since all 33 are ground wirings 15, they have a strip line structure. Further, the first layer wiring 30 on the upper dielectric layer 25 has a microstrip line structure because the second layer wiring 31 serving as the ground wiring 15 is provided on the lower surface of the upper dielectric layer 25.
Since the signal wiring of the inner layer is sandwiched between the upper and lower layers via the dielectric layer, electric and electromagnetic shielding becomes possible, and the high frequency characteristics are stabilized.

また、上段誘電体層25と中段誘電体層26との間のグランド配線15は、図9に示すように、編み目(メッシュ)構造となっている。このため、編み目部分55には、上段誘電体層25と中段誘電体層26の誘電体層が入り込み、グランド配線の上下の誘電体層の接合強度が高くなり、剥がれ難い多層配線基板2となる。   The ground wiring 15 between the upper dielectric layer 25 and the middle dielectric layer 26 has a stitch (mesh) structure as shown in FIG. For this reason, the dielectric layers of the upper dielectric layer 25 and the middle dielectric layer 26 enter the stitch portion 55, the bonding strength between the dielectric layers above and below the ground wiring is increased, and the multilayer wiring board 2 is difficult to peel. .

前記第1層配線30,第2層配線31,第3層配線32,第4層配線33の各配線は10〜20μm程度の厚さとなっている。そして、多層配線基板2全体の厚さは、例えば0.9mmとなる。   Each of the first layer wiring 30, the second layer wiring 31, the third layer wiring 32, and the fourth layer wiring 33 has a thickness of about 10 to 20 μm. The overall thickness of the multilayer wiring board 2 is, for example, 0.9 mm.

一方、第1層配線30,第2層配線31,第3層配線32,第4層配線33の各配線は、図2および図4に示すように、所望の誘電体層から所望の深さの誘電体層まで貫通延在するブラインド型ビィア40や最上段の誘電体層から最下段の誘電体層まで貫通延在する貫通型ビィア41、さらには所望の誘電体層から最下段の誘電体層まで貫通延在するサーマルビィア16によって電気的に接続されている。これらブラインド型ビィア40,貫通型ビィア41およびサーマルビィア16はビィアホールにAgを充填させた構造となっている。   On the other hand, as shown in FIGS. 2 and 4, each of the first layer wiring 30, the second layer wiring 31, the third layer wiring 32, and the fourth layer wiring 33 has a desired depth from a desired dielectric layer. Blind via 40 extending from the uppermost dielectric layer to the lowermost dielectric layer, and a blind via 40 extending from the uppermost dielectric layer to the lowermost dielectric layer. They are electrically connected by thermal vias 16 extending through the layers. The blind via 40, the through via 41, and the thermal via 16 have a structure in which a via hole is filled with Ag.

また、3枚の重なる上段誘電体層25,中段誘電体層26,下段誘電体層27の両側面にも、半円弧断面の端面スルーホール20が設けられ、下段誘電体層27の第4層配線33で形成される各外部端子5(入力端子6、グランド端子7,811,12、ゲインコントロール端子9、出力端子10、電源端子13)に接続されている。   Also, on both side surfaces of the three upper dielectric layers 25, the middle dielectric layer 26, and the lower dielectric layer 27 which are overlapped with each other, the end surface through holes 20 having a semicircular cross section are provided, and the fourth layer of the lower dielectric layer 27 is formed. The external terminals 5 (the input terminal 6, the ground terminals 7, 811 and 12, the gain control terminal 9, the output terminal 10, and the power supply terminal 13) formed by the wiring 33 are connected.

前記上段誘電体層25には、図2乃至図5に示すように、矩形の窪み42,43が設けられ、これら窪み42,43の底には半導体チップ44,45が固定されている。窪み42,43によって、半導体チップ44,45の図示しない上面の電極面と、配線面の高さは略同じ高さとなる。このため、半導体チップ44,45の電極と配線とを接続する導電性のワイヤ46はその張り高さ(ループ)を低く形成できるため、短い長さで配線と半導体チップの電極を接続できることになり、抵抗の低減から高周波特性の向上が達成できる。例えば出力ゲインの向上を達成することができる。   As shown in FIGS. 2 to 5, rectangular recesses 42 and 43 are provided in the upper dielectric layer 25, and semiconductor chips 44 and 45 are fixed to the bottoms of the recesses 42 and 43. Due to the depressions 42 and 43, the height of the electrode surface on the upper surface (not shown) of the semiconductor chips 44 and 45 is substantially the same as the height of the wiring surface. For this reason, since the conductive wire 46 connecting the electrodes of the semiconductor chips 44 and 45 and the wiring can be formed with a low tension (loop), the wiring and the electrode of the semiconductor chip can be connected with a short length. In addition, improvement in high-frequency characteristics can be achieved from reduction in resistance. For example, an improvement in output gain can be achieved.

前記半導体チップ45は、図2および図4に示すように、グランド配線15となる第2層配線31に銀ペースト等の接合材47を使用して固定される。また、半導体チップ44,45が固定される部分には、多数のサーマルビィア16が設けられ、半導体チップ44,45から発生する熱を速やかに外部に伝達するようになっている。熱は、多層配線基板2の裏面のグランド配線15およびレジスト膜14を介して実装基板に放熱される。したがって、半導体チップ44,45は安定した動作を行う。   As shown in FIGS. 2 and 4, the semiconductor chip 45 is fixed to the second layer wiring 31 serving as the ground wiring 15 using a bonding material 47 such as a silver paste. Further, a large number of thermal vias 16 are provided in portions where the semiconductor chips 44 and 45 are fixed, so that heat generated from the semiconductor chips 44 and 45 is quickly transmitted to the outside. The heat is radiated to the mounting board via the ground wiring 15 and the resist film 14 on the back surface of the multilayer wiring board 2. Therefore, the semiconductor chips 44 and 45 perform a stable operation.

多層配線基板2の表面には、図2乃至図4に示すように、能動部品としてツェナーダイオード(ZD)50が搭載されている。また、受動部品としてはチップ型の抵抗(R〜R)51、チップ型のコンデンサ(C〜C)52,コンデンサ(バイパスコンデンサ)53が搭載されている。 As shown in FIGS. 2 to 4, a Zener diode (ZD) 50 is mounted on the surface of the multilayer wiring board 2 as an active component. In addition, chip-type resistors (R 1 to R 6 ) 51, chip-type capacitors (C 1 to C 9 ) 52, and capacitors (bypass capacitors) 53 are mounted as passive components.

また、図2および図3に示すように、半導体チップ44,45、ワイヤ46、一部の抵抗51,コンデンサ52,コンデンサ53等は、耐湿性向上のためにレジン54によって被覆されている。   As shown in FIGS. 2 and 3, the semiconductor chips 44 and 45, the wires 46, and some of the resistors 51, the capacitors 52, and the capacitors 53 are covered with a resin 54 for improving moisture resistance.

なお、本実施例1では内層の配線は修正できない。このため、線路特性を測定した後、線路特性に合った各部品(抵抗,コンデンサ等)を選択して組み込むことによって所望の電気特性を得ることができる。
本実施例1では、電界効果トランジスタを2段に組み込んで、800〜1000MHzとなる携帯電話用の高周波パワーモジュールとなる。
In the first embodiment, the wiring in the inner layer cannot be corrected. For this reason, after measuring the line characteristics, the desired electrical characteristics can be obtained by selecting and incorporating components (resistance, capacitor, etc.) that match the line characteristics.
In the first embodiment, a high-frequency power module for mobile phones of 800 to 1000 MHz is obtained by incorporating field-effect transistors in two stages.

本実施例1の高周波パワーモジュールは以下の効果を有する。
(1)高周波パワーモジュールは、電界効果トランジスタ等の能動部品や受動部品を主面に搭載した多層配線基板2と、この多層配線基板2の主面側に固定されたキャップ4とによって形成された矩形体構造となっていることから、従来のようにパッケージからリードを突出させたり、取付用フィンを突出させないため小型となる。特に長くリードを突出させないため、実装面積の大幅な縮小が達成できる。実装の場合、E型の場合、実装面積は20mm×14.35mmとなるが、本実施例1の場合は12.3mm×8mmと大幅に小さくなる。
The high-frequency power module according to the first embodiment has the following effects.
(1) The high-frequency power module is formed by a multilayer wiring board 2 on which active components and passive components such as a field effect transistor are mounted on a main surface, and a cap 4 fixed to the main surface side of the multilayer wiring substrate 2. Because of the rectangular structure, the leads are not protruded from the package and the mounting fins are not protruded unlike the related art, so that the size is reduced. Particularly, since the leads do not protrude for a long time, the mounting area can be significantly reduced. In the case of mounting, in the case of the E type, the mounting area is 20 mm × 14.35 mm, but in the case of the first embodiment, it is significantly reduced to 12.3 mm × 8 mm.

(2)多層配線基板2はストリップライン構造にマイクロストリップライン構造を積み重ねた構造となるため、伝送線路(信号配線等)の長さを長くとっても、伝送線路は2段に設けられるため、多層配線基板の大きさは小さくでき、高周波パワーモジュールの小型化が達成できる。   (2) Since the multilayer wiring board 2 has a structure in which a microstrip line structure is stacked on a strip line structure, the transmission lines are provided in two stages even if the length of the transmission line (such as a signal wiring) is increased, so that the multilayer wiring is provided. The size of the substrate can be reduced, and downsizing of the high-frequency power module can be achieved.

(3)誘電体層間に設けられた信号配線はその上下を誘電体層を介してグランド配線で挟まれる構造となることから、電気・電磁的シールドがなされ、高周波特性が安定する。   (3) Since the signal wiring provided between the dielectric layers has a structure in which the signal wiring is sandwiched above and below by the ground wiring via the dielectric layer, an electric / electromagnetic shield is performed, and the high-frequency characteristics are stabilized.

(4)内層のグランド配線は編み目構造となっていることから、編み目部分には誘電体層が入り込み、グランド配線の上下の誘電体層の接合強度が高くなり、剥がれ難い多層配線基板となる。したがって、耐湿性に優れた高周波パワーモジュールとなる。   (4) Since the ground wiring in the inner layer has a stitch structure, the dielectric layer enters the stitch portion, the bonding strength between the dielectric layers above and below the ground wiring is increased, and a multilayer wiring board that is difficult to peel off is obtained. Therefore, a high-frequency power module having excellent moisture resistance is obtained.

(5)能動部品において、半導体チップ44,45は多層配線基板2の主面に設けられた窪み42,43に固定され、半導体チップの電極面と多層配線基板の配線面の高さは略同一高さとなり、前記半導体チップの電極と前記配線を接続する前記ワイヤ46は略直線状に延在している。したがって、ワイヤが短くなり、抵抗が軽減されて高周波特性が良好となる。例えば出力ゲインが大きくなる。   (5) In the active component, the semiconductor chips 44 and 45 are fixed to the depressions 42 and 43 provided on the main surface of the multilayer wiring board 2, and the heights of the electrode surface of the semiconductor chip and the wiring surface of the multilayer wiring board are substantially the same. The height of the wire 46 connects the electrode of the semiconductor chip and the wiring, and the wire 46 extends substantially linearly. Therefore, the wire is shortened, the resistance is reduced, and the high-frequency characteristics are improved. For example, the output gain increases.

(6)多層配線基板2の所望部分には、所望の誘電体層から最下層の誘電体層まで貫通延在するサーマルビィア16が設けられている。したがって、熱放散性が高くなり、安定した電気特性が得られる。   (6) A thermal via 16 is provided at a desired portion of the multilayer wiring board 2 so as to extend from a desired dielectric layer to a lowermost dielectric layer. Therefore, heat dissipation is enhanced, and stable electric characteristics can be obtained.

(7)サーマルビィア16の上には半導体チップ44,45が位置している。したがって、半導体チップ44,45で発熱した熱は速やかに外部に放散され、電界効果トランジスタが安定動作する。   (7) The semiconductor chips 44 and 45 are located on the thermal via 16. Therefore, the heat generated by the semiconductor chips 44 and 45 is quickly dissipated to the outside, and the field effect transistor operates stably.

(8)多層配線基板2裏面の電極端子5において、グランド配線15はその表面が実装用接合材に濡れないレジスト膜14で部分的に覆われて相互に独立した複数のグランド端子7,8,11,12となっている。したがって、各電極端子5に均一に実装用接合材が濡れるため、各電極端子5は確実に実装用接合材を介して実装基板に固定される。   (8) In the electrode terminals 5 on the back surface of the multilayer wiring board 2, the ground wiring 15 is partially covered with a resist film 14 that does not wet the mounting bonding material, and a plurality of mutually independent ground terminals 7, 8,. 11 and 12. Therefore, since the mounting bonding material is uniformly wetted on each electrode terminal 5, each electrode terminal 5 is securely fixed to the mounting board via the mounting bonding material.

(9)多層配線基板2の裏面の電極端子5の配列間隔は同一ピッチとなっている。したがって、各電極端子5は実装用接合材の片寄りもなく実装用接合材のブリッジ等の不良も発生しなくなる。また、実装のセルフアライン化も可能となる。   (9) The arrangement intervals of the electrode terminals 5 on the back surface of the multilayer wiring board 2 are the same. Therefore, each electrode terminal 5 does not have a bias of the bonding material for mounting, and a defect such as a bridge of the bonding material for mounting does not occur. In addition, self-alignment of mounting becomes possible.

(10)多層配線基板2の裏面の電極端子5のうち、少なくともグランド端子7,8,11,12以外の電極端子は、多層配線基板2の側面の上下に延在する端面スルーホール20を介して各層の配線に接続されている。すなわち、高周波パワーモジュールはLCC(リードレス・チップ・キャリア)構造となり、小型化が達成できる。   (10) Of the electrode terminals 5 on the rear surface of the multilayer wiring board 2, at least the electrode terminals other than the ground terminals 7, 8, 11, and 12 are provided through end face through holes 20 extending vertically on the side surface of the multilayer wiring board 2. To the wiring of each layer. That is, the high-frequency power module has an LCC (leadless chip carrier) structure, and can be reduced in size.

(11)多層配線基板2は低温焼成多層セラミック基板となることから、配線は融点の低い銀系金属(Ag−Pt)からなる高導電性金属で形成できるため、抵抗の低減から高周波特性が良好となる。すなわち、出力ゲインの向上を図ることができる。   (11) Since the multilayer wiring board 2 is a multilayer ceramic substrate fired at a low temperature, the wiring can be formed of a highly conductive metal made of a silver-based metal (Ag-Pt) having a low melting point. It becomes. That is, the output gain can be improved.

以上本発明者によってなされた発明を実施例に基づき具体的に説明したが、本発明は上記実施例に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることはいうまでもない、たとえば、図10に示すように、キャップ4は、多層配線基板2に設けた窪み60の縁にフック61を介して着脱自在に取り付ける構造とすれば、多層配線基板2へのキャップ4の着脱が容易となる。   Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and it is needless to say that various modifications can be made without departing from the gist of the invention. For example, as shown in FIG. 10, if the cap 4 is configured to be detachably attached to the edge of the recess 60 provided in the multilayer wiring board 2 via the hook 61, the cap 4 Can be easily attached and detached.

また、前記実施例では、多層配線基板2は多層配線構造となっていることから、誘電体層の厚さをさらに薄くでき、容量の増大を図ることができる。また、多層配線基板2となることから、信号配線の長さもさらに長くできるため、特性インピーダンスの増大を図ることも可能である。この場合、酸化チタンやチタン酸バリウム等誘電率の高い材料を誘電体層(誘電体板)として使用すれば、容量の増大はさらに高くなる。   Further, in the above embodiment, since the multilayer wiring board 2 has a multilayer wiring structure, the thickness of the dielectric layer can be further reduced, and the capacitance can be increased. In addition, since the multilayer wiring board 2 is used, the length of the signal wiring can be further increased, so that the characteristic impedance can be increased. In this case, if a material having a high dielectric constant, such as titanium oxide or barium titanate, is used as the dielectric layer (dielectric plate), the increase in capacitance is further increased.

また、前記多層配線基板2は、ガラスセラミック以外の配線基板材料を用いて形成できる。
また、低温焼成多層配線基板の場合、高導電性金属による配線としては、金や銅を使用できる。
Further, the multilayer wiring board 2 can be formed using a wiring board material other than glass ceramic.
In the case of a low-temperature fired multilayer wiring board, gold or copper can be used as the wiring made of a highly conductive metal.

以上の説明では主として本発明者によってなされた発明をその背景となった利用分野である高周波パワーモジュールに適用した場合について説明したが、それに限定されるものではない。本発明は少なくとも混成集積回路装置には適用できる。   In the above description, the case where the invention made by the inventor is mainly applied to the high frequency power module which is the application field as the background has been described, but the invention is not limited to this. The present invention is applicable to at least a hybrid integrated circuit device.

本発明の実施例1である高周波パワーモジュールの外観を示す斜視図である。FIG. 1 is a perspective view illustrating an appearance of a high-frequency power module that is Embodiment 1 of the present invention. 本実施例1の高周波パワーモジュールの断面図である。FIG. 2 is a cross-sectional view of the high-frequency power module according to the first embodiment. 本実施例1のキャップを取り外した高周波パワーモジュールを示す平面図である。FIG. 3 is a plan view illustrating the high-frequency power module with the cap removed according to the first embodiment. 本実施例1の高周波パワーモジュールにおける多層配線基板の構造を示す一部の斜視図である。FIG. 2 is a partial perspective view illustrating a structure of a multilayer wiring board in the high-frequency power module according to the first embodiment. 本実施例1の高周波パワーモジュールにおける多層配線基板の表面、すなわち上段誘電体層の露出面に形成される配線パターン(第1層配線)を示す平面図である。FIG. 4 is a plan view showing a wiring pattern (first-layer wiring) formed on the surface of the multilayer wiring board in the high-frequency power module according to the first embodiment, that is, on the exposed surface of the upper dielectric layer. 本実施例1の高周波パワーモジュールにおける多層配線基板の上段誘電体層と中段誘電体層との間に形成される配線パターン(第2層配線)を示す平面図である。FIG. 3 is a plan view showing a wiring pattern (second-layer wiring) formed between the upper dielectric layer and the middle dielectric layer of the multilayer wiring board in the high-frequency power module according to the first embodiment. 本実施例1の高周波パワーモジュールにおける多層配線基板の中段誘電体層と下段誘電体層との間に形成される配線パターン(第3層配線)を示す平面図である。FIG. 4 is a plan view showing a wiring pattern (third-layer wiring) formed between the middle dielectric layer and the lower dielectric layer of the multilayer wiring board in the high-frequency power module of the first embodiment. 本実施例1の高周波パワーモジュールにおける多層配線基板の裏面、すなわち下段誘電体層の露出面に形成される配線パターン(第4層配線)を示す底面図である。FIG. 5 is a bottom view showing a wiring pattern (fourth layer wiring) formed on the back surface of the multilayer wiring board, that is, on the exposed surface of the lower dielectric layer in the high-frequency power module of the first embodiment. 本実施例1の高周波パワーモジュールにおけるグランド配線となる第2層配線および第4層配線の一部を示す平面図である。FIG. 3 is a plan view showing a part of a second-layer wiring and a fourth-layer wiring serving as ground wiring in the high-frequency power module of the first embodiment. 本発明の他の実施例である高周波パワーモジュールを示す断面図である。It is sectional drawing which shows the high frequency power module which is another Example of this invention.

符号の説明Explanation of reference numerals

1…混成集積回路装置(高周波パワーモジュール)、2…多層配線基板、3…半田、4…キャップ、5…電極端子(外部端子)、6…入力端子(Pin)、7…グランド端子(GND)、8…グランド端子(GND)、9…ゲインコントロール端子(Vapc)、10…出力端子(Pout)、11,12…グランド端子(GND)、13…電源端子(Vdd)、14…レジスト膜、15…グランド配線、16…サーマルビィア、20…端面スルーホール、21…端面壁、22…側壁、23…接続片、25…上段誘電体層、26…中段誘電体層、27…下段誘電体層、30…第1層配線、31…第2層配線、32…第3層配線、33…第4層配線、35…信号配線、36…電源配線、40…ブラインド型ビィア、41…貫通型ビィア、42,43…窪み、44,45…半導体チップ、46…ワイヤ、47…接合材、50…ツェナーダイオード、51…抵抗、52…コンデンサ、53…コンデンサ、54…レジン DESCRIPTION OF SYMBOLS 1 ... Hybrid integrated circuit device (high frequency power module), 2 ... Multilayer wiring board, 3 ... Solder, 4 ... Cap, 5 ... Electrode terminal (external terminal), 6 ... Input terminal (P in ), 7 ... Ground terminal (GND) ), 8 ground terminal (GND), 9 gain control terminal (V apc ), 10 output terminal (P out ), 11, 12 ground terminal (GND), 13 power supply terminal (V dd ), 14. Resist film, 15: ground wiring, 16: thermal via, 20: end surface through hole, 21: end surface wall, 22: side wall, 23: connection piece, 25: upper dielectric layer, 26: middle dielectric layer, 27: lower stage Dielectric layer, 30 first-layer wiring, 31 second-layer wiring, 32 third-layer wiring, 33 fourth-layer wiring, 35 signal wiring, 36 power-supply wiring, 40 blind-type via, 41 Through-type vias, 2, 43 ... recess, 44, 45 ... semiconductor chip, 46 ... wire, 47 ... bonding material, 50 ... Zener diode, 51 ... resistors, 52 ... capacitor, 53 ... capacitor, 54 ... Resin

Claims (4)

多層配線基板と、
前記多層配線基板の主面に搭載された能動部品および受動部品と、
前記能動部品の電極と前記多層配線基板の配線とを接続した導電性のワイヤと、
前記多層配線基板の裏面に設けられた前記多層配線の複数の電極端子とを有することを特徴とする混成集積回路装置。
A multilayer wiring board;
Active components and passive components mounted on the main surface of the multilayer wiring board,
A conductive wire connecting the electrode of the active component and the wiring of the multilayer wiring board,
A hybrid integrated circuit device, comprising: a plurality of electrode terminals of the multilayer wiring provided on a back surface of the multilayer wiring board.
多層配線基板と、
前記多層配線基板の主面に搭載された少なくとも一つ以上の能動部品および受動部品と、
前記能動部品の電極と前記多層配線基板の配線とを接続した導電性のワイヤと、
前記多層配線基板の主面を覆うように多層配線基板に固定されたキャップと、
前記多層配線基板の裏面に設けられた前記多層配線の複数の電極端子とを有することを特徴とする混成集積回路装置。
A multilayer wiring board;
At least one or more active components and passive components mounted on the main surface of the multilayer wiring board,
A conductive wire connecting the electrode of the active component and the wiring of the multilayer wiring board,
A cap fixed to the multilayer wiring board so as to cover a main surface of the multilayer wiring board,
A hybrid integrated circuit device, comprising: a plurality of electrode terminals of the multilayer wiring provided on a back surface of the multilayer wiring board.
請求項2記載の混成集積回路装置において、
前記キャップは多層配線基板に設けた窪み部分によって形成された引っ掛かり部分にフックを介して着脱自在に取り付けられていることを特徴とする混成集積回路装置。
The hybrid integrated circuit device according to claim 2,
The hybrid integrated circuit device according to claim 1, wherein the cap is detachably attached via a hook to a hook formed by a recess provided in the multilayer wiring board.
請求項1乃至3のいずれか一に記載の混成集積回路装置において、
前記能動部品はレジンにより被覆されていることを特徴とする混成集積回路装置。
The hybrid integrated circuit device according to any one of claims 1 to 3,
A hybrid integrated circuit device, wherein the active component is covered with a resin.
JP2004170999A 2004-06-09 2004-06-09 Hybrid integrated circuit device Pending JP2004253821A (en)

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Related Parent Applications (1)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007227596A (en) * 2006-02-23 2007-09-06 Shinko Electric Ind Co Ltd Semiconductor module and its manufacturing method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007227596A (en) * 2006-02-23 2007-09-06 Shinko Electric Ind Co Ltd Semiconductor module and its manufacturing method

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