JP2004179649A - Method and apparatus for manufacturing ultra-thin semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method and an apparatus for manufacturing an ultra-thin semiconductor device thinner than the conventional 50 μm, for example, about 1 to 10 μm.
A low-porous Si layer, a high-porous Si layer, a low-porous Si layer, and a single-crystal Si layer are formed on a seed substrate, and a low-porous Si layer is formed on a support substrate. The porous Si layer 27, the low porous Si layer 28, the single crystal Si layer 29, and the insulating layer 30 are formed, and the seed substrate 20 and the support substrate 25 are bonded to each other on the surface on which the insulating layer 30 is formed. Separated from the highly porous Si layer 22 of the substrate 20, the surface of the single crystal Si layer 24 is etched and flattened by hydrogen annealing treatment, and a semiconductor device and a bump-like bump electrode are formed on the single crystal Si layer 24, and scribed. In the line, at least a groove is formed up to the high-porosity Si layer 27, and the surface of the single-crystal Si layer 24 is protected with a conductive UV-irradiation-curable tape having no adhesive residue. From the support substrate 25 Is separated.
[Selection diagram] Fig. 4

Description

  The present invention relates to a method and an apparatus for manufacturing an ultra-thin semiconductor device for separating a semiconductor layer formed on a substrate from the substrate to obtain an ultra-thin semiconductor device.

  At present, a thin semiconductor chip having a thickness of about 50 μm is produced by holding the surface of a semiconductor wafer with a protective tape and grinding the back surface, grinding the back surface and polishing the back surface, or grinding the back surface and chemically etching.

  For example, in Patent Document 1, the inventor of the present application discloses forming a dicing groove having a desired chip thickness of, for example, 50 μm in a scribe line, holding the front surface with a protective tape, grinding the back surface to the dicing groove, and fabricating the back surface. It has been proposed to produce a thin semiconductor chip by grinding and polishing the back surface, or grinding the back surface and etching by Si.

  Further, Patent Document 2 discloses that a dicing groove having a desired chip thickness of, for example, 50 μm in depth is formed in a scribe line, and a photocurable resin film is formed on an inner wall of the dicing groove, thereby causing cracks and chipping. Is described.

  Further, in Patent Document 3 and Patent Document 4, the present inventor formed a dicing groove having a desired chip thickness of, for example, 50 μm deep in a scribe line, and formed an epoxy-based dicing groove with the surface on which the bump electrode was formed. It has been proposed that after sealing with resin or the like, a thin semiconductor chip is manufactured by grinding the back surface, grinding the back surface and polishing the back surface up to the dicing groove, or grinding the back surface and etching by Si.

  By the way, as a method of manufacturing an SOI (Silicon On Insulator) substrate, there are known ELTRAN (trademark) technology of Canon Inc., SMART CUT (trademark) technology of Soitec, France, SIMOX (Separation by IMplanted OXygen) technology, and the like.

  For example, in the ELTRAN method, as disclosed in Patent Document 5, the surface of a seed Si wafer is first chemically treated by anodic oxidation into a porous sponge structure having an infinite number of fine holes having a diameter of 0.01 μm. A single crystal Si layer is epitaxially grown on the porous Si. Further, the surface of the single crystal Si layer is thermally oxidized to form an insulating film, which is bonded to the handle Si wafer, and then the seed Si wafer is separated at the porous layer by water jet. Thereafter, the porous layer left on the handle Si wafer is removed by ultra-high selective etching. Finally, an SOI substrate is manufactured by smoothing the surface by hydrogen annealing. Patent Document 6 discloses that separation of a seed Si wafer is performed by pulling and peeling a porous layer.

  On the other hand, in the SMART CUT method, as described in Patent Documents 7, 8, 9, and 10 and the like, a high hydrogen ion implantation layer is formed at a predetermined depth from the surface of a Si wafer, and is separately thermally oxidized to form an insulating film. Is bonded to the Si wafer on which is formed, and then subjected to a peeling heat treatment to peel in the high hydrogen ion implantation region, and finally, the surface is smoothed by hydrogen annealing treatment to produce an SOI substrate.

JP-A-4-297056 JP-A-6-85055 JP-A-2000-40711 JP 2000-40773 A Japanese Patent No. 2608351 JP-A-11-195562 Japanese Patent No. 3048201 JP 2000-196047 A JP 2001-77044 A JP-A-5-211128

  In the current mainstream back grinding, back grinding and back polishing, or back processing and mechanical processing methods such as Si etching as described above, or a mechanical and chemical processing method, a semiconductor chip thickness of about 50 μm is a limit. is there. However, for a three-dimensional laminated chip such as a high-capacity memory, a thinner ultra-thin semiconductor chip is desired.

  The point of the ELTRAN method described in Patent Document 5 is to separate a seed Si wafer at a porous layer by a water jet. However, when the wafer size is large, it is difficult to separate the seed Si wafer. Yield and quality tend to be problems due to chipping, cracking, and the like. Further, in the method described in Patent Document 6, since the porous layer is pulled and peeled, the yield and the quality tend to be problematic due to the occurrence of cracks, chips, cracks, etc., especially in thinner semiconductor devices.

  On the other hand, the point of the SMART CUT method described in Patent Documents 7, 8, 9, 10 and the like is that the peeling annealing causes strain in the high hydrogen ion implanted layer due to the pressure action and crystal rearrangement action in the hydrogen microbubbles. The two substrates are separated by pulling. However, as the size of the wafer becomes large, it becomes difficult to separate the substrates. Therefore, particularly in a thin semiconductor device, cracks, chips, cracks, etc. tend to cause problems in yield and quality.

  In addition, in all SOI substrates, an ultra-thin single-crystal Si layer is formed on the surface of the Si substrate via an insulating film, but a thick Si substrate basically serves as a support for obtaining mechanical strength. . Therefore, although the surplus part is finally removed by grinding the back surface, the method is the same mechanical processing method or the mechanical and chemical processing method as described above, so that the semiconductor chip thickness of about 50 μm is limited. It is.

  Therefore, an object of the present invention is to provide a method and an apparatus for manufacturing an ultra-thin semiconductor device having a thickness smaller than the conventional 50 μm, for example, about 1 to 10 μm.

  The method for manufacturing an ultra-thin semiconductor device of the present invention includes a step of bonding a seed substrate and a support substrate made of a semiconductor via an insulating layer, and a step of separating the seed substrate from a porous layer formed on the seed substrate. Separating the support substrate from the porous layer formed on the support substrate.

  According to the present manufacturing method, an ultra-thin SOI substrate is manufactured by separating the seed substrate and the support substrate from the porous layer formed on each of the seed substrate and the support substrate bonded via the insulating layer. You.

  The method for manufacturing an ultra-thin semiconductor device of the present invention includes a step of forming a porous layer on both a seed substrate and a support substrate each comprising a semiconductor, and a step of forming a porous layer on both the seed substrate and the support substrate via the respective porous layers. A step of forming a semiconductor layer, a step of forming an insulating layer on at least one of a seed substrate and a supporting substrate via a semiconductor layer, a step of bonding the seed substrate and the supporting substrate on a surface on which the insulating layer is formed, A step of separating the porous layer of the seed substrate from the porous layer of the seed substrate, a step of etching and flattening the surface of the semiconductor layer of the seed substrate by hydrogen annealing, a step of forming a semiconductor device on the semiconductor layer, Separating from the porous layer of the supporting substrate.

  In the present production method, a porous layer and a semiconductor layer are formed on both the seed substrate and the support substrate, and these two substrates are bonded to each other with an insulating layer interposed therebetween. The surface of the semiconductor layer of the seed substrate is etched and flattened by the annealing treatment, whereby an ultra-thin SOI layer is formed on the support substrate. Thereafter, a semiconductor device is formed on the semiconductor layer of the ultra-thin SOI layer and separated from the supporting substrate at the porous layer, whereby an ultra-thin semiconductor device is obtained.

  Here, it is desirable that the porous layer formed on the seed substrate has a higher porosity than the porous layer formed on the supporting substrate or is thicker than the porous layer formed on the supporting substrate. Thereby, the seed substrate that separates earlier than the support substrate is easier to separate, and the separation of the seed substrate during the separation of the seed substrate can be prevented.

  The method for manufacturing an ultra-thin semiconductor device of the present invention includes a step of bonding a seed substrate and a support substrate made of a semiconductor via an insulating layer, and a step of separating the seed substrate from an ion-implanted layer formed on the seed substrate. Separating the support substrate from the ion-implanted layer formed on the support substrate.

  According to the present manufacturing method, an ultra-thin SOI substrate is manufactured by separating the seed substrate and the support substrate from the ion-implanted layers respectively formed on the seed substrate and the support substrate bonded via the insulating layer. You.

  The method for manufacturing an ultra-thin semiconductor device according to the present invention includes a step of forming a first ion-implanted layer on a seed substrate made of a semiconductor; a step of forming an insulating layer on a support substrate; A step of bonding the first ion-implanted layer and the insulating layer covalently by heat treatment, and performing a peeling anneal treatment to separate the seed substrate from the first ion-implanted layer by heat treatment; Forming a surface of the semiconductor layer by hydrogen annealing, flattening the surface of the semiconductor layer by etching, and forming a semiconductor device on the etched semiconductor layer. Forming a second ion-implanted layer at a predetermined depth from the substrate, performing an annealing process for removing the second ion-implanted layer, and separating the support substrate from the second ion-implanted layer.

  In the present manufacturing method, a support substrate on which an insulating layer is formed is attached to a seed substrate on which a first ion-implanted layer is formed, and the semiconductor substrate is formed by separating the seed substrate at the first ion-implanted layer after annealing for peeling. Further, the surface of the semiconductor layer is etched and flattened by hydrogen annealing, whereby an ultra-thin SOI layer is formed on the supporting substrate. Thereafter, a semiconductor device is formed on the semiconductor layer of the SOI layer, a second ion-implanted layer is formed on the support substrate, and the ultra-thin SOI layer is separated at the second ion-implanted layer after the peeling annealing process. Thus, an ultra-thin semiconductor device can be obtained. Further, since the formation of the second ion-implanted layer is performed after the heat treatment step at 500 ° C. or higher for forming the semiconductor device on the semiconductor layer of the SOI layer, the implanted second ion-implanted layer is not affected by these heat treatments. The support substrate can be separated at a desired position.

  The method for manufacturing an ultra-thin semiconductor device of the present invention includes a step of bonding a seed substrate and a support substrate made of a semiconductor via an insulating layer, and a step of separating the seed substrate from an ion-implanted layer formed on the seed substrate. Separating the support substrate from the porous layer formed on the support substrate.

  According to the present manufacturing method, the seed substrate and the support substrate are separated from the ion-implanted layer and the porous layer formed on the seed substrate and the support substrate that are bonded to each other via the insulating layer, respectively. Since the substrate is manufactured, an ultra-thin semiconductor device using the ultra-thin SOI substrate can be obtained.

  The method for manufacturing an ultra-thin semiconductor device according to the present invention includes a step of forming an ion-implanted layer on a seed substrate made of a semiconductor; a step of forming a porous layer on a support substrate made of a semiconductor; Forming a semiconductor layer through the layer, forming an insulating layer on the semiconductor layer, bonding the ion-implanted layer of the seed substrate and the insulating layer of the support substrate, and heat-treating the ion-implanted layer of the seed substrate. For covalently bonding the semiconductor substrate and the insulating layer of the supporting substrate, performing a peeling annealing process, separating the seed substrate from the ion-implanted layer, and etching and flattening the surface of the semiconductor layer by a hydrogen annealing process And forming a semiconductor device on the etched semiconductor layer, and separating the supporting substrate from the porous layer.

  In this production method, a porous substrate, a semiconductor layer, and a supporting substrate on which an insulating layer is formed are attached to a seed substrate on which an ion-implanted layer is formed, and the ion-implanted layer of the seed substrate and the insulating layer of the supporting substrate are shared by heat treatment. After bonding, the seed substrate is separated at the ion-implanted layer after the peeling annealing treatment to form a semiconductor layer, and the surface of the semiconductor layer is etched and flattened by a hydrogen annealing treatment to form an ultrathin film on the supporting substrate. A type SOI layer is formed. Thereafter, a semiconductor device is formed on the semiconductor layer of the ultra-thin SOI layer, and then separated from the supporting substrate at the porous layer, whereby an ultra-thin semiconductor device is obtained.

  In the method for manufacturing an ultra-thin semiconductor device according to the present invention, the support substrate is separated from the semiconductor layer to at least the porous layer or the second ion-implanted layer along the dividing line when dividing into the ultra-thin semiconductor devices. If it is performed after forming grooves (cutting grooves for blade dicing, grooves for wet etching or dry etching, etc.), the ultra-thin SOI layer separated from the supporting substrate in a later step is previously pelletized and divided. After the separation of the thin SOI layer, an ultra-thin semiconductor device already pelletized is obtained. In forming the groove, the ultra-thin SOI layer is supported by the support substrate, so that the occurrence of cracks and chips at the time of forming the cut groove is prevented.

  The method for manufacturing an ultra-thin semiconductor device according to the present invention includes the steps of: forming a porous layer on a support substrate; forming a semiconductor layer on the support substrate via the porous layer; A step of forming, for example, a kerf from the semiconductor layer to at least the porous layer along a dividing line when dividing the device, and a step of separating the support substrate from the porous layer after forming the kerf And

  In the present manufacturing method, a porous layer and a semiconductor layer are formed on a support substrate, and further, for example, by forming a kerf along a dividing line at the time of dividing at least the porous layer into each ultrathin semiconductor device, a The semiconductor layer separated from the supporting substrate in the step is pelletized in advance. Then, by separating the pelletized semiconductor layer from the supporting substrate at the porous layer, an ultra-thin semiconductor device can be obtained. Since the semiconductor layer is supported by the support substrate when forming the kerfs, the occurrence of cracks and chips due to the formation of the kerfs is prevented.

  The method for manufacturing an ultra-thin semiconductor device according to the present invention includes a step of forming a semiconductor layer on a surface of a supporting substrate, a step of forming an ion-implanted layer at a predetermined depth from the substrate surface, and a step of peeling the ion-implanted layer. Performing an annealing process, forming, for example, a kerf from the semiconductor layer to at least the ion-implanted layer along a dividing line when dividing into each ultrathin semiconductor device, and after forming the kerf, Separating the supporting substrate from the ion-implanted layer.

  In the present manufacturing method, a semiconductor layer and an ion-implanted layer are formed on a support substrate, and further, for example, by forming a kerf along a dividing line at the time of dividing each ultrathin semiconductor device up to at least the ion-implanted layer, The semiconductor layer separated from the supporting substrate in the step is pelletized in advance. Then, by separating the pelletized semiconductor layer from the supporting substrate at the ion implantation layer, an ultra-thin semiconductor device can be obtained. Since the semiconductor layer is supported by the supporting substrate during the formation of the kerfs, the occurrence of cracks and chips due to the formation of the kerfs is prevented.

By the way, for example, unlike a lattice constant of a single crystal Si layer, a silicon germanium (hereinafter, referred to as SiGe) layer of a strain applying semiconductor for applying a strain to the single crystal Si layer is formed on the porous Si layer, and then the semiconductor epitaxial growth is performed. Forming a strained channel single crystal Si layer using the SiGe layer of the strain applying semiconductor as a seed, or forming a strain applying semiconductor SiGe layer on a single crystal Si substrate by semiconductor epitaxial growth, and then applying the strain applying semiconductor SiGe by semiconductor epitaxial growth. A single crystal Si layer of a strain channel layer is formed using the layer as a seed, or a SiGe layer of a strain applying semiconductor is formed on the insulating layer, and a single crystal Si layer of a strain channel layer is formed using the SiGe layer of the strain applying semiconductor as a seed. When strain is applied to the strained channel semiconductor layer, As a result, the electron structure is changed, and as a result, electron scattering is suppressed due to degeneracy and electron mobility can be further increased, which is about 1.76 times as large as that of the conventional single-crystal Si layer of the strain-free channel layer. A very high electron mobility is realized, and a high-performance, high-quality, ultra-thin semiconductor device composed of a MOSTFT having high electron-hole mobility and high driving capability can be realized.
At this time, the germanium concentration in the strain applying semiconductor layer gradually increases from the contact surface of the porous Si layer, from the contact surface of the single-crystal Si substrate, or from the contact surface of the insulating layer, and increases. If the gradient composition is set to a desired concentration on the surface of the SiGe layer, for example, a Ge concentration of 20 to 30%, a desired and significantly high electron mobility is realized.

  Here, the separation from the porous layer can be performed by jetting a high-pressure fluid jet of a gas, a liquid, or a mixture of a gas and a liquid onto the rotating porous layer. In particular, in the case of jetting a high-pressure fluid jet of a mixture of gas and liquid, gas bubbles are mixed into the liquid, and the bubbles can be separated more effectively. Further, if the high-pressure fluid jet is added with fine solids, the fine solids can more effectively separate by directly colliding with the porous layer. Further, if the high-pressure fluid jet is applied with ultrasonic waves, the ultrasonic vibration acts on the porous layer, and separation from the porous layer can be performed more effectively.

  Alternatively, separation from the porous layer can be performed by laser processing or laser water jet processing on the rotating porous layer. In addition, when a kerf is formed, if separation from the porous layer is performed by high-pressure fluid jet processing or laser processing or laser water jet processing on the rotating porous layer, the porous layer can be more effectively removed from the porous layer. Separation can be performed.

  Further, if a semiconductor device and a protruding connection electrode connected to the semiconductor device are formed in the semiconductor layer before forming the kerf, the semiconductor layer is formed when the semiconductor device and the connection electrode are formed. Since the semiconductor device and the connection electrodes are supported by the support substrate, the occurrence of cracks and chipping due to the formation of the semiconductor device and the connection electrode is prevented.

  Furthermore, after forming the kerf, in a state where the surface of the semiconductor layer including the semiconductor device formed on the semiconductor layer and all of the protruding connection electrodes is covered with a conductive ultraviolet irradiation curable tape having no adhesive residue, It is desirable to separate the support substrate.

  Since the ultraviolet irradiation curing type tape has a strong adhesive force, the semiconductor layer is held by the ultraviolet irradiation curing type tape, and the ultra-thin SOI layer or the ultra-thin semiconductor layer is protected while the connection electrodes and the surface of the semiconductor layer are protected. Can be separated from the supporting substrate. In addition, the ultraviolet irradiation curing type tape is weakened in adhesive strength by irradiation with ultraviolet light and is easily peeled off. The ultraviolet irradiation curing type tape can be removed without damage and no adhesive residue. Further, since the ultraviolet irradiation curing type tape is conductive, the semiconductor device formed on the semiconductor layer is damaged by static electricity when the ultra thin SOI layer or the ultra thin semiconductor layer is separated and the ultraviolet irradiation curing type tape is removed. Can be prevented.

  Note that, depending on the type of semiconductor device formed on the semiconductor layer, there is a case where there is no risk of electrostatic damage or a case where glue residue does not pose a problem. It is not limited to the presence of adhesive residue and the presence or absence of conductivity, and a normal ultraviolet irradiation curing type tape or a thermally expandable peeling tape can also be used.

  Further, it is preferable that the porous layer of the supporting substrate be made conductive by adding an n-type or p-type impurity. Thus, it is possible to prevent electrostatic damage and shield electromagnetic waves during packaging of a semiconductor device formed on the semiconductor layer of the ultra-thin SOI layer.

  Separation from the second ion-implanted layer is achieved by separating the semiconductor layer formed on the semiconductor layer of the ultra-thin SOI layer and the semiconductor layer including all of the protruding connection electrodes and the supporting substrate from conductive ultraviolet light having no adhesive residue. It is desirable to carry out by pulling and peeling while holding with an irradiation curing type tape.

  Prevents cracking and chipping of ultra-thin semiconductor devices by holding and protecting the surface of the connection electrodes and semiconductor layers by pulling and separating the semiconductor layers from the substrate while holding them with the strong adhesive force of the ultraviolet irradiation curing type tape. can do. In addition, since the adhesive force is weakened by the irradiation of the ultraviolet irradiation curing type tape with the ultraviolet light and the tape is easily separated, the tape can be removed without separation after separation. Further, since the ultraviolet irradiation curing type tape is conductive, it is possible to prevent the semiconductor device formed on the semiconductor layer from being damaged by static electricity at the time of peeling.

  Separation from the ion implantation layer can be performed by laser processing or laser water jet processing on the rotating ion implantation layer. In particular, when the kerf is formed, if separation is performed by laser processing or laser water jet processing on the ion implantation layer, separation from the ion implantation layer can be performed more effectively.

The porous semiconductor layer formed on the seed substrate preferably has a higher porosity than the porous semiconductor layer formed on the support substrate. Further, in the second method for manufacturing an ultra-thin electro-optical display device according to the present invention, it is preferable that the porous semiconductor layer formed on the seed substrate be thicker than the porous semiconductor layer formed on the support substrate. Thereby, the porosity and the thickness of the porous semiconductor layers of the seed substrate and the support substrate can be reduced, and during the process of forming the display element and the peripheral circuit, the thermal expansion of the porous semiconductor layer formed on the support substrate by the single-crystal semiconductor layer is performed. Adverse effects such as warpage distortion can be prevented.
In the method of manufacturing an ultra-thin semiconductor device according to the present invention, it is preferable that the periphery of the surface of the support substrate including the ultra-thin SOI layer after the separation of the seed substrate is C-chamfered. Accordingly, not only in the double porous semiconductor layer separation method but also in the double ion implantation layer separation method and the porous / ion implantation layer separation method, the surface of the support substrate including the ultra-thin SOI layer after the seed substrate is separated By chamfering the peripheral portion, chipping, cracking and cracking of the ultra-thin SOI layer at the peripheral portion can be prevented.
The angle and width of the C chamfer can be set arbitrarily, and it is preferable to use a grindstone, diamond wheel, laser or the like. Further, if necessary, light etching may be performed with a hydrofluoric acid-based etchant to remove Si dust and microcracks.

  Further, in the method for manufacturing an ultra-thin semiconductor device of the present invention, the diameter of the seed substrate on which the single-crystal semiconductor layer is formed via the porous semiconductor layer is set such that the single-crystal semiconductor layer and the insulating layer are formed via the porous semiconductor layer. After bonding larger or smaller than the diameter of the supporting substrate, high pressure fluid jet injection or laser water jet injection is applied to the porous semiconductor layer of the seed substrate from the sideways or oblique direction to separate the seed substrate, and the seed is separated. It is desirable that the periphery of the surface of the support substrate including the ultra-thin SOI layer after the substrate separation be C-chamfered. Thereby, high pressure fluid jet injection or laser water jet injection is applied to the porous semiconductor layer of the seed substrate from the sideways or oblique direction to separate the seed substrate, and at the same time, high pressure fluid jet injection to the porous semiconductor layer of the support substrate is performed. Alternatively, since the impact force of laser water jet injection is weakened, the support substrate does not separate from the porous semiconductor layer of the support substrate.

  By the way, an insulating layer forming the SOI layer is a silicon oxide film, a silicon oxynitride film, a stacked film of silicon oxide and silicon nitride, a silicon nitride film, a stacked film of silicon oxide, silicon nitride, and silicon oxide in order. In addition, it is desirable to include at least one of the aluminum oxide films, and it is particularly desirable to include a nitride silicon film. Accordingly, it is possible to prevent the halogen element from penetrating from the support substrate side to the semiconductor layer during the packaging or the semiconductor device forming process. Further, during the semiconductor device forming process, the semiconductor layer can be prevented from being affected by the thermal expansion of the porous layer formed on the supporting substrate.

  In the method for manufacturing a semiconductor device of the present invention, after forming the kerf, a resin protective film is formed on the surface of the semiconductor layer including all of the semiconductor device and the protruding connection electrode formed on the semiconductor layer and in the kerf, The surface of the resin protective film is polished to expose the protruding connection electrodes, and after the support substrate is separated, the resin protective film in the kerf is pelletized and divided, thereby forming an ultra-thin resin-sealed one surface. A semiconductor device is obtained.

  Here, it is desirable to separate the support substrate by the same method as described above. As described above, it is desirable to separate the support substrate in a state where the semiconductor layer including the exposed protruding connection electrodes is covered with a conductive ultraviolet-ray-curable tape having no adhesive residue. Furthermore, by performing the pelletizing division including the ultraviolet irradiation curing type tape, the ultra-thin semiconductor device after division can be separated from the ultraviolet irradiation curing type tape by ultraviolet irradiation at any time, so that holding, storage, transportation, etc. It is possible to do.

  Furthermore, a plurality of ultrathin semiconductor devices after the pelletization division are laminated and fixed via an insulating adhesive, and a via hole is formed to penetrate the protruding connection electrode of each laminated ultrathin semiconductor device, By filling and fixing the via hole with a conductive paste, an ultra-multilayer semiconductor chip size package in which ultra-thin semiconductor devices are stacked and required electrical connection resistance and mechanical strength are secured is obtained.

  An apparatus for manufacturing a semiconductor device according to the present invention is a semiconductor device manufacturing apparatus for obtaining a semiconductor device by applying a high-pressure fluid jet ejected from a fine nozzle to a separation layer of a rotating substrate to obtain a semiconductor device. A jig having a slit for controlling the width of the high-pressure fluid jet is provided between the nozzle and the nozzle. The separation layer in the high-pressure fluid jet separation includes a porous layer and an ion-implanted layer subjected to release annealing.

  According to this manufacturing apparatus, it is possible to control the width of the high-pressure fluid jet ejected from the fine nozzle by the slit and accurately hit the target separation layer. Thereby, as in the case of the semiconductor device of the present invention, in a case where a plurality of porous layers are formed as a plurality of separation layers on one substrate, the high-pressure fluid is accurately applied only to a target porous layer among the plurality of porous layers. It is possible to separate the target porous layer from the target porous layer by applying a jet without affecting other porous layers.

  Further, an apparatus for manufacturing an ultra-thin semiconductor device according to the present invention obtains an ultra-thin semiconductor device by applying a laser beam irradiated from a laser output section to a separation layer of a rotating substrate to separate the substrate.

  According to this manufacturing apparatus, it becomes possible to accurately irradiate the laser beam to the target separation layer and to separate the laser beam from the target separation layer without affecting other separation layers. The separation layer in the laser processing separation includes a porous layer and an ion-implanted layer that has not been subjected to release annealing.

Further, an apparatus for manufacturing an ultra-thin semiconductor device according to the present invention obtains an ultra-thin semiconductor device by applying a water jet including a laser beam irradiated from an output section to a separation layer of a rotating substrate and separating the substrate. .
According to this manufacturing apparatus, it is possible to accurately apply the water jet including the laser beam to the target separation layer and separate the target from the target separation layer without affecting other separation layers. The separation layer in the laser water jet processing separation includes a porous layer and an ion-implanted layer that has not been peeled and annealed.

  According to the present invention, the following effects can be obtained.

(1) A seed substrate made of a semiconductor and a supporting substrate are bonded together via an insulating layer, the seed substrate is separated from the porous layer formed on the seed substrate, and the supporting substrate is separated from the porous layer formed on the supporting substrate. (Double porous layer separation method), a seed substrate made of a semiconductor and a supporting substrate are bonded together via an insulating layer, and the seed substrate is separated from the ion-implanted layer formed on the seed substrate and formed on the supporting substrate. (Double ion implantation layer separation method), or an ion implantation layer formed on a seed substrate by bonding a seed substrate made of a semiconductor and a support substrate via an insulating layer. The structure (separation method of porous layer and ion-implanted layer) that separates the seed substrate from the porous substrate and the porous substrate formed on the support substrate Thinner than the semiconductor chip thickness of about 50μm was Tsu, it can be produced, for example an ultra-thin SOI substrate of about 1 to 10 [mu] m. Then, an ultra-thin semiconductor device can be obtained by forming a semiconductor device on this ultra-thin SOI substrate. In the ultrathin semiconductor device thus obtained, the thickness of the ultrathin SOI layer is about 10 μm or less, so that the heat dissipation of the semiconductor device formed on this semiconductor layer is remarkably improved, and the characteristics of the ultrathin semiconductor device are improved. Improvement can be realized. With the ultra-thin SOI substrate of the present invention, which can be controlled to an arbitrary thickness, the leakage current can be suppressed low, the speed of the LSI can be increased, the power can be reduced by low-voltage operation, and the cost can be reduced. As a result, a small, lightweight, ultra-thin, and high-performance semiconductor device can be realized, which contributes to the realization of small, lightweight, and thin electronic products.
For example, unlike the lattice constant of the single-crystal Si layer, after forming a strain-applied semiconductor SiGe layer for applying strain to the single-crystal Si layer on the porous Si layer, the strain-applied semiconductor SiGe layer is seeded by semiconductor epitaxial growth. After forming a single crystal Si layer of a strain channel layer or forming a SiGe layer of a strain applying semiconductor on a single crystal Si substrate by semiconductor epitaxial growth, a single crystal of the strain channel layer is seeded using the SiGe layer of the strain applying semiconductor as a seed by semiconductor epitaxial growth. A strain is applied to the strained channel semiconductor layer by forming a Si layer or forming a strained semiconductor SiGe layer on the insulating layer, and forming a strained channel single crystal Si layer using the strained semiconductor SiGe layer as a seed. When applied, the band structure changes, and as a result, degeneracy is released and electron scattering occurs. Suppressed and can further increase the electron mobility, so that a high electron / hole mobility that achieves a significant improvement of about 1.76 times the electron mobility as compared with the single crystal semiconductor layer of the conventional strain-free channel layer. A high-performance, high-definition, high-quality ultra-thin semiconductor device of a MOSTFT having a high driving capability is realized. At this time, the germanium concentration in the strain-applying semiconductor layer gradually increases from the contact surface of the porous Si layer, from the contact surface of the single-crystal Si substrate, or from the contact surface of the insulating layer, and increases. By setting the gradient composition to a desired concentration, for example, 20 to 30%, a desired and significant improvement in electron mobility is realized.

(2) A porous layer is formed on a support substrate, a semiconductor layer is formed on the support substrate via the porous layer, and at least a porous layer is formed from the semiconductor layer along a dividing line when dividing into each ultrathin semiconductor device. After the kerf is formed up to the porous layer and the kerf is formed, the support substrate is separated from the porous layer (porous layer separation method), or the semiconductor layer is formed on the surface of the support substrate, Forming an ion-implanted layer at a predetermined depth, performing annealing treatment for stripping the ion-implanted layer, and forming a kerf from the semiconductor layer to at least the ion-implanted layer along a dividing line when dividing into each ultrathin semiconductor device Then, the support substrate is separated from the ion-implanted layer after forming the kerfs (ion-implanted layer separation method), so that the thickness of the semiconductor chip is about 50 μm, which is the limit of the conventional mechanical and chemical processing methods. Thin, eg 1-1 The μm approximately no insulating layer ultra-thin semiconductor device can be manufactured. The ultra-thin semiconductor device thus obtained has a semiconductor layer thickness of about 10 μm or less, so that the heat dissipation of the semiconductor device formed on this semiconductor layer is remarkably improved, and the characteristics of the ultra-thin semiconductor device are improved. it can. As a result, a small, lightweight, ultra-thin, and high-performance semiconductor device can be realized, which contributes to the realization of small, lightweight, and thin electronic products.

(3) In each manufacturing method, the seed substrate and the support substrate are separated from each other while being held by an ultraviolet irradiation curing type tape, thereby strongly holding the seed substrate and the support substrate and protecting the surfaces of the seed substrate and the support substrate. It can be separated in the state where it was done. Further, after separation, the UV-curable tape can be easily removed by UV-curing, so that the yield and production of ultra-thin semiconductor devices can be prevented by preventing cracks, chips, and cracks in the ultra-thin semiconductor layer and ultra-thin SOI layer. The nature becomes high.

(4) The structure in which the separation of the support substrate is performed after forming a kerf from the semiconductor layer to at least the porous layer or the second ion-implanted layer along the dividing line at the time of dividing into each ultrathin semiconductor device, Since the ultra-thin SOI layer and ultra-thin semiconductor layer separated from the supporting substrate in the step of (1) are previously pelletized and divided, high-pressure fluid jet injection separation, laser processing separation, laser water jet processing separation or tensile separation from the lateral direction For example, the ultra-thin SOI layer and the ultra-thin semiconductor layer can be efficiently separated without generating cracks, chips, or cracks. Thus, an ultra-thin semiconductor device can be manufactured with high yield and high productivity.

(5) In each manufacturing method, the peeled seed substrate and the support substrate can be reused, so that the cost can be reduced.

(6) By including a nitride-based silicon film in the insulating layer constituting the ultra-thin SOI layer, it is possible to prevent the halogen element from penetrating from the support substrate side to the semiconductor layer during packaging or device processing. it can. Further, it is possible to reduce or prevent the semiconductor layer from being warped and distorted due to the expansion of the porous layer formed on the supporting substrate during the device process. As a result, characteristics, yield, and quality are improved.

(7) By adding n-type or p-type impurities to the porous layer of the support substrate to make it conductive, it is possible to prevent electrostatic damage during packaging and to shield electromagnetic waves. The quality and reliability of the semiconductor device are improved.

(8) There is a problem of cracking, chipping, cracking, workability, etc. of the substrate in the formation of the extraction electrode after ultra-thinning. However, in the present invention, in the case of a thick substrate, bumps mainly composed of plating or stud bumps such as Au wires are used. After the protruding connection electrodes are formed, kerfs are formed, separated and ultrathin, so that yield and quality can be improved and productivity can be increased.

(9) After forming the kerfs in each of the manufacturing methods, the semiconductor layer including all the semiconductor devices formed on the semiconductor layer and the protruding electrodes is covered with a conductive ultraviolet-ray-curing tape having no adhesive residue. By separating the supporting substrate, the semiconductor layer divided by the kerfs is held with strong adhesive force, and the semiconductor device formed on the semiconductor layer and the surface of the protruding connection electrode are protected while the ultra-thin semiconductor is protected. Since the devices can be separated, cracking, chipping, and cracking of the ultra-thin semiconductor device divided by the kerfs can be prevented, and electrostatic damage to semiconductor devices and electrode connection failure can be prevented. Further, after separation, the adhesive can be easily removed by UV irradiation curing without adhesive residue, so that the yield and productivity are increased.

(10) In the double porous layer separation method, by setting the thickness of the semiconductor layer formed on the seed substrate to be equal to or less than the thickness of the semiconductor layer formed on the support substrate, the thickness of the porous layer during the semiconductor device manufacturing process is reduced. Expansion and the like due to oxidation can reduce or prevent distortion in a semiconductor layer for manufacturing a semiconductor device, thereby improving yield and quality.

(11) After forming a kerf in each manufacturing method, a resin protective film is formed on the surface of the semiconductor layer including all of the semiconductor device formed on the semiconductor layer and the protruding connection electrode and in the kerf. The surface of the substrate is polished to expose the protruding connection electrodes, and after the support substrate is separated, the resin protective film in the kerf is pelletized and divided to provide a high-quality resin seal that is protected and held on one side by resin. A stop-type ultra-thin semiconductor device can be manufactured with high yield and high productivity.

(12) By separating the supporting substrate after covering the semiconductor layer including the protruding connection electrodes exposed in each of the manufacturing methods with no adhesive residue, and separating the supporting substrate, The entire semiconductor layer can be separated from the supporting substrate and further divided into pellets while the entire semiconductor layer is held, and the exposed protruding extraction electrode and the surface of the semiconductor layer are protected, so that it is ultrathin. Cracking and chipping of the semiconductor device can be prevented, and reliable pelletization can be obtained with high productivity. Furthermore, since semiconductor characteristics failure due to electrostatic damage can be prevented, high yield and quality can be obtained.

(13) A plurality of ultrathin semiconductor devices after the pelletization division are laminated with an adhesive and fixed with an adhesive, and a via hole is formed to penetrate the protruding connection electrode of each laminated ultrathin semiconductor device. By filling and fixing a conductive paste in the via hole, mechanical and electrical connection can be obtained by contact in the thickness direction of the electrode, so that an ultra-multilayer chip size package with high quality and high reliability can be obtained.

(14) The ultra-thin semiconductor device is pelletized while being held on the UV-irradiation-curable tape by performing the pelletizing division including the UV-irradiation-curable tape, and can be separated at any time by UV-irradiation curing. Storage and transportation can be performed in the state of supporting the ultraviolet irradiation-curable tape. Thus, cracking and chipping of the ultra-thin semiconductor device during holding, storage, transportation, and the like can be prevented.

(A) Double Porous Layer Separation Method In the present embodiment, separation is performed from a double-formed porous Si layer (separating a seed substrate from a porous Si (silicon) layer formed on a seed substrate, A method of manufacturing an ultra-thin semiconductor device by separating a supporting substrate from a porous Si layer formed in step (1) will be described. FIG. 1 to FIG. 7 are manufacturing process diagrams of an ultra-thin semiconductor device by a double porous Si layer separation method according to an embodiment of the present invention.

(1) A porous Si layer is formed on a seed Si wafer substrate (hereinafter, referred to as “seed substrate”) 20 and a handle Si wafer substrate (hereinafter, referred to as “support substrate”) 25 by anodization (see FIG. 1). . At this time, a highly porous Si layer 22 having a higher porosity than the supporting substrate 25 is formed on the seed substrate 20.

[1] First, 1 × 10 ¹⁹ boron is deposited on a seed substrate 20 of p-type single-crystal Si (resistivity: 0.01 to 0.02 Ω · cm) by chemical vapor deposition (CVD) of monosilane gas and diborane gas. A p-type impurity is added at a concentration of about atoms / cm ³ to form a high-concentration epitaxially grown single-crystal Si layer (corresponding to a low-porous Si layer 21 described later) having a thickness of about 10 μm.

[2] A p-type impurity is added to the surface of the high-concentration layer at a concentration of about 5 × 10 ¹⁴ atoms / cm ³ by CVD using monosilane gas and diborane gas, and a low-concentration epitaxially grown single-crystal Si layer having a thickness of about 20 μm is added. (Corresponding to a highly porous Si layer 22 described later).

[3] Further, a p-type impurity is added to the surface of the low-concentration layer at a concentration of about 5 × 10 ¹⁹ atoms / cm ³ by CVD using monosilane gas and diborane gas, and a single-crystal Si layer having a high concentration of about 5 μm is epitaxially grown. A layer (corresponding to a low-porous Si layer 23 described later) is formed.

[4] Thereafter, by an anodizing method, for example, using a mixed solution in which a 50% hydrogen fluoride solution and ethyl alcohol are mixed in a volume ratio of 2: 1 to the electrolytic solution at a current density of 10 mA / cm ² for about 5 minutes Then, the low-porosity Si layers 21 and 23 having a low porosity are formed in the high-concentration layer, and the high-porosity Si layer 22 having a high porosity is formed in the low-concentration layer.

[5] Similarly to the above, a support substrate 25 of p-type single crystal Si (resistivity: 0.01 to 0.02 Ω · cm) is formed on a support substrate 25 of about 1 × 10 ¹⁹ atoms / cm ³ of boron by a CVD method using a monosilane gas or a diborane gas. A p-type impurity is added at a concentration to form a high-concentration epitaxially grown single-crystal Si layer having a thickness of about 10 μm (corresponding to a low-porous Si layer 26 described later).

[6] A p-type impurity is added to the surface of the high-concentration layer at a concentration of about 1 × 10 ¹⁵ atoms / cm ³ of boron by a CVD method using silane gas and diborane gas, and a low-concentration epitaxially grown single-crystal Si layer having a thickness of about 2 μm is formed. (Corresponding to a highly porous Si layer 27 described later).

[7] Further, a p-type impurity is added to the surface of the low-concentration layer at a concentration of about 3 × 10 ¹⁹ atoms / cm ³ by CVD using a monosilane gas or a diborane gas, and single-crystal Si is epitaxially grown at a high concentration of about 10 μm. A layer (corresponding to a low-porous Si layer 28 described later) is formed.

[8] Thereafter, by an anodizing method, for example, using a mixed solution obtained by mixing a 50% hydrogen fluoride solution and ethyl alcohol in a volume ratio of 2: 1 to the electrolytic solution at a current density of 10 mA / cm ² for about 5 minutes The low-porous Si layers 26 and 28 having low porosity are formed in the high-concentration layer, and the high-porosity Si layer 27 having high porosity is formed in the low-concentration layer.

  When the porous layer is formed by the anodization method, the porous layer can be composed of a plurality of layers having different porosity. For example, as described above, in addition to the three-layer structure in which the first low-porous Si layer 21, the high-porous Si layer 22, and the second low-porous Si layer 23 are sequentially formed on the seed substrate 20, A two-layer structure in which a high-porous Si layer 22 and a low-porous Si layer 23 are sequentially formed on the substrate 20 may be used. Similarly, the support substrate 25 may have a two-layer structure in which a highly porous Si layer 27 and a low porous Si layer 23 are sequentially formed on the support substrate 25.

  At this time, the porosity of the high porous Si layer is in the range of 40 to 80%, and the porosity of the low porous Si layer is in the range of 10 to 30%. The thickness of each of the plurality of layers having different porosity can be arbitrarily adjusted by changing the current density and time during anodization and the type or concentration of the formation solution during anodization.

  After the porous Si layer is formed, the inner wall of the porous Si hole is preferably oxidized by about 1 to 3 nm by performing dry oxidation at about 400 ° C. Thereby, it is possible to prevent the porous Si from undergoing a structural change due to the subsequent high-temperature treatment.

In addition, for the low-porous Si layers 23 and 28, the impurity concentration should be high (1 × 10 ¹⁹ atoms / cm ³ or more) and the porosity should be as low as possible (about 10 to 30%). preferable. This is because it is necessary to form an excellent crystalline single crystal Si layer 24 on these low porous Si layers 23 and 28 for forming a semiconductor device described later.

At this time, in order to reduce distortion of a single-crystal Si layer 24 (see FIG. 2) described later,
Porosity: Low porous Si layer 23 <Low porous Si layer 28
Film thickness: low porous Si layer 23 <low porous Si layer 28
It is preferred that

In addition, in order to facilitate separation of the seed substrate 20 in a later step, and to prevent the support substrate 25 from being separated when the seed substrate 20 is separated,
Porosity: Highly porous Si layer 22> Highly porous Si layer 27
Film thickness: Highly porous Si layer 22> Highly porous Si layer 27
It is preferred that

  In addition, in the dissolution reaction of Si in anodization, holes are necessary for the anodic reaction of Si in the hydrogen fluoride solution. Therefore, it is preferable to use P-type Si which is easily made porous, but is not limited thereto. Not something.

  The seed substrate 20 and the support substrate 25 are not only monocrystalline Si substrates manufactured by the CZ (Czochralski) method, the MCZ (Magnetic Field Applied Czochralski) method, the FZ (Floating Zone) method, and the like, but also have a hydrogen-annealed substrate surface. A processed single crystal Si substrate, an epitaxial single crystal Si substrate, or the like can be used. Of course, a single crystal compound semiconductor substrate such as a SiGe substrate, a SiC substrate, a GaAs substrate, or an InP substrate can be used instead of the single crystal Si substrate.

(2) Epitaxially grown single-crystal Si layers 24 and 29 as semiconductor layers are formed on both the seed substrate 20 and the support substrate 25, and at least one of them is an SiO ₂ oxide film or SiO ₂ / Si as an insulating layer 30. _A 3N ₄ / SiO ₂ laminated film is formed (see FIG. 2). The point here is that the thickness of the single crystal Si layer 24 forming one or both of the semiconductor element and the semiconductor integrated circuit is made smaller than the thickness of the single crystal Si layer 29.

  First, in a CVD epitaxial growth apparatus, prebaking is performed at about 1000 to 1100 ° C. in a hydrogen atmosphere to seal the holes on the surfaces of the low-porous Si layers 23 and 28 to flatten the surface. Thereafter, the temperature is lowered to 1020 ° C., and CVD using monosilane gas as a source gas is performed to form epitaxially grown single crystal Si layers 24 and 29 having a thickness of about 1 to 10 μm. At this time, the impurity concentration may be controlled by appropriately adding diborane, phosphine gas or the like.

In forming the single crystal Si layers 24 and 29 by the CVD method, a source gas such as SiH ₂ Cl ₂ , SiHCl ₃ , and SiCl ₄ can be used in addition to monosilane (SiH ₄ ). The method for forming the single crystal Si layers 24 and 29 is not limited to the CVD method, but may be an MBE method, a sputtering method, or the like.

  Here, the single-crystal Si layer 24 epitaxially grown on the seed substrate 20 for device fabrication has a thickness equal to or less than the thickness of the single-crystal Si layer 29 epitaxially grown on the other support substrate 25. This is to reduce and prevent the occurrence of distortion in the epitaxially grown single crystal Si layer 24 for device fabrication due to expansion of the highly porous Si layer 27 due to oxidation during the device process.

The thickness of the epitaxially grown single crystal Si layer 24 for device fabrication is arbitrarily changed depending on the device to be fabricated. The effective thickness after forming the SiO ₂ oxide film (insulating layer 30) is about 50 nm in the case of a MOS-LSI (Metal-Oxide Semiconductor Large Scale Integrated circuit). In this case, it is about 5 to 6 μm. The thickness of the single-crystal Si layer 29 is desirably about 5 to 10 μm because it will eventually become a gantry.

The thickness of the SiO ₂ oxide film (insulating layer 30) of the single-crystal Si layer 29 is desirably 200 to 500 nm so as not to be affected by the thermal oxidation distortion of the porous layer 27. If the thickness is increased to about μm by thermal oxidation for a long time, the single crystal Si layer 29 is warped due to the thermal oxidation distortion of the porous layer 27.

Note that the insulating layer 30 (SiO ₂ oxide film) is not only a silicon oxide film (SiO ₂ ) but also a silicon oxide film / nitride formed by forming a silicon nitride film on the single crystal Si layer 29 by low-pressure CVD and thermally oxidizing the silicon nitride film. A stacked film of silicon films (for example, SiO ₂ ; 400 nm / Si ₃ N ₄ ; 50 nm) or a silicon oxide film / silicon nitride film / silicon oxide film (for example, SiO ₂ ; 200 nm / Si ₃ N ₄ ; 50 nm / SiO ₂ ; 200 nm). Alternatively, a silicon oxynitride film (SiON), a silicon nitride film (Si ₃ N ₄ ), an aluminum oxide film, or a composite film thereof can be used.

  In short, the presence of the nitrided silicon film having an appropriate thickness allows the halogen element to penetrate from the support substrate 25 side and contaminate the single crystal Si layer 24 during packaging in a later step or a semiconductor device forming process. Can be prevented. Further, it is possible to reduce and prevent the occurrence of warping distortion in the epitaxially grown single-crystal Si layer 29 for manufacturing a semiconductor device due to expansion of the highly porous Si layer 27 due to oxidation during the semiconductor device formation process.

  As a countermeasure against electrostatic damage and electromagnetic wave shielding when packaging a semiconductor device formed on the single-crystal Si layer 29, an n-type or p-type impurity having an arbitrary concentration is added to the low-porous Si layer 28 during ion implantation or epitaxy growth. Is added, and activated at the time of forming an oxide film to make it conductive. On the other hand, it is desirable to add an arbitrary concentration of impurities to the single crystal Si layer 24 according to the type of the semiconductor device.

By the way, as one of means for increasing electron mobility, a technique of applying a strain to a channel semiconductor layer is known. This is because, when strain is applied to the channel semiconductor layer, the band structure changes, and as a result, degeneration is released and electron scattering is suppressed, so that electron mobility can be increased.
Specifically, a strain-applying semiconductor layer of a mixed crystal layer made of a material having a larger lattice constant than Si on a single crystal Si substrate, for example, a SiGe mixed crystal layer having a Ge concentration of 20 to 30% (hereinafter, referred to as a SiGe layer) ) Is formed, and a single-crystal Si layer as a channel semiconductor layer is formed on the SiGe layer, whereby a strained single-crystal Si layer (hereinafter referred to as a strained channel layer) is formed due to a difference in lattice constant. . It has been reported that the use of this strained channel layer can achieve a significant improvement in electron mobility of about 1.76 times compared to the case of using an unstrained channel layer. (J. Welser, J. L. Hoyt, S. Takagi, and J. F. Gibbons, IEDM94-373)

Therefore, for example, when a single-crystal Si layer 24 as a strain applying semiconductor layer which is a SiGe layer having a Ge concentration of 20 to 30% and a single-crystal Si layer as a strain channel layer is formed thereon, A MOSTFT display section and peripheral circuits that achieve a significant improvement in electron mobility of about 1.76 times as compared with the single-crystal Si layer of the channel layer are realized, so that high-performance, high-definition, high-quality ultra-thin electricity An optical display device is realized.
If the Ge composition ratio is large, it is better. If the Ge composition ratio is much less than 0.2, a remarkable improvement in the mobility of the MOSTFT cannot be expected. If the Ge composition ratio exceeds 0.5, the SiGe layer surface unevenness increases and the film quality deteriorates. However, about 0.3 is preferable.
The Ge concentration is gradually increased in the single crystal Si layer 12 as a strain applying semiconductor layer, which is a SiGe layer, to have a gradient composition having a desired concentration on the surface, for example, a Ge concentration of 20 to 30%. It is preferable to form a single-crystal Si layer as a strain channel layer by Si epitaxial growth using the layer as a seed.

Examples of the method of forming the SiGe layer include an epitaxial growth method such as a CVD method and an MBE method, a liquid phase growth method such as an LPE (Liqud Phase Epitaxy) method, and a solid phase growth method of a polySiGe layer and an amorphous SiGe layer. However, any other crystal growth method that can control the Ge composition ratio may be used.
Examples of the Si source include monosilane (SiH ₄ ), disilane (Si ₂ H ₆ ), trisilane (Si ₃ H ₈ ) and tetrasilane (Si ₄ H ₁₀ ), which are hydride raw materials, and dichlorosilane (SiH ₂ Cl), which is a halide raw material. ₂ ), trichlorosilane (SiHCl ₃ ), silicon tetrachloride (SiCl ₄ ), and the like, and Ge raw materials such as germane (GeH ₄ ), germanium tetrachloride (GeCL ₄ ), and germanium tetrafluoride (GeF ₄ ) are suitable. .

  Instead of the SiGe layer as the strained semiconductor layer, a mixed crystal layer of Si and other elements such as SiC or SiN, a Group 2-6 mixed crystal layer such as a ZnSe layer, or a 3-5 layer such as GaAs or InP. A mixed crystal layer made of materials having different lattice constants, such as a group mixed crystal layer, may be used.

(3) The seed substrate 20 and the support substrate 25 are bonded (see FIG. 3).
At room temperature, the surfaces of the single-crystal Si layer 24 of the seed substrate 20 and the surface of the insulating layer 30 of the support substrate 25 are brought into contact with each other and bonded by Van der Waals force. Thereafter, a heat treatment is performed at 400 ° C. for 30 minutes for covalent bonding to strengthen the bonding. The heat treatment is performed in nitrogen, an inert gas, or a mixed gas of nitrogen and an inert gas. At this time, it is confirmed that there is no dust or dirt on the surfaces of both substrates. In addition, when there is a foreign substance, it is separated and washed.

  Alternatively, two superimposed substrates are set in a reduced pressure heat treatment furnace, and are held at a predetermined pressure (for example, 133 Pa (1 Torr) or less) by evacuation, and are brought into close contact with each other by a pressure when a break occurs to the atmospheric pressure after a certain period of time. Alternatively, a continuous operation of performing heat treatment bonding by heating and heating in nitrogen, an inert gas, or a mixed gas of nitrogen and an inert gas continuously may be performed.

(4) The seed substrate 20 is separated from the highly porous Si layer 22 by a high-pressure fluid jet spray separation method such as a water jet or an air jet (see FIG. 4). At this time, it is important that the support substrate 25 is not separated from the highly porous Si layer 27. The separation is performed in a state where the seed substrate 20 and the support substrate 25 are held by an ultraviolet irradiation curing type tape (hereinafter, referred to as “UV tape”) 17.

  In the present embodiment, a high-pressure fluid jet spray separation apparatus as an apparatus for manufacturing an ultra-thin semiconductor device shown in FIG. 26 is used. FIG. 26 is a schematic sectional view of a high-pressure fluid jet spray separation apparatus according to an embodiment of the present invention.

  The high-pressure fluid jet spray-peeling apparatus shown in FIG. 26 includes a pair of holders 81a and 81b that vacuum-suction and rotate a substrate from above and below, and a fine nozzle 83 that sprays a high-pressure fluid jet. The guard ring stopper 80 is a cylindrical jig surrounding the holders 81a and 81b. The guard ring stopper 80 has a slit hole 84 having a diameter of about 10 to 50 μm through which the width of the high-pressure fluid jet ejected from the fine nozzle 83 is controlled and passed. The diameter of the slit hole 84 is determined based on the correlation between the water pressure and the wind pressure of the high-pressure fluid jet.

  In such a high-pressure fluid jet spray-peeling apparatus, for example, a base body in which the seed substrate 20 and the support substrate 25 shown in FIG. 3 are bonded between holders 81a and 81b. Two high-porous Si layers 22 and 27 are formed on the substrate. The layer (separation layer) to be separated here is the high-porous Si layer 22. In FIG. 26, illustrations other than the highly porous Si layers 22 and 27 are omitted for simplicity.

  Here, the height of the guard ring stopper 80 and the heights of the seed substrate 20 and the support substrate 25 sandwiched between the holders 81a and 81b are adjusted so that the high-pressure fluid jet to be separated from the high-pressure fluid jet ejected from the fine nozzle 83 is separated. Fine-tune to hit 22 accurately. Thereafter, the holders 81a and 81b are rotated, and the pressure of the high-pressure fluid jet ejected from the fine nozzle 83 is applied to the high-porous Si layer 22 to separate the seed substrate 20.

  At this time, the width of the high-pressure fluid jet ejected from the fine nozzle 83 is controlled by the slit hole 84 of the guard ring stopper 80, and the height thereof is finely adjusted so as to accurately hit the highly porous Si layer 22 to be separated. Therefore, it does not hit the portion other than the target high porous Si layer 22 so strongly that it is separated. Thereby, even when two high porous Si layers 22 and 27 are present as shown in FIG. 26, the high porous Si layers 22 and 27 are separated from the target high porous Si layer 22 without affecting the other high porous Si layers 27. be able to.

  Alternatively, a laser processing and peeling apparatus (not shown) that separates the separation layer of the rotating substrate by applying a laser beam irradiated from a laser output unit may be used. The only difference between this laser processing peeling device and the above-mentioned high-pressure fluid jet spray peeling device is that the laser output unit is equivalent to the combination of the above-mentioned fine nozzle 83 and slit hole 84, and the other components are the same. It is.

  In this laser processing peeling apparatus, the high-porous Si layer 22 is separated from the high-porous Si layer 22 by laser processing (ablation processing, thermal processing, or the like) by irradiating one or more lasers from the lateral direction of the rotating substrate. can do.

  Here, as the laser, a laser beam such as a visible light, a near ultraviolet ray, a far ultraviolet ray, a near infrared ray, a far infrared ray or the like comprising a carbon dioxide laser, a YAG (Yttrium Aluminum Garnet) laser, an excimer laser, a harmonic modulation laser, or the like can be used. .

In laser processing, at least one or more pulse wave or continuous wave laser light to be absorbed by the processing object is irradiated, and a method of separating by thermal processing or ablation processing, and having a wavelength transparent to the processing object at least one pulse wave or continuous wave near-infrared laser (Nd: YAG laser, Nd: YVO ₄ laser, Nd: YLF laser, a titanium sapphire laser, etc.) irradiates focused within the object, and multi There is a method in which an optical damage phenomenon due to photon absorption is generated to form a modified region (for example, a crack region, a melt-processed region, a refractive index change region, etc.), and separation is performed with a relatively small force starting there. It may be used properly according to.

In general, in the latter case, the light-condensing point is adjusted inside the object to be processed, for example, a single-crystal semiconductor substrate, and the peak power density at the light-condensing point (electric field intensity at the light-condensing point of the pulsed laser light) is 1 × 10 ^8. When the laser beam is irradiated under the condition of (W / cm ² ) or more and the pulse width is 1 μS or less, an optical damage phenomenon due to multiphoton absorption occurs inside the object to be processed, and this optical damage causes heat distortion inside. Is induced, thereby forming a modified region, for example, a crack region therein, which is separated by a relatively small force starting from the modified region. However, compared to a single crystal semiconductor substrate, a single crystal of a porous semiconductor layer or an ion implantation layer described later is used. In the case of a semiconductor layer, an optical damage phenomenon due to multiphoton absorption is caused by the peak power density described below to form a modified region (for example, a crack region, a melt-processed region, a refractive index change region, etc.). Are possible, it is easy separation from the porous semiconductor layer and later ion implanted layer.

In the case of laser processing, the laser beam is focused on the inside of the object to be processed (that is, the inside of the porous semiconductor layer or the ion implantation layer described later) by a condenser lens in any of the above methods, and the focus is gradually rotating. It can be separated by moving it inside the object to be processed. In particular, in the case of the present invention, since the object to be processed is a porous Si layer or an ion-implanted layer, the separation by the laser beam can be performed efficiently with high precision.
At this time, using a support jig which is fluid-cooled as necessary as described later, the support substrate is removed from the porous layer or the ion-implanted layer while cooling the ultrathin semiconductor substrate side on which the semiconductor device is formed via a UV tape. May be separated. Thereby, fluctuation or deterioration of the semiconductor characteristics can be prevented.

Further, a laser water jet processing / separation apparatus (not shown) for irradiating the high porous Si layer 11b of the rotating substrate with a laser water jet combining a laser beam and a water jet from an output unit to separate the laser water jet may be used. it can. The difference between this laser water jet processing peeling apparatus and the above-mentioned laser processing peeling apparatus and the high pressure fluid jet spray peeling apparatus corresponds to the laser water jet output unit in which the above-mentioned fine nozzle 83 and slit hole 84 are combined. It is only a thing, and others are almost the same configuration.
Laser waterjet processing The stripping method combines the advantages of waterjet and laser and utilizes the complete reflection of the laser light at the water / air interface. This is a method in which the light is reflected and guided in parallel, and separated by thermal processing or ablation processing by absorption of the laser light. Unlike a conventional laser processing method in which thermal deformation is a problem, the laser water jet is constantly cooled by water, so that the thermal effect on the separation surface, for example, thermal deformation, is reduced.
In the laser water jet processing separation method, for example, at least one or more pulse wave or continuous wave near-infrared laser (Nd: YAG laser, Nd: YVO ₄ laser, Nd: YLF laser, titanium sapphire laser, etc.) is optional. Processing of irradiating one or more laser water jets sealed in a water column of pure water or ultrapure water from the lateral direction of the highly porous Si layer 11b of the rotating substrate (ablation processing, thermal processing, etc.) ), It is possible to separate from the highly porous Si layer 11b.

As the laser, laser light such as visible light, near-infrared ray, far-infrared ray, near-ultraviolet ray, or far-ultraviolet ray, such as a carbon dioxide laser, a YAG laser, an excimer laser, and a harmonic modulation laser, can be used. The water column of the water jet having an arbitrary water pressure may be tap water. However, depending on the type of the laser, a water column of pure water or ultra-pure water that does not attenuate the laser without scattering it by diffuse reflection is desirable.
Further, the above-described high-pressure fluid jet spray peeling method, laser processing peeling method, and laser water jet peeling method are used for video signal processing LSI, memory LSI, CPU LSI, DSPLSI by peeling an ultra-thin semiconductor layer or an ultra-thin SOI semiconductor layer. It can also be used for manufacturing semiconductor devices such as audio signal processing LSIs, CCDs, CMOS sensors, and BiCMOS. In addition, high-pressure fluid jet injection, laser processing and laser water jet processing can be used to cut single-crystal or polycrystalline semiconductor substrates or transparent or opaque support substrates, or to slice rotating single-crystal or polycrystalline semiconductor ingots. Can also be used.

At this time, as shown in FIGS. 27A and 27B, the diameter of the seed substrate 20 on which the single crystal semiconductor layer 24 is formed via the porous semiconductor layers 21, 22, and 23 is changed to the porous semiconductor layers 26 and 27. , 28 are preferably slightly smaller or larger than the diameter of the support substrate 25 on which the single crystal semiconductor layer 29 is formed.
Then, for example, in the case of FIG. 27 (a) seed substrate diameter> supporting substrate diameter, from the sideways direction, and in the case of FIG. Is applied to the highly porous semiconductor layer 22 of the seed substrate 20 to separate the seed substrate 20, and at the same time, to prevent the support substrate from separating from the highly porous semiconductor layer 27 of the support substrate 25.

  Thereby, the porosity and the thickness of the porous semiconductor layers of the seed substrate 20 and the support substrate 25 can be reduced, and the single crystal semiconductor layer 24 is formed on the support substrate 25 during the process of forming the display element and the peripheral circuit. It is possible to prevent adverse effects due to thermal expansion of the elements 26, 27, and 28, for example, receiving warp distortion.

  Then, as shown in FIG. 28A, the peripheral portion of the surface of the support substrate 25 including the single crystal semiconductor layers 24 and 29 and the porous semiconductor layers 23, 26, 27, and 28 after the separation of the seed substrate is C-chamfered. By doing so, chipping, cracking, and cracking of the ultra-thin SOI layer and the like in the peripheral portion are prevented, so that yield and quality are improved, and cost reduction is realized.

(5) The surfaces of the low-porous Si layer 23 and the single-crystal Si layer 24 are etched by hydrogen annealing. FIGS. 5A and 5B show a state after etching. FIG. 5A shows an example in which SiO ₂ 30 a is formed as the insulating layer 30, and FIG. 5B shows SiO ₂ 30 a / Si ₃ N ₄ 30 b / SiO ₂ as the insulating layer 30. Examples in the case where 30a are formed are shown.

Here, all of the remaining high-porosity Si layer 22 and low-porosity Si layer 23 and a part of the surface of the single-crystal Si layer 24 are etched by hydrogen annealing to obtain a desired thickness and high flatness, for example, 50 nm thick. Is formed. Hydrogen annealing is performed at an etching rate of 0.0013 nm / min at 1050 ° C. and 0.0022 nm / min at 1100 ° C.
If necessary, the single-crystal Si layer 13 having a higher crystallinity and an arbitrary thickness may be further stacked by Si epitaxial growth using the hydrogen-annealed single-crystal Si layer 32 as a seed.
FIGS. 22A and 22B show a state in which the single-crystal Si layer 13 is laminated after the etching of the hydrogen annealing treatment. FIG. 22A shows an example in which SiO ₂ 36a is formed as the insulating layer 36, and FIG. Examples in the case where SiO ₂ 36a / Si ₃ N ₄ 36b / SiO ₂ 36a are formed are shown.
At this time, as described in (A), a single-crystal Si layer 32 as a strain applying semiconductor layer, which is a SiGe layer having a Ge concentration of, for example, 20 to 30%, is formed via the porous Si layer of the seed substrate. When the single-crystal Si layer 13 as a strain channel layer is formed on the single-crystal Si layer 32 after the substrate separation, the electron mobility is about 1.76 times as large as that of the conventional single-crystal Si layer 32 as the strain-free channel layer. As a result, the MOSTFT display section and peripheral circuits that achieve the improvement of the above are realized, so that a high-performance, high-definition, high-quality ultra-thin electro-optical display device is realized.
If the Ge composition ratio is large, it is better. If the Ge composition ratio is much less than 0.2, a remarkable improvement in the mobility of the MOSTFT cannot be expected. If the Ge composition ratio exceeds 0.5, the SiGe layer surface unevenness increases and the film quality deteriorates. However, about 0.3 is preferable.
The Ge concentration is gradually increased in the single crystal Si layer 32 as a strain applying semiconductor layer, which is a SiGe layer, to have a gradient composition having a desired concentration on the surface, and a strain channel layer is formed on the SiGe layer having the gradient composition. It is preferable to sequentially form the single-crystal Si layer 13 of FIG.
That is, the single crystal Si layer 32 of the strain applying semiconductor layer has a gradient composition from a portion in contact with the insulating layer 36 so that the Ge concentration gradually increases and the surface concentration becomes a desired value of, for example, a Ge concentration of 20 to 30%. Preferably, the single crystal Si layer 13 as the strain channel layer is formed by Si epitaxial growth using the single crystal Si layer 32 as the strain applying semiconductor layer, which is a SiGe layer having the gradient composition, as a seed.

(6) A semiconductor device such as an nMOSTFT (n-MOS Thin Film Transistor), a pMOSTFT (p-MOS TFT), a CMOSTFT, a bipolar TFT, a diode, a coil, a capacitor, etc., a MOS LSI, Semiconductors such as semiconductor integrated circuits such as Bip LSI, BiCMOS LSI (Bipolar Complementary Metal-Oxide Semiconductor LSI), CCD (Charge-Coupled Device), CMOS (Complementary Metal-Oxide Semiconductor) sensor, microprocessor, logic IC (Integrated Circuit), and memory A large number of devices are formed, and bump electrodes 15 are formed as a plurality of projecting connection electrodes connected to these semiconductor devices (see FIG. 6). When a compound semiconductor substrate is used as the seed substrate 20, a compound semiconductor device such as SiC, GaAs, and InP can be formed.

  The bump electrode 15 may be a peripheral bump around the chip, an inner area bump inside the chip, or a combination of both. The bump may be a bump mainly composed of plating or a stud bump such as an Au wire. In the case of a stud bump such as an Au wire, not only the single crystal Si layer 24 but also the single crystal Si layer Care should be taken not to damage the lower surface 29 and the low-porous Si layer 26. The height of the bump electrode 15 may be arbitrarily selected in accordance with a desired ultra-thin semiconductor device thickness, for example, in the range of 1 to 10 μm.

  In the case of forming a solder bump, a known formation method such as a super-jafit method, a super solder method, or a beam solder PC (pre-coat) method can be adopted.

  The Super Jafit method is, for example, to form an adhesive film by treating the surface of a barrier metal layer composed of a laminated film of Cr and Cu only on an Al pad with a chemical, and bringing the adhesive film into contact with solder powder. In this method, a solder bump is formed by applying solder powder to the surface of the barrier metal layer and performing heat treatment. According to the super-jafit method, bumps made of lead-free Sn-Ag-based or Sn-Zn-based solder are formed.

  With the super solder method, solder powder is not contained in the system, the solder is synthesized in the paste by the reaction of organic acid lead and organic acid tin, and deposited on the copper on the barrier metal layer surface similar to the above, to form solder bumps It is a method of forming. According to the super solder method, a bump made of Sn-Pb based solder is formed.

  The beam solder PC method is to form a film by depositing tin and lead on a copper surface by a substitution reaction in a galvanic cell composed of base copper, tin and lead, and form a solder bump by electrolytic plating. Is the way. According to the beam solder PC method, bumps made of Sn-Pb-based solder are formed.

(7) A cutting line 16 is formed by dicing at least into the low-porous Si layer 26 in a dividing line at the time of dividing into each ultra-thin semiconductor device, a so-called scribe line. The surface of the single crystal Si layer 24 is protected including all the semiconductor devices and the bump electrodes 15 formed on the layer 24.

The groove 16 is formed by dry etching (plasma etching with SF ₆ , CF ₄ , Cl + O ₂ , HBr + O ₂ , reverse sputter etching, etc.), wet etching (HF + H ₂ O ₂ + H ₂ O mixed solution, HF + HNO ₃ + CH ₃ Hydrofluoric acid-based etchants such as COOH mixture, alkali-based etchants, etc.) and mechanical processing (cutting grooves with blade dicing, diamond cutter, cemented carbide cutter, ultrasonic cutter, etc.), carbon dioxide laser, YAG laser, excimer laser By laser processing or the like to form an arbitrary width so as to be located at least inside the high-porosity Si layer 27 or at the interface between the low-porosity Si layer 28 and the high-porosity Si layer 27 from the surface of the single-crystal Si layer. Is also good. Thereby, separation from the separation layer can be easily performed.

Among them, in the case of dry etching or wet etching having a high etching selectivity between Si and an insulating film (SiO ₂ , Si ₃ N _4, etc.), or by a combination of mechanical processing and dry etching or wet etching, an ultra-thin film is obtained. By promoting side etching of the porous Si layer below the SOI structure insulating film, separation at the time of peeling may be promoted.

It is preferable that the UV tape 17 be made of a transparent UV tape base material 17a and a conductive UV irradiation-curable adhesive 17b with strong adhesive force and no adhesive residue. Further, it is desirable that the thickness of the UV-irradiation-curable adhesive 17 b is at least equal to or greater than the height of the bump electrode 15. By short-circuiting all of the bump electrodes 15 with the conductive UV-irradiation-curable adhesive 17b in this manner, electrostatic breakdown during the manufacturing process can be prevented, and semiconductor characteristics failure due to electrostatic damage can be prevented. it can. The surface resistance of the UV-irradiation-curable adhesive 17b before and after curing is desirably a level that prevents electrostatic damage of about 10 ⁶ to 10 ¹² Ω / □.

(8) A high-pressure fluid jet jet peeling such as a water jet, an air jet, or a water air jet similar to that described above, laser processing peeling, laser water jet processing peeling, tensile peeling, or the like, is used to separate the highly porous Si layer 27 from the supporting substrate 25. Is separated, UV-cured and cured, and the UV tape is peeled off to obtain an ultra-thin semiconductor device chip as an ultra-thin semiconductor device (see FIG. 7).

  Here, since the low-porous Si layer 28 remains in the ultra-thin semiconductor device chip, the adhesion to the sealing resin or the like is improved. Furthermore, since the low-porous Si layer 28 is doped with an n-type or p-type impurity at an arbitrary concentration and has conductivity, it is possible to prevent electrostatic damage at the time of packaging and to shield electromagnetic waves. As a result, the quality and reliability of the ultra-thin semiconductor device chip are improved.

  The separated support substrate 25 can be reused by performing surface re-polishing, etching, heat treatment in an atmosphere containing hydrogen, or the like, as necessary. Alternatively, it can be used as a substrate for another purpose.

  Incidentally, the separation of the seed substrate 20 from the highly porous Si layer 22 and the separation of the support substrate 25 from the highly porous Si layer 27 described in (4) and (8), respectively, are carried out by water jet and air as described above. In addition to jets, jets of water, liquids such as etchants and alcohols, air, gases such as nitrogen gas and argon gas, and jets of a mixture of a liquid and a gas in which the gas is mixed in an appropriate ratio with the liquid. Can be performed. Particularly, in jetting a jet of a mixture of a liquid and a gas, gas bubbles are mixed into the liquid, and the bubbles can be separated more effectively.

  At this time, using the manufacturing apparatus shown in FIG. 26, the high-pressure fluid jet 82 is pinched and rotated by the holders 81a and 81b, and the high-pressure fluid jet 82 is Can be removed by spraying. In the case of spraying a high-pressure fluid jet, when ultrasonic waves are applied to the fluid, ultrasonic vibrations act on the porous layer, so that separation from the porous layer can be performed more effectively.

  Further, an ultrafine powder of fine particles or powder (abrasive, ice, plastic pieces, etc.) may be added to the high-pressure fluid jet 82. If a fine solid is added to the high-pressure fluid jet in this way, the fine solid directly collides with the high-porosity Si layers 22 and 27, thereby enabling more effective separation.

Alternatively, the rotating high porous Si layers 22 and 27 can be separated from each other by laser processing (ablation processing, thermal processing, multiphoton absorption modified laser processing, etc.) by irradiating one or more lasers from the lateral direction. . The details of the laser processing are the same as those described in (4).
Alternatively, the rotating high porous Si layers 22 and 27 can be separated from each other by laser water jet processing by irradiating one or more laser water jets from the lateral direction. The details of the laser water jet processing are the same as those described in (4).

  Further, at the time of separating the support substrate 25 from the highly porous Si layer 27 described in (8), the semiconductor device formed on the single-crystal Si layer 24 and the prevention of characteristic fluctuation due to heat of the protruding connection electrode connected to the semiconductor device, etc. For this purpose, if necessary, the Si substrate 10 may be separated while being cooled via a UV tape using a cooled support jig.

  Further, since the UV irradiation curing type adhesive 17b of the UV tape 17 has a strong adhesive force, the UV tape 17 holds the single-crystal Si layer 24 and the like, and the surface of the single-crystal Si layer 24 and the bump electrodes 15 and the like are used. Since the single crystal Si layer 24 can be separated from the supporting substrate 25 in the protected state, cracking and chipping of the ultra-thin semiconductor device can be prevented. Further, since the UV tape 17 is conductive, it is possible to prevent the semiconductor device formed on the single-crystal Si layer 24 from being damaged by static electricity at the time of separation. In addition, since the adhesive strength of the UV irradiation-curable adhesive 17b is weakened by the irradiation curing of UV (ultraviolet) rays, it can be removed without separation after separation.

  As described above, in the double porous layer separation method according to the present embodiment, the seeds are separated from the highly porous Si layers 22 and 27 formed on the seed substrate 20 and the support substrate 25 bonded to each other with the insulating layer 30 interposed therebetween. By separating the substrate 20 and the support substrate 25, an ultra-thin SOI substrate including the single-crystal Si layer 29, the insulating layer 30, and the single-crystal Si layer 24 is manufactured. Thereby, an ultra-thin semiconductor device using this ultra-thin SOI substrate can be obtained.

  Further, in the present embodiment, since the separation is performed after forming the kerf 16 along the dividing line at the time of dividing into each ultra-thin semiconductor device, the ultra-thin semiconductor device separated from the support substrate 25 in a later step The SOI layer is previously pelletized. For this reason, an ultra-thin semiconductor device that has already been pelletized and divided after the support substrate 25 is separated can be obtained. A semiconductor device is obtained. Further, when forming the kerfs 16, the ultra-thin SOI layer is supported by the support substrate 25, so that the occurrence of cracks and chips when the kerfs 16 are formed is also prevented.

(B) Double ion-implanted layer separation method In the present embodiment, separation is performed from the double-formed high-concentration hydrogen ion-implanted layer (separate the seed substrate from the high-concentration hydrogen ion-implanted layer formed on the seed substrate and support it). A method of manufacturing an ultra-thin semiconductor device by separating a supporting substrate from a high-concentration hydrogen ion-implanted layer formed on a substrate will be described. 8 to 12 are manufacturing process diagrams of the ultra-thin semiconductor device by the double hydrogen ion implantation layer separation method according to the embodiment of the present invention.

(1) SiO ₂ 41a (see FIG. 8A) or an SiO ₂ 41a / Si ₃ N ₄ 41b / SiO ₂ 41a laminated film (see FIG. 8B) is formed as an insulating layer on the support substrate 40; A high-concentration hydrogen ion implantation layer 43 is formed on the seed substrate 42. Note that hydrogen ions are implanted at a depth of about 1 μm at a dose of 100 keV and a dose of 5 × 10 ¹⁶ to 1 × 10 ¹⁷ atoms / cm ² . The support substrate 40 and the seed substrate 42 used here conform to (A).

(2) The support substrate 40 and the seed substrate 42 are bonded together (see FIG. 9).
After cleaning the support substrate 40 and the seed substrate 42, the thermally oxidized film SiO ₂ 41a (see FIG. 9A) or the SiO ₂ 41a / Si ₃ N ₄ 41b / SiO ₂ 41a laminated film of the support substrate 40 at room temperature (see FIG. 9). (See (b)) The surface and the surface of the high-concentration hydrogen ion implanted layer (single-crystal Si layer) 43 of the seed substrate 42 are brought into contact with each other and bonded by Van der Waals force. Thereafter, a heat treatment is performed at 400 ° C. for 30 minutes for covalent bonding to strengthen the bonding. The heat treatment conditions are the same as described in (A).

(3) After annealing for peeling, UV tapes 45 are attached to the back surfaces of both the support substrate 40 and the seed substrate 42, respectively, and pulled and peeled (see FIG. 10).
The annealing for peeling is performed by heat treatment at 400 to 600 ° C. for 10 to 20 minutes, or rapid thermal annealing (RTA) (rapid thermal annealing) of rapid heating and cooling for a short time (halogen lamp annealing 800 ° C. for several seconds, Xe flash lamp annealing about 1000). (A few milliseconds at a temperature, laser ablation with a carbon dioxide laser, etc.).
Thereby, the ion-implanted high-concentration hydrogen is expanded, the strain is generated in the high-concentration hydrogen ion-implanted layer 43 by the pressure action and the crystal rearrangement action in the microbubbles, and the UV tape 45 peels off the high-concentration hydrogen ion-implanted layer. Then, the UV tape 45 is peeled from the support substrate 40 by UV irradiation curing. It is preferable that the RTA radiates heat from the seed substrate 42 to be separated.

Alternatively, the separation from the ion implantation layer can be performed by laser processing by irradiating the rotating ion implantation layer 43 with one or more laser beams from the lateral direction. For example, in the case of the high-concentration hydrogen ion implantation layer 43, the high-concentration hydrogen implanted by the ion implantation is expanded by local heating of the high-concentration hydrogen ion implantation layer 43 during rotation by laser irradiation, and the pressure action in the microbubbles and the crystallization Strain is generated in the high-concentration hydrogen ion implanted layer 43 by the arrangement effect, and the high-concentration hydrogen ion implanted layer 43 can be separated by pulling and peeling.
Alternatively, the separation from the ion implantation layer can be performed by laser water jet processing by irradiating the rotating ion implantation layer 43 with one or more laser water jets from the lateral direction. For example, in the case of the high-concentration hydrogen ion implantation layer 43, the high-concentration hydrogen implanted by the ion implantation is expanded by local heating of the high-concentration hydrogen ion implantation layer 43 during rotation by the laser water jet, and the pressure action and the crystal within the microbubbles are increased. The high-concentration hydrogen ion implanted layer 43 is distorted by the rearrangement action, and can be separated by pulling and separating.

Thereafter, after the seed substrate is separated as shown in FIG. 28 (b), the single crystal Si layer (hydrogen ion implanted layer) 43, the thermal oxide film SiO ₂ 41a and the peripheral portion of the surface of the support substrate are C-chamfered. Since chipping, cracking, and cracking of the ultra-thin SOI layer at the peripheral portion are prevented, yield and quality are improved, and cost reduction is realized.

(4) Etching is performed by hydrogen annealing to obtain a highly flat single-crystal Si layer 43.
A part of the surface of the single crystal Si layer 43 is etched by hydrogen annealing to form a single crystal Si layer 43 having a desired thickness and flatness, for example, a 50 nm thickness. Hydrogen annealing is performed at an etching rate of 0.0013 nm / min at 1050 ° C. and 0.0022 nm / min at 1100 ° C.
If necessary, a single-crystal Si layer having a higher crystallinity and an arbitrary thickness may be stacked by Si epitaxial growth using the single-crystal Si layer 43 etched by hydrogen annealing as a seed.

At this time, similarly to (A), Ge is grown by Si epitaxial growth such as CVD on the surface of the single crystal Si substrate 42 as a seed substrate so that the peeled hydrogen ion implanted layer (single crystal Si layer) 43 becomes a strain applying semiconductor layer. The single crystal Si layer 43 of the strain applying semiconductor layer may be formed as a SiGe layer having a concentration of 20 to 30%.
Then, the hydrogen ions may be implanted at a high concentration so as to have this thickness (depth) to form a hydrogen ion implanted layer (single-crystal Si layer) 43.

  As a result, a display portion and a peripheral circuit of a MOSTFT that achieve a significant improvement in electron mobility of about 1.76 times as compared with the single crystal Si layer 43 of the conventional strain-free channel layer are realized, so that high performance and high definition are achieved. Thus, a high-quality ultra-thin electro-optical display device is realized.

At this time, the graded composition is such that the Ge concentration at the strained portion of the hydrogen ion implanted layer in the SiGe layer is a desired concentration, and the Ge concentration on the surface of the single crystal Si layer 43 that is the strain applying semiconductor layer after the separation of the seed substrate is equal to the desired concentration. Preferably, the single crystal Si layer 43 as the strain channel layer is formed by Si epitaxial growth using the single crystal Si layer 43 of the strain applying semiconductor layer, which is the SiGe layer having the gradient composition, as a seed.
That is, the single crystal Si layer 43 of the strain applying semiconductor layer has a gradient composition from the portion of the insulating layer in contact with the SiO ₂ film 41a, the Ge concentration gradually increases, and the surface concentration is, for example, a desired value of 20 to 30%. It is preferable that

(5) A semiconductor device such as a semiconductor element or a semiconductor integrated circuit is formed in the single-crystal Si layer 43 by a general-purpose technique, as in (A). When a compound semiconductor substrate is used as the seed substrate 42, a compound semiconductor device such as SiC, GaAs, InP or the like can be formed.

(6) After the heat treatment step at 500 ° C. or higher in the semiconductor device process step, high-concentration hydrogen ions are implanted at a depth of 3 to 5 μm from the surface, and annealing is performed for peeling to generate distortion 46 (FIG. 11). reference).

The hydrogen ion implantation is performed at 300 to 500 keV and 5 × 10 ¹⁶ to 1 × 10 ¹⁷ atoms / cm ² . Annealing for peeling is performed by the same heat treatment at 400 to 600 ° C. for 10 to 20 minutes or by rapid heating and rapid cooling RTA. As a result, the ion-implanted hydrogen is expanded, and a strain 46 is generated in the high-concentration hydrogen ion-implanted layer by the pressure action and the crystal rearrangement action in the microbubbles.

At this time, device constituent films such as a silicon oxide film and a silicon nitride film exist on the support substrate 40, and a high-concentration hydrogen ion implanted layer is formed under the insulating layer (SiO ₂ 41a) by penetrating these. Distortion is generated by heat treatment. Further, if the annealing for peeling is performed by RTA of rapid heating and rapid cooling, distortion 46 can be generated without adversely affecting device characteristics and the like.

  When the annealing for stripping is performed in the RTA process of rapid heating and rapid cooling, it is desirable to radiate heat from the back surface of the support substrate 40 to be separated in order to prevent fluctuation or deterioration in characteristics of the semiconductor device. At this time, depending on the type of the semiconductor device, heat is radiated from the back surface of the support substrate 40, and the surface of the single-crystal Si layer 43 on which the semiconductor device is formed is fluid-cooled via a UV tape (for example, a liquid such as water or alcohol, Cooling with a gas such as air or nitrogen gas, or a mixture of these liquids and gases at an appropriate ratio) can prevent the characteristics of the semiconductor device from being deteriorated.

(7) The bump electrode 47 is formed.
The bump electrode 47 conforms to (A), but in the case of a stud bump such as an Au wire, be careful not to damage not only the single crystal Si layer 43 but also the single crystal Si layer 44 of the pedestal due to the impact of wire bonding. I do.

  Note that, depending on the type of the semiconductor device formed in the single-crystal Si layer 43, after forming the bump electrode 47, hydrogen ion implantation of (6) may be performed and annealing 46 for peeling may be performed to generate the distortion 46. .

(8) A cut groove 48 is formed in the scribe line by blade dicing at least up to the strain 46 of the high-concentration hydrogen ion implanted layer, and a UV tape 45 made of a UV tape base material 45a and a UV-curable adhesive 45b is attached to both sides of the substrate. At the same time, it is pulled away from the strain 46 of the hydrogen ion implanted layer (see FIG. 12). Thereafter, the UV tape is cured by UV irradiation, and the UV tape is peeled off to obtain an ultra thin semiconductor device chip as an ultra thin semiconductor device. The groove 48 may be formed according to (A) other than the blade dicing. Furthermore, after forming the groove 48, a strain 46 may be generated in the ion-implanted layer by peeling annealing.

  The ultra-thin semiconductor device chip thus obtained has good adhesion to a sealing resin or the like since the peeled surface of the hydrogen ion implanted layer is rough. Also, by adding an n-type or p-type impurity at an arbitrary concentration to this layer to make it conductive, it is possible to prevent electrostatic damage during packaging and to shield electromagnetic waves. Quality and reliability are improved.

  The separated support substrate 40 can be reused by performing surface re-polishing, etching, heat treatment in an atmosphere containing hydrogen, or the like, as necessary. Alternatively, it can be used as a substrate for another purpose.

As described above, in the double ion implantation layer separation method according to the present embodiment, the high-concentration hydrogen ion implantation layers formed on the seed substrate 42 and the support substrate 40 bonded via the insulating layer (SiO ₂ 41a), respectively, By separating the seed substrate 42 and the support substrate 40, an ultra-thin SOI substrate including the single-crystal Si layer 44, the SiO ₂ 41a, and the single-crystal Si layer 43 is manufactured. Thereby, an ultra-thin semiconductor device using this ultra-thin SOI substrate can be obtained.

  Further, in the present embodiment, since the separation is performed after forming the cut groove 48 along the dividing line when dividing into each ultra-thin semiconductor device, the ultra-thin semiconductor device separated from the support substrate 40 in a later step The SOI layer is previously pelletized. For this reason, after the support substrate 40 is separated, an ultra-thin semiconductor device that has already been pelletized is obtained. Since the ultra-thin SOI layer is supported by the support substrate 40 when the cut groove 48 is formed, the occurrence of cracks, chips, and cracks is prevented as described in (A).

  Although the embodiment in which hydrogen ions are implanted has been described in the present embodiment, in addition, high-concentration ions such as nitrogen, helium, and rare gas are implanted, and the seed substrate and the support are supported from these high-concentration ion-implanted layers. It is also possible to obtain an ultra-thin semiconductor device by separating the substrate.

  Further, in the present embodiment, the mode in which the separation from the hydrogen ion implanted layer is performed by pulling and peeling has been described, but the separation can be performed by another separation method similar to that described in (A).

(C) Separation Method of Porous Layer / Ion-Implanted Layer In this embodiment, the porous Si layer is separated from the high-concentration hydrogen-ion-implanted layer (separation of the seed substrate from the high-concentration hydrogen-ion-implanted layer formed on the seed substrate) Then, a method of manufacturing an ultra-thin semiconductor device by separating the support substrate from the porous Si layer formed on the support substrate will be described. FIG. 13 to FIG. 18 are manufacturing process diagrams of an ultra-thin semiconductor device by a porous Si layer / hydrogen ion implantation layer separation method according to the embodiment of the present invention. Note that the seed substrate 50 and the support substrate 52 used here conform to (A).

(1) Inject hydrogen ions into the seed substrate 50. The injection method conforms to (B).

(2) A low-porous Si layer 53, a high-porous Si layer 54, and a low-porous Si layer 55 are formed on the support substrate 52 by anodization, a single-crystal Si layer 56 epitaxially grown is formed, and SiO ₂ oxidation is performed. An insulating layer 57 made of a film or a SiO ₂ / Si ₃ N ₄ / SiO ₂ laminated film is formed. The formation method conforms to (A).

(3) The seed substrate 50 and the support substrate 52 are attached (see FIG. 14).
At room temperature, the surface of the high-concentration hydrogen ion implanted layer 51 of the seed substrate 50 and the surface of the insulating layer 57 of the support substrate 52 are brought into contact with each other and bonded by Van der Waals force. Thereafter, a heat treatment is performed at 400 ° C. for 30 minutes for covalent bonding to strengthen the bonding. The heat treatment method conforms to (B).

(4) Distortion 59 is generated in the high-concentration hydrogen ion implanted layer 51 by the annealing treatment for peeling, and the UV tape 45 is attached to both the seed substrate 50 and the support substrate 52, and pulled and peeled (see FIG. 15).
The peeling anneal conforms to (B), but at this time, it is important to adjust the porosity and thickness so as not to peel off from the highly porous Si layer 54.

  At this time, as shown in FIG. 28C, after the seed substrate is separated, a single-crystal Si layer (hydrogen ion implanted layer) 51, an insulating layer 57, a single-crystal Si layer 56, a low-porosity Si layer 55, a high-porosity Si layer The peripheral portion of the surface of the Si layer 54, the low-porous Si layer 53, and the support substrate 52 is chamfered to prevent chipping, cracking, and cracking of the ultra-thin SOI layer and the like at the peripheral portion. And the cost is reduced.

(5) The surface of the peeled single-crystal Si layer 51 is etched by hydrogen annealing to form a single-crystal Si layer 51 having a desired thickness and high flatness, for example, 50 nm. Hydrogen annealing is performed at an etching rate of 0.0013 nm / min at 1050 ° C. and 0.0022 nm / min at 1100 ° C.
If necessary, a single crystal Si layer having a higher crystallinity and an arbitrary thickness may be laminated by Si epitaxial growth using the single crystal Si layer 51 etched by hydrogen annealing as a seed.

At this time, similarly to (A), Ge is grown by Si epitaxial growth such as CVD on the surface of the single crystal Si substrate 50 as a seed substrate so that the peeled hydrogen ion implanted layer (single crystal Si layer) 51 becomes a strain applying semiconductor layer. The single crystal Si layer 51 of the strain applying semiconductor layer may be formed as a SiGe layer having a concentration of 20 to 30%, and the single crystal Si layer of the strain channel layer may be formed by Si epitaxial growth using the single crystal Si layer 51 as a seed. .
Then, the hydrogen ions may be implanted at a high concentration so as to have this thickness (depth) to form a hydrogen ion implanted layer (single-crystal Si layer) 51.

  As a result, a MOSTFT display portion and a peripheral circuit that achieve a significant improvement in electron mobility of about 1.76 times as compared with the single crystal Si layer 51 of the conventional strain-free channel layer can be realized, so that high performance and high definition can be achieved. Thus, a high-quality ultra-thin electro-optical display device is realized.

At this time, the Ge concentration in the strained portion of the hydrogen ion implanted layer in the SiGe layer is set to a gradient composition such that the Ge concentration becomes a desired concentration, so that the Ge concentration on the surface of the single crystal Si layer 43 which is the strain applying semiconductor layer after separation of the seed substrate is reduced. Preferably, the concentration is set to a desired concentration, and the single crystal Si layer 43 as a strain channel layer is formed by Si epitaxial growth using the single crystal Si layer 43 as the strain applying semiconductor layer of the SiGe layer having the gradient composition as a seed.
In other words, the single crystal Si layer 51 of the strain applying semiconductor layer has a gradient composition from the portion in contact with the insulating layer 57 so that the Ge concentration gradually increases and the surface concentration becomes a desired value of, for example, 20 to 30% Ge concentration. Is preferred.

(6) A semiconductor device such as a semiconductor element or a semiconductor integrated circuit is formed in the single-crystal Si layer 51 by a general-purpose technique, as in (A). When a compound semiconductor substrate is used as the seed substrate 50, a compound semiconductor device such as SiC, GaAs, and InP can be formed.

(7) The bump electrode 47 is formed (see FIG. 16).
The bump electrode 47 conforms to (A), but in the case of a stud bump such as an Au wire, not only the single-crystal Si layer 51 but also the single-crystal Si layer 56 serving as a mount is not damaged by the impact of wire-bonding. Be careful.

(8) After the kerf 60 is cut into the scribe line by blade dicing to at least the low-porous Si layer 56, the surface is protected with a UV tape 45 or the like (see FIG. 17). The UV tape 45 conforms to (A). Needless to say, the groove 60 may be formed by a method according to (A) other than blade dicing.

(9) The support substrate 52 is separated from the highly porous Si layer 54 by a high-pressure fluid jet spray peeling method such as a water jet or an air jet, and is cured by UV irradiation to peel off the UV tape 45. An ultra-thin semiconductor device chip is obtained (see FIG. 18). Note that the separation method of the support substrate 52 can be performed by a method similar to that described in (A).

  Here, since the low-porous Si layer 55 remains in the ultra-thin semiconductor device chip, the adhesion to the sealing resin or the like is improved. Also, by adding an n-type or p-type impurity at an arbitrary concentration to this layer to make it conductive, it is possible to prevent electrostatic damage during packaging and to shield electromagnetic waves. Quality and reliability are improved. Further, as described above, the separated support substrate 52 can be reused.

(D) Porous Layer Separation Method In (A), (B), and (C), a method of manufacturing an ultra-thin semiconductor device having an SOI structure having a semiconductor layer on an insulating layer has been described. Depending on the type and quality of the device, an ultra-thin semiconductor device without an insulating layer by a porous layer separation method described below may be used.

  That is, a step of forming a porous layer on the supporting substrate, a step of forming a semiconductor layer on the supporting substrate via the porous layer, and at least a step of dividing the semiconductor layer along the dividing line for dividing the semiconductor device into ultrathin semiconductor devices. The method for manufacturing an ultra-thin semiconductor device may include a step of forming a kerf up to the porous layer and a step of separating the supporting substrate from the porous layer after forming the kerf.

  As described above, the porous layer and the semiconductor layer are formed on the supporting substrate, and the kerfs are formed along the dividing line at the time of dividing at least the porous layer into the respective ultra-thin semiconductor devices. The semiconductor layer separated from the supporting substrate is previously pelletized. Therefore, when the pelletized semiconductor layer is separated from the supporting substrate in the porous layer, cracks, chips, and cracks do not occur, and an ultra-thin semiconductor device without an insulating layer can be obtained. Since the semiconductor layer is supported by the supporting substrate when forming the kerfs, the occurrence of cracks, chips, and cracks due to the formation of the kerfs is prevented.

  In addition, before forming the kerf, a semiconductor device and a protruding connection electrode connected to the semiconductor device are formed in the semiconductor layer, and thereafter, the semiconductor layer including all of the semiconductor device and the protruding connection electrode is formed. The supporting substrate may be separated in a state where the surface of the support substrate is covered with a conductive ultraviolet irradiation curing type tape having no adhesive residue.

  The details of the above steps are the same as those described in (A). As for the method for separating the supporting substrate, a high-pressure fluid jet spray separation method, a laser processing separation method, a laser water jet processing separation method, and a tension separation method can be used as described in (A). In addition, the respective steps such as formation of a kerf, formation of a resin protective film, polishing, and pelletizing division may be in accordance with (A).

(E) Ion-implanted layer separation method As in (D), depending on the type and quality of the required semiconductor device, an ultra-thin semiconductor device without an insulating layer by the ion-implanted layer separation method described below may be used.

  That is, a step of forming a semiconductor layer on the surface of the support substrate, a step of forming an ion-implanted layer at a predetermined depth from the substrate surface, and a step of performing an annealing process for peeling the ion-implanted layer; Forming a kerf from the semiconductor layer to at least the ion-implanted layer along a dividing line when dividing the substrate, and separating the support substrate from the ion-implanted layer after forming the kerf The method of manufacturing the device may be used. The peeling annealing may be performed after the formation of the kerf. Further, after the formation of the kerfs, an ion-implanted layer may be formed and annealing treatment for peeling may be performed.

  As described above, the semiconductor layer and the ion-implanted layer are formed on the supporting substrate, and at least the ion-implanted layer is formed along the dividing line at the time of dividing the semiconductor device into ultrathin semiconductor devices. The semiconductor layer separated from the supporting substrate is previously pelletized. Therefore, an ultra-thin semiconductor device without an insulating layer can be obtained without cracking, chipping, or cracking when the pelletized semiconductor layer is separated from the supporting substrate in the ion implantation layer. Since the semiconductor layer is supported by the supporting substrate when forming the kerfs, the occurrence of cracks, chips, and cracks due to the formation of the kerfs is prevented.

  In addition, before forming the kerf, a semiconductor device and a protruding connection electrode connected to the semiconductor device are formed in the semiconductor layer, and thereafter, the semiconductor layer including all of the semiconductor device and the protruding connection electrode is formed. The supporting substrate may be separated in a state where the surface of the support substrate is covered with a conductive ultraviolet irradiation curing type tape having no adhesive residue. At this time, an annealing treatment for peeling may be performed after the formation of the protruding connection electrodes.

  The details of the above steps are the same as those described in (B). As for the method for separating the supporting substrate, a high-pressure fluid jet spray separation method, a laser processing separation method, a laser water jet processing separation method, and a tension separation method can be used as described in (B). In addition, the respective steps such as formation of a kerf, formation of a resin protective film, polishing, and pelletizing division may be in accordance with (A).

(F) Method for Manufacturing Single-Side Resin-Encapsulated Ultra-Thin Semiconductor Chip Size Package (CSP; Chip Size Package) In the present embodiment, (A), (B), (C), (D), (E) A method for manufacturing a single-sided resin-sealed ultra-thin semiconductor chip size package (hereinafter referred to as CSP) by each method will be described.
A method of manufacturing the CSP according to the present embodiment will be described with reference to manufacturing process diagrams shown in FIGS. In the above-mentioned manufacturing methods (A), (B), (C), (D), and (E), a common process up to the formation of the bump electrode is used.

(1) Cut grooves 48 and 60 are formed in the scribe line by blade dicing to at least the strain 46 of the high-concentration hydrogen ion implanted layer (see FIG. 19A) or the highly porous Si layer 54 (see FIG. 19B). Then, the surfaces of the single crystal Si layers 44 and 58 and the insides of the cut grooves 48 and 60 are filled and sealed with an epoxy resin 70 or the like as a resin protective film. Thereafter, the epoxy resin 70 is polished on one side such as optical polishing or CMP to expose the bump electrodes 47, and the bump electrodes 47 are Au-plated as necessary.

  Since the layer of the epoxy-based resin 70 serves as a support base for the chip, the thickness is at least equal to or greater than the height of the bump electrode 47 that is projected. In addition, the surface of the single-crystal Si layer 44 may be coated with a silane coupling agent to improve the adhesion with the epoxy resin 70.

  Here, the resin sealing is performed by a transfer molding method, an injection molding method, an extrusion molding method, an insert molding method, a compression molding method, a spin coating method, or the like. The sealing resin is a thermosetting resin such as an epoxy resin, a polyimide resin, a phenol resin, an epoxy acrylate resin, an acrylic resin, a silicone resin, a polyimide silicone resin, an unsaturated polyester resin, or a liquid crystal polymer, a polyphenylene sulfide resin, or a polysulfone resin. Use a transparent, translucent or opaque resin such as a heat-resistant thermoplastic resin. Then, the surfaces of the single-crystal Si layers 44 and 58 and the insides of the cut grooves 48 and 60 are sealed using these sealing resins, and post-heating treatment is performed according to the molding method and resin characteristics.

(2) The UV tape 45 is adhered to the epoxy resin 70 and the support substrate 40 and held, and is separated from the high-concentration hydrogen ion-implanted layer by strain separation 46 (see FIG. 20A), or a highly porous Si layer. From FIG. 54 (see FIG. 20B), separation is performed by a high-pressure fluid jet spray separation method such as a water jet or an air jet. The separation here can be performed by the same laser processing separation method and laser water jet processing separation method as described in (A). The UV tape 45 conforms to (A), but it is desirable to use a conductive tape having no adhesive residue for the same reason as described in (A).

(3) The epoxy resin 70 filled in the scribe line from the single crystal Si layer 56 side is subjected to full-cut blade dicing by alignment of a cross mark composed of the exposed Si layer 71 and the epoxy resin 70, and UV The UV tape 45 is peeled off by irradiation hardening to obtain a single-sided resin-sealed ultra-thin semiconductor device chip (CSP) (see FIG. 21). At this time, pelletization may be performed by a method other than blade dicing, such as laser ablation such as carbon dioxide gas laser, YAG laser, and excimer laser, a diamond cutter, a cemented carbide cutter, and an ultrasonic cutter.

(4) The CSP thus obtained can be mounted on a printed wiring board (PCB), an IC card, or the like using a conductive paste 72 such as a silver paste or a solder paste (see FIG. 22). When mounting on a substrate, an anisotropic conductive film may be used, and a solder bump of the CSP may be connected to a conductive portion of the substrate through the anisotropic conductive film to conduct electricity.

  As described above, when the CSP is mounted on the PCB or the like using the conductive paste 72 and reflowed for electrical and mechanical connection, since the back surface of the Si layer 71 is exposed, the thermal conductivity is high and the thermal efficiency is good. Therefore, the connection of the CSP to the PCB is easy, and the productivity is high.

  Further, since the back surface of the Si layer 71 is exposed, heat dissipation efficiency during device operation is high, and characteristics and quality are improved. In addition, since the front and side surfaces are sealed with a resin protective film such as the epoxy resin 70, moisture resistance and mechanical strength can be maintained, and the quality and reliability are high.

(G) Method of Manufacturing Ultra-Multilayer Chip Size Package A method of manufacturing an ultra-multilayer chip size package of an ultra-thin semiconductor device chip according to the present embodiment will be described with reference to FIG. FIG. 23 is a sectional view of an ultra-multilayer chip size package of an ultra-thin semiconductor device chip. At this time, an ultra-multi-layer chip size package may be manufactured by laminating an arbitrary number of the single-sided resin-sealed ultra-thin semiconductor chip size packages manufactured in (F) above.

(1) As shown in FIG. 23, an arbitrary number of, for example, ultra-thin semiconductor memory chips manufactured by any one of the above methods (A), (B), (C), (D), and (E). For example, 100 chips are laminated, and each chip is fixed with an insulating thermosetting adhesive 73.

(2) Drill a via hole 74 in the bump electrode 47 (or pad electrode).

(3) The conductive paste 72 is filled in the via hole 74, cured under predetermined conditions, and made conductive. Here, the via hole 74 is smaller than the bump electrode 47, and the conductive paste 72 filled in the via hole 74 contacts the bump electrode 47 and the wiring 75 to obtain electrical and mechanical contact.

(4) If necessary, parts other than the bump electrodes 47 (or pad electrodes) are sealed with an epoxy resin (not shown) or the like.

  In the case of the MOS LSI of the present embodiment, the thickness of one ultra-thin semiconductor chip is about 5 to 10 μm. It becomes a super multilayer chip size package.

  In the above-described embodiment, the bump electrodes 47 are formed on the chip surface as shown in FIG. 24. However, as shown in FIG. 25, the internal wiring 76 penetrating the separated single crystal Si layer 58 is provided. It is also possible to form a bump electrode 47 on the peeled back surface, or to perform wire bonding.

  By the way, it is difficult to hold, store, and transport an ultra-thin semiconductor device manufactured by each of the above-described manufacturing methods alone because of problems such as cracking and chipping. Therefore, when the ultra-thin semiconductor device held on the UV tape is divided into pellets, it is desirable to cut the entire device including the UV tape, and to hold, store, and carry the device in a state where the device can be cured by UV irradiation and can be always peeled off. In other words, since it is difficult to hold and store only the manufactured ultra-thin semiconductor device, storage, transportation, and the like are performed in a UV-irradiation-curable tape supporting state in which the UV-irradiation-cured state is ready for peeling. It is desirable.

It is sectional drawing which shows the manufacturing process of the ultra-thin semiconductor device by the double porous Si layer separation method. It is sectional drawing which shows the manufacturing process of the ultra-thin semiconductor device by the double porous Si layer separation method. It is sectional drawing which shows the manufacturing process of the ultra-thin semiconductor device by the double porous Si layer separation method. It is sectional drawing which shows the manufacturing process of the ultra-thin semiconductor device by the double porous Si layer separation method. FIGS. 4A and 4B are cross-sectional views illustrating a process of manufacturing an ultra-thin semiconductor device by a double porous Si layer separation method, in which FIG. 4A illustrates an example in which SiO ₂ is formed as an insulating layer, and FIG. FIG. 3 is a diagram showing an example in the case where SiO ₂ / Si ₃ N ₄ / SiO ₂ is formed. It is sectional drawing which shows the manufacturing process of the ultra-thin semiconductor device by the double porous Si layer separation method. It is sectional drawing which shows the manufacturing process of the ultra-thin semiconductor device by the double porous Si layer separation method. FIGS. 4A and 4B are cross-sectional views illustrating a process of manufacturing an ultra-thin semiconductor device by a double hydrogen ion implantation layer separation method, in which FIG. 4A illustrates an example in which SiO ₂ is formed as an insulating layer, and FIG. FIG. 3 is a diagram showing an example in the case where SiO ₂ / Si ₃ N ₄ / SiO ₂ is formed. FIGS. 4A and 4B are cross-sectional views illustrating a process of manufacturing an ultra-thin semiconductor device by a double hydrogen ion implantation layer separation method, in which FIG. 4A illustrates an example in which SiO ₂ is formed as an insulating layer, and FIG. FIG. 3 is a diagram showing an example in the case where SiO ₂ / Si ₃ N ₄ / SiO ₂ is formed. It is sectional drawing which shows the manufacturing process of the ultra-thin semiconductor device by the double hydrogen ion implantation layer separation method. It is sectional drawing which shows the manufacturing process of the ultra-thin semiconductor device by the double hydrogen ion implantation layer separation method. It is sectional drawing which shows the manufacturing process of the ultra-thin semiconductor device by the double hydrogen ion implantation layer separation method. It is sectional drawing which shows the manufacturing process of the ultra-thin semiconductor device by a porous Si layer and a hydrogen ion implantation layer separation method. It is sectional drawing which shows the manufacturing process of the ultra-thin semiconductor device by a porous Si layer and a hydrogen ion implantation layer separation method. It is sectional drawing which shows the manufacturing process of the ultra-thin semiconductor device by a porous Si layer and a hydrogen ion implantation layer separation method. It is sectional drawing which shows the manufacturing process of the ultra-thin semiconductor device by a porous Si layer and a hydrogen ion implantation layer separation method. It is sectional drawing which shows the manufacturing process of the ultra-thin semiconductor device by a porous Si layer and a hydrogen ion implantation layer separation method. It is sectional drawing which shows the manufacturing process of the ultra-thin semiconductor device by a porous Si layer and a hydrogen ion implantation layer separation method. FIGS. 4A and 4B are cross-sectional views illustrating a manufacturing process of a single-sided resin-sealed ultra-thin semiconductor chip size package, in which FIG. 4A illustrates a method using a double hydrogen ion implantation layer separation method, and FIG. FIG. 3 is a view showing a method according to a method, a double porous Si layer separation method, and a porous Si layer / hydrogen ion implantation layer separation method. FIGS. 4A and 4B are cross-sectional views illustrating a manufacturing process of a single-sided resin-sealed ultra-thin semiconductor chip size package, in which FIG. 4A illustrates a method using a double hydrogen ion implantation layer separation method, and FIG. FIG. 3 is a view showing a method according to a method, a double porous Si layer separation method, and a porous Si layer / hydrogen ion implantation layer separation method. (A) is a sectional view showing a manufacturing process of a single-sided resin-sealed ultra-thin semiconductor chip size package, and (b) is a view from the dicing surface of (a). (A) is sectional drawing which shows the manufacturing process of the single-sided resin sealing type ultra-thin semiconductor chip size package. It is sectional drawing which shows the manufacturing process of the super multilayer chip size package of a super thin semiconductor device chip. FIG. 3 is an enlarged view of a bump electrode forming portion on a chip surface. It is an enlarged view which shows another example of a bump electrode formation part. 1 is a schematic cross-sectional view of an apparatus for manufacturing an ultra-thin semiconductor device according to an embodiment of the present invention. It is sectional drawing which shows the manufacturing process of the ultra-thin semiconductor device by the double porous Si layer separation method. It is sectional drawing for demonstrating C chamfering of the peripheral part of the support substrate surface after seed substrate separation.

Explanation of reference numerals

21, 23, 26, 28, 53, 55 Low porous Si layer 22, 27, 54 High porous Si layer 24, 29, 44, 56, 58 Single crystal Si layer 15, 47, 75 Bump electrode 16, 48, Reference Signs List 60 Cut groove 17, 45 UV tape 17a, 45a UV tape base material 17b, 45b UV irradiation curing adhesive 20, 42, 50 Seed substrate 25, 40, 52 Support substrate 30, 57 Insulating layer 30a, 41a SiO ₂
30b, 41b Si ₃ N ₄
43,51 High concentration hydrogen ion implanted layer (single crystal Si layer)
46,59 Strain in high concentration hydrogen ion implanted layer 70 Epoxy resin 71 Exposed Si layer 72 Conductive paste 73 Insulating thermosetting adhesive 74 Via hole 75 Wiring 76 Internal wiring 80 Guard ring stopper 81a, 81b Holder 82 High pressure fluid Jet 83 Fine nozzle 84 Slit hole

Claims (102)

A step of bonding a seed substrate and a supporting substrate each made of a semiconductor via an insulating layer,
Separating the seed substrate from the porous layer formed on the seed substrate,
Separating the support substrate from the porous layer formed on the support substrate. A step of forming a porous layer on both the seed substrate and the support substrate each made of a semiconductor,
Forming a semiconductor layer on both the seed substrate and the support substrate via the porous layer,
Forming an insulating layer on at least one of the seed substrate and the support substrate via the semiconductor layer;
Bonding the seed substrate and the support substrate on the surface on which the insulating layer is formed,
The step of separating the seed substrate from the porous layer of the seed substrate,
Etching and flattening the surface of the semiconductor layer by hydrogen annealing;
Forming a semiconductor device on the semiconductor layer;
Separating the support substrate from the porous layer of the support substrate. The ultra-thin film according to claim 2, wherein the separation from the porous layer is performed by jetting a high-pressure fluid jet of a gas, a liquid, or a mixture of a gas and a liquid onto the rotating porous layer. Of manufacturing a semiconductor device. 4. The method according to claim 3, wherein the high-pressure fluid jet is obtained by adding a fine solid. 4. The method according to claim 3, wherein the high-pressure fluid jet is applied with an ultrasonic wave. 3. The method according to claim 2, wherein the separation from the porous layer is performed by laser processing the rotating porous layer. 3. The method according to claim 2, wherein the separation from the porous layer is performed by laser water jet processing on the rotating porous layer. 3. The ultra-thin semiconductor device according to claim 2, wherein the separation of the support substrate is performed after forming a groove from the semiconductor layer to at least the porous layer along a dividing line when dividing the semiconductor device into ultra-thin semiconductor devices. Of manufacturing a semiconductor device. 9. The ultra thin device according to claim 8, wherein the separation from the porous layer is performed by jetting a high-pressure fluid jet of a gas, a liquid, or a mixture of a gas and a liquid onto the rotating porous layer. Of manufacturing a semiconductor device. The method for manufacturing an ultra-thin semiconductor device according to claim 9, wherein the high-pressure fluid jet is obtained by adding a fine solid. The method according to claim 9, wherein the high-pressure fluid jet is applied with an ultrasonic wave. 9. The method according to claim 8, wherein the separation from the porous layer is performed by laser processing the rotating porous layer. 9. The method according to claim 8, wherein the separation from the porous layer is performed by laser water jet processing on the rotating porous layer. 3. The method according to claim 2, wherein an n-type or p-type impurity is added to the porous layer of the support substrate to make the porous layer conductive. 3. The method for manufacturing an ultra-thin semiconductor device according to claim 2, wherein the separation of the seed substrate and the supporting substrate is performed in a state where the seed substrate and the supporting substrate are held by an ultraviolet irradiation curing type tape. 9. The method according to claim 8, wherein a semiconductor device and a protruding connection electrode connected to the semiconductor device are formed in the semiconductor layer before the groove is formed. After forming the groove, in a state where the surface of the semiconductor layer, including all of the semiconductor devices and the protruding connection electrodes formed in the semiconductor layer, is covered with an antistatic ultraviolet irradiation curable tape having no adhesive residue, 17. The method according to claim 16, wherein the supporting substrate is separated. 3. The method according to claim 2, wherein the porous layer formed on the seed substrate has a higher porosity than the porous layer formed on the support substrate. The method according to claim 2, wherein the porous layer formed on the seed substrate is thicker than the porous layer formed on the support substrate. The insulating layer,
Silicon oxide film,
Silicon oxynitride film,
A stacked film of silicon oxide and silicon nitride,
Silicon nitride film,
A stacked film in which silicon oxide, silicon nitride, and silicon oxide are sequentially stacked;
3. The method of manufacturing an ultra-thin semiconductor device according to claim 2, wherein the method includes at least one of an aluminum oxide film. After forming the groove,
Forming a resin protective film on the surface of the semiconductor layer including all of the semiconductor device and the protruding connection electrode formed on the semiconductor layer and in the groove;
Polishing the surface of the resin protective film to expose the protruding connection electrodes,
9. The method of manufacturing an ultra-thin semiconductor device according to claim 8, further comprising, after separating the support substrate, pelletizing the resin protective film in the groove. 22. The support substrate is separated in a state where the surface of the semiconductor layer including the exposed protruding connection electrodes is covered with an antistatic ultraviolet irradiation curable tape having no adhesive residue. The manufacturing method of the ultra-thin semiconductor device described in the above. 23. The method of manufacturing an ultra-thin semiconductor device according to claim 22, wherein the pelletizing division is performed including the ultraviolet irradiation curing type tape. A plurality of ultra-thin semiconductor devices after the pelletizing division are laminated and fixed via an insulating adhesive,
Forming a via hole penetrating the projecting connection electrode of each of the laminated ultra-thin semiconductor devices;
22. The method according to claim 21, wherein a conductive paste is filled and fixed in the via hole. The method for manufacturing an ultra-thin semiconductor device according to claim 24, wherein a portion other than the protruding connection electrodes is sealed with a resin protective film. A step of bonding a seed substrate and a supporting substrate each made of a semiconductor via an insulating layer,
Separating the seed substrate from the ion-implanted layer formed on the seed substrate,
Separating the support substrate from the ion-implanted layer formed on the support substrate. Forming a first ion-implanted layer on a seed substrate made of a semiconductor;
Forming an insulating layer on a supporting substrate made of a semiconductor;
Bonding a first ion-implanted layer of the seed substrate and an insulating layer of the support substrate, and covalently bonding the first ion-implanted layer and the insulating layer by heat treatment;
Performing a peeling annealing process to separate the seed substrate from the first ion-implanted layer to form a semiconductor layer;
Etching and flattening the surface of the semiconductor layer by hydrogen annealing;
Forming a semiconductor device on the etched semiconductor layer,
After these steps,
Forming a second ion-implanted layer at a predetermined depth from the surface of the support substrate;
Performing a peeling annealing treatment of the second ion-implanted layer;
Separating the support substrate from the second ion-implanted layer. 28. The method according to claim 27, wherein the separation from the second ion-implanted layer is performed by laser processing the rotating second ion-implanted layer. 28. The method according to claim 27, wherein the separation from the second ion-implanted layer is performed by laser water jet processing on the rotating second ion-implanted layer. 28. The method according to claim 27, wherein the separation of the supporting substrate is performed after forming a groove from the semiconductor layer to at least the second ion-implanted layer along a dividing line at the time of dividing into each ultrathin semiconductor device. A method for manufacturing an ultra-thin semiconductor device. Separation from the second ion-implanted layer is performed by curing the semiconductor layer including the semiconductor device formed on the semiconductor layer and all of the protruding connection electrodes and the support substrate by curing the semiconductor layer and the support substrate with antistatic ultraviolet irradiation without residual adhesive. 28. The method for manufacturing an ultra-thin semiconductor device according to claim 27, wherein the method is performed by pulling and peeling while holding the mold tape. 31. The method according to claim 30, wherein the separation from the second ion-implanted layer is performed by laser processing the rotating second ion-implanted layer. 31. The method according to claim 30, wherein the separation from the second ion-implanted layer is performed by laser water jet processing on the rotating second ion-implanted layer. 28. The method of manufacturing an ultra-thin semiconductor device according to claim 27, wherein the separation of the seed substrate and the support substrate is performed while holding the substrate with an ultraviolet irradiation curing tape. 31. The method according to claim 30, wherein a semiconductor device and a protruding connection electrode connected to the semiconductor device are formed in the semiconductor layer before the groove is formed. After forming the groove, in a state where the surface of the semiconductor layer, including all of the semiconductor devices and the protruding connection electrodes formed in the semiconductor layer, is covered with an antistatic ultraviolet irradiation curable tape having no adhesive residue, The method for manufacturing an ultra-thin semiconductor device according to claim 35, wherein the support substrate is separated. The insulating layer,
Silicon oxide film,
Silicon oxynitride film,
A stacked film of silicon oxide and silicon nitride,
Silicon nitride film,
A stacked film in which silicon oxide, silicon nitride, and silicon oxide are sequentially stacked;
The method for manufacturing an ultra-thin semiconductor device according to claim 27, further comprising at least one of an aluminum oxide film. The method for manufacturing an ultra-thin semiconductor device according to claim 27, wherein the annealing for peeling is performed by rapid thermal annealing. The method for manufacturing an ultra-thin semiconductor device according to claim 38, wherein the annealing for peeling radiates heat from a back surface of the support substrate. The method for manufacturing an ultra-thin semiconductor device according to claim 39, wherein the surface of the semiconductor layer is fluid-cooled through an ultraviolet irradiation curing type tape. After forming the groove,
Forming a resin protective film on the surface of the semiconductor layer including all of the semiconductor device and the protruding connection electrode formed on the semiconductor layer and in the groove;
Polishing the surface of the resin protective film to expose the protruding connection electrodes,
31. The method of manufacturing an ultra-thin semiconductor device according to claim 30, further comprising, after separating the support substrate, pelletizing the resin protective film in the groove. 42. The supporting substrate according to claim 41, wherein the support substrate is separated after covering the surface of the semiconductor layer including the exposed protruding connection electrodes with an antistatic ultraviolet irradiation curing type tape having no adhesive residue. A method for manufacturing an ultra-thin semiconductor device. 43. The method for manufacturing an ultra-thin semiconductor device according to claim 42, wherein the pelletizing division is performed including the ultraviolet irradiation curing type tape. A plurality of ultra-thin semiconductor devices after the pelletizing division are laminated and fixed via an insulating adhesive,
Forming a via hole penetrating the projecting connection electrode of each of the laminated ultra-thin semiconductor devices;
42. The method of manufacturing an ultra-thin semiconductor device according to claim 41, wherein a conductive paste is filled and fixed in the via hole. The method for manufacturing an ultra-thin semiconductor device according to claim 44, wherein a portion other than the protruding connection electrodes is sealed with a resin protective film. A step of bonding a seed substrate and a supporting substrate each made of a semiconductor via an insulating layer,
Separating the seed substrate from the ion-implanted layer formed on the seed substrate,
Separating the support substrate from the porous layer formed on the support substrate. A step of forming an ion-implanted layer on a seed substrate made of a semiconductor,
A step of forming a porous layer on a support substrate made of a semiconductor,
Forming a semiconductor layer on the support substrate via the porous layer,
Forming an insulating layer on the semiconductor layer;
Bonding the ion-implanted layer of the seed substrate and the insulating layer of the support substrate, and covalently bonding the ion-implanted layer of the seed substrate and the insulating layer of the support substrate by heat treatment;
Performing a peeling annealing process, separating the seed substrate from the ion-implanted layer,
Etching and flattening the surface of the semiconductor layer by hydrogen annealing;
Forming a semiconductor device on the etched semiconductor layer;
Separating the support substrate from the porous layer. 48. The method according to claim 47, wherein the separation from the porous layer is performed by laser processing the rotating porous layer. 48. The method according to claim 47, wherein the separation from the porous layer is performed by laser water jet processing on the rotating porous layer. 48. The ultra-thin semiconductor device according to claim 47, wherein the separation of the support substrate is performed after forming a groove from the semiconductor layer to at least the porous layer along a dividing line at the time of dividing the semiconductor device into each ultra-thin semiconductor device. Of manufacturing a semiconductor device. 51. The ultra thin device according to claim 50, wherein the separation from the porous layer is performed by jetting a high-pressure fluid jet of a gas, a liquid, or a mixture of a gas and a liquid onto the rotating porous layer. Of manufacturing a semiconductor device. The method for manufacturing an ultra-thin semiconductor device according to claim 51, wherein the high-pressure fluid jet is obtained by adding a fine solid. The method of manufacturing an ultra-thin semiconductor device according to claim 51, wherein the high-pressure fluid jet is applied with an ultrasonic wave. The method for manufacturing an ultra-thin semiconductor device according to claim 50, wherein the separation from the porous layer is performed by laser processing the rotating porous layer. The method for manufacturing an ultra-thin semiconductor device according to claim 50, wherein the separation from the porous layer is performed by laser water jet processing on the rotating porous layer. The method for manufacturing an ultra-thin semiconductor device according to claim 47, wherein an n-type or p-type impurity is added to the porous layer of the support substrate to make the porous layer conductive. The method for manufacturing an ultra-thin semiconductor device according to claim 47, wherein the separation of the seed substrate and the support substrate is performed while holding the substrate with an ultraviolet irradiation curing tape. The method of manufacturing an ultra-thin semiconductor device according to claim 50, wherein a semiconductor device and a protruding connection electrode connected to the semiconductor device are formed in the semiconductor layer before the groove is formed. After forming the groove, in a state where the surface of the semiconductor layer, including all of the semiconductor devices and the protruding connection electrodes formed in the semiconductor layer, is covered with an antistatic ultraviolet irradiation curable tape having no adhesive residue, The method for manufacturing an ultra-thin semiconductor device according to claim 58, wherein the support substrate is separated. The insulating layer,
Silicon oxide film,
Silicon oxynitride film,
A stacked film of silicon oxide and silicon nitride,
Silicon nitride film,
A stacked film in which silicon oxide, silicon nitride, and silicon oxide are sequentially stacked;
The method for manufacturing an ultra-thin semiconductor device according to claim 47, further comprising at least one of an aluminum oxide film. The method of manufacturing an ultra-thin semiconductor device according to claim 47, wherein the annealing for peeling is performed by rapid thermal annealing. After forming the groove,
Forming a resin protective film on the surface of the semiconductor layer including all of the semiconductor device and the protruding connection electrode formed on the semiconductor layer and in the groove;
Polishing the surface of the resin protective film to expose the protruding connection electrodes,
The method of manufacturing an ultra-thin semiconductor device according to claim 50, further comprising, after separating the support substrate, pelletizing the resin protective film in the groove. 63. The supporting substrate is separated in a state where the surface of the semiconductor layer including the exposed protruding connection electrodes is covered with an antistatic ultraviolet irradiation curing type tape having no adhesive residue. The manufacturing method of the ultra-thin semiconductor device described in the above. 64. The method for manufacturing an ultra-thin semiconductor device according to claim 63, wherein the pelletizing division is performed including the ultraviolet irradiation curing type tape. A plurality of ultra-thin semiconductor devices after the pelletizing division are laminated and fixed via an insulating adhesive,
Forming a via hole penetrating the projecting connection electrode of each of the laminated ultra-thin semiconductor devices;
65. The method for manufacturing an ultra-thin semiconductor device according to claim 64, wherein a conductive paste is filled and fixed in the via hole. Forming a porous layer on the supporting substrate;
Forming a semiconductor layer on the support substrate via the porous layer,
Forming a groove from the semiconductor layer to at least the porous layer along a dividing line when dividing into each ultra-thin semiconductor device;
Separating the support substrate from the porous layer after the formation of the groove. 67. The ultra thin device according to claim 66, wherein the separation from the porous layer is performed by injection of a high-pressure fluid jet of a gas, a liquid, or a mixture of a gas and a liquid onto the rotating porous layer. Of manufacturing a semiconductor device. The method of manufacturing an ultra-thin semiconductor device according to claim 67, wherein the high-pressure fluid jet is a liquid to which a fine solid is added. The method for manufacturing an ultra-thin semiconductor device according to claim 67, wherein the high-pressure fluid jet is applied with an ultrasonic wave. 67. The method according to claim 66, wherein the separation from the porous layer is performed by laser processing the rotating porous layer. 67. The method according to claim 66, wherein the separation from the porous layer is performed by laser water jet processing on the rotating porous layer. 67. The method of manufacturing an ultra-thin semiconductor device according to claim 66, wherein the separation of the supporting substrate is performed in a state where the supporting substrate is held by an ultraviolet irradiation curing type tape. 67. The method according to claim 66, wherein a semiconductor device and a protruding connection electrode connected to the semiconductor device are formed in the semiconductor layer before forming the groove. After the formation of the groove, the surface of the semiconductor layer, including all of the semiconductor devices and the protruding connection electrodes formed in the semiconductor layer, is covered with an antistatic ultraviolet irradiation curable tape having no adhesive residue. The method for manufacturing an ultra-thin semiconductor device according to claim 73, wherein the supporting substrate is separated. After forming the groove,
Forming a resin protective film on the surface of the semiconductor layer including all of the semiconductor device and the protruding connection electrode formed on the semiconductor layer and in the groove;
Polishing the surface of the resin protective film to expose the protruding connection electrodes,
The method for manufacturing an ultra-thin semiconductor device according to claim 73, further comprising, after separating the support substrate, pelletizing the resin protective film in the groove. The support substrate is separated in a state where the surface of the semiconductor layer including the exposed protruding connection electrodes is covered with an antistatic ultraviolet irradiation hardening tape having no adhesive residue. 75. The method for manufacturing an ultra-thin semiconductor device according to 75. The method for manufacturing an ultra-thin semiconductor device according to claim 76, wherein the pelletizing division is performed including the ultraviolet irradiation curing type tape. A plurality of ultra-thin semiconductor devices after the pelletizing division are laminated and fixed via an insulating adhesive,
Forming a via hole penetrating the projecting connection electrode of each of the laminated ultra-thin semiconductor devices;
The method for manufacturing an ultra-thin semiconductor device according to claim 75, wherein a conductive paste is filled and fixed in said via hole. The method for manufacturing an ultra-thin semiconductor device according to claim 78, wherein a portion other than the protruding connection electrodes is sealed with a resin protective film. Forming a semiconductor layer on the surface of the supporting substrate;
Forming an ion-implanted layer at a predetermined depth from the substrate surface,
Performing an annealing treatment for stripping the ion-implanted layer;
Forming a groove from the semiconductor layer to at least the ion-implanted layer along a dividing line when dividing into each ultra-thin semiconductor device;
Separating the support substrate from the ion-implanted layer after forming the groove. The method for manufacturing an ultra-thin semiconductor device according to claim 80, wherein the separation from the ion implantation layer is performed by laser processing on the rotating ion implantation layer. The method for manufacturing an ultra-thin semiconductor device according to claim 80, wherein the separation from the ion-implanted layer is performed by laser water jet processing on the rotating ion-implanted layer. The method for manufacturing an ultra-thin semiconductor device according to claim 80, wherein the separation of the supporting substrate is performed while the supporting substrate is held by an ultraviolet irradiation curing type tape. The method for manufacturing an ultra-thin semiconductor device according to claim 80, wherein a semiconductor device and a protruding connection electrode connected to the semiconductor device are formed in the semiconductor layer before forming the groove. After the formation of the groove, the surface of the semiconductor layer, including all of the semiconductor devices and the protruding connection electrodes formed in the semiconductor layer, is covered with an antistatic ultraviolet irradiation curable tape having no adhesive residue. The method for manufacturing an ultra-thin semiconductor device according to claim 80, wherein the support substrate is separated. The method for manufacturing an ultra-thin semiconductor device according to claim 80, wherein the annealing for peeling is performed by rapid thermal annealing. 89. The method of manufacturing an ultra-thin semiconductor device according to claim 86, wherein the annealing for peeling radiates heat from a back surface of the support substrate. The method for manufacturing an ultra-thin semiconductor device according to claim 87, wherein the surface of the semiconductor layer is fluid-cooled through an ultraviolet irradiation curing tape. After forming the groove,
Forming a resin protective film on the surface of the semiconductor layer including all of the semiconductor device and the protruding connection electrode formed on the semiconductor layer and in the groove;
Polishing the surface of the resin protective film to expose the protruding connection electrodes,
The method of manufacturing an ultra-thin semiconductor device according to claim 80, further comprising, after separating the support substrate, pelletizing the resin protective film in the groove. 90. The support substrate is separated after covering the surface of the semiconductor layer including the exposed protruding connection electrodes with an antistatic ultraviolet irradiation curing type tape having no adhesive residue. Method for manufacturing ultra-thin semiconductor device. A plurality of ultra-thin semiconductor devices after the pelletizing division are laminated and fixed via an insulating adhesive,
Forming a via hole penetrating the projecting connection electrode of each of the laminated ultra-thin semiconductor devices;
The method for manufacturing an ultra-thin semiconductor device according to claim 89, wherein a conductive paste is filled and fixed in the via hole. The method of manufacturing an ultra-thin semiconductor device according to claim 91, wherein a portion other than the protruding connection electrodes is sealed with a resin protective film. 3. A channel semiconductor layer in which a channel is induced and a strain applying semiconductor layer having a lattice constant different from that of the channel semiconductor layer and applying strain to the channel semiconductor, are formed on the porous semiconductor layer. The manufacturing method of the ultra-thin semiconductor device according to any one of claims 25 to 47 and 47 to 79. 3. A channel semiconductor layer in which a channel is induced, and a strain applying semiconductor layer having a lattice constant different from that of the channel semiconductor layer and applying a strain to the channel semiconductor, is formed on the single crystal semiconductor layer. The method of manufacturing an ultra-thin semiconductor device according to any one of claims to 25, 27 to 45, and 47 to 92. A channel semiconductor layer in which a channel is induced, and a strain applying semiconductor layer having a lattice constant different from that of the channel semiconductor layer and applying a strain to the channel semiconductor, is formed on the insulating layer. The method for manufacturing an ultra-thin semiconductor device according to any one of claims 25, 27 to 45, and 47 to 65. The method for manufacturing an ultra-thin semiconductor device according to any one of claims 93, 94, and 95, wherein the channel semiconductor layer is a silicon layer, and the strain applying semiconductor layer is a silicon germanium layer. The germanium concentration in the strain applying semiconductor layer gradually increases from the contact surface of the porous semiconductor layer, from the contact surface of the single crystal semiconductor layer, or from the contact surface of the insulating layer, The method for manufacturing an ultra-thin semiconductor device according to claim 96, wherein the composition has a gradient composition having a desired concentration on the surface. The peripheral portion of the surface of the support substrate including the ultra-thin SOI layer after separation of the seed substrate is C-chamfered, wherein: 65. The method of manufacturing an ultra-thin semiconductor device according to any one of items 65. After laminating the diameter of the seed substrate on which the single-crystal semiconductor layer is formed via the porous semiconductor layer to be larger or smaller than the diameter of the support substrate on which the single-crystal semiconductor layer and the insulating layer are formed via the porous semiconductor layer, and then bonding them. The high pressure fluid jet injection or the laser water jet injection is applied to the porous semiconductor layer of the seed substrate from the side or oblique direction to separate the seed substrate, and the surface of the support substrate including the ultra-thin SOI layer after the separation of the seed substrate is separated. 26. The method for manufacturing an ultra-thin semiconductor device according to claim 2, wherein the peripheral portion is chamfered. An apparatus for manufacturing an ultra-thin semiconductor device, which obtains an ultra-thin semiconductor device by applying a high-pressure fluid jet ejected from a fine nozzle to a separation layer of a rotating substrate and separating the semiconductor layer,
An apparatus for manufacturing an ultra-thin semiconductor device, comprising a jig having a slit formed between the separation layer and the fine nozzle for controlling the width of the high-pressure fluid jet. An apparatus for manufacturing an ultra-thin semiconductor device which obtains an ultra-thin semiconductor device by applying a laser beam irradiated from a laser output portion to a separation layer of a rotating substrate to separate the substrate. An apparatus for manufacturing an ultra-thin semiconductor device which obtains an ultra-thin semiconductor device by applying a laser water jet irradiated from an output section to a separation layer of a rotating substrate to separate the substrate.

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