JP2004165945A - Fir digital filter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a FIR digital filter whose circuit size can be made small. <P>SOLUTION: A selector 51 selectively outputs an input data signal and a signal output from a delay element 61 under the control from a switching control unit 101, and supplies it to a delay element 61. The data signal from the delay element 61 is output to a data signal output terminal 14 as a data signal sampled with the same frequency as an input clock signal via a latch 41. A tap coefficient signal is output from a memory 112 under the output timing control from a memory control unit 111. A multiplier 71 multiplies the output from the delay element 61 by the tap coefficient signal. The output data from the multiplier 71 is output as a tap output signal g1 via an adder 81 and a latch 43, and output to a filter signal output terminal 13 via a latch 42. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an FIR digital filter, and more particularly, to a circuit size reduction of a FIR (Finite Impulse Response) digital filter.
[0002]
[Prior art]
Conventionally, in an FIR digital filter, as shown in FIG. 4, delay elements 200 to 20m (m is a positive integer), multipliers 210 to 21n (n is a positive integer, n = m + 1), an adder 220 To 220 m.
[0003]
In the above-mentioned FIR digital filter, a plurality of delay elements 200 to 20m are connected in series between a data signal input terminal and a data signal output terminal, and a tap is formed at each connection.
[0004]
A plurality of multipliers 210 to 21n for multiplying tap coefficients H0 to Hn are connected to each tap, and an output terminal of each of the multipliers 210 to 21n is connected to a plurality of adders 220 to 220m. Is calculated and output (for example, see Patent Document 1).
[0005]
[Patent Document 1]
JP-A-2001-177378 (pages 2, 3; FIG. 5)
[0006]
[Problems to be solved by the invention]
In the above-mentioned conventional FIR digital filter, when the number of taps of the FIR digital filter is increased in order to obtain good characteristics, the number of multipliers is equal to the number of taps and the number of adders is one less than the number of taps. Is required.
[0007]
For example, in the case of a digital filter having 1000 taps, 1000 multipliers and 999 adders are required. When a filter with a large number of taps is configured, a large number of multipliers and adders are required as described above, so that the circuit scale becomes enormous and it is very difficult to form an integrated circuit.
[0008]
Therefore, an object of the present invention is to solve the above-mentioned problems and to provide an FIR digital filter capable of reducing the circuit scale.
[0009]
[Means for Solving the Problems]
The FIR digital filter according to the present invention includes a first clock which is m times (m is a positive integer) times an input clock signal obtained by sampling an input data signal, and a second clock which performs phase control on the input clock signal. , A product-sum calculator that performs a predetermined filter coefficient calculation process on the input data signal based on the first clock, and outputs a tap output signal, and the product-sum calculator And a first latch that samples the tap output signal from the second clock with the second clock.
[0010]
That is, the FIR (Finite Impulse Response) digital filter of the present invention performs phase control on the first clock and the input clock signal, which are m times (m is a positive integer) the input clock signal obtained by sampling the input data signal. A clock generator for generating a second clock, a product-sum calculator for performing a predetermined filter coefficient calculation process on the input data signal based on the first clock, and an output signal of the product-sum calculator. And a latch for sampling with a second clock.
[0011]
The product-sum operation unit includes a delay element for delaying an input signal by (m-1) stages, a selector for switching between an output signal of the delay element and an input data signal, a switching control unit for switching the selector, and a tap coefficient. A memory for storing signals, a memory control unit for controlling output of the memory, one multiplier for multiplying a tap coefficient signal output from the memory by an output signal from the delay element, It has one accumulator for sequentially accumulating the result of multiplying the delayed output signal and outputting the result, and a latch for sampling the output signal from the delay element at the input clock frequency.
[0012]
The accumulator has one adder for adding the output signal from the multiplier and the tap output signal output from the latch, a selector for switching between the output signal from the multiplier and the addition result from the adder, It comprises a switching control unit for switching the selector, and a latch for holding the output signal of the selector.
[0013]
With the above-described configuration, the FIR digital filter of the present invention can greatly reduce the circuit scale. Therefore, the FIR digital filter can be realized by a smaller integrated circuit than before, and the FIR digital filter has Characteristics can be maintained.
[0014]
Further, the FIR digital filter of the present invention can be realized by configuring the filter with m taps by multiplying the clock by m times. That is, in the FIR digital filter of the present invention, when the number of taps is increased, a filter having a large number of taps can be realized by increasing the multiple m of the input clock in the clock generator. In this case, m is the number of taps. For example, if m = 2000, a filter having 2,000 taps can be realized.
[0015]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a FIR (Finite Impulse Response) digital filter according to an embodiment of the present invention. In FIG. 1, an FIR digital filter according to an embodiment of the present invention samples an input data signal d1 input from a data signal input terminal 12 and clocks the input data signal a1 input from a clock signal input terminal 11 by m times. a clock generator 21 that generates b1 and clocks c1 and h1 of which the phase of the input clock signal a1 is controlled, a product-sum calculator 31 that performs a filter calculation process, and a tap output signal output from the product-sum calculator 31 and a latch 42 for sampling g1 at the input clock frequency (clock c1).
[0016]
The product-sum calculator 31 delays the input signal by (m-1) stages, a selector 51 that switches between the output signal e1 of the delay element 61 and the input data signal d1, and a switch that switches the selector 51. A control unit 101, a memory 112 for storing a tap coefficient signal f1, a memory control unit 111 for controlling the output of the memory 112, a tap coefficient signal f1 output from the memory 112, and an output signal e1 from the delay element 61 , A single accumulator 91 for sequentially accumulating the result of multiplying the tap coefficient signal f1 and the delayed output signal e1, and outputting the result. A latch 41 for sampling the output signal e1 at the input clock frequency (clock h1).
[0017]
The accumulator 91 includes one adder 81 for adding the output signal m1 from the multiplier 71 and the tap output signal g1 output from the latch 43, and the output signal m1 from the multiplier 71 and the output signal from the adder 81. The selector 52 includes a selector 52 for switching the addition result n1, a switching control unit 102 for switching the selector 52, and a latch 43 for holding the output signal q1 of the selector 52.
[0018]
FIG. 2 is a timing chart showing the operation of the FIR digital filter according to the embodiment of the present invention. FIG. 2 shows timings in the case where m = 4 as an example. The operation of the FIR digital filter according to the embodiment of the present invention will be described with reference to FIGS.
[0019]
An input clock signal a1 is input from a clock signal input terminal 11, and this input clock signal a1 is a clock that samples an input data signal d1 from a data signal input terminal 12. Therefore, the data signal d1 input from the data signal input terminal 12 is sampled by the input clock signal a1. The timing relationship between the input clock signal a1 and the input data signal d1 is as shown in FIG.
[0020]
The clock generator 21 outputs the input clock signal a1 as a clock b1 multiplied by m, and the product-sum calculator 31 performs a filter operation based on the clock b1 multiplied by m. For example, the timing relationship between the clock b1 quadrupled output from the clock generator 21 and the input clock signal a1 when m = 4 is as shown in FIG.
[0021]
The clock generator 21 supplies the clock h1 to the latch 41 and the clock c1 to the latch 42. The clocks c1 and h1 are clocks having the same sampling frequency as the input clock signal a1, but the phase of the input clock signal a1 is changed in order to match the timing with the data signals input to the latches 41 and 42. It is generated under control and output to the respective latches 41 and 42.
[0022]
The selector 51 selectively outputs the input data signal d1 and the data signal e1 output from the delay element 61 delayed by (m-1) stages, and supplies the data signal e1 to the delay element 61. The switching control unit 101 supplies a switching control signal r1 that outputs a High pulse to the selector 51 once every m times, and switches the selector 51. For example, the timing relationship among the delay element 61, the switching control unit 101, and the selector 51 when m = 4 is as shown in FIG.
[0023]
In FIG. 2, the switching control signal r1 output from the switching control unit 101 is output as a High pulse once every four times. The selector 51 selects the input data signal (A, B, C, D) when the switching control signal r1 is High pulse, and outputs the output data [(X, Y) of the delay element 61 when the switching control signal r1 is Low pulse. , Z), (Y, Z, A), (Z, A, B), (A, B, C)].
[0024]
The output data k1 of the selector 51 is input to the delay element 61, delayed by three stages, and input again to the selector 51. As described above, data processing between the selector 51 and the delay element 61 is repeatedly performed cyclically, and the data signal e1 output from the delay element 61 is supplied to the latch 41.
[0025]
As shown in FIG. 2, the clock h1 used in the latch 41 matches the timing of the data signal e1 output from the delay element 61. Is output. Therefore, the data signal e1 is output to the data signal output terminal 14 via the latch 41 as the data signal s1 (here, W, X, Y, Z) sampled at the same frequency as the input clock signal a1.
[0026]
The memory control unit 111 controls the output timing from the memory 112 and outputs the tap coefficient signal f1. The tap coefficient signal f1 corresponds to the tap coefficients H0 to Hn of the conventional example shown in FIG. The tap coefficients are all stored in the memory 112, output by the clock b 1 multiplied by m under the control of the memory control unit 111, and supplied to the multiplier 71.
[0027]
Since the data signal e1 output from the delay element 61 is also supplied to the multiplier 71, the multiplier 71 outputs the data signal e1 in synchronization with the output from the delay element 61. The multiplication with the tap coefficient signal f1 is performed. The input timing to the multiplier 71 is, for example, as shown in FIG. 2 when m = 4.
[0028]
In FIG. 2, the tap coefficient signal f1 is set to (X, Y, Z, A) every four data signals e1 output from the delay element 61, and the timing is adjusted to four taps ( Here, H3 to H0) are output, and are sequentially multiplied by X * H3, Y * H2, Z * H1, and A * H0. The result m1 of the multiplier 71 is output as Mb0 to Mb3, as shown in FIG.
[0029]
One of the outputs from the multiplier 71 is directly supplied to the selector 52. The other of the outputs from the multiplier 71 is supplied to an adder 81. The adder 81 adds the output m1 from the multiplier 71 and the tap output signal g1 output from the latch 43, and supplies the addition result to the selector 52.
[0030]
The switching control section 102 switches the selector 52 once every m times as a switching control signal p1 for outputting a High pulse. For example, when m = 4, the timing relationship among the latch 43, the adder 81, the switching control unit 102, and the selector 52 is as shown in FIG.
[0031]
In FIG. 2, the switching control signal p <b> 1 output from the switching control unit 102 outputs a High pulse once every four times. The selector 52 selects the output data m1 (Mb0, Mc0, Md0, Me0) of the multiplier 71 when the switching control signal p1 is a High pulse, and the output data n1 of the adder 81 when the switching control signal p1 is a Low pulse. (Ab1 to Ab3, Ac1 to Ac3, Ad1 to Ad3) are selected and output.
[0032]
The output data q1 of the selector 52 is delayed by one stage in the latch 43 and then input to the adder 81 again. As described above, the switching control unit 102, the adder 81, the selector 52, and the latch 43 constitute an accumulator 91. The accumulator 91 sequentially accumulates the multiplied results and outputs the result. ing.
[0033]
The accumulator 91 clears the accumulated result by selecting the output data of the multiplier 71 by the selector 52, and becomes the initial value of the accumulation, and starts the successive accumulation again. The arithmetic processing or data processing up to this point is configured as the product-sum calculator 31 by the selectors 51 to accumulator 91 described above.
[0034]
As shown in FIG. 2, the clock c1 used in the latch 42 is input to the clock generator 21 in order to match the timing with the tap output signal g1 output from the accumulator 91 of the product-sum calculator 31. The clock signal a1 is output with its phase controlled. Therefore, the tap output signal g1 is output to the filter signal output terminal 13 via the latch 42 as the tap output signal t1 (here, Az3, Aa3, Ab3, Ac3) sampled at the same frequency as the input clock signal a1. .
[0035]
As described above, the FIR digital filter according to the embodiment of the present invention can significantly reduce the circuit scale. For example, when the number of taps is 1000 in the conventional FIR digital filter, 1000 multipliers and 999 adders are required. On the other hand, in the FIR digital filter according to the embodiment of the present invention, the clock multiplied by m is used. Is set to 1000 times, only one multiplier 71 and one accumulator 91 are required. Therefore, the circuit scale can be significantly reduced, and the good characteristics of the FIR digital filter can be maintained.
[0036]
Furthermore, in the FIR digital filter according to the embodiment of the present invention, when the number of taps is increased, a filter having a large number of taps can be realized by increasing the multiple m of the input clock signal a1 in the clock generation unit 21. . That is, m is the number of taps. For example, if m = 2000, a filter having 2,000 taps can be realized.
[0037]
FIG. 3 is a block diagram showing the configuration of the FIR digital filter according to one embodiment of the present invention. In FIG. 3, the FIR digital filter according to one embodiment of the present invention adds product-sum calculators 31 to 35 connected in series in five stages and tap output signals g1 to g5 from the respective product-sum calculators 31 to 35. It comprises an adder 121, a clock generator 21, and a latch 42. Since the operation of the clock generator 21 is the same as that of the above-described embodiment of the present invention, the description of the operation is omitted.
[0038]
The input data signal d1 input from the data signal input terminal 12 is supplied to the product-sum calculator 31 in the first stage, and the data signal s1 is output from the product-sum calculator 31 by the operation of the product-sum calculator 31 described above. Then, it is supplied to the product-sum calculator 32 in the second stage. Hereinafter, similarly to this operation, the operation is performed by the third-stage product-sum operation unit 33, the fourth-stage product-sum operation unit 34, and the fifth-stage product-sum operation unit 35.
[0039]
The tap output signals g1 to g5 output from the product-sum calculators 31 to 35 are supplied to the adder 121 to calculate a final accumulation result. As described above, the addition result u1 output from the adder 121 is output to the filter signal output terminal 13 via the latch 42 as the tap output signal t1 sampled at the same frequency as the input clock signal a1.
[0040]
In this embodiment, even when the frequency of the clock signal multiplied by m is limited in the digital filter, the circuit scale is greatly reduced as compared with the conventional digital filter by connecting the product-sum calculators 31 to 35 in series. It is an example showing that it can be performed. For example, in the case of a conventional FIR digital filter having 1,000 taps, 1000 multipliers and 999 adders are required. In the present embodiment, however, the maximum clock in the product-sum calculators 31 to 35 is used. Even if the frequency is limited to 200 times the input clock, only five multipliers and five accumulators in the product-sum calculators 31 to 35 and one adder 121 are required. Therefore, the circuit scale can be reduced, and good characteristics of the FIR digital filter can be maintained.
[0041]
Further, when increasing the number of taps, a filter with a large number of taps can be provided by connecting the number of product-sum operation units in n stages. That is, when the maximum clock frequency is limited in the digital filter as described above, m × n is the number of taps. For example, if m = 200 and n = 10, a filter having 2,000 taps can be realized. .
[0042]
As described above, in the FIR digital filter according to the present embodiment, the circuit scale can be significantly reduced, and the good characteristics of the FIR digital filter can be maintained.
[0043]
Furthermore, in the FIR digital filter according to the present embodiment, when the number of taps is increased, a filter having a large number of taps can be realized by increasing the multiple m of the input clock signal a1 in the clock generator 21. In this case, m is the number of taps. For example, if m = 2000, a filter having 2,000 taps can be realized.
[0044]
【The invention's effect】
As described above, according to the present invention, the first clock obtained by multiplying the input clock signal by sampling the input data signal by m (m is a positive integer) and the second clock obtained by performing phase control on the input clock signal are used. , A sum-of-products arithmetic unit for performing a predetermined filter coefficient arithmetic process on an input data signal based on a first clock and outputting a tap output signal, and a tap from the sum-of-products arithmetic unit By providing a latch for sampling the output signal with the first clock, an effect that the circuit scale can be reduced can be obtained.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of an FIR digital filter according to an embodiment of the present invention.
FIG. 2 is a timing chart showing an operation of the FIR digital filter according to the embodiment of the present invention.
FIG. 3 is a block diagram showing a configuration of an FIR digital filter according to one embodiment of the present invention.
FIG. 4 is a block diagram showing a configuration of a conventional FIR digital filter.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 11 Clock signal input terminal 12 Data signal input terminal 13 Filter signal output terminal 14 Data signal output terminal 21 Clock generators 31 to 35 Product sum calculators 41 to 43 Latches 51 and 52 Selectors 61 Delay elements 71 Multipliers 81 Adders 91 Cumulative Arithmetic units 101 and 102 switching control unit 111 memory control unit 112 memory 121 adder

Claims (8)

A clock generator that generates a first clock that is m times (m is a positive integer) times the input clock signal obtained by sampling the input data signal and a second clock that performs phase control on the input clock signal; A product-sum calculator that performs a predetermined filter coefficient operation on the input data signal based on the first clock and outputs a tap output signal; and outputs the tap output signal from the product-sum calculator to the A first latch sampling at two clocks. The product-sum operation unit includes a delay element that delays an input signal by (m−1) stages, a first selector that switches an output signal of the delay element and the input data signal, and a memory that stores a tap coefficient signal in advance. A multiplier that multiplies a tap coefficient signal output from the memory by an output signal from the delay element, an accumulator that sequentially accumulates and outputs a multiplication result of the multiplier, and A second latch that samples the output signal of the second clock with the second clock.
2. The FIR digital filter according to claim 1, wherein an output of said accumulator is output as said tap output signal. 3. The FIR digital filter according to claim 2, further comprising first switching control means for switching the first selector based on the first clock. 4. The FIR digital filter according to claim 2, further comprising a memory control unit that controls output of the tap coefficient signal from the memory based on the first clock. The accumulator, an adder for adding the output signal from the multiplier and the tap output signal, a second selector for switching between the output signal from the multiplier and the addition result from the adder, 5. The FIR digital filter according to claim 2, further comprising: a latch for holding an output signal of said second selector at said first clock. 6. The FIR digital filter according to claim 5, further comprising second switching control means for switching the second selector based on the first clock. 7. The FIR digital filter according to claim 1, wherein the multiply-accumulate units are connected in a plurality of stages in series. The FIR digital filter according to any one of claims 1 to 7, wherein when increasing the number of taps, a multiple m of the input clock signal in the clock generator is increased.

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