JP2004157663A - Wiring pattern generation method and wiring pattern generation device - Google Patents

Abstract

An object of the present invention is to provide a semiconductor integrated circuit in which appropriate wiring delay measures are taken and which have desired characteristics. In addition, the degree of freedom in wiring layout is increased, and the chip area is reduced and the performance of the semiconductor integrated circuit is improved. Reduction of man-hours for correction and reduction of the time required for layout.
After determining an arrangement position of elements mounted on a semiconductor integrated circuit, a distance of a shortest path connecting the elements is calculated to calculate a provisional delay value, and the provisional delay value is calculated for each wiring. The required number of contacts in multi-layer wiring and the position are determined so that the required delay value is obtained. A wiring pattern is generated based on the wiring pattern.
[Selection diagram] Fig. 1

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a wiring pattern generation method and a wiring pattern generation device, and more particularly to a layout method of a semiconductor integrated circuit designed using a computer, and particularly to a wiring in consideration of timing.
[0002]
[Prior art]
Not to mention computers, the range of use of LSIs is expanding to communication devices such as mobile phones, general household products, toys, and automobiles.
[0003]
Under such circumstances, the LSI is positioned as a key device in each product, and a large-scale and high-speed LSI is required to secure the competitiveness of the product. As the product cycle becomes shorter, automation of LSI design is indispensable to meet these demands. In recent years, attention has been paid to the design of semiconductor integrated circuits using LSI computers. In each of the LSI design flows, the layout process and the wiring process performed at the time of layout are designed using an automatic layout tool, and the development period is shortened by reducing the number of man-hours.
[0004]
In the flow using a general automatic layout tool performed today, cell arrangement processing is performed using circuit connection information (netlist) while considering congestion and timing, and the cell arrangement position is determined. Wiring between terminals to be connected later is performed.
[0005]
Normally, in the routing process, the degree of congestion is evaluated from the result of the rough routing process, a rough routing route is determined, it is confirmed that the routing can be performed at this stage, and the routing is performed in the detailed routing process so as to satisfy the graphic design rule. Is going.
[0006]
However, when there is an area where wiring is congested, a wiring path different from the estimation at the time of general wiring may be taken in order to avoid the congestion. When such a detour path is taken, the distance of the wiring becomes long as a result, the resistance value and the capacitance value of the wiring increase, and the required delay value may not be satisfied. Conversely, if there is a path to which a delay is to be added, a logically redundant buffer must be inserted in series in order to obtain a desired delay with the cell delay, resulting in an increase in area and This has led to an increase in power.
[0007]
Conventionally, there has been proposed a method of estimating a schematic wiring route, evaluating wiring properties and timing properties, and performing wiring again in consideration of a constraint condition (see Patent Document 1). In this method, provisional schematic wiring is performed to satisfy a required delay value and a wiring path is obtained, thereby extracting a resistance value and a capacitance value of a wiring of interest, calculating a provisional delay value, and calculating a violation. If there is, the temporary wiring processing is performed again. In addition, there has been proposed a method of designing a wiring in which priority is given to a wiring having a large violation with respect to a delay value so that the congestion degree and the timing are compatible and the delay value is reduced.
[0008]
[Patent Document 1]
JP 2000-223578 A
[Problems to be solved by the invention]
By the way, the number of contacts passing through the wiring path has a great influence on the delay in the wiring. However, in the above method, no consideration is given to the contact that passes when the wiring layer is switched.
[0010]
In today's semiconductor integrated circuits, a multilayer wiring structure is used in order to realize high integration. For this reason, the wiring for connecting the terminals includes a contact (via) formed in the interlayer insulating film for changing the wiring between the wiring for connecting the same wiring layer and the wiring layer.
[0011]
For the wiring connecting the same wiring layer, the wiring width and the wiring interval are determined for each process. With the automatic layout tool, the wiring connecting the vertical direction (the direction perpendicular to the substrate surface) and the horizontal direction (the direction parallel to the substrate surface) ) Are predetermined. In the multilayer wiring process, wiring layers are allocated to each of the vertical direction and the horizontal direction.
[0012]
For example, in the case of four-layer wiring, the first and third wiring layers are allocated in the horizontal direction, and the second and fourth layers are allocated in the vertical direction. Therefore, when the wiring layer is changed, that is, when the wiring layer is bent by 90 degrees, it is necessary to pass through the contact. Although the shape of the contact differs depending on the design rule for each process, it is generally set to be smaller than the normal wiring width, so that the resistance value increases, which is one of the causes that affects the wiring delay.
[0013]
For this reason, there is a problem that it cannot be said that sufficient measures against wiring delay are taken even by the above method.
[0014]
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor integrated circuit which has appropriate wiring delay measures and has desired characteristics.
It is another object of the present invention to increase the degree of freedom in wiring layout, reduce the chip area, and improve the performance of a semiconductor integrated circuit.
It is another object of the present invention to reduce the number of repair steps and reduce the time required for layout.
[0015]
[Means for Solving the Problems]
Therefore, the wiring method of the present invention determines the arrangement position of the elements mounted on the semiconductor integrated circuit, calculates the distance of the shortest path connecting the elements, calculates a provisional delay value, and calculates the provisional delay value. Then, the required delay value for each wiring is compared with each other, and the case of the wiring is classified based on the comparison result.
[0016]
When the provisional delay value calculated on the shortest path is substantially equal to the required delay value, the maximum number and position of contacts are determined. Thereafter, re-schematic wiring and re-detailed wiring are performed using the determined contact position information. In this processing, priority wiring is performed so as to always pass through the determined contact in the wiring path, and wiring is performed so as to maintain the calculated shortest path delay value.
[0017]
If the delay calculated by the provisional detailed wiring route is smaller than the required delay time, the contact position is determined at a position that is not on the shortest route (such that the shortest route cannot be connected), and By carrying out priority wiring so as to pass through, a detour path is taken and wired.
[0018]
In addition, for a wiring that does not require a delay value, the number of contacts and the position are not specified, the wiring is performed with the lowest priority, and the wiring is routed while bypassing a high congestion area. Is used effectively to realize a highly integrated LSI.
[0019]
A wiring pattern generating apparatus used for realizing the wiring pattern includes a distance calculating unit that calculates a distance of a shortest path connecting cells from connection information in a layout design of a semiconductor integrated circuit, based on the distance of the shortest path. A delay value calculating means for calculating a provisional delay value, a timing delay of the circuit is evaluated from design data, and a request delay value calculating means for calculating a required delay value required between cells; Pattern generation means for comparing the provisional delay value with the provisional delay value to determine the number and position of contacts used in performing multilayer wiring, and generating a wiring pattern based on the determined contact position.
[0020]
The present invention has been made in view of the following facts.
[0021]
That is, from the viewpoint of delay values, the present inventors consider that each wiring constituting a semiconductor integrated circuit has a wiring that must be suppressed to a required wiring delay value or less, and a wiring that has a required wiring delay value or more. Have been found to be able to be divided into three types: wiring that must have a delay and wiring that does not require delay (they only need to be electrically connected).
[0022]
Of the three types, when the wiring delay value must be kept below the required wiring delay value (hereinafter referred to as Case 1), the data transition time between flip-flops becomes longer than the clock cycle and a setup timing violation occurs. Such a case and a case where a delay value of an interface with the outside of the semiconductor chip is required belong to this. In such a case, it is desirable to connect the signal wiring path with the shortest path in order to reduce the resistance value and the capacitance value.
[0023]
By the way, if the positions of the terminals to be connected are determined after the cell arrangement processing, the distance of the shortest path of the signal connecting the terminals can be calculated. This distance is generally called the Manhattan distance.
[0024]
As shown in FIG. 2, when the terminals 201 and 202 are connected to each other, and their coordinates are (x1, y1) and (x2, y2), the Manhattan distance L indicated by 203 is given by the following equation (1). Can be
L = | x2-x1 | + | y2-y1 | ... Formula (1)
That is, the Manhattan distance is the length of the shortest path in the wiring method using the wiring grid. However, the route connected by the Manhattan distance is not limited to one route shown in FIG.
[0025]
FIG. 3 is a diagram illustrating the number of routes connected by the Manhattan distance. If there are M paths in the X direction and N paths in the Y direction, the number of paths that can be wired between the terminal 301 and the terminal 302 is M and N, respectively. It increases according to. In this case, the sum of the distances of the wirings is equal in any of the routes, but the number of switching wirings, that is, the number of contacts is different.
[0026]
Further, FIG. 4 shows a wiring route when the number of contacts increases to 2, 3, and 4. As described above, even if wiring is performed in the shortest route, the resistance value of the wiring is increased by passing through the contact, and as a result, the delay value due to the wiring is increased and the required delay condition cannot be satisfied. was there. In such a case, it is necessary to limit not only the wiring path but also the maximum usable number of contacts.
[0027]
Further, when the delay value must be equal to or more than the required wiring delay value (hereinafter referred to as Case 2), the variation (skew) of the signal arrival delay time of two or more terminals is suppressed, and the delay between flip-flops is reduced. Is too small, a hold time error occurs in which the data signal arrives before the clock arrival time of the subsequent flip-flop, or a delay value of the interface with the outside of the semiconductor chip is required. Conventionally, when such a timing violation occurs, a delay cell or the like is inserted between the terminals to add a delay value of the cell, thereby delaying the propagation delay between the terminals.
However, this method has a problem in that the connection information (netlist) of the circuit must be corrected, and the number of development steps increases. Furthermore, the insertion of the delay cells causes a problem that the area for the inserted cells increases and the power consumption increases. In this case, in order to increase the delay due to the wiring, it is necessary to make the distance of the wiring path longer than the shortest path.
[0028]
In addition, as a wiring that does not require a delay (there is only an electrical connection) (hereinafter, this case is referred to as case 3), for example, a reset signal that is not critical in time, a mode switching signal, a test circuit, and the like belong. . These signals only need to be electrically connected, and need not necessarily be wired in the shortest path. However, this does not mean that the wiring delay may be unlimitedly large, and the signal propagation time (slew) constraint that is equal to or more than the library specified value of each cell must be satisfied. These signals are signals that are allowed to pass through the contacts indefinitely and repeat the bypass wiring even in an area where the wiring is congested.
In this case, by increasing the wiring area while avoiding the wiring paths in the first case and the second case, it is possible to suppress an increase in area due to the wiring.
Thus, the layout is designed for the semiconductor integrated circuit by dividing the case according to the degree of delay requirement.
[0029]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described.
It is assumed that the terminals described in this embodiment include all wiring layers, and that the wiring in the vertical direction and the wiring in the horizontal direction are assigned to each wiring layer. For further simplification, the number of wiring layers is one in each of the vertical and horizontal directions.
[0030]
In this method, it is detected whether or not there is a request for a cell delay value, and if this request is made, a provisional delay value is calculated based on the shortest path, and the provisional delay value is used as the request delay value. It is characterized in that it is determined whether or not the condition is satisfied, and the contact position and the number of contacts are adjusted based on the result of this determination.
[0031]
That is, when there is a request for the cell delay value, a delay value with the shortest path and the number of contacts of one is calculated, and when it is desired to maintain the wiring delay for the wiring having the required delay, The case is divided into two cases where it is desired to increase the wiring delay with respect to the value.
[0032]
Thereafter, in each case, the number and position of the contacts are determined, and when performing the rewiring, the intended delay value can be obtained by giving a constraint that always passes through the determined contact position. Timing violations caused by wiring paths can be reduced, which is effective in improving the performance of LSI and reducing the number of repair steps. In addition, it is possible to prevent the increase in chip size by bypassing the wiring even if there is an area where the wiring is congested even if there is an area where the wiring is congested by making a detour path for wiring that does not require delay. Become.
[0033]
FIG. 1 shows a processing flow of a layout method for a semiconductor integrated circuit according to the present embodiment.
In this method, first, cells existing in a circuit are arranged using any method such as a manual arrangement, an automatic arrangement tool, and a timing-driven arrangement tool (step 101). At this time, the coordinates between the terminals to be connected are determined.
[0034]
Thereafter, it is determined whether or not the wiring of interest has a requirement for a required delay value in the design data (step 102).
If there is a request for a delay value in the determination step 102 (case 1 and case 2 described above), the delay value of the line of interest is provisionally calculated based on the shortest path (step 103).
[0035]
On the other hand, if there is no request for the delay value in the judgment step 102 (case 3 described above), the process proceeds to the remaining wiring process, that is, the wiring process with the lowest priority (step 108).
[0036]
In step 103, the delay value when the shortest path is taken is calculated. At this time, taking into account the capacitance between adjacent wirings, for example, it is assumed that the number of contacts is one (this is assumed to be temporary). Detailed wiring).
[0037]
Then, the provisional delay value of the wiring of interest calculated in step 103 is compared with the required delay value (step 104).
If it is desired to maintain the provisional delay value due to the wiring based on the result of the determination step 104 (case 1 described above), the process proceeds to a usable contact number determination processing step to determine the number of contacts and to set the contact position within the shortest path possible area. It is determined (step 105).
[0038]
On the other hand, if it is desired to increase the delay value in the determination step 104, the distance to be increased from the shortest path is calculated based on the delay value to be increased, and the contact position and the number of contacts are determined outside the shortest path area (step 106).
[0039]
Next, a process for maintaining the wiring delay (case 1) will be described. In the flow of FIG. 1, in step 105 for determining the number of available contacts and the position, the maximum allowable number of contacts of a wiring to be noted is determined. FIG. 5 is a diagram showing this contact number determination processing step.
[0040]
First, reference is made to the calculated delay value of the shortest route calculated in step 103 (step 501). Then, the required delay value of the circuit is referred to from the design data (step 502).
[0041]
Then, the maximum number of available contacts that can be used in the shortest route is calculated (step 503). The maximum number of available contacts is determined based on the difference between the required delay value and the provisional delay value of the shortest path.
[0042]
Then, referring to the wiring congestion degree (step 504), the contacts within the determined number are arranged in the shortest path area (step 505).
At this time, as the number of usable contacts is smaller, the wiring path is more limited. FIG. 6 and FIG. 7 are diagrams illustrating limited wiring paths. In this case, the position of the contact to be determined must be located inside a region 603 indicated by rectangular hatching with a straight line connecting the two vertices 201 and 202 as diagonal lines, and at a portion where the tracks overlap. This is because, if the contact position is determined in a portion other than the region 603, the shortest route cannot be formed. Here, it is assumed that there are five wiring tracks between the terminals in each of the X and Y directions. For example, when the number of usable contacts is set to 1, only two paths that can pass between the vertices 601 or 602 can be connected between terminals.
[0043]
Further, when the number of used contacts is set to 2, as shown in FIG. 2, a route passing through the vertices 701 and 704 simultaneously, a route passing through the vertices 702 and 705 simultaneously, and There are a total of six systems: a path that passes through the vertices 707 and 710 simultaneously, a path that passes through the vertices 708 and 711 simultaneously, and a path that passes through the vertices 709 and 712 simultaneously. In this way, as the number of available contacts increases, the number of wiring paths increases, the degree of freedom of wiring increases, and wiring can be performed avoiding a congested area.
[0044]
Next, a process for increasing the wiring delay (case 2) will be described with reference to FIG. First, the provisional delay value calculated in step 103 is referred to (step 801). Next, the required delay value is referred to (step 802), the provisional delay value is compared with the required delay value, the amount of delay to be added in the wiring is calculated, and the shortest path possible area (the area in FIG. 9) is calculated. 901) is calculated (step 803). Then, referring to the wiring congestion degree (step 804), the contact position is determined outside the shortest path possible area in the area with a small congestion degree (step 805).
[0045]
FIG. 9 schematically illustrates this. For example, in FIG. 9, the contact position is determined at a point coordinate 902 outside the rectangular area 901 having a diagonal line connecting two points and at the intersection of the tracks. When the subsequent wiring processing is performed, a route as shown in FIG. 10 is taken, so that it is possible to increase the capacitance value due to the increase in the wiring distance and the resistance value due to the increase in the number of contacts, thereby increasing the delay value of the wiring. .
[0046]
Finally, a case where there is no request for a delay value (case 3) will be described. In this case, no matter what detour path is taken, the wiring may have any number of contacts, so that it is not necessary to specify the number of contacts or the position. Further, the wiring priority is set lower, and wiring is performed while avoiding the already wired area. By doing so, the free area of the wiring area can be effectively used, and the increase in area due to the present invention can be suppressed.
[0047]
According to the present embodiment, it is determined whether or not it is an area where the control of the delay value is necessary, and the delay value is controlled only when it is necessary. In addition, it is possible to increase the degree of freedom of the wiring layout, to reduce the chip area, and to reduce the time required for the layout.
[0048]
In addition, since the layout is determined in consideration of the number of contacts and the contact position in the calculation of the delay value, timing violations caused by the wiring paths can be reduced, and a more accurate layout can be realized more efficiently. It becomes possible.
Furthermore, since adjustments such as increasing the number of contacts are made in the portions where the delay value needs to be increased, it is possible to provide a semiconductor integrated circuit having a function close to the design value without increasing the chip area. It becomes possible.
[0049]
In the above-described embodiment, it is determined whether or not the area is the area where the control of the delay value is necessary, and the delay value is controlled only when it is necessary. Alternatively, the process may be skipped to the step 103 of calculating the provisional delay value directly from the distance of the shortest path. As a result, although the degree of freedom is slightly reduced, it is possible to reduce the timing violation caused by the wiring path.
[0050]
【The invention's effect】
As described above, according to the method for generating a wiring pattern of the present invention, it is determined whether or not an area requires control of a delay value, and the delay value is controlled based on the determination result. Therefore, there is no need to limit more than necessary, and the degree of freedom of the wiring layout can be increased.
Therefore, the chip area can be reduced and the performance of the semiconductor integrated circuit can be improved, the number of repair steps can be reduced, and the time required for layout can be reduced.
Further, according to the wiring pattern generation device of the present invention, it is possible to easily lay out a high-performance semiconductor integrated circuit.
[Brief description of the drawings]
FIG. 1 is a flowchart of an overall process in a layout design method according to an embodiment.
FIG. 2 is a diagram illustrating a Manhattan distance.
FIG. 3 is a drawing showing the number of wiring paths between two points.
FIG. 4 is a diagram showing that the number of contacts used is different even when the shortest route wiring is performed between two points.
FIG. 5 is a flowchart showing a process for suppressing a wiring delay value.
FIG. 6 is a diagram showing a wiring path when the number of used contacts is set to 1 in order to suppress a wiring delay value.
FIG. 7 is a diagram showing a wiring path when the number of contacts used is set to 2 in order to suppress a wiring delay value.
FIG. 8 is a flowchart showing a process for increasing a wiring delay value.
FIG. 9 is a diagram illustrating a case where a used contact position is determined outside a shortest path range in order to increase a wiring delay value.
FIG. 10 is a diagram illustrating a wiring path when a used contact position is determined outside a shortest path range in order to increase a wiring delay value.

Claims (3)

In a layout design of a semiconductor integrated circuit, a step of obtaining a distance of a shortest path of a wiring connecting between cells in the circuit;
Calculating a provisional delay value based on the distance of the shortest path,
Estimating the timing of the circuit from the connection information and calculating a required delay value required between cells;
Comparing the required delay value and the provisional delay value, based on the comparison result, to obtain a required delay value, to determine the number and position of contacts used when performing multilayer wiring,
Generating a wiring pattern based on the determined contact position. 2. The method according to claim 1, further comprising, prior to the step of calculating the provisional delay value, evaluating a timing property of the circuit from connection information and determining whether there is a request for delay based on the obtained evaluation result. 3. The wiring pattern generation method according to 1. In the layout design of the semiconductor integrated circuit, from the connection information, distance calculation means for calculating the distance of the shortest path connecting the cells,
Delay value calculating means for calculating a provisional delay value based on the distance of the shortest path,
Request delay value calculation means for evaluating the timing of the circuit from the design data and calculating a required delay value required between cells;
The required delay value is compared with the provisional delay value, and the number and position of contacts used in performing multilayer wiring are determined based on the comparison result so as to be the required delay value, based on the determined contact position. A wiring pattern generating device for generating a wiring pattern by using the wiring pattern generating device.

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