JP2004153293A - Capacitance element, semiconductor memory device and method for manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To maintain the oxygen barrier property of a lower electrode in a capacitor and to prevent a capacitor insulating film made of a metal oxide of the capacitor from being reduced.
A side surface of a lower electrode is made of aluminum oxide having a thickness of about 5 to 100 nm, and is covered with a first insulating barrier layer for preventing diffusion of oxygen and hydrogen. The upper surface of the upper electrode 33 and each side surface of the upper electrode 33, the capacitor insulating film 32, and the buried insulating film 16 are made of aluminum oxide having a thickness of about 5 nm to 100 nm, and have a second insulating property for preventing hydrogen diffusion. It is covered by the barrier layer 17. The second insulating barrier layer 17 is in contact with the first insulating barrier layer 15 in a region beside the lower electrode 31.
[Selection diagram] Fig. 1

Description

  The present invention relates to a capacitor having a metal oxide in a capacitor insulating film, a semiconductor memory device having the capacitor, and a method for manufacturing the same.

  In recent years, with the progress of digital technology in electronic devices, the tendency to process and store large amounts of data has been promoted, and the functions required for electronic devices have become more sophisticated, and semiconductors used in electronic devices have been increasingly used. 2. Description of the Related Art The miniaturization of the dimensions of a device and a semiconductor element constituting the semiconductor device is rapidly progressing.

  In connection with this, for example, in order to realize high integration of a dynamic RAM device, a technique of using a high dielectric as a capacitor insulating film instead of the conventional silicon oxide or silicon nitride has been widely studied and developed. .

  Furthermore, research and development on ferroelectric films having spontaneous polarization characteristics have been actively conducted with the aim of putting a non-volatile RAM device capable of performing high-speed write and read operations at an unprecedented low operating voltage to practical use. I have. In a semiconductor memory device using a high-dielectric or ferroelectric for a capacitor insulating film, a stack-type memory cell is used instead of a conventional planar-type memory cell for a highly integrated memory element having a storage capacity of a megabit class. It is becoming.

  Hereinafter, a conventional semiconductor memory device will be described with reference to the drawings.

  FIG. 15 shows a cross-sectional configuration of a main part of a conventional semiconductor memory device disclosed in Japanese Patent Application Laid-Open No. 11-8355.

  As shown in FIG. 15, a conventional semiconductor memory device includes a source / drain region 102 formed on a semiconductor substrate 101 and a gate electrode 104 formed on a channel region of the semiconductor substrate 101 via a gate insulating film 103. Transistors 105. An interlayer insulating film 106 covering the entire surface including the transistor 105 is formed over the semiconductor substrate 101, and a contact plug 107 electrically connected to one of the source / drain regions 102 is formed on the interlayer insulating film 106. Is formed.

An insulating hydrogen barrier layer 108 made of silicon nitride (Si ₃ N ₄ ) is formed on the interlayer insulating film 106, and a conductive hydrogen barrier layer made of titanium nitride (TiN) is formed on the upper end of the contact plug 107. 109 are formed.

A lower electrode 110 containing iridium dioxide (IrO ₂ ) or ruthenium dioxide (RuO ₂ ) is formed on the insulating hydrogen barrier layer 108 so as to be connected to the conductive hydrogen barrier layer 109.

A buried insulating film 111 made of silicon oxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ), silicon oxynitride (SiON), or the like is formed between the lower electrodes 110 on the insulating hydrogen barrier layer 108. I have.

On the buried insulating film 111 including the lower electrode 110, a capacitive insulating material made of a ferroelectric substance such as lead zircon titanate (Pb (Zr, Ti) O ₃ ) or strontium bismuth tantalate (SrBi ₂ Ta ₂ O ₉ ) is used. A film 112 is formed, and an upper electrode 113 containing iridium dioxide or ruthenium dioxide is formed on the capacitor insulating film 112. On the upper electrode 113, an insulating hydrogen barrier layer 114 made of silicon nitride or the like is formed.

  However, the conventional semiconductor memory device has two problems as described below.

  First, there is a problem that a conductive oxide film made of iridium dioxide or ruthenium dioxide which constitutes the lower electrode 110 and serves as a barrier against oxygen is reduced by hydrogen generated at the time of manufacturing, thereby deteriorating the barrier property against oxygen. are doing.

  Second, there is a problem in that the high dielectric substance or the ferroelectric substance constituting the capacitive insulating film 112 is reduced by hydrogen generated at the time of manufacturing, and the electrical characteristics of the capacitive element deteriorate.

  First, a first problem in which the lower electrode having an oxygen barrier property is reduced during manufacturing will be described with reference to FIGS. 16 (a) and 16 (b).

As shown in FIG. 16A, when the buried insulating film 111A is formed after patterning the lower electrode 110 containing iridium dioxide or ruthenium dioxide, monosilane (SiH ₄ ) or ammonia (NH ₃ ) as a source gas is used. ), Iridium dioxide or ruthenium dioxide is easily reduced. This reduction reaction becomes particularly apparent when a plasma CVD method is used for forming the buried insulating film 111A.

  As a result, the diffusion barrier property against oxygen atoms in the lower electrode 111 is degraded, and as shown in FIG. 16B, the capacitance insulating film 112 made of a high dielectric or ferroelectric formed on the lower electrode 110 is reduced. At the time of oxygen annealing at about 650 ° C. to 800 ° C., which is essential for crystallization, oxygen ions diffused from the capacitor insulating film 112 diffuse inside the lower electrode 110 to the interface with the contact plug 107, thereby reducing contact resistance. Poor contact such as increase occurs.

  Next, a second problem that the capacitive insulating film made of a high dielectric substance or a ferroelectric substance is reduced during manufacturing will be described with reference to FIG.

  In an actual semiconductor memory device, as shown in FIG. 15 or FIG. 17, a plurality of capacitors and transistors are both two-dimensionally arranged in an array. As described above, a metal oxide is often used when the capacitor insulating film 112 of the capacitor elements arranged in an array is made of a high dielectric or a ferroelectric. Therefore, of the capacitance elements arranged in an array, the reduction of the capacitance elements located at the peripheral portion 100 by hydrogen ions can be prevented by providing the insulating hydrogen barrier layer 108 provided below the capacitance element and the insulating hydrogen barrier layer 108 provided above the capacitance element. It is impossible only with the insulating hydrogen barrier layer 114. This is because, as shown in FIG. 17, although diffusion of hydrogen ions from above and below the semiconductor substrate 101 can be prevented, of the plurality of capacitors arranged in an array, This is because diffusion of hydrogen ions from a direction parallel to the substrate surface (lateral direction) cannot be prevented.

  Japanese Patent Application Laid-Open No. 2001-237393 discloses a configuration in which one capacitance element in a semiconductor memory device is completely covered with a hydrogen barrier layer. However, a plurality of capacitance quanta are arranged on a two-dimensional array. In the semiconductor memory device, if all of the plurality of capacitors cannot be completely covered with the hydrogen barrier layer, deterioration of the characteristics of the capacitors cannot be prevented.

  Japanese Patent Application Laid-Open No. H11-126881 discloses a semiconductor memory device in which a plurality of capacitive elements are completely covered by a hydrogen barrier layer. However, the publication does not show means for applying a voltage to the upper electrode 110 shown in FIG. Here, if a contact hole for applying a voltage to the upper electrode 110 is provided, the hydrogen barrier layer 111 covering the upper electrode 110 must be etched. At this time, if etching is performed to open the hydrogen barrier layer 111, Japanese Patent Application Laid-Open No. 2001-44376 discloses that the hydrogen generated during the ashing process of the resist after the opening and the subsequent wiring process, that is, the filling of the contact hole with the plug. It is described that the capacitance element is degraded by hydrogen generated by a series of processes such as film formation and patterning of wiring, sintering of wiring with hydrogen gas, and formation of an insulating film between wirings.

  As described above, in the conventional semiconductor memory device, it is difficult to completely cover the memory cell array including the plurality of capacitance elements arranged in an array with the hydrogen barrier layer.

  SUMMARY OF THE INVENTION It is a first object of the present invention to solve the above-mentioned conventional problem and to maintain the oxygen barrier property of a lower electrode in a capacitor, and to reduce a capacitor insulating film made of a metal oxide of the capacitor. It is a second object of the present invention to prevent the deterioration of the characteristics of the capacitor even when the memory cell array is covered by one or more blocks. This is the purpose of 3.

  In order to achieve the first object, the present invention provides a structure in which a side surface of a lower electrode in a capacitor is covered with a first insulating barrier layer for preventing diffusion of oxygen and hydrogen, and the second object is achieved. In order to achieve the third object, the side surface of the capacitive insulating film in the capacitive element is covered with a second insulating barrier layer for preventing diffusion of hydrogen. In order to achieve the third object, an insulating barrier layer for preventing diffusion of hydrogen is provided. , The capacitor is covered in units of one or more blocks included in the memory cell array.

  Specifically, the first capacitor element according to the present invention achieves the first object, and has a lower electrode, a capacitor insulating film made of a metal oxide formed on the lower electrode, and a capacitor on the capacitor insulating film. The formed upper electrode, comprising a buried insulating film filling the periphery of the lower electrode, the lower electrode includes a conductive barrier layer for preventing diffusion of oxygen, and at least the side surface of the conductive barrier layer among the side surfaces of the lower electrode. An insulating barrier layer for preventing diffusion of hydrogen is formed so as to be in contact with the insulating barrier layer.

  According to the first capacitive element, the insulating barrier layer for preventing diffusion of hydrogen is formed so as to contact at least the side surface of the conductive barrier layer among the side surfaces of the lower electrode. Diffusion of hydrogen generated during film formation to the lower electrode is suppressed by the insulating barrier layer formed on the side surface of the lower electrode. As a result, when the conductive barrier layer for preventing diffusion of oxygen constituting the lower electrode is made of, for example, a metal oxide, reduction of the conductive barrier layer by hydrogen can be prevented. Sex can be maintained.

  In the first capacitor, the buried insulating film is preferably formed in an atmosphere containing hydrogen.

In the first capacitor, the buried insulating film is preferably made of silicon oxide (SiO ₂ ) or silicon nitride (Si ₃ N ₄ ).

  In the first capacitor, it is preferable that the insulating barrier layer also prevent diffusion of oxygen.

  In the first capacitor, the conductive barrier layer preferably includes a stacked film including a first conductive barrier layer for preventing diffusion of oxygen and hydrogen and a second conductive barrier layer for preventing diffusion of oxygen. .

  In this case, the first conductive barrier layer is made of titanium aluminum nitride (TiAlN), titanium aluminum (TiAl), titanium nitride silicide (TiSiN), tantalum nitride (TaN), tantalum nitride silicide (TaSiN), and tantalum aluminum nitride (TaSiN). TaAlN) and tantalum aluminum (TaAl), or a laminated film including at least two of them.

In this case, the second conductive barrier layer, the iridium (IrO ₂₎ dioxide, iridium, which are sequentially formed from the lower layer (Ir) and iridium dioxide (IrO ₂₎ consisting of a multilayer film, ruthenium dioxide (RuO ₂ ) And a laminated film composed of ruthenium (Ru) and ruthenium dioxide (RuO ₂ ) sequentially formed from the lower layer, or a laminated film including at least two of them. Is preferred.

In the first capacitor, the insulating barrier layer preferably includes one of aluminum oxide (Al ₂ O ₃ ), titanium aluminum oxide (TiAlO), and tantalum aluminum oxide (TaAlO).

A second capacitive element according to the present invention achieves the first object, and includes a lower electrode, a capacitive insulating film made of a metal oxide formed on the lower electrode, and an upper portion formed on the capacitive insulating film. comprising an electrode and an insulator film to fill the periphery of the lower electrode, the lower electrode is iridium dioxide (IrO2), consisting of a sequentially formed iridium from the lower layer (Ir) and iridium dioxide (IrO ₂₎ film stack, dioxide Ruthenium (RuO ₂ ), and / or a laminated film including ruthenium (Ru) and ruthenium dioxide (RuO ₂ ) sequentially formed from a lower layer, or a laminated film including at least two of them. Aluminum oxide (Al ₂ O ₃ ) and titanium oxide so as to be in contact with at least the side surfaces of the conductive barrier layer among the side surfaces of the lower electrode. An insulating barrier layer including at least one of aluminum (TiAlO) and tantalum aluminum oxide (TaAlO) is formed.

  According to the second capacitor, the lower electrode having the conductive barrier layer containing a metal oxide made of iridium dioxide or ruthenium dioxide has aluminum oxide, oxide, or the like so as to be in contact with at least the side surface of the conductive barrier layer. Since the insulating barrier layer containing at least one of titanium aluminum and tantalum aluminum oxide is formed, diffusion of hydrogen generated during the formation of the buried insulating film into the lower electrode was formed on the side surface of the lower electrode. Suppressed by the insulating barrier layer. As a result, reduction of the conductive barrier layer by hydrogen can be prevented, so that the conductive barrier layer can maintain a barrier property against oxygen.

  A first method of manufacturing a semiconductor memory device according to the present invention achieves the first object, and includes a transistor formed on a semiconductor substrate and having a source region and a drain region, and covering the transistor on the semiconductor substrate. And a contact plug formed so as to be electrically connected to the source region or the drain region of the transistor in the interlayer insulating film, and the present invention in which the lower electrode is formed on the contact plug. And the first or second capacitance element.

  According to the first semiconductor memory device, since the first or second capacitance element according to the present invention is provided, diffusion of hydrogen generated during the formation of the buried insulating film into the lower electrode is formed on the side surface of the lower electrode. Is suppressed by the insulating barrier layer. As a result, when the conductive barrier layer for preventing diffusion of oxygen constituting the lower electrode is made of, for example, a metal oxide, reduction of the conductive barrier layer by hydrogen can be prevented, so that deterioration of characteristics of the capacitor is prevented. be able to.

  A first method for manufacturing a semiconductor memory device according to the present invention achieves the first object, forms a gate electrode on a semiconductor substrate, and then forms a source region and a drain region on the side of the gate electrode in the semiconductor substrate. Forming a transistor by forming a transistor, a second step of forming an interlayer insulating film on a semiconductor substrate including the transistor, and electrically connecting a source region or a drain region to the interlayer insulating film. A third step of forming a contact plug to be formed, a fourth step of forming a first conductive film including a conductive barrier layer for preventing diffusion of oxygen on the interlayer insulating film, and a first conductive film A fifth step of forming a lower electrode from the first conductive film on the interlayer insulating film by patterning so that the lower electrode is electrically connected to the contact plug; A sixth step of forming an insulating barrier layer for preventing diffusion of hydrogen so as to cover the surface and the side surface, and forming a first insulating film on the insulating barrier layer, and then forming the first insulating film and the insulating film. A flattening step for exposing the lower electrode to the conductive barrier layer, and forming a metal oxide on the flattened first insulating film and the insulating barrier layer including on the exposed lower electrode. An eighth step of forming a second conductive film on the second insulating film, a second conductive film on the second insulating film, and a second conductive film and a second insulating film so as to include a lower electrode. By patterning the film and the first insulating film, an upper electrode is formed from the second conductive film on the lower electrode, a capacitor insulating film is formed from the second insulating film, and the lower electrode is formed from the first insulating film. A ninth step of forming a buried insulating film filling the periphery of the electrode.

  According to the first method for manufacturing a semiconductor memory device, the first conductive film is patterned so as to be electrically connected to the contact plug, and the lower electrode is formed from the first conductive film on the interlayer insulating film. Thereafter, an insulating barrier layer for preventing diffusion of hydrogen is formed on the interlayer insulating film so as to cover the side surface of the lower electrode. Therefore, before forming the buried insulating film filling the lower electrode, an insulating barrier layer is formed on the upper surface and side surfaces of the lower electrode, so that the conductive barrier layer for preventing diffusion of oxygen constituting the lower electrode is made of metal. When the conductive barrier layer is made of an oxide, reduction of the conductive barrier layer by hydrogen can be prevented, so that the conductive barrier layer can maintain a barrier property against oxygen.

  In the first method for manufacturing a semiconductor memory device, the buried insulating film is preferably formed in an atmosphere containing hydrogen.

  In the first method for manufacturing a semiconductor memory device, the fourth step includes a step of forming a first conductive barrier layer for preventing diffusion of oxygen and hydrogen and a step of forming a second conductive barrier layer for preventing diffusion of oxygen. And a step of forming.

  A third capacitive element according to the present invention achieves the second object, and includes a lower electrode, a capacitive insulating film made of a metal oxide formed on the lower electrode, and an upper portion formed on the capacitive insulating film. An electrode, and a buried insulating film filling the periphery of the lower electrode, wherein the lower electrode includes a conductive barrier layer for preventing diffusion of oxygen and hydrogen, and is in contact with at least a side surface of the conductive barrier layer among the side surfaces of the lower electrode. A first insulating barrier layer for preventing diffusion of hydrogen is formed, and a second insulating barrier layer for preventing diffusion of hydrogen is formed so as to cover the upper surface and side surfaces of the upper electrode and the side surfaces of the capacitive insulating film. The second insulating barrier layer covers the lower electrode and is in contact with the first insulating barrier layer.

  According to the third capacitive element, since the side surface of the capacitive insulating film made of a metal oxide is covered with the second insulating barrier layer for preventing diffusion of hydrogen, hydrogen generated at the time of manufacturing can be removed from the side surface of the capacitive insulating film. The metal oxide is not reduced by diffusion. In addition, since the second insulating barrier layer for preventing diffusion of hydrogen covers the lower electrode and is in contact with the first insulating barrier layer, the capacitor element is covered by the second insulating barrier layer without gaps. Therefore, reduction of the capacitor by hydrogen can be prevented. As a result, a capacitor having predetermined electric characteristics can be obtained.

  In the third capacitor, the buried insulating film is preferably formed in an atmosphere containing hydrogen.

In the third capacitor, the buried insulating film is preferably made of silicon oxide (SiO ₂ ) or silicon nitride (Si ₃ N ₄ ).

  In the third capacitor, the first insulating barrier layer preferably prevents diffusion of oxygen.

  In the third capacitor, the conductive barrier layer preferably includes a stacked film including a first conductive barrier layer for preventing diffusion of oxygen and hydrogen and a second conductive barrier layer for preventing diffusion of oxygen. .

  In this case, the first conductive barrier layer is made of titanium aluminum nitride (TiAlN), titanium aluminum (TiAl), titanium nitride silicide (TiSiN), tantalum nitride (TaN), tantalum nitride silicide (TaSiN), and tantalum aluminum nitride (TaSiN). TaAlN) and tantalum aluminum (TaAl), or a laminated film including at least two of them.

In this case, the second conductive barrier layer, the iridium (IrO ₂₎ dioxide, iridium, which are sequentially formed from the lower layer (Ir) and iridium dioxide (IrO ₂₎ consisting of a multilayer film, ruthenium dioxide (RuO ₂ ) And a laminated film composed of ruthenium (Ru) and ruthenium dioxide (RuO ₂ ) sequentially formed from the lower layer, or a laminated film including at least two of them. Is preferred.

In the third capacitor, the first insulating barrier layer and the second insulating barrier layer may be made of aluminum oxide (Al ₂ O ₃ ), titanium aluminum oxide (TiAlO), or tantalum aluminum oxide (TaAlO). preferable.

A fourth capacitive element according to the present invention achieves the second object, and includes a lower electrode, a capacitive insulating film formed of a metal oxide formed on the lower electrode, and an upper portion formed on the capacitive insulating film. An electrode, and a buried insulating film filling the periphery of the lower electrode. The lower electrode is made of titanium aluminum nitride (TiAlN), titanium aluminum (TiAl), titanium nitride silicide (TiSiN), tantalum nitride (TaN), tantalum nitride silicide ( A lower electrode including a conductive barrier layer formed of any one of TaSiN), tantalum aluminum nitride (TaAlN), and tantalum aluminum (TaAl), or a stacked film including at least two of them; the to be in contact with a side surface of at least the conductive barrier layer of the side surfaces, aluminum oxide (Al ₂ O _3), oxide Chitan'aru A first insulating barrier layer including at least one of titanium (TiAlO) and tantalum aluminum oxide (TaAlO) is formed, and is oxidized so as to cover the upper surface and side surfaces of the upper electrode and the side surfaces of the capacitive insulating film. A second insulating barrier layer containing at least one of aluminum (Al ₂ O ₃ ), titanium aluminum oxide (TiAlO) and tantalum aluminum oxide (TaAlO) is formed, and the second insulating barrier layer is , And covers the lower electrode and is in contact with the first insulating barrier layer.

  According to the fourth capacitive element, the lower electrode includes a conductive layer barrier layer made of titanium, aluminum, silicon, or tantalum or a nitride thereof, and the side surface of the conductive barrier layer has an oxide of aluminum, titanium and aluminum. And a first insulating barrier layer made of an oxide of tantalum and an oxide of aluminum. Further, a second insulating barrier layer made of one of the same material group as the first insulating barrier layer covers the upper surface and the side surface of the upper electrode, the side surface of the capacitive insulating film, and the lower electrode. Since the capacitor element is formed so as to be in contact with the first insulating barrier layer, the capacitor element is covered with no gap by the second insulating barrier layer, so that reduction of the capacitor element by hydrogen can be prevented. As a result, a capacitor having predetermined electric characteristics can be obtained.

  A second semiconductor memory device according to the present invention includes a transistor formed on a semiconductor substrate and having a source region and a drain region; an interlayer insulating film formed on the semiconductor substrate so as to cover the transistor; A contact plug formed in the film so as to be electrically connected to a source region or a drain region of the transistor; and a third or fourth capacitor according to the present invention in which a lower electrode is formed on the contact plug. ing.

  According to the second semiconductor memory device, since the third or fourth capacitance element according to the present invention is provided, diffusion of hydrogen generated during the formation of the buried insulating film into the lower electrode is formed on the side surface of the lower electrode. Is suppressed by the insulating barrier layer. Further, since the side surface of the capacitor insulating film made of metal oxide is covered with the second insulating barrier layer for preventing diffusion of hydrogen, hydrogen generated during manufacturing diffuses from the side surface of the capacitor insulating film and Is not reduced. In addition, since the second insulating barrier layer for preventing diffusion of hydrogen covers the lower electrode and is in contact with the first insulating barrier layer, the capacitor element is covered by the second insulating barrier layer without gaps. Therefore, reduction of the capacitor by hydrogen can be prevented. As a result, a capacitor having desired electric characteristics can be obtained.

  In a second method for manufacturing a semiconductor memory device according to the present invention, after forming a gate electrode on a semiconductor substrate, a transistor is formed by forming a source region and a drain region on the side of the gate electrode on the semiconductor substrate, respectively. A first step, a second step of forming an interlayer insulating film on a semiconductor substrate including a transistor, and a third step of forming a contact plug in the interlayer insulating film to be electrically connected to a source region or a drain region. A step of forming a first conductive film including a conductive barrier layer for preventing diffusion of oxygen and hydrogen on the interlayer insulating film; and electrically connecting the first conductive film to a contact plug. A fifth step of forming a lower electrode from the first conductive film on the interlayer insulating film by patterning so as to be connected; and covering the upper surface and side surfaces of the lower electrode on the interlayer insulating film. Forming the insulating barrier layer for preventing diffusion of hydrogen as described above, and forming the first insulating film on the insulating barrier layer, and then forming the first insulating film and the insulating barrier layer. A seventh step of flattening the lower electrode by exposing the lower electrode, and a second step of metal oxide on the flattened first insulating film and the insulating barrier layer including on the exposed lower electrode. An eighth step of forming an insulating film, a second conductive film over the second insulating film, and a second conductive film, a second insulating film, and a first conductive film so as to include a lower electrode. By patterning the insulating film, an upper electrode is formed from the second conductive film on the lower electrode, a capacitive insulating film is formed from the second insulating film, and the periphery of the lower electrode is filled from the first insulating film. A ninth step of forming a buried insulating film, a step of covering the upper electrode, the capacitor insulating film and the buried insulating film, and In contact with the side of the insulating barrier layer and the lower electrode, and a tenth step of forming a second insulating barrier layer to prevent diffusion of hydrogen.

  According to the second method for manufacturing a semiconductor memory device, the effect of the first method for manufacturing a semiconductor memory device can be obtained, and the upper electrode, the capacitor insulating film, and the buried insulating film filling the periphery of the lower electrode are patterned. Thereafter, a second insulating barrier layer for preventing diffusion of hydrogen is formed so as to cover the upper electrode, the capacitor insulating film and the buried insulating film, and to be in contact with the first insulating barrier layer on the side of the lower electrode. It is possible to prevent the capacitor insulating film made of the metal oxide of the capacitor from being reduced during the manufacturing.

  In the second method for manufacturing a semiconductor memory device, the first insulating film is preferably formed in an atmosphere containing hydrogen.

  In the second method for manufacturing a semiconductor memory device, the ninth step is a step of patterning the first insulating barrier layer with the same shape as that of the first insulating film after patterning the first insulating film. It is preferable to include

  In this case, the portion of the first insulating barrier layer other than the portion covering the lower electrode and the portion covered by the buried insulating film is removed by etching, so that the insulating barrier layer is removed after the tenth step. When patterning, only the second insulating barrier layer may be etched. As a result, the etching time can be reduced as compared with the case where the two layers of the first insulating barrier layer and the second insulating barrier layer are etched. Therefore, the process margin for the problem that the resist disappears during the etching can be increased even in a portion where the thickness of the resist film is small above the capacitive element portion having a large absolute step.

  In the method for manufacturing a second semiconductor memory device, the fourth step includes forming a first conductive barrier layer for preventing diffusion of oxygen and hydrogen, and forming a second conductive barrier layer for preventing diffusion of oxygen. And a step of forming.

  A third semiconductor memory device according to the present invention achieves the third object, and includes a first transistor formed on a semiconductor substrate and having a source region and a drain region, and a first transistor formed on the semiconductor substrate. An interlayer insulating film formed so as to cover the transistor; a first contact plug formed in the interlayer insulating film so as to be electrically connected to a source region or a drain region of the first transistor; A lower electrode including a conductive barrier layer formed to be electrically connected to the first contact plug and preventing diffusion of hydrogen, and a capacitor insulation formed of a metal oxide formed on the lower electrode A memory cell array comprising a film and an upper electrode formed on the capacitive insulating film and provided for each of one or more blocks composed of a plurality of lower electrodes. So as to cover the periphery of the number of blocks, the insulating barrier layer to prevent diffusion of hydrogen are formed.

  According to the third semiconductor memory device, a lower electrode including a conductive barrier layer for preventing diffusion of hydrogen, a capacitor insulating film, and one or more blocks formed on the lower electrode and including a plurality of lower electrodes And an upper electrode provided in the memory cell array, and an insulating barrier layer for preventing diffusion of hydrogen is formed so as to cover the periphery of one block or a plurality of blocks constituting the memory cell array. Therefore, deterioration of the characteristics of the capacitor can be reliably prevented.

  In the block of the third semiconductor memory device, the upper electrode is electrically connected to a second contact plug connected to a source region or a drain region of the second transistor through a conductive barrier film for preventing diffusion of hydrogen. Is preferably connected.

  With this configuration, even when the capacitance element is covered by the insulating barrier layer for each block, it is possible to apply a voltage to the upper electrode through the second contact plug without opening the insulating barrier layer. Since the capacitor can be prevented from being exposed to hydrogen due to an opening in the insulating barrier layer and a wiring process, deterioration of characteristics of the capacitor can be prevented.

  In the block of the third semiconductor memory device, the upper electrode is preferably electrically connected to the second contact plug connected to the source region or the drain region of the second transistor with the lower electrode interposed. .

  With this configuration, the second transistor and the upper electrode are electrically connected only by forming an opening exposing the lower electrode in the capacitive insulating film of one of the capacitive elements in the block.

  A fourth semiconductor memory device according to the present invention achieves the third object, and includes a first transistor formed on a semiconductor substrate and having a source region and a drain region, and a first transistor formed on the semiconductor substrate. An interlayer insulating film formed so as to cover the transistor; a first contact plug formed in the interlayer insulating film so as to be electrically connected to a source region or a drain region of the first transistor; A lower electrode including a conductive barrier layer formed to be electrically connected to the first contact plug and preventing diffusion of hydrogen, and a capacitor insulation formed of a metal oxide formed on the lower electrode And a memory cell array formed on the capacitive insulating film and comprising an upper electrode provided for each of one or more blocks composed of a plurality of lower electrodes. In addition, a first insulating barrier layer for preventing diffusion of hydrogen is formed so as to cover the bottom surface of the block. The first insulating barrier layer covers the upper surface and the side surface of the upper electrode and the side surface of the capacitive insulating film, and covers the upper surface and the side surface of the block. A second insulating barrier layer for preventing diffusion of hydrogen is formed, and the second insulating barrier layer is in contact with the first insulating barrier layer around one block or a plurality of blocks.

  According to the fourth semiconductor memory device, in addition to the effect of the third semiconductor memory device, the first insulating barrier layer for preventing diffusion of hydrogen so as to be in contact with the plurality of lower electrodes and to cover the bottom surface of the block is provided. Is formed, deterioration of the characteristics of the capacitor can be prevented more reliably.

  In the fourth semiconductor memory device, the conductive barrier layer is made of titanium aluminum nitride (TiAlN), titanium aluminum (TiAl), titanium nitride silicide (TiSiN), tantalum nitride (TaN), tantalum silicide nitride (TaSiN), or tantalum aluminum nitride. (TaAlN) and tantalum aluminum (TaAl), or a laminated film including at least two of them.

In the fourth semiconductor memory device, the first insulating barrier layer or the second insulating barrier layer is formed of one of aluminum oxide (Al ₂ O ₃ ), titanium aluminum oxide (TiAlO), and tantalum aluminum oxide (TaAlO). It is preferable to include at least one.

In the fourth semiconductor memory device, it is preferable that the first insulating barrier layer is made of silicon nitride (Si ₃ N ₄ ).

  In a third method for manufacturing a semiconductor memory device according to the present invention, a transistor is formed by forming a gate electrode on a semiconductor substrate and then forming a source region and a drain region on the side of the gate electrode on the semiconductor substrate, respectively. A first step, a second step of forming an interlayer insulating film on a semiconductor substrate including a transistor, and a third step of forming a contact plug in the interlayer insulating film to be electrically connected to a source region or a drain region. A step of forming a first conductive film including a conductive barrier for preventing diffusion of oxygen and hydrogen on the interlayer insulating film; and electrically connecting the first conductive film to a contact plug. A fifth step of forming a plurality of lower electrodes from the first conductive film on the interlayer insulating film by patterning such that the upper surface of the plurality of lower electrodes is formed on the interlayer insulating film. A sixth step of forming a first insulating barrier layer for preventing diffusion of hydrogen so as to cover the side surface, and forming a first insulating film on the first insulating barrier layer; A seventh step of flattening the insulating film and the first insulating barrier layer so as to expose the plurality of lower electrodes, and a step of flattening the first insulating film and the first layer including the plurality of exposed lower electrodes. An eighth step of forming a second insulating film made of a metal oxide on the entire surface above the insulating barrier layer, and a ninth step of forming a second conductive film on the second insulating film And patterning the second conductive film, the second insulating film, and the first insulating film so as to include the block constituted by the plurality of lower electrodes, so that the second conductive film covers the block. An upper electrode is formed, a capacitor insulating film is formed from the second insulating film, and a plurality of lower electrodes are formed from the first insulating film. A tenth step of forming a buried insulating film that fills side portions of the poles; and, in the block, covering the upper electrode, the capacitor insulating film and the buried insulating film, and An eleventh step of forming a second insulating barrier layer for preventing diffusion of hydrogen so as to be in contact therewith.

  According to the third method for manufacturing a semiconductor memory device, the first insulating barrier layer for preventing diffusion of hydrogen is formed so as to cover the side surfaces of the plurality of lower electrodes formed on the interlayer insulating film. Subsequently, after forming a first insulating film on the first insulating barrier layer, an upper electrode, a capacitor insulating film, and a buried insulating film are formed so as to cover the block. Further, the second insulating barrier layer is formed in the block so as to cover the upper electrode, the capacitor insulating film and the buried insulating film, and to be in contact with the first insulating barrier layer on the side of the block. This can prevent the deterioration of the characteristics of the capacitive element.

  According to a fourth method of manufacturing a semiconductor memory device of the present invention, a first transistor is formed by forming a gate electrode on a semiconductor substrate and then forming a source region and a drain region on each side of the semiconductor substrate on the side of the gate electrode. A first step of forming a second transistor and a second transistor; a second step of forming an interlayer insulating film on a semiconductor substrate including the first transistor and the second transistor; A third step of forming a first contact plug and a second contact plug electrically connected to the source region or the drain region of the transistor and the second transistor, respectively; A fourth step of forming a first conductive film including a conductive barrier layer for preventing diffusion of hydrogen, and forming the first conductive film with a first contact plug and a second capacitor. A fifth step of forming a plurality of lower electrodes from the first conductive film on the interlayer insulating film by patterning so as to be electrically connected to the respective plugs, and a plurality of lower electrodes on the interlayer insulating film. A sixth step of forming a first insulating barrier layer for preventing diffusion of hydrogen so as to cover the upper and side surfaces of the electrode, and after forming a first insulating film on the first insulating barrier layer, A seventh step of flattening the first insulating film and the first insulating barrier layer so as to expose a plurality of lower electrodes, and a step of flattening the first insulating film including the plurality of exposed lower electrodes. An eighth step of forming a second insulating film made of a metal oxide on the entire surface of the film and the first insulating barrier layer, and a second insulating film in a block constituted by a plurality of lower electrodes. Lower electrode connected to second contact plug in film A ninth step of removing the upper part, a tenth step of forming a second conductive film on the second insulating film and on a lower electrode connected to the second contact plug, and a block By patterning the second conductive film, the second insulating film, and the first insulating film as described above, an upper electrode is formed from the second conductive film so as to cover the block, and the capacitor insulating from the second insulating film. An eleventh step of forming a film and forming a buried insulating film filling the side portions of the plurality of lower electrodes from the first insulating film, and covering the upper electrode, the capacitor insulating film and the buried insulating film in the block, And a twelfth step of forming a second insulating barrier layer for preventing diffusion of hydrogen so as to be in contact with the first insulating barrier layer on the side of the block.

  According to the fourth method for manufacturing a semiconductor memory device, the effect of the third method for manufacturing a semiconductor memory device can be obtained, and in addition, the second insulating film serving as a capacitive insulating film can be formed in a block including a plurality of lower electrodes. In order to remove the upper part of the lower electrode connected to the second contact plug in the insulating film, the upper electrode is provided from the second transistor to the second contact plug without providing an opening in the second insulating barrier layer. Voltage can be applied through the As a result, an opening and a wiring process for the second insulating barrier layer covering the upper electrode are not required, and exposure to hydrogen is prevented, so that deterioration of characteristics of the capacitor can be prevented.

  In a fifth method of manufacturing a semiconductor memory device according to the present invention, a transistor is formed by forming a gate electrode on a semiconductor substrate and then forming a source region and a drain region on the side of the gate electrode on the semiconductor substrate. A first step, a second step of forming an interlayer insulating film on a semiconductor substrate including a transistor, and a third step of forming a first insulating barrier layer for preventing diffusion of hydrogen on the interlayer insulating film A step of forming a contact plug electrically connected to a source region or a drain region in the interlayer insulating film and the first insulating barrier layer; and a step of forming a contact plug on the first insulating barrier layer. A fifth step of forming a first conductive film including a conductive barrier layer that prevents diffusion of hydrogen, and patterning the first conductive film so that the first conductive film is electrically connected to a contact plug. A sixth step of forming a plurality of lower electrodes from the first conductive film on the insulating barrier layer, and forming a first insulating film on the first insulating barrier layer including on the plurality of lower electrodes. After the formation, a seventh step of flattening the first insulating film so as to expose the plurality of lower electrodes, and a step of forming a flattened first insulating film including the exposed plurality of lower electrodes. An eighth step of forming a second insulating film made of a metal oxide on the entire upper surface, a ninth step of forming a second conductive film on the second insulating film, and a plurality of lower electrodes Forming an upper electrode from the second conductive film so as to cover the block by patterning the second conductive film, the second insulating film, and the first insulating film so as to include the block constituted by A capacitor insulating film is formed from the second insulating film, and a side portion between the plurality of lower electrodes is buried from the first insulating film. A tenth step of forming a buried insulating film, and diffusion of hydrogen so as to cover the upper electrode, the capacitor insulating film and the buried insulating film in the block and to make contact with the first insulating barrier layer on the side of the block. An eleventh step of forming a second insulating barrier layer for preventing

  According to the fifth method of manufacturing a semiconductor memory device, an interlayer insulating film and a first insulating barrier layer for preventing diffusion of hydrogen are formed thereon, and thereafter, the interlayer insulating film and the first insulating barrier layer are contacted. Form a plug. Subsequently, after forming a plurality of lower electrodes, a first insulating film is formed on the first insulating barrier layer including the formed plurality of lower electrodes, and then the upper electrode and the capacitor are formed so as to cover the block. An insulating film and a buried insulating film are formed. Further, the second insulating barrier layer is formed in the block so as to cover the upper electrode, the capacitor insulating film and the buried insulating film, and to be in contact with the first insulating barrier layer on the side of the block. This can prevent the deterioration of the characteristics of the capacitive element.

  According to a sixth method of manufacturing a semiconductor memory device of the present invention, a first transistor is formed by forming a gate electrode on a semiconductor substrate, and then forming a source region and a drain region on the side of the gate electrode on the semiconductor substrate. A first step of forming a second transistor, a second step of forming an interlayer insulating film on a semiconductor substrate including the first transistor and the second transistor, and a step of forming hydrogen on the interlayer insulating film. A third step of forming a first insulating barrier layer for preventing diffusion, and a first contact plug electrically connected to a source region or a drain region, respectively, in the interlayer insulating film and the first insulating barrier layer And a fourth step of forming a second contact plug and a fifth step of forming a first conductive film including a conductive barrier layer for preventing diffusion of hydrogen on the first insulating barrier layer. The first conductive film is patterned on the first insulating barrier layer by patterning the first conductive film so as to be electrically connected to the first contact plug and the second contact plug, respectively. Forming a plurality of lower electrodes from the first step, and forming a first insulating film on the first insulating barrier layer including over the plurality of lower electrodes. A seventh step of flattening the plurality of lower electrodes so as to expose the plurality of lower electrodes, and a second step made of metal oxide on the entire surface of the flattened first insulating film including the exposed plurality of lower electrodes. An eighth step of forming an insulating film of the second type, and a ninth step of removing an upper part of the lower electrode connected to the second contact plug in the second insulating film in a block constituted by the plurality of lower electrodes. Process, and on the second insulating film and the second contact A tenth step of forming a second conductive film on the lower electrode connected to the plug, and patterning the second conductive film, the second insulating film, and the first insulating film so as to include a block Forming an upper electrode from the second conductive film so as to cover the block, forming a capacitive insulating film from the second insulating film, and burying the side portions of the plurality of lower electrodes from the first insulating film. An eleventh step of forming a film, and a step of preventing diffusion of hydrogen so as to cover the upper electrode, the capacitor insulating film and the buried insulating film in the block, and to contact the first insulating barrier layer on the side of the block. A twelfth step of forming the second insulating barrier layer.

  According to the sixth method for manufacturing a semiconductor memory device, the effect of the fifth method for manufacturing a semiconductor memory device can be obtained, and the second insulating film serving as a capacitive insulating film can be formed in a block including a plurality of lower electrodes. In order to remove the upper part of the lower electrode connected to the second contact plug in the insulating film, the upper electrode is provided from the second transistor to the second contact plug without providing an opening in the second insulating barrier layer. Voltage can be applied through the As a result, an opening and a wiring process for the second insulating barrier layer covering the upper electrode are not required, and exposure to hydrogen is prevented, so that deterioration of characteristics of the capacitor can be prevented.

  In the third or fifth method for manufacturing a semiconductor memory device, the tenth step may include, after patterning the first insulating film, patterning the first insulating barrier layer with the same shape as the first insulating film. Is preferably included.

  In the fourth or sixth method for manufacturing a semiconductor memory device, the eleventh step may include, after the patterning of the first insulating film, patterning of the same shape as the first insulating film with respect to the first insulating barrier layer. Is preferably included.

  According to the capacitor of the present invention, even when the conductive barrier layer for preventing diffusion of oxygen constituting the lower electrode is made of a metal oxide, reduction of the conductive barrier layer by hydrogen can be prevented. The barrier layer can maintain the barrier property against oxygen.

  According to the semiconductor storage device of the present invention, since the semiconductor device includes the capacitor of the present invention, deterioration of characteristics due to hydrogen during manufacturing of the capacitor can be prevented.

  According to the method for manufacturing a semiconductor memory device according to the present invention, since the capacitor according to the present invention is formed, deterioration of characteristics due to hydrogen during the manufacturing of the capacitor can be prevented.

(1st Embodiment)
A first embodiment of the present invention will be described with reference to the drawings.

  FIG. 1A shows a cross-sectional configuration of a main part of a semiconductor memory device including a capacitor according to a first embodiment of the present invention.

  As shown in FIG. 1A, the semiconductor memory device according to the first embodiment includes a plurality of cell transistors 20 including MOSFETs formed on a semiconductor substrate 11 made of, for example, silicon (Si), and each cell transistor 20. And a capacitor element 30 formed for each cell transistor 20 on the interlayer insulating film 13 covering the semiconductor device. Each cell transistor 20 is partitioned and insulated from each other by a shallow trench isolation (STI) 12 formed on a semiconductor substrate 11.

  Each cell transistor 20 includes a source / drain region 21 formed on the semiconductor substrate 11 and a gate electrode 23 formed on a channel region of the semiconductor substrate 11 with a gate insulating film 22 interposed therebetween.

  Each capacitive element 30 includes a lower electrode 31, a capacitive insulating film 32, and an upper electrode 33, which are sequentially stacked from the substrate side.

As shown in FIG. 1B, the lower electrode 31 is made of titanium aluminum nitride (TiAlN) having a thickness of about 40 nm to 100 nm, and has a first conductive barrier layer 31a for preventing diffusion of oxygen and hydrogen. A second conductive barrier layer 31b made of iridium (Ir) having a thickness of about 50 nm to 100 nm and preventing diffusion of oxygen, and a third conductive material made of iridium dioxide (IrO ₂ ) having a thickness of about 50 nm to 100 nm and preventing diffusion of oxygen. And a conductive layer 31d made of platinum (Pt) having a thickness of about 50 nm to 100 nm.

The capacitance insulating film 32 is made of strontium bismuth tantalum niobate (SrBi ₂ (Ta _1-x Nb _x ) ₂ O ₉ ) having a bismuth layered perovskite structure having a thickness of about 50 nm to 150 nm (where x is 0 ≦ x ≦ 1). ), And the upper electrode 33 is made of platinum having a thickness of about 50 to 100 nm.

As shown in FIG. 1A, an interlayer insulating film 13 made of, for example, silicon oxide (SiO ₂ ) is formed on the semiconductor substrate 11 so as to cover each cell transistor 20. And a plurality of contacts made of tungsten (W) or polysilicon whose lower end is electrically connected to one of the source / drain regions 21 and whose upper end is electrically connected to the lower electrode 31 of each capacitor 30. A plug 14 is formed.

The side surface of the lower electrode 31 and the region on the interlayer insulating film 13 on the side of the lower electrode 31 are made of, for example, aluminum oxide (Al ₂ O ₃ ) having a thickness of about 5 nm to 100 nm, and a first area for preventing diffusion of oxygen and hydrogen. Is covered with the insulating barrier layer 15.

  Here, the diameter of the lower electrode 31 in the substrate surface direction is smaller than the diameter of the capacitance insulating film 32 and the upper electrode 33 in the substrate surface direction. 31 overhangs from the periphery.

A region on the side of the lower electrode 31 and below the overhanging portion of the capacitive insulating film 32 is buried with a buried insulating film 16 made of silicon oxide (SiO ₂ ) or silicon nitride (Si ₃ N ₄ ).

  The buried insulating film 16 electrically insulates the lower electrodes 31 adjacent to each other, and the surface thereof is flattened so as to be almost the same height as the surface of the lower electrode 31.

  The capacitor insulating film 32, the upper electrode 33, and the buried insulating film 16 are formed by etching with the same mask, respectively, while the first insulating barrier layer 15 is formed by the upper electrode 33, the capacitor insulating film 32, and the like. Etching is performed using a different mask.

  The upper surface of the upper electrode 33 and each side surface of the upper electrode 33, the capacitor insulating film 32, and the buried insulating film 16 are made of, for example, aluminum oxide having a thickness of about 5 nm to 100 nm, and a second insulating barrier layer for preventing diffusion of hydrogen 17. At this time, the second insulating barrier layer 17 is in contact with the upper surface of the insulating barrier layer 15 in the region on the side of the lower electrode 31, that is, in the region on the lower side of the buried insulating film 16. As a result, the side surface of the lower electrode 31 is covered with the first insulating barrier layer 15 that prevents diffusion of oxygen and hydrogen. Further, the upper electrode 33, the capacitor insulating film 32, and the buried insulating film 16 are formed without gaps by the first insulating barrier layer 15 for preventing diffusion of oxygen and hydrogen and the second insulating barrier layer 17 for preventing diffusion of hydrogen. Covered.

  Here, the first insulating barrier layer 15 and the second insulating barrier layer 17 are not provided in a region other than the capacitor 30, for example, in a region where a contact hole to the source / drain region 21 is formed.

  Hereinafter, a method for manufacturing a semiconductor memory device including the capacitor configured as described above will be described.

  FIGS. 2A to 2C and FIGS. 3A and 3B show cross-sectional configurations in the order of steps of the method for manufacturing the semiconductor memory device according to the first embodiment of the present invention. .

  First, as shown in FIG. 2A, a gate insulating film 22 and a gate electrode 23 are formed on a semiconductor substrate 11 made of silicon, and a sidewall insulating film is formed on side surfaces of the gate insulating film 22 and the gate electrode 23. 24 are formed. Subsequently, impurities are implanted into the semiconductor substrate 11 using the gate electrode 23 and the sidewall insulating film 24 as a mask to form a source / drain region 21. Here, if impurity implantation is performed before the formation of the sidewall insulating film 24, the source / drain region 21 can be configured to have an LDD structure or an extension structure. Thereafter, an interlayer insulating film 13 made of silicon oxide is deposited over the entire surface including the plurality of cell transistors 20 on the semiconductor substrate 11 by the CVD method. Subsequently, the upper surface of the deposited interlayer insulating film 13 is flattened using a chemical mechanical polishing (CMP) method or the like. Subsequently, contact holes are respectively formed in one of the source / drain regions 21 of each cell transistor 20 in the interlayer insulating film 13 by a lithography method and a dry etching method, and a conductor film made of tungsten or polysilicon is formed by a CVD method. Deposit to fill the holes. Subsequently, a plurality of contact plugs 14 are formed by performing etch-back or chemical mechanical polishing on the deposited conductor film to remove the conductor film on the interlayer insulating film 13.

Next, a first conductive barrier layer made of titanium aluminum nitride for preventing diffusion of oxygen and hydrogen and an iridium for preventing diffusion of oxygen are formed on the interlayer insulating film 13 including the plurality of contact plugs 14 by, for example, a sputtering method. A second conductive barrier layer, a third conductive barrier layer made of iridium dioxide for preventing diffusion of oxygen, and a conductive layer made of platinum are sequentially deposited to form a lower electrode forming film. Subsequently, the lower electrode forming film is patterned by the lithography method and the dry etching method so as to include the contact plugs 14 to form a plurality of lower electrodes 31 made of the lower electrode forming film. Thereafter, a first insulating film made of aluminum oxide having a thickness of about 5 nm to 100 nm and preventing diffusion of oxygen and hydrogen is formed on the interlayer insulating film 13 by sputtering or CVD so as to cover the upper surface and side surfaces of the lower electrode 31. The conductive barrier layer 15 is formed. Here, it is preferable to perform heat treatment in an oxidizing atmosphere after the formation of the first insulating barrier layer 15 because aluminum oxide included in the first insulating barrier layer 15 is densified. Subsequently, a silicon oxide or silicon nitride film having a thickness of about 400 nm to 600 nm is formed by CVD using, for example, monosilane (SiH ₄ ) as a raw material in an atmosphere containing hydrogen so as to cover the first insulating barrier layer 15. A buried insulating film 16 is deposited.

  Next, as shown in FIG. 2B, each of the buried insulating films 16 and the first insulating barrier layer 15 is planarized by using a CMP method until the respective lower electrodes 31 are exposed. The periphery of the lower electrode 31 is buried with the buried insulating film 16. Therefore, the upper surface of the lower electrode 31 has substantially the same height as the exposed surfaces of the buried insulating film 16 and the first insulating barrier layer 15.

Next, as shown in FIG. 2C, the first insulating barrier layer 15 and the buried insulating film are formed by a metalorganic decomposition method (MOD method), a metalorganic chemical vapor deposition method (MOCVD method), or a sputtering method. A capacitor insulating film made of strontium bismuth tantalum niobate (SrBi ₂ (Ta _1-x Nb _x ) ₂ O ₉ ) having a bismuth layered perovskite structure with a thickness of about 50 nm to 150 nm over the entire surface of the lower electrode 16 and the lower electrode 31 The formation film 32A is formed. Subsequently, an upper electrode forming film 33A made of platinum having a thickness of about 50 nm to 100 nm is formed on the capacitive insulating film forming film 32A by a sputtering method. Thereafter, heat treatment is performed in an oxygen atmosphere at a temperature of about 650 ° C. to 800 ° C. to crystallize the metal oxide forming the capacitance insulating film forming film 32A.

  Next, as shown in FIG. 3A, a resist pattern (not shown) is formed on the upper electrode formation film 33A by a lithography method, and the formed upper electrode formation film 33A is formed by using the formed resist pattern as a mask. Dry etching is sequentially performed on the capacitor insulating film forming film 32A and the buried insulating film 16 to form the upper electrode 33 from the upper electrode forming film 33A, and form the capacitor insulating film 32 from the capacitor insulating film forming film 32A. Thus, the capacitive element 30 including the lower electrode 31, the capacitive insulating film 32, and the upper electrode 33 electrically connected to the contact plug 14 is formed.

  Here, the patterning of the first insulating barrier layer 15 is not performed, and the etching is terminated when the first insulating barrier layer 15 is exposed when the embedded insulating film 16 is etched.

  Next, as shown in FIG. 3B, the upper surface and side surfaces of the upper electrode 33, and the capacitive insulating film 32 and the buried insulating film 16 are formed on the first insulating barrier layer 15 by CVD or sputtering. A second insulating barrier layer 17 made of aluminum oxide having a thickness of about 5 nm to 100 nm and preventing diffusion of hydrogen is formed so as to cover the side surfaces of the second insulating barrier layer 17. As a result, the second insulating barrier layer 17 is in contact with the upper surface of the first insulating barrier layer 15 in the region on the side of the lower electrode 31, here on the lower side of the buried insulating film 16, without any gap. Become.

  Note that regions other than the capacitor 30 in the first insulating barrier layer 15 and the second insulating barrier layer 17, for example, a region where another contact hole is formed with the source / drain region 21 are removed by etching. .

  As described above, according to the first embodiment, since the first insulating barrier layer 15 for preventing diffusion of oxygen and hydrogen covers the side surface of the lower electrode 31 of the capacitor 30, the oxygen constituting the lower electrode 31 can be reduced. It is possible to prevent a conductive oxide such as iridium oxide serving as a barrier from being reduced by hydrogen and deteriorating its oxygen barrier property.

  Further, the second insulating barrier layer 17 for preventing diffusion of hydrogen covers the entire capacitive element 30 without contact by contact with the first insulating barrier layer 15 for preventing diffusion of oxygen and hydrogen. It is possible to prevent the electrical characteristics of the capacitor 30 from deteriorating due to reduction of the constituent metal oxides by hydrogen.

  Hereinafter, the electrical characteristics of the semiconductor memory device according to the first embodiment and the semiconductor memory device according to the related art will be compared.

  First, the evaluation results of the contact resistance between the contact plug 14 and the lower electrode 31 will be described.

  FIG. 4 shows the measurement results of the in-plane contact resistance of a silicon wafer having a diameter of about 20.3 cm (corresponding to 8 inches) between the first embodiment and the conventional example. As shown in FIG. 4, in the case of the semiconductor memory device according to the conventional example, the contact resistance varies widely from 45Ω to 7000Ω. This is because iridium dioxide, which is a conductive oxide serving as an oxygen barrier of the lower electrode 110 according to the conventional example, is reduced by hydrogen to deteriorate the oxygen barrier property, and is necessary for crystallization of a high dielectric or ferroelectric. This is because oxygen diffuses inside the lower electrode 110 and oxidizes the surface of the contact plug 107 during high-temperature oxygen annealing. On the other hand, in the case of the semiconductor memory device according to the first embodiment, the contact resistance is in the range of 25 Ω to 35 Ω in the wafer surface, the variation is extremely small, and the resistance value is 25 Ω to 40 Ω. You can see that it is done.

  Next, evaluation results of reduction resistance of the semiconductor memory device according to the first embodiment will be described.

  FIG. 5 is for evaluation, and shows respective remanent polarization (2Pr) values of the capacitive element 30 before and after performing a hydrogen annealing process at 400 ° C. on the capacitive element 30. As shown in FIG. 5, in the capacitance element 30 according to the first embodiment, even when the hydrogen annealing treatment is performed, the remanent polarization characteristics hardly change, and it can be seen that the reduction by hydrogen can be sufficiently prevented. Thus, the electrical characteristics of the capacitor and the semiconductor memory device according to the first embodiment are significantly improved.

(Modification of First Embodiment)
FIGS. 6A to 6C show first to third modifications of the semiconductor memory device according to the first embodiment of the present invention, in which a first insulating barrier covering a lower electrode and a side surface thereof is provided. The cross-sectional configuration with the vicinity of the layer is shown. Here, in FIGS. 6A to 6C, the same components as those shown in FIG. 1A are denoted by the same reference numerals, and description thereof will be omitted.

  First, as shown in a first modification of FIG. 6A, the upper end portion of the first insulating barrier layer 15 that covers the side surface of the lower electrode 31 does not necessarily cover the entire side surface of the lower electrode 31. What is necessary is just to form so as to cover at least the side surface of the third conductive barrier layer 31c made of iridium dioxide which is a conductive metal oxide.

  In this case, the height of the upper surface of the buried insulating film 16 may be the same as the upper end of the first insulating barrier layer 15 as shown in a first modification of FIG. As shown in a second modification of FIG. 6B, the upper surface of the conductive layer 31d of the lower electrode 31 may be the same as the first modification, and as shown in a third modification of FIG. It may be formed to be lower than the upper end of the layer 15.

(Second embodiment)
Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.

  FIG. 7 shows a cross-sectional configuration of a main part of a semiconductor memory device including a capacitor according to a second embodiment of the present invention. In FIG. 7, the same components as those shown in FIG.

  As shown in FIG. 7, in the second embodiment, the second insulating barrier layer 17 is formed directly on the interlayer insulating film 13, and the first insulating barrier layer 15A has a gate length. It is divided between the capacitive elements 30 adjacent in the direction.

  FIGS. 8A and 8B show main steps of a method for manufacturing a semiconductor memory device according to the second embodiment.

  Here, only differences from the first embodiment will be described.

  In the first embodiment, as shown in FIG. 3A, the same mask is used for patterning of the buried insulating film 16 burying the capacitive insulating film 32, the upper electrode 33, and the lower electrode 31 constituting the capacitive element 30. In this case, patterning of the first insulating barrier layer 15 is not performed.

  On the other hand, as shown in FIGS. 7 and 8A, in the semiconductor memory device according to the second embodiment, in the etching step of patterning the upper electrode 33, the capacitor insulating film 32, and the like, the same process as the upper electrode 33 is performed. After the buried insulating film 16 is etched using the mask, the first insulating barrier layer 15 is etched to form the first insulating barrier layer 15A. At this time, an etching gas containing fluorocarbon as a main component is used for etching the buried insulating film 16 made of silicon oxide or silicon nitride, and a chlorine gas is used for etching the first insulating barrier layer 15A made of aluminum oxide. An etching gas as a main component is used.

  Next, as shown in FIG. 8B, in the subsequent step of forming the second insulating barrier layer 17 for preventing diffusion of hydrogen, the second insulating barrier layer 17 And comes into contact with the end surface of the first insulating barrier layer 15 located below the buried insulating film 16.

  Also in the second embodiment, regions other than the capacitive element 30 in the first insulating barrier layer 15A and the second insulating barrier layer 17, for example, a region where another contact hole with the source / drain region 21 is formed. Are removed by etching.

  As described above, according to the second embodiment, similarly to the first embodiment, the first insulating barrier layer 15A for preventing diffusion of oxygen and hydrogen covers the side surface of the lower electrode 31 of the capacitor 30. Therefore, it is possible to prevent a conductive oxide such as iridium oxide which is an oxygen barrier constituting the lower electrode 31 from being reduced by hydrogen and deteriorating its oxygen barrier property.

  Further, since the second insulating barrier layer 17 for preventing the diffusion of hydrogen covers the entire capacitor element 30 without contact with the first insulating barrier layer 15A for preventing the diffusion of oxygen and hydrogen, the capacitor insulating film 32 is covered. It is possible to prevent the electrical characteristics of the capacitor 30 from deteriorating due to reduction of the constituent metal oxides by hydrogen. As a result, also in the second embodiment, it is possible to realize a semiconductor memory device including the capacitor element 30 having excellent electrical characteristics similar to the measurement results shown in FIGS.

  Further, the second embodiment has other effects as described below.

  That is, in the step of removing the insulating barrier layers 15 and 17 formed in the region other than the capacitive element 30 on the interlayer insulating film 13, in the first embodiment, the second insulating barrier layer 17 and the first insulating barrier layer 17 are removed. It is necessary to perform etching on two layers of the insulating barrier layer 15. On the other hand, in the second embodiment, since only the second insulating barrier layer 17 needs to be etched, the etching time can be greatly reduced. In addition, although a step is formed on the interlayer insulating film 13 between a portion where the capacitor 30 is provided and a portion where the capacitor 30 is not provided, the thickness of the resist pattern is reduced above the capacitor 30 by shortening the etching time. The resist hardly disappears during the etching even in the part, and the process margin can be expanded.

(Third embodiment)
Hereinafter, a third embodiment of the present invention will be described with reference to the drawings.

  FIGS. 9A to 9C show a semiconductor memory device according to a third embodiment of the present invention, and FIG. 9A shows a plan configuration of a cell block including a plurality of cells constituting a memory cell array. 9 (b) shows a cross-sectional configuration along line IXb-IXb in FIG. 9 (a), and FIG. 9 (c) shows a cross-sectional configuration along line IXc-IXc in FIG. 9 (a). In FIGS. 9A to 9C, the same components as those shown in FIG. 7 are denoted by the same reference numerals, and description thereof will be omitted.

As shown in FIG. 9A, for example, 2 ⁿ or (2 ⁿ +1) (where n is the number of) on the main surface of the semiconductor substrate 11 along the gate electrode (word line) 23 of the cell transistor 20. The cell block 50 includes the lower electrode 31 (which is an integer of 3 or more). The capacitance insulating film 32 and the upper electrode 33 of the capacitance element 30 are formed for each cell block 50 so as to cover the plurality of lower electrodes 31 included in the cell block 50.

  Further, as shown in FIGS. 9A and 9C, the second insulating barrier layer 17 covers two cell blocks 50 adjacent to each other and also has a side portion in a direction in which the gate electrode 23 extends. Are in contact with the interlayer insulating film 13. Further, as shown in FIG. 9B, similarly to the second embodiment, the second insulating barrier layer 17 extends in the direction crossing the gate electrode 23 in each cell block 50, that is, in the gate length direction. The side part is in contact with the interlayer insulating film 13.

  As a result, the lower electrode 31 of the capacitive element 30 has its side surface covered with the first insulating barrier layer 15A and the upper surface of the upper electrode 33 of the capacitive element, including the side surface of the buried insulating film 16 burying the lower electrode 31. The side surfaces and the side surfaces of the capacitive insulating film 32 are covered by the second insulating barrier layer 17 in cell block units (here, two block units). At this time, the second insulating barrier layer 17 is in contact with the first insulating barrier layer 15A located below the buried insulating film 16 at its end face.

  In addition, as shown in FIGS. 9A and 9C, the upper electrode 33 is electrically connected to one of the plurality of lower electrodes 31 with respect to the capacitance insulating film 32 of each cell block 50. The upper electrode plug 33a is formed by filling the opening 32a with a part of the upper electrode 33 so as to be connected to the upper electrode plug 33a. Here, as an example, the lower electrode 31 located at the right end is used as the upper electrode connection electrode 31A, and thereby, the contact plug 14, the upper electrode connection electrode 31A, and the upper electrode plug 33a from the source / drain region 21 of the cell transistor 20. , A predetermined voltage can be applied to the upper electrode 33.

  As described above, unlike the cell transistor (first transistor) 20 electrically connected to the lower electrode 31 of the capacitive element 30 via the contact plug (first contact plug) 14, the upper electrode connecting electrode 31A Does not constitute the capacitive element 30. Therefore, the operation of the cell transistor (second transistor) 20 electrically connected to the upper electrode connecting electrode 31A via the contact plug (second contact plug) 14 is different from that of the first transistor.

  As described above, in the third embodiment, since the operation voltage can be applied to the upper electrode 33 via the cell transistor 20, the upper surface of the upper electrode 33, that is, the second insulating barrier layer 17 can be applied to the upper electrode 33. There is no need to open a contact hole. For this reason, since it is not necessary to provide an opening in the second insulating barrier layer 17 covering the cell block 50, the ashing process of the resist after the opening, the plug filling process, and the wiring process become unnecessary. As a result, after the second insulating barrier layer 17 is formed, the capacitor 30 is not exposed to hydrogen, so that deterioration of the characteristics of the capacitor 30 can be prevented.

  In the third embodiment, the configuration is such that the second insulating barrier layer 17 covers the two cell blocks 50. However, the configuration is not limited to this, and any configuration may be used as long as it covers one or more cell blocks 50. .

  Further, the electrical connection between the upper electrode 33 and the cell transistor 20 does not necessarily require the upper electrode connecting electrode 31A to be interposed, and the upper electrode plug 33a and the contact plug 14 may be directly connected. However, since all the capacitive elements 30 included in the cell block 50 have the same structure, it is preferable to interpose the upper electrode connecting electrode 31A having the same structure as the lower electrode 31 because the process is simplified.

  Hereinafter, a method of manufacturing a semiconductor memory device including the capacitor element and the upper electrode connecting electrode configured as described above will be described with reference to the drawings.

  FIGS. 10A to 10C and FIGS. 11A and 11B show a method for manufacturing a semiconductor memory device according to the third embodiment of the present invention. 3 shows a cross-sectional configuration in the order of steps along line IXc-IXc.

  First, the gate insulating film 22, the gate electrode 23 and the sidewall insulating film 24 shown in FIG. 9B are selectively formed on the semiconductor substrate 11 made of silicon, and then the gate electrode 23 on the semiconductor substrate 11 is formed. A plurality of cell transistors 20 are formed by forming source / drain regions 21 on both sides of the cell transistor 20.

  Next, as shown in FIG. 10A, an interlayer insulating film 13 made of, for example, silicon oxide such as BPSG is deposited on the entire surface including the plurality of cell transistors 20 on the semiconductor substrate 11 by the CVD method. Subsequently, the upper surface of the deposited interlayer insulating film 13 is planarized by a CMP method or the like. Subsequently, contact holes are respectively formed in one of the source / drain regions 21 of each cell transistor 20 in the interlayer insulating film 13 by a lithography method and a dry etching method, and a conductor film made of tungsten or polysilicon is formed by a CVD method. Deposit to fill the holes. Subsequently, a plurality of contact plugs 14 are formed by removing the conductive film on the interlayer insulating film 13 by etch-back method or CMP method for the deposited conductive film. Next, a first conductive barrier layer 31a made of titanium aluminum nitride for preventing diffusion of oxygen and hydrogen is formed on the interlayer insulating film 13 including the formed contact plug 14 by, for example, a sputtering method, and iridium for preventing diffusion of oxygen. , A third conductive barrier layer made of iridium dioxide for preventing diffusion of oxygen, and a conductive layer made of platinum are sequentially deposited to form a lower electrode forming film. Here, the thickness of the first conductive barrier layer 31a for preventing diffusion of oxygen and hydrogen is about 40 nm to 100 nm, and the second conductive barrier layer 31b and the second conductive barrier layer 31b for preventing diffusion of oxygen. , And the thickness of the conductive layer are each about 50 nm to 100 nm. Subsequently, the lower electrode forming film is patterned by the lithography method and the dry etching method so as to include the contact plugs 14 to form a plurality of lower electrodes 31 made of the lower electrode forming film. Thereafter, a first film made of aluminum oxide having a film thickness of about 20 nm to 200 nm and preventing diffusion of oxygen and hydrogen is formed on the interlayer insulating film 13 by sputtering or CVD so as to cover the upper surface and side surfaces of the lower electrode 31. An insulating barrier layer 15 is formed. Here, it is preferable to perform a heat treatment in an oxidizing atmosphere after the formation of the first insulating barrier layer 15 because aluminum oxide included in the first insulating barrier layer 15 is densified. Subsequently, a buried insulating layer of silicon oxide or silicon nitride having a thickness of about 400 nm to 600 nm is formed so as to cover the first insulating barrier layer 15 by a CVD method in a hydrogen-containing atmosphere using, for example, monosilane as a raw material. A film 16 is deposited.

  Next, as shown in FIG. 10B, each lower portion of the buried insulating film 16 and the first insulating barrier layer 15 is planarized by using a CMP method until the lower electrode 31 is exposed. The periphery of the electrode 31 is buried with the buried insulating film 16. Therefore, the upper surface of the lower electrode 31 has substantially the same height as the exposed surfaces of the buried insulating film 16 and the first insulating barrier layer 15.

Next, as shown in FIG. 10C, the thickness is 50 nm over the entire surface of the first insulating barrier layer 15, the buried insulating film 16, and the lower electrode 31 by the MOD method, the MOCVD method, or the sputtering method. forming a capacitor insulating film forming film 32A made of tantalum niobate, strontium bismuth _{(SrBi 2 (Ta 1-x} Nb x) 2 O 9) having a bismuth layered perovskite structure of about ～150Nm. Subsequently, the upper portion of the upper electrode connecting electrode 31A in the formed capacitor insulating film forming film 32A is selectively removed by lithography and dry etching. Thus, an opening 32a is formed in the capacitor insulating film forming film 32A, and the upper electrode connecting electrode 31A is exposed from the formed opening 32a. Subsequently, an upper electrode forming film 33A made of platinum having a thickness of about 50 nm to 150 nm is formed by sputtering so as to fill the opening 32a on the capacitor insulating film forming film 32A. As a result, the opening 32a is filled with platinum to form the upper electrode plug 33a, and the upper electrode 33A is electrically connected to the upper electrode connecting electrode 31A by the upper electrode plug 33a. Thereafter, heat treatment is performed in an oxygen atmosphere at a temperature of about 650 ° C. to 800 ° C. to crystallize the metal oxide forming the capacitance insulating film forming film 32A.

  Next, as shown in FIG. 11A, using a resist mask (not shown) for masking each cell block 50, the upper electrode forming film 33A, the capacitor insulating film forming film 32A, the buried insulating film 16, and Dry etching is sequentially performed on the first insulating barrier layer 15 to form the upper electrode 33 from the upper electrode forming film 33A, and form the capacitive insulating film 32 from the capacitive insulating film forming film 32A. At this time, a first insulating barrier layer 15A obtained by patterning the first insulating barrier layer 15 is obtained.

  Next, as shown in FIG. 11B, the upper and side surfaces of the upper electrode 33 and the capacitor insulating film 32, which are patterned for each cell block 50, on the interlayer insulating film 13 by the CVD method or the sputtering method. A second insulating barrier layer made of aluminum oxide having a thickness of about 5 nm to 100 nm and preventing diffusion of hydrogen over the entire surface so as to cover the side surface of the buried insulating film 16 and the end surface of the first insulating barrier layer 15A. 17 is formed. Thus, a configuration is obtained in which the second insulating barrier layer 17 is in contact with the end surface of the first insulating barrier layer 15A located below the buried insulating film 16 around the cell block 50. Subsequently, as shown in FIG. 9A, the formed second insulating barrier layer 17 is patterned by dry etching so as to include two cell blocks 50 adjacent to each other. However, patterning of the second insulating barrier layer 17 is not necessarily performed.

  As a modification of the manufacturing method according to the third embodiment, as in the manufacturing method according to the first embodiment, the upper electrode 33, the capacitor insulating film 32, and the like shown in FIG. In the step of patterning each time, the first insulating barrier layer 15 is not subjected to patterning, and the first insulating barrier layer 15 is continuously patterned with the second insulating barrier layer 17 in a subsequent step shown in FIG. May be patterned.

(Fourth embodiment)
Hereinafter, a fourth embodiment of the present invention will be described with reference to the drawings.

  FIGS. 12A to 12C show a semiconductor memory device according to a fourth embodiment of the present invention, and FIG. 12A shows a plan configuration of a cell block including a plurality of cells constituting a memory cell array. FIG. 12B shows a cross-sectional configuration taken along line XIIb-XIIb in FIG. 12A, and FIG. 12C shows a cross-sectional configuration taken along line XIIc-XIIc in FIG. In FIGS. 12A to 12C, the same components as those shown in FIGS. 9A to 9C are denoted by the same reference numerals, and description thereof will be omitted.

  As shown in FIGS. 12B and 12C, the first insulating barrier layer 45 according to the fourth embodiment is formed only on the interlayer insulating film 13, and therefore, the contact plug 14 is formed penetrating through the interlayer insulating film 13 and the first insulating barrier layer 45. Further, the first conductive barrier layer 31 a constituting the lower electrode 31 of the capacitor 30 is formed on the first insulating barrier layer 45.

Here, as in the first to third embodiments, the first insulating barrier layer 45 for preventing diffusion of oxygen and hydrogen is preferably made of aluminum oxide, titanium aluminum oxide, or tantalum aluminum oxide. It is preferable to use silicon nitride (Si ₃ N ₄ ) or silicon oxynitride (SiON). The use of silicon nitride or silicon oxynitride facilitates formation of a contact hole when forming the contact plug 14 as compared with aluminum oxide or the like.

  Further, as shown in FIG. 12A, the second insulating barrier layer 17 is formed so as to cover two cell blocks 50 adjacent to each other. Further, as shown in FIG. 12B, the second insulating barrier layer 17 is in contact with the interlayer insulating film 13 in a direction crossing the gate electrode 23 in each cell block 50. As a result, the lower electrode 31 of the capacitor 30 includes the upper surface and the side surface of the upper electrode 33 of the capacitor and the side surface of the capacitor insulating film 32 including the side surface of the buried insulating film 16 burying the lower electrode 31. It is covered by the barrier layer 17 in cell block units (here, two block units). At this time, the second insulating barrier layer 17 is in contact with the first insulating barrier layer 15 located below the buried insulating film 16 at its end face.

  Further, similarly to the third embodiment, an opening 32a is provided so that the upper electrode 33 is electrically connected to any one of the plurality of lower electrodes 31, and the upper electrode 33 is formed in the opening 32a. The upper electrode plug 33a is formed by being partially filled. Therefore, an operating voltage can be applied to the upper electrode 33 via the cell transistor 20 without opening the second insulating barrier layer 17 that covers the upper and side surfaces of the cell block 50. Therefore, the ashing process of the resist after the opening, the filling process of the plug, and the wiring process are not required, and the capacitor 30 is not exposed to hydrogen after the formation of the second insulating barrier layer 17. Deterioration of the characteristics of the element 30 can be prevented.

  In the fourth embodiment, the second insulating barrier layer 17 covers the two cell blocks 50 as in the third embodiment. However, the present invention is not limited to this. Any configuration that covers the block 50 may be used.

  The electrical connection between the upper electrode 33 and the cell transistor 20 does not necessarily require the upper electrode connection electrode 31A to be interposed.

  Hereinafter, a method of manufacturing a semiconductor memory device including the capacitor element and the upper electrode connecting electrode configured as described above will be described with reference to the drawings.

  FIGS. 13A to 13C and FIGS. 14A and 14B show a method of manufacturing a semiconductor memory device according to the fourth embodiment of the present invention. The cross-sectional configuration in the order of steps along the line XIIc-XIIc is shown.

  First, the gate insulating film 22, the gate electrode 23, and the sidewall insulating film 24 shown in FIG. 12B are selectively formed on the semiconductor substrate 11 made of silicon. A plurality of cell transistors 20 are formed by forming the source / drain regions 21 in the regions on both sides of.

  Next, as shown in FIG. 13A, an interlayer insulating film 13 made of silicon oxide such as BPSG is deposited on the semiconductor substrate 11 over the entire surface including the plurality of cell transistors 20 by the CVD method. Subsequently, the upper surface of the deposited interlayer insulating film 13 is flattened by a CMP method or the like, and thereafter, is formed of, for example, silicon nitride or aluminum oxide having a thickness of about 20 nm to 200 nm by a CVD method or a sputtering method, and contains oxygen and hydrogen. A first insulating barrier layer 45 for preventing diffusion is formed. Subsequently, contact holes are respectively formed in the interlayer insulating film 13 and one of the source / drain regions 21 of each cell transistor 20 in the first insulating barrier layer 45 by lithography and dry etching, and tungsten or tungsten is formed by CVD. A conductor film made of polysilicon is deposited so as to fill each contact hole. Subsequently, a plurality of contact plugs 14 are formed by removing the conductive film on the interlayer insulating film 13 by etch-back method or CMP method for the deposited conductive film. Thereafter, a first conductive barrier layer 31a made of titanium aluminum nitride for preventing diffusion of oxygen and hydrogen is formed on the interlayer insulating film 13 including the formed contact plug 14 by, for example, a sputtering method. A second conductive barrier layer, a third conductive barrier layer made of iridium dioxide for preventing diffusion of oxygen, and a conductive layer made of platinum are sequentially deposited to form a lower electrode forming film. Here, the thickness of the first conductive barrier layer 31a for preventing diffusion of oxygen and hydrogen is about 40 nm to 100 nm, and the second conductive barrier layer 31b and the second conductive barrier layer 31b for preventing diffusion of oxygen. , And the thickness of the conductive layer are each about 50 nm to 100 nm. Subsequently, the lower electrode forming film is patterned by the lithography method and the dry etching method so as to include the contact plugs 14 to form a plurality of lower electrodes 31 made of the lower electrode forming film. Subsequently, a buried insulating film 16 made of silicon oxide or silicon nitride having a thickness of about 400 nm to 600 nm is formed so as to cover the plurality of lower electrodes 31 by, for example, a CVD method in an atmosphere containing hydrogen using monosilane as a raw material. accumulate.

  Next, as shown in FIG. 13B, the buried insulating film 16 is planarized by using a CMP method until the lower electrode 31 is exposed to the buried insulating film 16 so that the periphery of each lower electrode 31 is buried. Embed by Therefore, the upper surface of the lower electrode 31 has substantially the same height as the exposed surface of the buried insulating film 16.

  Next, as shown in FIG. 13C, a bismuth layered perovskite structure having a thickness of about 50 nm to 150 nm is formed over the entire surface of the buried insulating film 16 and the lower electrode 31 by MOD, MOCVD, or sputtering. A capacitor insulating film forming film 32A made of strontium bismuth tantalum niobate having the same is formed. Subsequently, the upper portion of the upper electrode connecting electrode 31A in the formed capacitor insulating film forming film 32A is selectively removed by lithography and dry etching. Thus, an opening 32a is formed in the capacitor insulating film forming film 32A, and the upper electrode connecting electrode 31A is exposed from the formed opening 32a. Subsequently, an upper electrode forming film 33A made of platinum having a thickness of about 50 nm to 150 nm is formed by sputtering so as to fill the opening 32a on the capacitor insulating film forming film 32A. As a result, the opening 32a is filled with platinum to form the upper electrode plug 33a, and the upper electrode 33A is electrically connected to the upper electrode connecting electrode 31A by the upper electrode plug 33a. Thereafter, heat treatment is performed in an oxygen atmosphere at a temperature of about 650 ° C. to 800 ° C. to crystallize the metal oxide forming the capacitance insulating film forming film 32A.

  Next, as shown in FIG. 14A, using a resist mask (not shown) for masking each cell block 50, the upper electrode forming film 33A, the capacitor insulating film forming film 32A, the buried insulating film 16, and Dry etching is sequentially performed on the first insulating barrier layer 45 to form the upper electrode 33 from the upper electrode forming film 33A, and form the capacitive insulating film 32 from the capacitive insulating film forming film 32A.

  Next, as shown in FIG. 14B, the upper surface and the side surface of the upper electrode 33 and the capacitor insulating film 32, which are patterned for each cell block 50, on the interlayer insulating film 13 by the CVD method or the sputtering method. And a second insulating barrier layer made of aluminum oxide having a thickness of about 5 nm to 100 nm to prevent diffusion of hydrogen over the entire surface so as to cover the side surface of the buried insulating film 16 and the end surface of the first insulating barrier layer 45. 17 is formed. Thus, a configuration is obtained in which the second insulating barrier layer 17 is in contact with the end surface of the first insulating barrier layer 45 located below the buried insulating film 16 around the cell block 50. Subsequently, as shown in FIG. 12A, the formed second insulating barrier layer 17 is patterned by dry etching so as to include two cell blocks 50 adjacent to each other. However, patterning of the second insulating barrier layer 17 is not necessarily performed.

  As a modification of the manufacturing method according to the fourth embodiment, as in the manufacturing method according to the first embodiment, the upper electrode 33, the capacitor insulating film 32, and the like shown in FIG. In the step of patterning each time, patterning is not performed on the first insulating barrier layer 45, and the first insulating barrier layer 45 is continuously formed with the second insulating barrier layer 17 in a subsequent step shown in FIG. May be patterned.

In the first to fourth embodiments, strontium bismuth tantalum niobate (SrBi ₂ (Ta _1-x Nb _x ) ₂ O ₉ ) is used for the capacitance insulating film 32, but the present invention is not limited to this. Any ferroelectric material having a layered perovskite structure may be used. For example, lead zirconate titanate, strontium barium titanate, tantalum pentoxide, or the like may be used.

In the first to fourth embodiments, aluminum oxide (Al ₂ O ₃ ) is used for the first insulating barrier layers 15, 15 A, and 45. Instead, titanium aluminum oxide (TiAlO) is used. ) Or tantalum aluminum oxide (TaAlO). By doing so, these metal oxides, including aluminum oxide, can almost completely prevent diffusion of oxygen and hydrogen from the buried insulating film 16 to the lower electrode 31 from the side direction. However, as described above, for the first insulating barrier layer 45 according to the fourth embodiment, silicon nitride (Si ₃ N ₄ ) or silicon oxynitride (SiON) is used because of its easy workability. Is preferred.

Similarly, the second insulating barrier layer 17 may use titanium aluminum oxide (TiAlO) or tantalum aluminum oxide (TaAlO) instead of aluminum oxide (Al ₂ O ₃ ). By doing so, diffusion of hydrogen from the direction perpendicular to and parallel to the substrate surface with respect to the capacitive insulating film 32 can be almost completely suppressed.

  Although the lower electrode 31 according to the first to fourth embodiments uses titanium aluminum nitride (TiAlN) as the first conductive barrier layer 31a, titanium aluminum (TiAl), nitride aluminum Composed of any one of titanium silicide (TiSiN), tantalum nitride (TaN), tantalum silicide (TaSiN), tantalum aluminum nitride (TaAlN), and tantalum aluminum (TaAl), or including TiAlN; It is preferable to be constituted by a laminated film including at least two of these. By doing so, it is possible to prevent oxygen from diffusing to the contact plug 14 during high-temperature oxygen annealing for crystallization of the high dielectric or ferroelectric constituting the capacitive insulating film 32, and to prevent the lower electrode Diffusion of hydrogen from the direction of the substrate 31 to the capacitance insulating film 32 can be prevented.

In addition, iridium (Ir) is used for the second conductive barrier layer 31b constituting the lower electrode 31, and iridium dioxide (IrO ₂ ) is used for the third conductive barrier layer 31c. I can't.

That is, as the second and third conductive barrier layers 31b and 31c, a single-layer film made of iridium dioxide (IrO ₂ ), a single-layer film made of ruthenium dioxide (RuO ₂ ), and ruthenium ( Any of the laminated films composed of Ru) and ruthenium dioxide (RuO ₂ ) may be used. Furthermore, it may be constituted by a laminated film including at least two of these single-layer films and laminated films, including a laminated film composed of iridium (Ir) and iridium dioxide (IrO ₂ ). In this way, at the time of high-temperature oxygen annealing for crystallization of the high dielectric or ferroelectric constituting the capacitive insulating film 32, oxygen diffuses to the contact plug 14, and the diffused oxygen is diffused into the contact plug 14. Oxidation of the surface can prevent an increase in contact resistance.

In the first to fourth embodiments, silicon oxide (SiO ₂ ) or silicon nitride (Si ₃ N ₄ ) is used for the buried insulating film 16 burying the region on the side of the lower electrode 31. Since the lower electrodes 31 adjacent to each other are electrically insulated from each other and can be easily planarized, the lower electrodes 31 are preferably used as a base layer for forming the capacitor insulating film 32.

FIG. 1A is a configuration sectional view illustrating a main part of a semiconductor memory device including a capacitor according to a first embodiment of the present invention.

FIG. 2B is a configuration sectional view illustrating a lower electrode of the capacitor according to the first embodiment of the present invention.
3A to 3C are cross-sectional views illustrating a method of manufacturing the semiconductor memory device according to the first embodiment of the present invention in the order of steps. 3A and 3B are cross-sectional views illustrating a method of manufacturing the semiconductor memory device according to the first embodiment of the present invention in the order of steps. 6 is a graph showing a measurement result of a contact resistance between a contact plug and a lower electrode of a capacitor in the semiconductor memory device according to the first embodiment of the present invention in comparison with a conventional example. 4 is a graph showing measurement results of respective remanent polarizations before and after performing a hydrogen anneal of the capacitive element in the semiconductor memory device according to the first embodiment of the present invention. (A) to (c) show a lower electrode in a semiconductor memory device according to a modification of the first embodiment of the present invention and the vicinity of a first insulating barrier layer that covers the side surface thereof, and It is a structure sectional view concerning a 1st modification, (b) is a structure sectional view concerning a 2nd modification, and (c) is a structure sectional view concerning a 3rd modification. FIG. 6 is a configuration sectional view illustrating a main part of a semiconductor memory device including a capacitor according to a second embodiment of the present invention. FIGS. 7A and 7B are cross-sectional views illustrating a method of manufacturing a semiconductor memory device according to a second embodiment of the present invention, which are different from those of the first embodiment. (A) to (c) show main parts of a semiconductor memory device according to a third embodiment of the present invention, (a) is a plan view showing a cell block constituting a memory cell array, and (b) is a plan view showing ( It is sectional drawing in the IXb-IXb line of (a), (c) is sectional drawing in the IXc-IXc line of (a). 9A to 9C are cross-sectional views illustrating a method for manufacturing a semiconductor memory device according to a third embodiment of the present invention, in the order of steps along line IXc-IXc in FIG. 9A and 9B are cross-sectional views illustrating a method for manufacturing a semiconductor memory device according to a third embodiment of the present invention, in the order of steps along line IXc-IXc in FIG. (A) to (c) show a main part of a semiconductor memory device according to a fourth embodiment of the present invention, (a) is a plan view showing a cell block constituting a memory cell array, and (b) is a plan view showing ( It is sectional drawing in the XIIb-XIIb line of a), (c) is sectional drawing in the XIIc-XIIc line of (a). (A)-(c) show the manufacturing method of the semiconductor memory device concerning 4th Embodiment of this invention, Comprising: It is a structure sectional drawing in the order of a process along XIIc-XIIc line of FIG.12 (a). 12A and 12B are cross-sectional views illustrating a method of manufacturing a semiconductor memory device according to a fourth embodiment of the present invention, in the order of steps along line XIIc-XIIc in FIG. FIG. 14 is a cross-sectional view illustrating a configuration of a main part of a conventional semiconductor memory device. 7A and 7B are schematic cross-sectional views showing a state in which a problem occurs in a lower electrode of a capacitor in a conventional semiconductor memory device. FIG. 10 is a schematic cross-sectional view illustrating a state in which a failure occurs in a capacitive insulating film of a capacitive element in a conventional semiconductor memory device.

Explanation of reference numerals

Reference Signs List 11 semiconductor substrate 12 shallow trench isolation 13 interlayer insulating film 14 contact plug 15 first insulating barrier layer 15A first insulating barrier layer 16 buried insulating film 17 second insulating barrier layer 20 cell transistor 21 source / drain region 22 Gate insulating film 23 Gate electrode 24 Side wall insulating film 30 Capacitance element 31 Lower electrode 31A Upper electrode connecting electrode 31a First conductive barrier layer 31b Second conductive barrier layer 31c Third conductive barrier layer 31d Conductive layer Reference Signs List 32 capacitor insulating film 32a opening 32A capacitor insulating film forming film 33 upper electrode 33A upper electrode forming film 33a upper electrode plug 45 first insulating barrier layer 50 cell block

Claims (13)

A lower electrode;
A capacitance insulating film made of a metal oxide formed on the lower electrode,
An upper electrode formed on the capacitive insulating film,
A buried insulating film filling the periphery of the lower electrode,
The lower electrode includes a conductive barrier layer that prevents diffusion of oxygen,
A capacitive element, wherein an insulating barrier layer for preventing diffusion of hydrogen is formed so as to contact at least a side surface of the conductive barrier layer among side surfaces of the lower electrode.   The capacitor according to claim 1, wherein the buried insulating film is formed in an atmosphere containing hydrogen. The capacitor according to claim 1, wherein the buried insulating film is made of silicon oxide (SiO ₂ ) or silicon nitride (Si ₃ N ₄ ).   The capacitor according to claim 1, wherein the insulating barrier layer also prevents diffusion of oxygen.   2. The device according to claim 1, wherein the conductive barrier layer includes a stacked film including a first conductive barrier layer for preventing diffusion of oxygen and hydrogen and a second conductive barrier layer for preventing diffusion of oxygen. The capacitive element according to 1.   The first conductive barrier layer includes titanium aluminum nitride (TiAlN), titanium aluminum (TiAl), titanium nitride silicide (TiSiN), tantalum nitride (TaN), tantalum nitride silicide (TaSiN), tantalum aluminum nitride (TaAlN), 6. The capacitive element according to claim 5, wherein the capacitive element is made of any one of aluminum and tantalum aluminum (TaAl) or a laminated film including at least two of them. The second conductive barrier layer is an iridium dioxide (IrO _2), iridium which are sequentially formed from the lower layer (Ir) and iridium dioxide (IrO ₂₎ consisting of a multilayer film, ruthenium dioxide (RuO _2), and from the lower layer It is characterized by being constituted by one of laminated films composed of ruthenium (Ru) and ruthenium dioxide (RuO ₂ ) formed sequentially, or by a laminated film containing at least two of them. The capacitive element according to claim 5, wherein The insulating barrier layer, an aluminum oxide (Al ₂ O _3), the capacity of claim 1, characterized in that it comprises any one of titanium aluminum oxide (TiAlO) and tantalum oxide aluminum (TaAlO) element. A lower electrode;
A capacitance insulating film made of a metal oxide formed on the lower electrode,
An upper electrode formed on the capacitive insulating film,
A buried insulating film filling the periphery of the lower electrode,
The lower electrode, iridium dioxide (IrO2), consisting of a sequentially formed iridium from the lower layer (Ir) and iridium dioxide (IrO ₂₎ film stack, ruthenium dioxide (RuO _2), and sequentially formed ruthenium from the lower layer ( Ru) and a conductive barrier layer constituted by a laminate film including ruthenium dioxide (RuO ₂ ), or a laminate film including at least two of them.
At least one of aluminum oxide (Al ₂ O ₃ ), titanium aluminum oxide (TiAlO), and tantalum aluminum oxide (TaAlO) is included so as to contact at least the side surface of the conductive barrier layer among the side surfaces of the lower electrode. A capacitive element having an insulating barrier layer formed thereon. A transistor formed on a semiconductor substrate and having a source region and a drain region;
An interlayer insulating film formed on the semiconductor substrate to cover the transistor;
A contact plug formed in the interlayer insulating film so as to be electrically connected to the source region or the drain region of the transistor;
10. A semiconductor memory device, comprising: the capacitor according to claim 1, wherein the lower electrode is formed on the contact plug. After forming a gate electrode on a semiconductor substrate, a first step of forming a transistor by forming a source region and a drain region respectively on the side of the gate electrode in the semiconductor substrate,
A second step of forming an interlayer insulating film on the semiconductor substrate including the transistor;
A third step of forming a contact plug electrically connected to the source region or the drain region in the interlayer insulating film;
A fourth step of forming a first conductive film including a conductive barrier layer for preventing diffusion of oxygen on the interlayer insulating film;
A fifth step of forming a lower electrode from the first conductive film on the interlayer insulating film by patterning the first conductive film so as to be electrically connected to the contact plug;
A sixth step of forming an insulating barrier layer for preventing diffusion of hydrogen over the interlayer insulating film so as to cover an upper surface and side surfaces of the lower electrode;
A seventh step of forming a first insulating film on the insulating barrier layer, and thereafter planarizing the first insulating film and the insulating barrier layer so as to expose the lower electrode;
A second insulating film made of a metal oxide on the planarized first insulating film and the insulating barrier layer including on the exposed lower electrode, and a second insulating film on the second insulating film; An eighth step of forming a conductive film of
An upper electrode is formed from the second conductive film on the lower electrode by patterning the second conductive film, the second insulating film, and the first insulating film so as to include the lower electrode. A ninth step of forming a capacitive insulating film from the second insulating film and forming a buried insulating film filling the periphery of the lower electrode from the first insulating film. Device manufacturing method.   12. The method according to claim 11, wherein the buried insulating film is formed in an atmosphere containing hydrogen.   The fourth step includes a step of forming a first conductive barrier layer for preventing diffusion of oxygen and hydrogen, and a step of forming a second conductive barrier layer for preventing diffusion of oxygen. The method of manufacturing a semiconductor memory device according to claim 11.

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