JP2004153285A - Thin film transistor, liquid crystal display device and thin film transistor circuit using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a thin film transistor (hereinafter, referred to as a TFT) capable of suppressing a local temperature rise due to self-heating and improving reliability without increasing the number of manufacturing steps, and an active device using the thin film transistor in a drive circuit or the like. Provided is a liquid crystal display device including a matrix substrate.
SOLUTION: In a TFT having a channel region 5 facing a gate electrode 4 via a gate insulating film and a self-aligned high-concentration source / drain region 8 connected to the channel region, the gate electrode is A structure having a bulging portion 44 which bulges in the central portion in the channel width direction while curving in the channel length direction.
[Selection] Fig. 6

Description

  The present invention relates to a thin film transistor (hereinafter, referred to as a TFT) and a liquid crystal display device using an active matrix substrate including a driving circuit configured using the thin film transistor. More specifically, the present invention relates to a structural technique for suppressing a temperature rise due to self-heating of a TFT.

  FIG. 13 shows a planar shape of a TFT widely used for an active matrix substrate for a liquid crystal display device and the like, and FIG. 1C shows a cross-sectional view taken along the line CC 'of FIG. In addition, a channel region 5 facing the gate electrode 4 via the gate insulating film 2 and a source / drain region 8 composed of a high-concentration region connected to the channel region 5 are provided. Here, conventionally, the gate electrode 4 is formed so as to have a substantially rectangular planar shape without protruding laterally (in the channel length direction). FIG. 14 shows a plan view of a TFT having an offset structure, and FIG. 1A is a cross-sectional view taken along the line AA ′. As shown in FIG. An offset region 7 in which impurities are not introduced or in which only the same amount of impurities as the channel region 5 is introduced by channel doping is formed in a portion facing the end of the electrode 4 via the gate insulating film 2. There are cases. Also in this case, the boundary between the offset region 7 and the high concentration source / drain region 8 is linear, and the offset length Loff is constant in the channel width direction.

  However, in a TFT having a conventional structure, if the current flowing through the TFT is increased to improve its characteristics and performance, the temperature rise in the channel region is large due to the self-heating of the TFT, and a local temperature rise occurs accordingly. Therefore, there is a problem that characteristics are deteriorated and reliability is deteriorated.

  Therefore, a method of adding a layer having high thermal conductivity between the layers constituting the TFT and using the layer as a heat dissipation layer to suppress the temperature rise of the TFT can be considered. However, according to this method, there is a problem that, when an active matrix substrate or the like is manufactured, a step of forming a film used as a heat radiation layer and a step of patterning the film are increased. Such an increase in the number of manufacturing steps is not preferable because it increases the manufacturing cost of the active matrix substrate and the like.

  In view of the above problems, an object of the present invention is to improve the structure around the channel region, thereby suppressing a local temperature rise due to self-heating without increasing the number of manufacturing steps and improving reliability. An object of the present invention is to provide a liquid crystal display device including a TFT that can be achieved and an active matrix substrate using the TFT for a driving circuit and the like.

  In order to solve the above-mentioned problem, in the present invention, a structure around a channel region is improved as described below to realize a TFT with a small temperature rise due to self-heating without increasing the number of manufacturing steps. Here, each configuration is shown by taking an example in which an offset gate structure is adopted. However, even when an LDD structure is adopted in place of the offset gate structure, the same effect can be obtained by a similar configuration. it can. When such an LDD structure is employed, in the following description, the offset region is replaced with an LDD region (low-concentration source / drain region), and the offset length is replaced with the LDD length.

  First, in the TFT according to the first type of the present invention, a channel region facing a gate electrode via a gate insulating film, a source / drain region connected to the channel region, and at least one of the source / drain region. In a TFT having an offset region formed between one side and the channel region, the offset region is characterized in that the offset length at the center in the channel width direction is longer than the offset length at the edge.

  Next, in the TFT according to the second type of the present invention, a channel region facing the gate electrode via the gate insulating film, a source / drain region connected to the channel region, In a TFT having at least one and an offset region formed between the channel region, the offset region is formed only in a central portion in a channel width direction.

  When current flows through the channel region of the TFT and self-heats, the temperature rise is small at the edge portion in the channel width direction, so the temperature rise is small. large. However, the TFTs according to the first and second types have an offset region in the center portion in the channel width direction, while the edge portion has an extremely short offset length, or has an offset length of 0, that is, with respect to the gate electrode. It is self-aligned. Therefore, the current tends to concentrate on the side of the edge portion in the channel width direction, so that the heat generation amount is large at the edge portion, but the temperature rise is small due to the good heat dissipation. On the other hand, the central portion in the channel width direction has poor heat dissipation, but the current flowing therethrough is small and the calorific value is small, so that the temperature rise is small. Moreover, in order to form such a structure, it is only necessary to change a mask pattern when implanting impurity ions. Therefore, according to the present invention, it is possible to suppress a local temperature increase due to self-heating and increase the reliability of the TFT without increasing the number of manufacturing steps.

  In the TFTs according to the first and second types, a boundary portion between the offset region and a source / drain region adjacent to the offset region has a central portion in a channel width direction curved toward the source / drain region. It is preferable to have a planar shape that protrudes so that That is, the offset region does not protrude toward the source / drain region in an angular shape. Therefore, the current distribution in the channel width direction draws a gentle curve, so that the current does not concentrate on a specific portion. Therefore, local temperature rise due to self-heating can be suppressed, and the reliability of the TFT can be improved.

  When such a configuration is adopted, it is preferable that the width dimension of the channel region is 50 μm or more. Further, the offset region preferably has an offset length at the central portion in the channel width direction of 2 μm or less, preferably in the range of 0.25 μm to 1.0 μm.

  Next, in the TFT according to the third type of the present invention, a channel region facing the gate electrode via the gate insulating film, a source / drain region connected to the channel region, In a TFT having at least one offset region formed between the channel region and the channel region, a plurality of the offset regions and the plurality of source / drain regions are alternately provided in a channel width direction.

  With this configuration, the current path in one TFT is divided in parallel. Therefore, since current does not concentrate on a specific portion, local temperature rise due to self-heating can be suppressed, and reliability of the TFT can be improved. In addition, in order to form such a structure, it is only necessary to change the mask pattern when implanting the impurity ions, so that the number of manufacturing steps does not increase.

  Such a configuration is employed when the width of the channel region is, for example, 200 μm or less.

  On the other hand, when the width of the channel region is, for example, 200 μm or more, the following configuration may be adopted.

  For example, the offset region is configured to be unevenly distributed at the center in the channel width direction. Alternatively, of the plurality of offset regions, an offset region at a central portion in the channel width direction may have a wider width than an offset region on an edge side. With such a configuration, similarly to the first and second types of TFTs, current tends to concentrate at the edge portion, so that the amount of heat generated is large, but the temperature rise is small due to good heat radiation. On the other hand, the central portion in the channel width direction has poor heat dissipation, but the current flowing therethrough is small and the calorific value is small, so that the temperature rise is small. Moreover, in order to form such a structure, it is only necessary to change a mask pattern when implanting impurity ions. Therefore, according to the present invention, it is possible to suppress a local temperature rise due to self-heating and improve reliability without increasing the number of manufacturing steps.

  Here, the offset region is configured such that the offset length is in a range from 0.2 μm to 2 μm, preferably in a range from 0.5 μm to 0.75 μm.

  Next, in a TFT according to a fourth type of the present invention, in a TFT having a channel region facing a gate electrode via a gate insulating film, and a source / drain region connected to the channel region, The electrode is provided with a bulging portion that bulges while being curved in the channel length direction at a central portion in the channel width direction.

  This configuration is substantially the same as the first and second types of TFTs. At the edge portion in the channel width direction, the current tends to concentrate due to the short channel length, so that the amount of heat generated is large. However, the temperature rise is small due to the good heat dissipation. On the other hand, in the central portion in the channel width direction, the current flowing therethrough is small and the calorific value is small because the channel length is long, so that the temperature rise is small. Moreover, in the central portion in the channel width direction, the gate electrode made of a material having high heat conductivity such as metal and having excellent heat dissipation is expanded, so that the heat dissipation is improved in this portion, Temperature rise can be suppressed. Further, since the gate electrode has a square shape and does not protrude, the current distribution in the channel width direction draws a gentle curve, so that the current does not concentrate on a specific portion. Moreover, in order to form such a structure, it is only necessary to change the mask pattern when the gate electrode is formed by patterning. Therefore, according to the present invention, it is possible to suppress a local temperature rise due to self-heating and improve reliability without increasing the number of manufacturing steps.

  The first to fourth types of TFTs configured as described above can be used as follows.

  For example, in the first to fourth types of TFTs, the TFTs may be configured as TFTs of the opposite conductivity type, and the TFTs of the opposite conductivity type may be connected to each other to form a thin film transistor circuit.

  In the first to third types of TFTs, these TFTs are each configured as a TFT of the opposite conductivity type, and the TFTs of the opposite conductivity type are connected to each other to form a thin film transistor circuit. Because of the offset gate structure, the offset length of the N-type TFT may be longer than the offset length of the P-type TFT among the TFTs of the opposite conductivity type. With this configuration, if the TFTs have the same structure, even if the N-type TFT has a larger on-state current than the P-type TFT, the on-state current of these TFTs can be reduced by optimizing the offset length. You can balance.

  In the first to fourth types of TFTs, the driving circuit constituted by them may be formed on an active matrix substrate of a liquid crystal display device.

  Further, when a driving circuit composed of the first to third types of TFTs is formed on an active matrix substrate of a liquid crystal display device, each of the TFTs has an offset gate structure. It is preferable that the offset length of the TFT used as the TFT be longer than the offset length of the TFT constituting the driving circuit. With this configuration, in the transfer characteristics of the TFT, the off-leak current of the TFT used as the pixel switching element can be reduced, and the decrease of the on-current level of the TFT forming the driving circuit can be suppressed.

  As described above, according to the present invention, in any of the above-described TFTs, the structure of the periphery of the channel region, such as the planar shape of the offset region and the planar shape of the gate electrode, is improved without increasing the number of manufacturing steps. In addition, local temperature rise due to self-heating is suppressed. Therefore, the reliability of the TFT can be improved.

BEST MODE FOR CARRYING OUT THE INVENTION

An embodiment of the present invention will be described with reference to the drawings. In the following description, portions having common functions are denoted by the same reference numerals to avoid duplication of description.
[Embodiment 1]
1A and 1B are longitudinal sectional views of a TFT having an offset gate structure, and FIG. 2 is a plan view of the TFT of the present embodiment. Here, FIG. 1A corresponds to a cross-sectional view taken along the line AA ′ passing through a central portion in the channel width direction in FIG. 2, and FIG. 1B shows an edge portion in the channel width direction in FIG. This corresponds to a cross-sectional view taken along the line BB '.

  As shown in FIG. 1A, a TFT has a gate electrode 4 made of a metal layer containing aluminum, tantalum, molybdenum, titanium, tungsten, or the like on a glass substrate 50, and a silicon oxide film on the gate electrode 4. And a source / drain region 8 connected to the channel region 5 with the gate insulating film 2 formed therebetween. This TFT has a structure in which a wiring layer 40 located on an upper layer side of an interlayer insulating film 52 made of a silicon oxide film is electrically connected to a high-concentration source / drain region 8 via a contact hole 9. On the front side of the glass substrate 50, a base protective film 51 made of a silicon oxide film is formed.

  When the TFT having such a structure is formed as an LDD structure or an offset gate structure, the withstand voltage is improved, and the channel length can be shortened. Therefore, the influence of the parasitic capacitance can be suppressed, and the off-leak current can be reduced. can do.

  Therefore, in the TFT according to the present embodiment, first, an impurity is introduced between the source / drain region 8 and the channel region 5 (a portion facing the end of the gate electrode 4 via the gate insulating film 2). An offset region 7 is formed which is not doped or has only the same impurity as channel region 5 introduced by channel doping.

  Further, as shown in FIG. 2, a boundary portion 70 between the offset region 7 and the high-concentration source / drain region 8 adjacent to the offset region 7 has a central portion in the channel width direction closer to the source / drain region 8. And has a planar shape protruding so as to be curved toward. Therefore, the offset region 7 has a structure in which the offset length Loffc at the center in the channel width direction is longer than the offset length offe at the edge. Therefore, the cross section taken along the line AA 'passing through the central portion in the channel width direction in FIG. 2 appears as shown in FIG. 1A, and the line BB' passing through the edge portion in the channel width direction in FIG. The cross section appears as shown in FIG.

  Here, the offset region 7 has a width dimension of 50 μm or more and is relatively wide, so that a large on-current can flow and ordinary photolithography technology is sufficient for forming a shape having a different offset length in the channel width direction. It is. In addition, the offset length Loffc at the central portion in the channel width direction is set to 2 μm or less from the viewpoint of securing a high on-current. However, from the viewpoint of maximizing the advantage of the above-described offset gate structure, the offset length Loffc is set to 0 μm. It is set in a range from 0.25 μm to 1.0 μm.

  In the TFT according to the present embodiment configured as described above, the current tends to concentrate on the side of the edge portion in the channel width direction of the offset region 7 due to the shorter offset length offe, and therefore, heat is generated at the edge portion. Although the amount is large, the temperature rise is small due to good heat dissipation. On the other hand, the central portion in the channel width direction has poor heat dissipation, but the long offset length Loffc causes a small current to flow therethrough and a small amount of heat, so that the temperature rise is small. Moreover, in order to form such a structure, it is only necessary to change a mask pattern when implanting impurity ions for forming the high concentration source / drain regions 8. Therefore, according to the present invention, it is possible to suppress a local temperature increase due to self-heating and increase the reliability of the TFT without increasing the number of manufacturing steps.

Further, in the present embodiment, the offset region 7 protrudes so as to bulge toward the source / drain region 8, and does not protrude in an angular shape. Therefore, the current distribution in the channel width direction in the offset region 7 draws a gentle curve, so that the current does not concentrate on a specific portion. Therefore, local temperature rise due to self-heating can be suppressed, and the reliability of the TFT can be improved.
[Embodiment 2]
1A and 1C are longitudinal sectional views of a TFT having an offset gate structure and a self-aligned structure, respectively, and FIG. 3 is a plan view of the TFT of the present embodiment. Here, FIG. 1A corresponds to a cross-sectional view taken along the line AA ′ passing through a central portion in the channel width direction in FIG. 3, and FIG. 1C shows an edge portion in the channel width direction in FIG. This corresponds to a cross-sectional view taken along line CC ′.

  As shown in FIG. 1A, the TFT according to this embodiment also has a portion between the source / drain region 8 and the channel region 5 (a portion facing the end of the gate electrode 4 via the gate insulating film 2). Is formed with an offset region 7 into which no impurity is introduced or into which only the same amount of impurity as the channel region 5 is introduced by channel doping.

In addition, as shown in FIG. 3, a boundary portion 70 between the offset region 7 and the source / drain region 8 adjacent to the offset region 7 has a central portion in the channel width direction directed toward the source / drain region 8. It has a planar shape protruding so as to be curved. Further, a boundary portion 70 between the offset region 7 and the source / drain region 8 overlaps the edge of the gate electrode 4 at the edge of the offset region 7.
For this reason, the offset length is provided only between the source / drain region 8 and the channel region 5 (the portion facing the end of the gate electrode 4 via the gate insulating film 2) in the center portion in the channel width direction. Has an offset region 7 of Loffc, and the offset region 7 has a shorter offset length from the central portion toward the edge portion, and is self-aligned with the gate electrode 4 at the edge portion. Therefore, the cross section taken along the line AA 'passing through the central portion in the channel width direction in FIG. 3 appears as shown in FIG. 1A, and the line CC' passing through the edge portion in the channel width direction in FIG. The cross section appears as shown in FIG.

Also here, the offset region 7 has a width dimension of 50 μm or more and is relatively wide, so that a large on-current can flow, and a normal photolithography technique is sufficient for forming a shape having a different offset length in the channel width direction. It is.
In addition, the offset length Loffc at the central portion in the channel width direction is set to 2 μm or less from the viewpoint of securing a high on-current. However, from the viewpoint of maximizing the advantage of the above-described offset gate structure, the offset length Loffc is set to 0 μm. It is set in a range from 0.25 μm to 1.0 μm.

Also in the TFT according to the present embodiment configured as described above, the current tends to concentrate on the side of the edge portion in the channel width direction in the offset region 7 because of the self-alignment. Although large, the temperature rise is small due to good heat dissipation. On the other hand, the central portion in the channel width direction has poor heat dissipation properties, but the offset length Loffc is longer, the current flowing therethrough is smaller, and the amount of heat generation is smaller, so that the temperature rise is smaller. A similar effect is achieved.
[Embodiment 3]
1A and 1C are longitudinal sectional views of a TFT having an offset gate structure and a self-aligned structure, respectively, and FIG. 4 is a plan view of the TFT of the present embodiment. Here, FIG. 1A corresponds to a sectional view taken along the line AA ′ passing through the offset region in FIG. 4, and FIG. 1C corresponds to CC ′ passing through a position outside the offset region in FIG. It corresponds to a line sectional view.

  As shown in FIG. 1A, the TFT according to this embodiment also has a portion between the source / drain region 8 and the channel region 5 (a portion facing the end of the gate electrode 4 via the gate insulating film 2). Has an offset region 7 having an offset length Loff into which no impurities are introduced or only impurities of the same level as the channel region 5 are introduced by channel doping.

  However, as shown in FIG. 4, in the present embodiment, the channel width is between the source / drain region 8 and the channel region 5 (the portion facing the end of the gate electrode 4 via the gate insulating film 2). A plurality of offset regions 7 and high-concentration source / drain regions 8 are alternately provided in the direction. In other words, the portion facing the edge of the gate electrode 4 via the gate insulating film 2 is a source / drain region 8 in which both end portions in the channel width direction are self-aligned with the gate electrode 4, and from there toward the center. Thus, the offset regions 7 and the source / drain regions 8 are alternately arranged in parallel. Therefore, a cross section taken along the line AA 'passing through the offset region 7 at the central portion in the channel width direction in FIG. 4 appears as shown in FIG. A cross section taken along the line CC ′ passing through the drain region 8, that is, a cross section taken along the line outside the offset region 7 appears as shown in FIG. 1C.

  Here, the channel region 5 has a width of 200 μm or less, but is still relatively wide from the viewpoint of a conventional TFT, so that a large on-current can flow and a plurality of offset regions 7 are formed in the channel width direction. However, ordinary photolithography technology is sufficient. Each offset region 7 is set within the range from 0.2 μm to 2 μm as follows. From the viewpoint of securing a high on-current and maximizing the advantage of the offset gate structure, It is set in the range of 0.5 μm to 0.75 μm.

In the TFT thus configured, the current path is divided in parallel in one TFT. Therefore, since current does not concentrate on a specific portion, local temperature rise due to self-heating can be suppressed, and reliability of the TFT can be improved.
In addition, even in such a structure, it is only necessary to change a mask pattern when implanting impurity ions for forming the high concentration source / drain regions 8, so that the number of manufacturing steps does not increase.
[Modification of Third Embodiment]
In the third embodiment, when the width of channel region 5 is, for example, 200 μm or more, the configuration may be as follows.

  For example, although not shown, when forming a plurality of offset regions 7, the width of the channel region 5, that is, the width of the source / drain region 8 is made as large as 200 μm or more, and the channel width is increased. The offset region 7 may be unevenly distributed in the central portion in the direction.

  Alternatively, as shown in the plan view of the TFT in FIG. 5, the width of the offset region 7 at the center in the channel width direction among the plurality of offset regions 7 is set to Woff1, and this width is set to the offset region 7 on the edge side. Is configured to be considerably wider than the width dimension Woff2. Here, since the channel region 5 has a considerably large width of 200 μm or more, a large on-current can flow, and even if a plurality of offset regions 7 are formed in the channel width direction, ordinary photolithography is sufficient. It is. Each offset region 7 is set within the range from 0.2 μm to 2 μm as follows. From the viewpoint of securing a high on-current and maximizing the advantage of the offset gate structure, It is set in the range of 0.5 μm to 0.75 μm.

Even in the case of such a configuration, as in the TFTs according to the first and second embodiments, in the source / drain region 8, the current tends to concentrate at the edge portion, so that the amount of generated heat is large, but the heat dissipation is good. Min, temperature rise is small. On the other hand, the central portion in the channel width direction has poor heat dissipation, but the current flowing therethrough is small and the calorific value is small, so that the temperature rise is small. Moreover, in order to form such a structure, it is only necessary to change a mask pattern when implanting impurity ions. Therefore, according to the present invention, there is an effect that the local temperature rise due to self-heating can be suppressed and the reliability can be improved without increasing the number of manufacturing steps.
[Embodiment 4]
FIG. 1C is a longitudinal sectional view of a TFT having a self-aligned structure, and FIG. 6 is a plan view of the TFT of this embodiment.

  As shown in FIG. 1C, also in the TFT according to this embodiment, the channel region 5 facing the gate electrode 4 via the gate insulating film 2 and the source / drain region 8 connected to the channel region 5 are formed. The source / drain regions 8 are high-concentration source / drain regions formed in a self-aligned manner with respect to the gate electrode 4. However, as shown in FIG. 6, in the TFT of the present embodiment, the gate electrode 4 has a bulging portion 44 which bulges while curving in a central portion in the channel width direction with a triangular shape rounded in the channel length direction. ing.

The TFT thus configured is substantially the same as the TFTs according to the first and second embodiments, and the current tends to concentrate at the edge portion in the channel width direction due to the short channel length Lche. Although the calorific value is large, the temperature rise is small due to good heat radiation. On the other hand, in the central portion in the channel width direction, the current flowing therethrough is small and the calorific value is small because the channel length Lchc is long, so that the temperature rise is small.
In addition, in the central portion in the channel width direction, the gate electrode 4 made of a material having high thermal conductivity such as metal and having excellent heat dissipation is expanded. It is possible to suppress a rise in temperature in the portion. In addition, since the gate electrode has an angular shape and does not protrude, the current distribution in the channel width direction draws a gentle curve, so that the current does not concentrate on a specific portion. Moreover, in order to form such a structure, it is only necessary to change a mask pattern when the gate electrode 4 is formed by patterning. Therefore, according to the present invention, it is possible to suppress a local temperature rise due to self-heating and increase the reliability of the TFT without increasing the number of manufacturing steps.
[Modification of Fourth Embodiment]
In forming the bulging portion 44 bulging while curving in the channel length direction at the center of the gate electrode 4, as shown in FIG. 7, only one of the gate electrodes 4 has a rounded triangular bulge. The protrusion 44 may be formed. In addition, as shown in FIG. 8A, the gate electrode 4 is formed in an elliptical shape, or as shown in FIG. 8B, the gate electrode 4 is formed in a circular shape, and the bulge is used as it is. 4 may be used as the bulging portion 44.
[Example of application to active matrix substrate]
The case where the present invention is applied to an active matrix substrate for a liquid crystal display device will be described with reference to the drawings.
(Overall configuration of active matrix substrate)
FIG. 9A is a block diagram schematically illustrating a configuration of an active matrix substrate of a liquid crystal display device.

As shown in FIG. 9A, in an active matrix substrate for a liquid crystal display device, a data line 90 and a scan line made of a metal film such as aluminum, tantalum, molybdenum, titanium, or tungsten are formed on a transparent substrate made of glass or the like. A pixel region defined by 91 is formed, and a liquid crystal capacitor 94 (liquid crystal cell) to which an image signal is input via the pixel TFT 30 exists. For the data line 90, a data side drive circuit 82 (data driver unit) including a shift register 84, a level shifter 85, a video line 87, and an analog switch 86 is configured. For the scanning line 91, a scanning driver circuit 83 (scan driver unit) including a shift register 88 and a level shifter 89 is configured. Note that a storage capacitor 93 is formed between the pixel region and the preceding scanning line 91, and the storage capacitor 93 has a function of improving the charge holding characteristics of the liquid crystal capacitor 94.
(Basic configuration of CMOS circuit)
In the driving circuits on the data side and the scanning side, as shown in FIG. 9B, a CMOS circuit is constituted by the N-type TFT 10 and the P-type TFT 20. Such a CMOS circuit constitutes an inverter circuit with one stage or two or more stages.

  When the CMOS circuit is configured by the N-type TFT 10 and the P-type TFT 20 in this manner, if the TFTs according to the above-described first to fourth embodiments are used, even if a large current flows, local heat generation occurs. Because of this, high reliability can be obtained.

Further, when the TFTs of Embodiments 1 to 3 are used, each TFT has an offset gate structure, so that the channel length can be shortened by the higher withstand voltage, so that the influence of the parasitic capacitance is suppressed. be able to. In this case, it is preferable that the offset length of the N-type TFT 10 be longer than the offset length of the P-type TFT 20. With this configuration, even if the N-type TFT has a larger on-state current than the P-type TFT in the case of a TFT having the same structure, by adjusting the offset length, the on-state current of these TFTs can be reduced. You can balance.
(TFT on active matrix substrate)
Further, as shown in FIG. 9A, a pixel switching TFT 30 is formed in the pixel area defined by the data line 90 and the scanning line 91. The TFTs according to Embodiments 1 to 4 may be used.

  Among them, when the TFTs of Embodiments 1 to 3 are used, since each TFT has an offset gate structure, the off-leakage current is small, so that a decrease in contrast, display unevenness, flicker, and the like can be prevented, and display quality can be prevented. Can be improved. However, when the off-leak current is reduced for the N-type and P-type drive circuit TFTs 10 and 20 by using the same offset gate structure as that of the N-type pixel TFT 30, the on-current becomes too small, and the drive circuit The operating speed decreases or the required power supply voltage increases. Such a reduction in the operating speed of the driving circuit has a problem that high-quality display is hindered in a liquid crystal display device. Further, an increase in the required power supply voltage hinders a reduction in power consumption. Therefore, by optimizing the structure of the TFTs used for different applications on the same substrate, it is possible to reduce the off-leak current and secure a large on-current for the drive circuit TFT, and to achieve the off-leak current for the pixel TFT. From the viewpoint of reducing the number of pixels, the offset length of the TFT 30 used as the pixel switching element is configured to be longer than the offset length of the TFTs 10 and 20 forming the driving circuit. Conversely, the offset length of the TFTs 10 and 20 constituting the drive circuit is configured to be shorter than the offset length of the TFT 30 used as a pixel switching element.

  As described above, in the active matrix substrate with a built-in drive circuit of the liquid crystal display device, as shown in FIG. 10, approximately three types of TFTs 10, 20, and 30 are formed. In FIG. 10, an N-type driving circuit TFT 10, a P-type driving circuit TFT 20, and an N-type pixel TFT 30 are formed on the same insulating substrate 50 from the left region to the right region. The state is shown.

  It will be described that the number of steps does not increase even if the three types of TFTs 10, 20, and 30 are manufactured using the TFTs according to the first to third embodiments in the active matrix substrate having such a configuration. Here, all of the TFTs according to the first to third embodiments have been described using the offset gate structure as an example. However, the same applies to an LDD structure having a low-concentration source / drain region in a portion corresponding to the offset region 7. Therefore, here, the case where all the TFTs are formed in the LDD structure will be basically described, and the offset gate structure will be described in the description. When the three types of TFTs 10, 20, and 30 are formed by the TFT according to the fourth embodiment, a normal self-aligned TFT is manufactured except for changing a mask pattern when patterning a gate electrode. Since it is the same as the case, the description is omitted.

First, as shown in FIG. 11A, a silicon oxide film having a thickness of about 2000 to 5000 angstroms is formed on a glass substrate 50 by plasma CVD using TEOS (tetraethoxysilane), oxygen gas, or the like as a source gas. Is formed. Next, the temperature of the substrate 50 is set to 350 ° C., and a semiconductor film made of an amorphous silicon film having a thickness of about 300 to 700 Å is formed on the surface of the base protective film 51 by a plasma CVD method. Next, a crystallization step such as laser annealing or a solid phase growth method is performed on the semiconductor film made of the amorphous silicon film to crystallize the semiconductor film to a polysilicon film. In the laser annealing method, for example, a line beam of an excimer laser having a beam length of 400 mm is used, and its output intensity is, for example, 200 mJ / cm ² . The line beam is scanned such that a portion corresponding to 90% of the peak value of the laser intensity in the width direction overlaps in each region.

  Next, the polysilicon film is patterned into the island-shaped semiconductor films 11, 21, and 31. The surface of the island-shaped semiconductor films 11, 21, and 31 is formed by plasma CVD using TEOS (tetraethoxysilane), oxygen gas, or the like as a source gas. Gate insulating films 12, 22, and 32 made of a silicon oxide film of 600 to 1500 angstroms are formed (gate insulating film forming step).

  Next, after a conductive film containing aluminum, tantalum, molybdenum, titanium, tungsten, or the like is formed by a sputtering method, the conductive film is patterned to form gate electrodes 14, 24, and 34 of each TFT (gate electrode forming step). .

Next, as shown in FIG. 11B, the formation regions of the N-type driver circuit TFT 10 and the N-type pixel TFT 30 are covered with a resist mask 61. In this state, when boron ions are implanted at a dose of about 10 ¹³ cm ⁻² , the silicon thin film 21 is self-aligned with the gate electrode 24 in a low-concentration P-type region having an impurity concentration of about 10 ¹⁸ cm ^−3. 23 are formed. The portion where the impurity is not introduced becomes the channel region 25.

  If this low concentration impurity implantation step is not performed, the P-type drive circuit TFT 20 has an offset gate structure instead of an LDD structure.

Next, as shown in FIG. 11C, a formation region of the P-type driver circuit TFT 20 is covered with a resist mask 62. In this state, when phosphorus ions are implanted at a dose of about 10 ¹³ cm ⁻² , the silicon thin films 11 and 31 have a low impurity concentration of about 10 ¹⁸ cm ^{−3 in} a self-aligned manner with respect to the gate electrodes 14 and 34. N-type regions 13 and 33 are formed. Note that portions where the impurities are not introduced become the channel regions 15 and 35.

  If this low concentration impurity implantation step is not performed, the N-type driver circuit TFT 10 and the N-type pixel TFT 30 have an offset gate structure instead of an LDD structure.

Next, as shown in FIG. 11D, in addition to the formation regions of the N-type driver circuit TFT 10 and the N-type pixel TFT 30, a resist mask 63 that covers the gate electrode 24 is formed. Here, the resist mask 63 is formed in a pattern such that the high-concentration source / drain regions 8 described in the first to third embodiments are formed. In this state, boron ions are implanted into the low-concentration P-type region 23 at a dose of about 10 ¹⁵ cm ⁻² to form a high-concentration source / drain region 26 having an impurity concentration of about 10 ²⁰ cm ⁻³ . The portion of the low-concentration P-type region 23 covered with the resist mask 63 remains as an LDD region 27 (low-concentration source / drain region). Thus, the P-type drive circuit TFT 20 is formed.

Next, as shown in FIG. 11E, a resist mask 64 is formed to cover the gate electrodes 14 and 34 in addition to the region where the P-type driver circuit TFT 20 is to be formed.
Here, the resist mask 64 is also formed in a pattern such that the high-concentration source / drain regions 8 described in the first to third embodiments are formed. In this state, phosphorus ions are implanted into the low-concentration N-type regions 13 and 23 at a dose of about 10 ¹⁵ cm ⁻² to form the high-concentration source / drain regions 16 and 36 having an impurity concentration of about 10 ²⁰ cm ^−3. . Portions of the low-concentration N-type regions 13 and 23 covered with the resist mask 64 remain as LDD regions 17 and 37 (low-concentration source / drain regions) having an impurity concentration of about 10 ¹⁸ cm ^-3 . Thus, the N-type driver circuit TFT 10 and the N-type pixel TFT 30 are formed.

Thereafter, as shown in FIG. 10, after forming an interlayer insulating film 52, annealing for activation is performed, and after a contact hole is formed, the source / drain electrodes 41, 42, 43, 44, and 45 are formed. If formed, an active matrix substrate can be manufactured. Further, the source / drain regions having the LDD structure are formed by four mask forming steps for forming the resist masks 61, 62, 63, and 64 and four impurity introducing steps. That is, only by matching the patterns of the resist masks 63 and 64 with the shapes of the high-concentration source / drain regions 8 described in Embodiments 1 to 3, TFTs according to these embodiments can be manufactured, and the number of steps does not increase. .
[Other structures]
The technique of improving the periphery of the channel region and improving the reliability of the TFT according to the present invention can be applied to the following cases. For example, since the edges of the channel region and the source / drain regions in the channel width direction are contaminated at the time of patterning, there is a case where it is desired to reduce the current flowing through the edges and concentrate the current in the central portion in the channel width direction. . In this case, as shown in FIG. 12A, contrary to the first and second embodiments, the portion between the source / drain region 8 and the channel region 5 (the portion facing the end of the gate electrode 4) Alternatively, the offset region 7 having a structure in which the offset length of the central portion in the channel width direction is considerably shorter than the offset length of the edge portion may be formed. In this case, the cross section taken along the line BB 'passing through the center portion in the channel width direction in FIG. 12 appears as shown in FIGS. 1B and 1C, and the edge portion in the channel width direction in FIG. The cross section taken along the line AA ′ appears as shown in FIG.
In the case of such a configuration, in the channel region 5 and the offset region 7 of the source / drain region 8, the current flowing therethrough can be suppressed by the longer offset length at the edge portion in the channel width direction.

  As shown in FIG. 12B, the gate electrode 4 may have a constricted portion 49 at the center in the channel width direction, contrary to the fourth embodiment. Also in the case of such a configuration, the channel region 5 can suppress the current flowing therethrough to a small amount because the channel length at the edge portion in the channel width direction is long.

(A) and (B) are longitudinal sectional views of a TFT having an offset gate structure, and (C) is a longitudinal sectional view of a TFT having a self-aligned structure. FIG. 2 is a plan view of the TFT according to Embodiment 1 of the present invention. FIG. 6 is a plan view of a TFT according to a second preferred embodiment of the present invention. FIG. 7 is a plan view of a TFT according to a third preferred embodiment of the present invention. FIG. 13 is a plan view of a TFT according to a modification of the third embodiment of the present invention. FIG. 14 is a plan view of a TFT according to a fourth preferred embodiment of the present invention. FIG. 15 is a plan view of a TFT according to a modification of the fourth embodiment of the present invention. (A) and (B) are each a plan view of a TFT according to another modification of the fourth embodiment of the present invention. 1A is a block diagram schematically showing a configuration of an active matrix substrate of a liquid crystal display device, and FIG. 1B is a circuit diagram of a CMOS circuit. It is sectional drawing of three types of TFT comprised in the active matrix substrate shown to FIG. 9 (A) and (B). FIG. 11 is a process sectional view illustrating an example of a method for manufacturing the active matrix substrate illustrated in FIG. 10. It is a top view of TFT which applied the present invention. FIG. 9 is a plan view of a conventional self-aligned TFT. FIG. 9 is a plan view of a conventional TFT having an offset gate structure.

Explanation of reference numerals

2, 12, 22, 32 Gate insulating film 4, 14, 24, 34 Gate electrode 5, 15, 25, 35 Channel region 16, 26, 36 High concentration source / drain region 7 Offset region 8, Source / drain region 9 Contact Holes 10, 20, 30 TFT
17, 27, 37 LDD region or offset region 40 Wiring layer 50 Glass substrate 51 Underlayer protective film 52 Interlayer insulating film

Claims (5)

In a thin film transistor including a channel region opposed to a gate electrode through a gate insulating film, and a source / drain region connected to the channel region,
The thin film transistor according to claim 1, wherein the gate electrode includes a bulging portion that bulges in a central portion in a channel width direction while bending in a channel length direction. 2. A thin film transistor circuit comprising: a thin film transistor having the structure defined in claim 1; and a thin film transistor of the opposite conductivity type, and the thin film transistors of the opposite conductivity type are connected by wiring. A thin-film transistor circuit in which each of the thin-film transistors having the structure defined in claim 1 or 2 constitutes a thin-film transistor of the opposite conductivity type, and the thin-film transistors of the opposite conductivity type are connected by wiring.
2. The thin film transistor circuit according to claim 1, wherein the offset length of the n-type thin film transistor is longer than the offset length of the p-type thin film transistor. A liquid crystal display device comprising an active matrix substrate having a drive circuit constituted by a thin film transistor having the structure defined in claim 1. A pixel switching element and a driving circuit in a pixel region are configured using the thin film transistor having the structure defined in claim 1, and the offset length of the thin film transistor used as the pixel switching element is the offset of the thin film transistor configuring the driving circuit. A liquid crystal display device using an active matrix substrate configured to be longer than the length.

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