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JP2004140244A - Semiconductor element storage package and semiconductor device using the same - Google Patents

Semiconductor element storage package and semiconductor device using the same Download PDF

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Publication number
JP2004140244A
JP2004140244A JP2002304717A JP2002304717A JP2004140244A JP 2004140244 A JP2004140244 A JP 2004140244A JP 2002304717 A JP2002304717 A JP 2002304717A JP 2002304717 A JP2002304717 A JP 2002304717A JP 2004140244 A JP2004140244 A JP 2004140244A
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Prior art keywords
wiring conductor
semiconductor element
ghz
base
ground
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JP3878901B2 (en
Inventor
Tetsuo Hirakawa
平川 哲生
Yoshinobu Sawa
澤 義信
Shin Matsuda
松田 伸
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Kyocera Corp
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Kyocera Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

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  • Wire Bonding (AREA)

Abstract

【課題】高周波電気信号を伝送させた際、反射等を起こして伝送特性が大きく劣化する。
【解決手段】40GHz〜80GHzの電気信号を送受信する半導体素子6が搭載される搭載部1aを有する基体1と、該基体1の前記搭載部1aより下面にかけて導出されている複数個のグランド配線導体2bおよび第1配線導体2aと、前記基体1の下面に形成され、前記グランド配線導体2bおよび第1配線導体2aに電気的に接続している複数個のグランド用パッド3bおよび入出力用パッド3aと、前記基体1の搭載部1aより上面もしくは側面にかけて導出されている第2配線導体4と、導電性の線材5aと絶縁性の外囲体5bとから成り、線材5aが前記第2配線導体4に電気的に接続されているコネクター5とで形成され、前記第2配線導体4の外表面の凹凸が50μm以下である。
【選択図】図1
[PROBLEMS] When a high-frequency electric signal is transmitted, reflection or the like is caused, and transmission characteristics are largely deteriorated.
A base 1 having a mounting portion 1a on which a semiconductor element 6 for transmitting and receiving electric signals of 40 GHz to 80 GHz is mounted, and a plurality of ground wiring conductors extending from the mounting portion 1a of the base 1 to a lower surface thereof. 2b and a first wiring conductor 2a, and a plurality of ground pads 3b and input / output pads 3a formed on the lower surface of the base 1 and electrically connected to the ground wiring conductor 2b and the first wiring conductor 2a. And a second wiring conductor 4 extending from the mounting portion 1a of the base 1 to the upper surface or the side surface, and a conductive wire 5a and an insulating envelope 5b, and the wire 5a is formed of the second wiring conductor. The second wiring conductor 4 is formed of a connector 5 electrically connected to the second wiring conductor 4 and has irregularities on the outer surface of 50 μm or less.
[Selection diagram] Fig. 1

Description

【0001】
【発明の属する技術分野】
本発明は高周波の電気信号を送受信する半導体素子を収納する半導体素子収納用パッケージ、およびその半導体素子収納用パッケージを用いて成る半導体装置に関するものである。
【0002】
【従来の技術】
従来、電気信号を送受信する半導体素子を収容するための半導体素子収納用パッケージは、一般に、酸化アルミニウム質焼結体、ムライト質焼結体、ガラスセラミックス、窒化アルミニウム質焼結体等の電気絶縁材料から成り、上面に半導体素子の搭載部が形成された基体と、タングステン、モリブデン、マンガン、銅、銀等の金属材料から成り、基体の半導体素子搭載部から下面にかけて被着導出された複数の電気信号の入出力用およびグランド用の配線導体と、この配線導体と電気的に接続するようにして基体の下面に形成された複数個のグランド用パッドおよび入出力用パッドと、基体の搭載部より上面もしくは側面にかけて導出されている出入力用の配線導体と、導電性の線材と絶縁性の外囲体とから成り、線材の一端が出入力用配線導体に接続され、他端が外部に導出されているコネクターとにより構成されている。
【0003】
かかる半導体素子収納用パッケージは、その搭載部に電気信号を送受信する半導体素子がAu−Snろう材あるいは半田等の接合材を介して接着固定されるとともに、半導体素子の電極が入出力配線導体、グランド用配線導体および出入力配線導体にボンディングワイヤや接続用リボン、半田等の導電性接続材を介して接続され、その後、必要に応じて蓋体等で半導体素子を封止することによって半導体装置となる。
【0004】
また前記半導体装置は基体の下面に形成されているグランド用パッドおよび入出力用パッドを外部電気回路基板の回路導体に半田バンプ等を介し接続させることによって内部に収容する半導体素子が外部電気回路に接続され、同時にコネクターに同軸ケーブル等を介し外部の通信装置等の外部機器を接続させることによって半導体素子と外部機器とが接続するようになっている。
【0005】
なお、前記半導体装置に使用されている半導体素子は複数の電気信号を合成して一つの電気信号に変換する、或いは一つの電気信号を分離して複数の電気信号に変換する機能を有しており、第1配線導体を介して入力される複数の周波数帯域が低い電気信号は半導体素子で合成されて一つの周波数帯域が高い電気信号となり、この周波数帯域の高い電気信号は第2配線導体を介してコネクターに伝送されるとともにコネクターより外部の通信装置等の外部機器に伝送され、またコネクターを介して外部機器より伝送された周波数帯域の高い電気信号は半導体素子で複数の周波数帯域が低い電気信号に変換され、各々の周波数帯域の低い電気信号は第1配線導体を介して外部電気回路に伝送されることとなる。
【0006】
また前記第2配線導体はタングステン、モリブデン、マンガン等の金属粉末に有機溶剤、溶媒を添加混合して得た導電ペーストを従来周知のスクリーン印刷法等の厚膜形成技術を採用することによって所定パターンに印刷するとともにこれを所定温度で焼き付けることによって形成されている。
【0007】
更に前記コネクターは鉄−ニッケル−コバルト合金等の金属の線材の周囲をガラス等の絶縁性材料から成る外囲体で取り囲んだ構造を有しており、コネクターの線材と第2配線導体とは、通常、2mm(2000μm)以上の長さにわたって接続されている。
【0008】
【特許文献1】
特開2002−164466号公報
【0009】
【発明が解決しようとする課題】
しかしながら、この従来の半導体素子収納用パッケージおよび半導体装置においては、第2配線導体が導電ペーストをスクリーン印刷法等の厚膜形成技術を採用し、所定パターンに印刷することによって形成されており導電ペーストを所定パターンに印刷する際、にじみが発生し、第2配線導体の外表面、特に側面において深さが100μm以上の凹凸が多数形成されている。そのためこの第2配線導体に40GHz〜80GHzの高周波の電気信号を伝送させた場合、高周波の電気信号は第2配線導体の表面に形成されている凹凸で反射を起こし、伝送特性が大きく劣化してしまうという欠点を有していた。
【0010】
本発明は上記欠点に鑑み案出されたもので、その目的は、第2配線導体の外表面で高周波電気信号が反射するのを有効に防止し、伝送特性の優れた半導体素子収納用パッケージおよび半導体装置を提供することにある。
【0011】
【課題を解決するための手段】
本発明の半導体素子収納用パッケージは、40GHz〜80GHzの電気信号を送受信する半導体素子が搭載される搭載部を有する基体と、該基体の前記搭載部より下面にかけて導出されている複数個のグランド配線導体および第1配線導体と、前記基体の下面に形成され、前記グランド配線導体および第1配線導体に電気的に接続している複数個のグランド用パッドおよび入出力用パッドと、前記基体の搭載部より上面もしくは側面にかけて導出されている第2配線導体と、導電性の線材と絶縁性の外囲体とから成り、線材が前記第2配線導体に電気的に接続されているコネクターとで形成され、前記第2配線導体の外表面の凹凸が50μm以下であることを特徴とするものである。
【0012】
また本発明の半導体装置は、上記構成の半導体素子収納用パッケージと、40GHz〜80GHzの電気信号を送受信する半導体素子とから成り、前記パッケージの搭載部に半導体素子を搭載固定するとともに該半導体素子の各電極を第1配線導体および第2配線導体に電気的に接続したことを特徴とするものである。
【0013】
本発明の半導体素子収納用パッケージおよび半導体装置によれば、第2配線導体の外表面に形成される凹凸の深さを50μm以下としたことから第2配線導体に40GHz〜80GHzの高周波の電気信号を伝送させたとしてもその高周波の電気信号は第2配線導体の外表面に形成されている凹凸で反射を起こすことはほとんどなく、これによって伝送特性を優れたものとなすことができる。
【0014】
【発明の実施の形態】
次に、本発明を添付図面に基づき詳細に説明する。
【0015】
図1は本発明の半導体素子収納用パッケージの一実施例を示し、1は基体、2aは第1配線導体、2bはグランド配線導体、3aは入出力用パッド、3bはグランド用パッド、4は第2配線導体、5はコネクターである。これら基体1、第1配線導体2a、グランド配線導体2b、入出力用パッド3a、グランド用パッド3b、第2配線導体4およびコネクター5により半導体素子6を収納するための半導体素子収納用パッケージ7が基本的に構成される。
【0016】
前記基体1は酸化アルミニウム質焼結体、ムライト質焼結体、ガラスセラミックス、窒化アルミニウム質焼結体等の電気絶縁材料から成り、例えば、酸化アルミニウム質焼結体から成る場合、酸化アルミニウム、酸化ケイ素、酸化マグネシウム、酸化カルシウム等の原料粉末に適当な有機溶剤、溶媒、可塑剤、分散剤を添加混合して泥漿物を作り、この泥漿物を従来周知のドクターブレード法やカレンダーロール法等のシート形成法を採用しシート状に形成してセラミックグリーンシート(セラミック生シート)を得、しかる後、それらセラミックグリーンシートに適当な打ち抜き加工を施すとともにこれを必要に応じて複数枚積層し、約1600℃の高温で焼成することによって製作される。
【0017】
また前記基体1は、半導体素子の搭載部1aから下面にかけて複数個の第1配線導体2aおよびグランド用配線導体2bが形成されており、該各配線導体2a、2bは半導体素子の電気信号入出力用、接地用の各電極を、入出力用パッド3aやグランド用パッド3bに接続するための導電路として作用し、搭載部1a側の一端には半導体素子6の電気信号入出力用、接地用の各電極が導電性接続材を介して電気的に接続される。
【0018】
前記第1配線導体2aおよびグランド用配線導体2b、入出力用パッド3aおよびグランド用パッド3bは、銅、銀、金、パラジウム、タングステン、モリブデン、マンガン等の金属材料から成り、例えば銅から成る場合であれば、銅粉末に有機溶剤等を添加して成る金属ペーストを基体1となるセラミックグリーンシートの表面に所定パターンに印刷しておくことにより形成される。
【0019】
この第1配線導体2aおよびグランド用配線導体2bの基体1下面側の一端は、それぞれ対応する入出力用パッド3aおよびグランド用パッド3bと電気的に接続しており、これらの入出力用パッド3a、グランド用パッド3bを外部電気回路の所定の信号用や接地用等の回路導体に接続することにより、半導体素子6の電気信号入出力用、接地用の各電極が外部電気回路と電気的に接続される。
【0020】
また前記基体1は、半導体素子の搭載部1aから上面や側面等にかけて第2配線導体4が形成されており、該第2配線導体4は半導体素子6の電極をコネクター5の線材5aに接続するための導電路として作用し、搭載部1a側の一端には半導体素子6の電極が導電性接続材8を介して電気的に接続される。
【0021】
前記第2配線導体4は、上述の第1配線導体2a等と同様に、銅、銀、金、パラジウム、タングステン、モリブデン、マンガン等の金属材料から成り、例えば銅から成る場合であれば、銅粉末に有機溶剤等を添加して成る金属ペーストを基体1となるセラミックグリーンシートの表面に所定パターンに印刷しておくことにより形成される。
【0022】
この第2配線導体4の基体1外表面側の一端はコネクター5の線材5aと電気的に接続しており、このコネクター5を同軸ケーブル等を介して通信装置等の外部機器に接続することにより半導体素子6と外部機器との間で高周波信号の送受信が行われる。
【0023】
前記コネクター5は、半導体素子収納用パッケージ7の第2配線導体4を同軸ケーブル等を介して外部機器に接続するための接続体として作用し、例えば、鉄−ニッケル−コバルト合金等の金属の線材の周囲を、絶縁性の外囲体5bで取り囲んだ構造である。
【0024】
前記線材5aと外囲体5bとから成るコネクター5は、例えば、鉄−ニッケル−コバルト合金から成る線材5aを、鉄−ニッケル−コバルト合金等の金属から成る円筒状の容器の中央にセットし、容器内にホウ珪酸ガラス等のガラス粉末を充填した後、ガラス粉末を加熱溶融させて線材5aの周囲に被着させることによって製作される。
【0025】
かくして上述の半導体素子収納用パッケージによれば、基体1の搭載部1aに半導体素子6を搭載するとともにガラス、樹脂、ロウ材等の接着材を介して固定し、しかる後、半導体素子6の各電極を第1配線導体2aおよびグランド用配線導体2bに、例えば、ボンディングワイヤ8を介して接続し、最後に蓋体10を基体1の上面に封止材を介して接合させ、半導体素子6を気密に封入することによって半導体装置11となる。
【0026】
この半導体装置11は基体1下面の入出力用パッド3aおよびグランド用パッド3bが外部電気回路基板の所定の信号用や接地用等の回路導体に半田バンプ等の外部端子を介して接続され、これによって半導体素子6の信号用、接地用の各電極は外部電気回路と電気的に接続される。
【0027】
また、この半導体装置11に取着されているコネクター5の線材5aに同軸ケーブル等の外部接続用の導線を接続することにより、半導体素子6の電極が通信装置等の外部機器に接続される。
【0028】
そしてかかる半導体装置11は、外部電気回路から供給される複数の周波数帯域が低い(5〜10GHz)電気信号を第1配線導体2aを介して半導体素子6に入力させ、半導体素子6でこれら入力された電気信号を合成して、一つの周波数帯域が高い(40〜80GHz)電気信号とするとともにこれを第2配線導体4を介してコネクター5に出力し、該コネクター5の線材5aを介して外部の通信装置等の外部機器に伝送する、或いは、外部の通信装置等の外部機器から伝送された一つの周波数帯域が高い(40〜80GHz)電気信号をコネクター5の線材5a及び第2配線導体4を介して半導体素子6に入力し、半導体素子6で入力された周波数帯域が高い(40〜80GHz)電気信号を複数の周波数帯域が低い(5〜10GHz)電気信号に変換するとともにこれらの個々の周波数帯域が低い電気信号を第1配線導体2aを介して外部電気回路に供給することとなる。
【0029】
本発明の半導体素子収納用パッケージおよびこれを用いた半導体装置においては、第2配線導体4の外表面に形成されている凹凸の深さを50μm以下としておくことが重要である。
【0030】
前記第2配線導体4の外表面に形成されている凹凸の深さを50μm以下とすると第2配線導体4に40GHz〜80GHzの高周波の電気信号を伝送させた際、高周波の電気信号は第2配線導体4の外表面に形成されている凹凸で反射することはほとんどなく、その結果、第2配線導体4での伝送特性が極めて優れたものとなる。
【0031】
前記第2配線導体4はその外表面に形成されている凹凸の深さが50μmを超えると第2配線導体4に40GHz〜80GHzの高周波の電気信号を伝送させた場合、高周波の電気信号は第2配線導体4の表面に形成されている凹凸で反射を起こし、伝送特性が大きく劣化してしまう。従って、前記第2配線導体4はその外表面に形成されている凹凸の深さを50μm以下にしておく必要がある。
【0032】
前記第2配線導体4の外表面に形成されている凹凸を50μm以下の大きさとするには、例えば、第2配線導体4の外表面にブラスト処理や化学エッチング処理を施すことによって行なわれ、ブラスト処理で第2配線導体4の外表面の凹凸を50μm以下とする場合には、第2配線導体4以外の領域を予めエポキシ樹脂等の有機樹脂でコーティングし、しかる後、第2配線導体4の表面に液体と研磨粒子を混合した混合物を空気圧で吹き付けて対象物の表面を平滑にすることによって行われる。
【0033】
なお、前記液体としては水が使用され、前記研磨剤粒子としてはアルミナ、窒化珪素、ガラス等の無機物粒子が使用される。
【0034】
また前記第2配線導体4が銅の場合、水と平均粒径が5μm乃至50μmのアルミナ粒子を混合したものを0.05MPa乃至0.3MPaの圧力で、0.05秒乃至0.3秒の時間吹き付けることによって好適に行なわれる。
【0035】
前記研磨剤粒子はその平均粒径が5μm未満となると第2配線導体4の外表面を平滑にする効果がなくなり、また50μmを超えると第2配線導体4の外表面の凹凸を50μm以下の小さな凹凸とすることができなくなることから前記研磨剤粒子は5μm乃至50μmの範囲とすると良い。
【0036】
更に、液体と研磨剤粒子を混合した混合物を吹き付ける空気圧は0.05MPa未満となると第2配線導体4の外表面を平滑にする研磨効果がなくなり、また0.3MPaを超えると第2配線導体4の外表面を研磨しすぎて平滑にする効果がなくなることから前記空気圧は0.05MPa乃至0.3MPaの範囲とすると良い。
【0037】
更に液体と研磨剤粒子とを混合した混合物を空気圧で吹き付ける吹き付け時間は0.05秒未満であると第2配線導体4の外表面を平滑にする研磨効果がなくなり、また0.3秒を超えると第2配線導体4の外表面を研磨しすぎて平滑にする効果がなくなることから前記吹き付け時間は0.05秒乃至0.3秒の範囲とすると良い。
【0038】
また更に、化学エッチング処理を施すことによって第2配線導体4の外表面の凹凸を50μm以下とする場合には、第2配線導体4以外の領域を予めエポキシ樹脂等の有機樹脂でコーティングした後、第2配線導体4の外表面を化学エッチングすることによって行なわれる。
【0039】
前記第2配線導体4が銅の場合、1.2mol/l乃至1.8mol/lの濃度で、温度30℃乃至50℃の塩化第二鉄溶液を0.05MPa乃至0.2MPaの圧力で吹き付け、第2配線導体4の外表面を化学エッチングすることによって行なわれる。
【0040】
前記塩化第二鉄溶液はその濃度が1.2mol/l未満となると第2配線導体4の外表面を平滑にする効果がなくなり、また1.8mol/lを超えるとエッチング速度が大きくなり第2配線導体4の外表面の凹凸を50μm以下の小さな凹凸とすることができなくなることから前記塩化第二鉄の濃度は1.2mol/l乃至1.8mol/lの範囲とすると良い。
【0041】
また前記塩化第二鉄の温度は30℃未満となると第2配線導体4の外表面を平滑にするエッチング効果がなくなり、また50℃を超えるとエッチング速度が大きくなり第2配線導体4の外表面の凹凸を50μm以下の小さな凹凸とすることができなくなることから前記温度は30℃乃至50℃の範囲とすると良い。
【0042】
更に前記塩化第二鉄の吹き付け圧力は0.05MPa未満となると第2配線導体4の外表面を平滑にするエッチング効果がなくなり、また0.2MPaを超えると第2配線導体4の外表面のエッチングが激しくなりすぎて第2配線導体4の外表面の凹凸を50μm以下の小さな凹凸とすることができなくなることから前記圧力は0.05MPa乃至0.2MPaの範囲とすると良い。
【0043】
なお、本発明は上述の実施例に限定されるものではなく、本発明の要旨を逸脱しない範囲であれば種々の変更は可能である。
【0044】
【発明の効果】
本発明の半導体素子収納用パッケージおよび半導体装置によれば、第2配線導体の外表面に形成される凹凸の深さを50μm以下としたことから第2配線導体に40GHz〜80GHzの高周波の電気信号を伝送させたとしてもその高周波の電気信号は第2配線導体の外表面に形成されている凹凸で反射を起こすことはほとんどなく、これによって伝送特性を優れたものとなすことができる。
【図面の簡単な説明】
【図1】本発明の半導体素子収納用パッケージおよびこの半導体素子収納用パッケージを用いた半導体装置の一実施例を示す断面図である。
【符号の説明】
1・・・・・基体
1a・・・・搭載部
2a・・・・第1配線導体
2b・・・・グランド配線導体
3a・・・・入出力用パッド
3b・・・・グランド用パッド
4・・・・・第2配線導体
5・・・・・コネクター
5a・・・・線材
5b・・・・外囲体
6・・・・・半導体素子
7・・・・・半導体素子収納用パッケージ
8・・・・・ボンディングワイヤ
10・・・・蓋体
11・・・・半導体装置
[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor element housing package for housing a semiconductor element for transmitting and receiving high-frequency electrical signals, and a semiconductor device using the semiconductor element housing package.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, semiconductor element housing packages for housing semiconductor elements for transmitting and receiving electric signals generally include electrically insulating materials such as aluminum oxide sintered bodies, mullite sintered bodies, glass ceramics, and aluminum nitride sintered bodies. And a plurality of electrical conductors made of a metal material such as tungsten, molybdenum, manganese, copper, silver, etc., which are attached and derived from the semiconductor element mounting portion of the base to the lower surface. A wiring conductor for signal input / output and ground; a plurality of ground pads and input / output pads formed on the lower surface of the base so as to be electrically connected to the wiring conductor; It consists of an input / output wiring conductor led out to the top or side, a conductive wire and an insulating envelope, and one end of the wire is used for input / output. Is connected to the conductor, the other end is constituted by a connector that is led to the outside.
[0003]
In such a package for housing a semiconductor element, a semiconductor element for transmitting and receiving an electric signal is bonded and fixed to a mounting portion thereof via a bonding material such as an Au-Sn brazing material or solder, and electrodes of the semiconductor element are connected to an input / output wiring conductor, The semiconductor device is connected to the ground wiring conductor and the input / output wiring conductor via a bonding wire, a connection ribbon, a conductive connecting material such as solder, and then, if necessary, sealing the semiconductor element with a lid or the like. It becomes.
[0004]
Further, the semiconductor device accommodated inside the semiconductor device by connecting the ground pad and the input / output pad formed on the lower surface of the base to the circuit conductor of the external electric circuit board via a solder bump or the like, so that the semiconductor element accommodated therein is connected to the external electric circuit. The semiconductor device and the external device are connected by connecting the external device such as an external communication device to the connector via a coaxial cable or the like at the same time.
[0005]
The semiconductor element used in the semiconductor device has a function of synthesizing a plurality of electric signals and converting it into one electric signal, or separating one electric signal and converting it into a plurality of electric signals. An electric signal having a plurality of low frequency bands input through the first wiring conductor is synthesized by the semiconductor element to become an electric signal having one frequency band, and the electric signal having a high frequency band is transmitted through the second wiring conductor. The high frequency band electric signal transmitted to the external device such as a communication device outside from the connector through the connector through the connector, and transmitted from the external device through the connector is a semiconductor device having a plurality of low frequency band electric signals. The electric signal converted into a signal and having a low frequency band is transmitted to an external electric circuit via the first wiring conductor.
[0006]
The second wiring conductor has a predetermined pattern by adopting a conventionally known thick film forming technique such as a screen printing method using a conductive paste obtained by adding an organic solvent and a solvent to a metal powder such as tungsten, molybdenum, and manganese. And printed at a predetermined temperature.
[0007]
Further, the connector has a structure in which a metal wire such as an iron-nickel-cobalt alloy is surrounded by an enclosure made of an insulating material such as glass, and the wire of the connector and the second wiring conductor are: Usually, they are connected over a length of 2 mm (2000 μm) or more.
[0008]
[Patent Document 1]
JP, 2002-164466, A
[Problems to be solved by the invention]
However, in this conventional semiconductor element housing package and semiconductor device, the second wiring conductor is formed by printing a conductive paste in a predetermined pattern by employing a thick film forming technique such as a screen printing method. When a predetermined pattern is printed, bleeding occurs, and many irregularities having a depth of 100 μm or more are formed on the outer surface, particularly the side surface, of the second wiring conductor. Therefore, when a high-frequency electric signal of 40 GHz to 80 GHz is transmitted to the second wiring conductor, the high-frequency electric signal is reflected by irregularities formed on the surface of the second wiring conductor, and transmission characteristics are greatly deteriorated. Had the disadvantage that
[0010]
The present invention has been devised in view of the above-described disadvantages, and has as its object to effectively prevent a high-frequency electric signal from being reflected on the outer surface of a second wiring conductor, and to provide a semiconductor element housing package having excellent transmission characteristics. A semiconductor device is provided.
[0011]
[Means for Solving the Problems]
A semiconductor device housing package according to the present invention includes a base having a mounting portion on which a semiconductor element that transmits and receives an electric signal of 40 GHz to 80 GHz is mounted, and a plurality of ground wirings extending from the mounting portion to a lower surface of the base. A conductor and a first wiring conductor, a plurality of ground pads and input / output pads formed on the lower surface of the base and electrically connected to the ground wiring conductor and the first wiring conductor; and mounting the base. A second wiring conductor extending from the portion to the upper surface or side surface, and a connector comprising a conductive wire and an insulating envelope, wherein the wire is electrically connected to the second wiring conductor. The outer surface of the second wiring conductor has an irregularity of 50 μm or less.
[0012]
Further, a semiconductor device of the present invention comprises a semiconductor element storage package having the above configuration, and a semiconductor element for transmitting and receiving an electric signal of 40 GHz to 80 GHz. The semiconductor element is mounted and fixed on a mounting portion of the package, and Each electrode is electrically connected to a first wiring conductor and a second wiring conductor.
[0013]
According to the semiconductor element housing package and the semiconductor device of the present invention, since the depth of the unevenness formed on the outer surface of the second wiring conductor is set to 50 μm or less, a high-frequency electric signal of 40 GHz to 80 GHz is applied to the second wiring conductor. Is transmitted, the high-frequency electric signal hardly causes reflection on the irregularities formed on the outer surface of the second wiring conductor, whereby the transmission characteristics can be improved.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, the present invention will be described in detail with reference to the accompanying drawings.
[0015]
FIG. 1 shows an embodiment of a package for housing a semiconductor element according to the present invention, wherein 1 is a base, 2a is a first wiring conductor, 2b is a ground wiring conductor, 3a is an input / output pad, 3b is a ground pad, and 4 is The second wiring conductor 5 is a connector. A semiconductor element housing package 7 for housing the semiconductor element 6 by the base 1, the first wiring conductor 2a, the ground wiring conductor 2b, the input / output pad 3a, the ground pad 3b, the second wiring conductor 4 and the connector 5 is provided. Basically configured.
[0016]
The base 1 is made of an electrically insulating material such as an aluminum oxide sintered body, a mullite sintered body, a glass ceramic, an aluminum nitride sintered body. A suitable organic solvent, solvent, plasticizer, and dispersant are added to and mixed with raw material powders such as silicon, magnesium oxide, and calcium oxide to form a slurry, and the slurry is formed by a conventionally known doctor blade method, calender roll method, or the like. A ceramic green sheet (ceramic green sheet) is obtained by forming a sheet by adopting a sheet forming method. Thereafter, the ceramic green sheet is subjected to an appropriate punching process, and a plurality of the green sheets are laminated as necessary. It is manufactured by firing at a high temperature of 1600 ° C.
[0017]
The base 1 is formed with a plurality of first wiring conductors 2a and ground wiring conductors 2b from the mounting portion 1a of the semiconductor element to the lower surface, and each of the wiring conductors 2a and 2b is connected to an electric signal input / output of the semiconductor element. Of the semiconductor element 6 at one end on the side of the mounting portion 1a, and serves as a conductive path for connecting each electrode for grounding and grounding to the input / output pad 3a and the grounding pad 3b. Are electrically connected via a conductive connecting material.
[0018]
The first wiring conductor 2a and the ground wiring conductor 2b, the input / output pad 3a and the ground pad 3b are made of a metal material such as copper, silver, gold, palladium, tungsten, molybdenum, or manganese. In this case, the metal paste is formed by printing a metal paste formed by adding an organic solvent or the like to copper powder on a surface of a ceramic green sheet serving as the substrate 1 in a predetermined pattern.
[0019]
One ends of the first wiring conductor 2a and the ground wiring conductor 2b on the lower surface side of the base 1 are electrically connected to corresponding input / output pads 3a and ground pads 3b, respectively. By connecting the ground pad 3b to a predetermined signal conductor or a circuit conductor for grounding of the external electric circuit, the electric signal input / output and ground electrodes of the semiconductor element 6 are electrically connected to the external electric circuit. Connected.
[0020]
The base 1 has a second wiring conductor 4 formed from the mounting portion 1a of the semiconductor element to the upper surface, the side surface, and the like. The second wiring conductor 4 connects the electrode of the semiconductor element 6 to the wire 5a of the connector 5. And an electrode of the semiconductor element 6 is electrically connected to one end of the mounting portion 1a via a conductive connecting material 8.
[0021]
The second wiring conductor 4 is made of a metal material such as copper, silver, gold, palladium, tungsten, molybdenum, or manganese, like the first wiring conductor 2a described above. It is formed by printing a metal paste obtained by adding an organic solvent or the like to the powder in a predetermined pattern on the surface of the ceramic green sheet serving as the base 1.
[0022]
One end of the second wiring conductor 4 on the outer surface side of the base 1 is electrically connected to a wire 5a of a connector 5, and the connector 5 is connected to an external device such as a communication device via a coaxial cable or the like. Transmission and reception of high-frequency signals are performed between the semiconductor element 6 and an external device.
[0023]
The connector 5 functions as a connector for connecting the second wiring conductor 4 of the semiconductor element housing package 7 to an external device via a coaxial cable or the like, and is, for example, a metal wire such as an iron-nickel-cobalt alloy. Is surrounded by an insulating outer body 5b.
[0024]
For the connector 5 composed of the wire 5a and the outer body 5b, for example, a wire 5a made of an iron-nickel-cobalt alloy is set at the center of a cylindrical container made of a metal such as an iron-nickel-cobalt alloy, After the glass powder such as borosilicate glass is filled in the container, the glass powder is heated and melted and adhered around the wire 5a.
[0025]
Thus, according to the above-described semiconductor element storage package, the semiconductor element 6 is mounted on the mounting portion 1a of the base 1 and fixed via an adhesive such as glass, resin, brazing material, and the like. The electrodes are connected to the first wiring conductor 2a and the ground wiring conductor 2b via, for example, bonding wires 8, and finally the lid 10 is joined to the upper surface of the base 1 via a sealing material, and the semiconductor element 6 is connected. The semiconductor device 11 is obtained by hermetically sealing.
[0026]
In the semiconductor device 11, input / output pads 3a and ground pads 3b on the lower surface of the base 1 are connected to predetermined signal and ground circuit conductors of an external electric circuit board via external terminals such as solder bumps. Accordingly, the signal and ground electrodes of the semiconductor element 6 are electrically connected to an external electric circuit.
[0027]
In addition, by connecting a conductor for external connection such as a coaxial cable to the wire 5a of the connector 5 attached to the semiconductor device 11, the electrode of the semiconductor element 6 is connected to an external device such as a communication device.
[0028]
The semiconductor device 11 causes a plurality of low-frequency band (5 to 10 GHz) electric signals supplied from an external electric circuit to be input to the semiconductor element 6 via the first wiring conductor 2a, and the semiconductor element 6 inputs these electric signals. The electric signals are combined into one electric signal having a high frequency band (40 to 80 GHz), and the electric signal is output to the connector 5 via the second wiring conductor 4 and externally connected via the wire 5a of the connector 5. Or a single high frequency band (40 to 80 GHz) electric signal transmitted from an external device such as an external communication device or the like to the external device such as a communication device. To the semiconductor element 6 via the semiconductor element 6, and the electric signal having a high frequency band (40 to 80 GHz) input by the semiconductor element 6 is converted into a plurality of low frequency bands (5 to 10 GHz). The supplying to the external electrical circuit through the first wiring conductor 2a of these individual frequency band lower electrical signals and converts into an electrical signal.
[0029]
In the semiconductor element housing package of the present invention and the semiconductor device using the same, it is important that the depth of the unevenness formed on the outer surface of the second wiring conductor 4 be 50 μm or less.
[0030]
When the depth of the unevenness formed on the outer surface of the second wiring conductor 4 is set to 50 μm or less, when the high-frequency electric signal of 40 GHz to 80 GHz is transmitted to the second wiring conductor 4, the high-frequency electric signal becomes the second electric signal. The light is hardly reflected by the irregularities formed on the outer surface of the wiring conductor 4, and as a result, the transmission characteristics of the second wiring conductor 4 are extremely excellent.
[0031]
When the depth of the unevenness formed on the outer surface of the second wiring conductor 4 exceeds 50 μm, when the high-frequency electric signal of 40 GHz to 80 GHz is transmitted to the second wiring conductor 4, the high-frequency electric signal is Reflection is caused by irregularities formed on the surface of the two-wiring conductor 4, and transmission characteristics are greatly deteriorated. Therefore, it is necessary that the depth of the irregularities formed on the outer surface of the second wiring conductor 4 be 50 μm or less.
[0032]
The irregularities formed on the outer surface of the second wiring conductor 4 can be reduced to a size of 50 μm or less, for example, by performing blasting or chemical etching on the outer surface of the second wiring conductor 4. In the case where the irregularities on the outer surface of the second wiring conductor 4 are reduced to 50 μm or less by the treatment, a region other than the second wiring conductor 4 is coated with an organic resin such as epoxy resin in advance, and then the second wiring conductor 4 is This is performed by spraying a mixture of a liquid and abrasive particles on the surface by air pressure to smooth the surface of the object.
[0033]
Note that water is used as the liquid, and inorganic particles such as alumina, silicon nitride, and glass are used as the abrasive particles.
[0034]
When the second wiring conductor 4 is made of copper, a mixture of water and alumina particles having an average particle diameter of 5 μm to 50 μm is applied at a pressure of 0.05 MPa to 0.3 MPa for 0.05 seconds to 0.3 seconds. It is suitably performed by spraying for a time.
[0035]
When the average particle diameter of the abrasive particles is less than 5 μm, the effect of smoothing the outer surface of the second wiring conductor 4 is lost, and when the average particle diameter exceeds 50 μm, the unevenness of the outer surface of the second wiring conductor 4 is reduced to 50 μm or less. It is preferable that the abrasive particles be in the range of 5 μm to 50 μm because unevenness cannot be obtained.
[0036]
Further, if the air pressure for spraying the mixture of the liquid and the abrasive particles is less than 0.05 MPa, the polishing effect to smooth the outer surface of the second wiring conductor 4 is lost, and if it exceeds 0.3 MPa, the second wiring conductor 4 The air pressure is preferably in the range of 0.05 MPa to 0.3 MPa, since the outer surface of the metal is not polished excessively and the smoothing effect is lost.
[0037]
Further, if the time for spraying the mixture of the liquid and the abrasive particles with air pressure is less than 0.05 seconds, the polishing effect for smoothing the outer surface of the second wiring conductor 4 is lost, and the time exceeds 0.3 seconds. Since the outer surface of the second wiring conductor 4 is excessively polished and the smoothing effect is lost, the spraying time is preferably set in the range of 0.05 to 0.3 seconds.
[0038]
Further, when the irregularities on the outer surface of the second wiring conductor 4 are reduced to 50 μm or less by performing a chemical etching process, a region other than the second wiring conductor 4 is coated with an organic resin such as an epoxy resin in advance, This is performed by chemically etching the outer surface of the second wiring conductor 4.
[0039]
When the second wiring conductor 4 is made of copper, a ferric chloride solution having a concentration of 1.2 mol / l to 1.8 mol / l and a temperature of 30 ° C. to 50 ° C. is sprayed at a pressure of 0.05 MPa to 0.2 MPa. Is performed by chemically etching the outer surface of the second wiring conductor 4.
[0040]
When the concentration of the ferric chloride solution is less than 1.2 mol / l, the effect of smoothing the outer surface of the second wiring conductor 4 is lost, and when the concentration exceeds 1.8 mol / l, the etching rate increases, and Since the irregularities on the outer surface of the wiring conductor 4 cannot be reduced to small irregularities of 50 μm or less, the concentration of the ferric chloride is preferably in the range of 1.2 mol / l to 1.8 mol / l.
[0041]
When the temperature of the ferric chloride is lower than 30 ° C., the etching effect for smoothing the outer surface of the second wiring conductor 4 is lost, and when the temperature exceeds 50 ° C., the etching rate is increased and the outer surface of the second wiring conductor 4 is increased. The temperature is preferably in the range of 30 ° C. to 50 ° C., since the unevenness cannot be reduced to 50 μm or less.
[0042]
Further, when the spray pressure of the ferric chloride is less than 0.05 MPa, the etching effect for smoothing the outer surface of the second wiring conductor 4 is lost, and when it exceeds 0.2 MPa, the etching of the outer surface of the second wiring conductor 4 is performed. The pressure is preferably in the range of 0.05 MPa to 0.2 MPa since the roughness becomes so intense that the unevenness on the outer surface of the second wiring conductor 4 cannot be reduced to a small unevenness of 50 μm or less.
[0043]
The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the present invention.
[0044]
【The invention's effect】
According to the semiconductor element housing package and the semiconductor device of the present invention, since the depth of the unevenness formed on the outer surface of the second wiring conductor is set to 50 μm or less, a high-frequency electric signal of 40 GHz to 80 GHz is applied to the second wiring conductor. Is transmitted, the high-frequency electric signal hardly causes reflection on the irregularities formed on the outer surface of the second wiring conductor, whereby the transmission characteristics can be improved.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing one embodiment of a package for housing a semiconductor element of the present invention and a semiconductor device using the package for housing a semiconductor element.
[Explanation of symbols]
1 Base 1a Mounting part 2a First wiring conductor 2b Ground wiring conductor 3a Input / output pad 3b Ground pad 4 ································································································································································· ..... Bonding wire 10 ... Lid 11 ... Semiconductor device

Claims (2)

40GHz〜80GHzの電気信号を送受信する半導体素子が搭載される搭載部を有する基体と、該基体の前記搭載部より下面にかけて導出されている複数個のグランド配線導体および第1配線導体と、前記基体の下面に形成され、前記グランド配線導体および第1配線導体に電気的に接続している複数個のグランド用パッドおよび入出力用パッドと、前記基体の搭載部より上面もしくは側面にかけて導出されている第2配線導体と、導電性の線材と絶縁性の外囲体とから成り、線材が前記第2配線導体に電気的に接続されているコネクターとで形成され、前記第2配線導体の外表面の凹凸が50μm以下であることを特徴とする半導体素子収納用パッケージ。A base having a mounting portion on which a semiconductor element for transmitting and receiving electric signals of 40 GHz to 80 GHz is mounted, a plurality of ground wiring conductors and first wiring conductors extending from the mounting portion of the base to a lower surface; And a plurality of ground pads and input / output pads electrically connected to the ground wiring conductor and the first wiring conductor, and are led out from the mounting portion of the base to the upper surface or the side surface. An outer surface of the second wiring conductor, the second wiring conductor being formed by a connector comprising a second wiring conductor, a conductive wire and an insulating envelope, wherein the wire is electrically connected to the second wiring conductor; A semiconductor device housing package, wherein the unevenness of the semiconductor device is 50 μm or less. 請求項1に記載の半導体素子収納用パッケージと40GHz〜80GHzの電気信号を送受信する半導体素子とから成り、前記パッケージの搭載部に半導体素子を搭載固定するとともに該半導体素子の各電極を第1配線導体および第2配線導体に電気的に接続したことを特徴とする半導体装置。2. A semiconductor element storage package according to claim 1, comprising: a semiconductor element for transmitting and receiving an electric signal of 40 GHz to 80 GHz. A semiconductor device electrically connected to a conductor and a second wiring conductor.
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Cited By (1)

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Publication number Priority date Publication date Assignee Title
JP2009231796A (en) * 2008-02-26 2009-10-08 Kyocera Corp Package and electronic apparatus

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JPS60248344A (en) * 1984-05-25 1985-12-09 松下電工株式会社 Metallic foil lined laminated board for high frequency
JPH0555746A (en) * 1991-08-29 1993-03-05 Hitachi Chem Co Ltd High frequency copper clad laminated board and printed circuit board
JP2002016165A (en) * 2000-06-29 2002-01-18 Kyocera Corp Device storage package
JP2002164466A (en) * 2000-11-27 2002-06-07 Kyocera Corp Package for storing semiconductor elements

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Publication number Priority date Publication date Assignee Title
JPS60248344A (en) * 1984-05-25 1985-12-09 松下電工株式会社 Metallic foil lined laminated board for high frequency
JPH0555746A (en) * 1991-08-29 1993-03-05 Hitachi Chem Co Ltd High frequency copper clad laminated board and printed circuit board
JP2002016165A (en) * 2000-06-29 2002-01-18 Kyocera Corp Device storage package
JP2002164466A (en) * 2000-11-27 2002-06-07 Kyocera Corp Package for storing semiconductor elements

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009231796A (en) * 2008-02-26 2009-10-08 Kyocera Corp Package and electronic apparatus

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