JP2004129419A - Operation method of inrush current prevention circuit and inrush current prevention circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To control rush current to a specified value and to reduce the resistance value of an FET to a required value within a short time. <P>SOLUTION: A method of operating a rush current preventing circuit includes the steps of inserting the FET, in series with a load having capacitive characteristics, changing a gate voltage of the transistor by a time constant change voltage by a time constant circuit, and preventing the rush current, by gradually changing conducting current of the transistor by the change of the gate voltage of the transistor. In this method, the starting voltage of the time constant change voltage of the time constant circuit is substantially brought into agreement with a highest gate voltage which will not energize the FET. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an inrush current prevention circuit operating method and an inrush current prevention circuit, and more particularly to an inrush current prevention circuit operation method and an inrush current prevention circuit for preventing an inrush current in a power supply device such as a switching power supply. .
[0002]
[Prior art]
2. Description of the Related Art Conventionally, various inrush current prevention circuits have been known as circuits for preventing an inrush current in a power supply device such as a switching power supply (for example, see Patent Document 1).
[0003]
[Patent Document 1]
FIG. 6 is an explanatory diagram of a circuit configuration of such a conventional inrush current prevention circuit.
[0004]
The circuit configuration shown in FIG. 6 includes a DC power supply 100, a switch (SW) 102, a capacitive load 104 as a load having a capacitive characteristic, and an inrush current prevention circuit 106.
[0005]
Here, in showing the capacitive load 104, the capacitive component and the load component are separated, and only the capacitive component (C) 104a is shown in parallel outside the load component (LOAD) 104b.
[0006]
The inrush current prevention circuit 106 is an N-type MOS-FET (hereinafter simply referred to as an “FET”) connected in series to the input line of the power supply and the capacitive load 104. The “FET” is a “Field Effect Transistor”. (Q1) 106a, a capacitor (C1) 106b that controls the gate voltage of the FET 106a by a charging voltage, and a resistor (R1) 106c that forms a CR time constant circuit with the capacitor 106b. And a resistor (R2) 106d that is a discharge resistor.
[0007]
Here, assuming that the inrush current prevention circuit 106 is not provided in the circuit configuration shown in FIG. 6, an inrush current flows through the low resistance of the voltage source due to the presence of the capacitive component 104a of the capacitive load 104. .
[0008]
However, if the inrush current prevention circuit 106 is provided as shown in FIG. 6, immediately after the switch 102 is turned on, no current flows since the FET 106a has a high resistance, but the capacitor 106b and the resistor 106c , The gate voltage of the FET 106a changes and gradually increases, and the resistance of the FET 106a gradually decreases. As a result, the conduction current of the FET 106a changes and gradually increases, and the power supply voltage is gradually applied to the capacitive load 104, thereby preventing an inrush current when the power is turned on.
[0009]
Note that the resistor 106d is a resistor for determining a gate voltage finally applied to the gate of the FET 106a by a voltage division with the resistor 106c.
[0010]
However, in the conventional circuit configuration of the inrush current prevention circuit as described above, the drain-source current of the FET greatly changes in a very small region where the gate voltage of the FET changes.
[0011]
For this reason, there is a problem that the inrush current cannot be reduced to a specified value or less unless the time constant of the CR time constant circuit constituted by the capacitor and the resistor, which is a time constant circuit, is not sufficiently large.
[0012]
On the other hand, if the time constant of the CR time constant circuit composed of a capacitor and a resistor, which is a time constant circuit, is sufficiently increased to solve such a problem, it takes time for the resistance value of the FET to drop to a required value. This has led to a new problem of being too expensive.
[0013]
[Problems to be solved by the invention]
The present invention has been made in view of the above-mentioned various problems of the related art, and an object of the present invention is to reduce the inrush current to a specified value and to reduce the inrush current in a short time. An object of the present invention is to provide an operation method of an inrush current prevention circuit and an inrush current prevention circuit that enable the resistance value of an FET to be reduced to a required value.
[0014]
In other words, an object of the present invention is to improve the conventional inrush current prevention circuit and its operation method to shorten the convergence time of the inrush current prevention circuit.
[0015]
[Means for Solving the Problems]
In order to achieve the above object, an operation method of an inrush current prevention circuit according to the present invention and an inrush current prevention circuit are provided in a conventional inrush current prevention circuit. In view of the fact that the FET is not in the conductive state, the change of the time constant changing voltage while the FET is not in the conductive state is skipped (skipped), and the time constant changing voltage is changed with the maximum voltage at which the FET does not conduct as the initial value. It was made.
[0016]
Further, the operation method of the inrush current prevention circuit and the inrush current prevention circuit according to the present invention are designed to prevent the time constant change voltage from changing at the final stage of the change of the time constant change voltage by the time constant circuit. The final voltage of the time constant change voltage by the time constant circuit is set to be higher than the final voltage applied to the gate of the FET, and the voltage actually applied to the gate of the FET is the final voltage applied to the gate of the FET. It is made to limit by the Zener diode so that it becomes.
[0017]
Further, the operation method of the inrush current prevention circuit and the inrush current prevention circuit according to the present invention suppress the gate voltage change speed in a range where the drain-source current greatly changes due to a slight gate voltage change of the FET. In addition, a negative feedback is applied.
[0018]
That is, according to the invention of claim 1 of the present invention, an FET is inserted in series with a load having a capacitive characteristic, and the gate voltage of the FET is changed by a time constant changing voltage by a time constant circuit. In the operation method of the inrush current prevention circuit for preventing the inrush current by gradually changing the conduction current of the FET by the change of the gate voltage of the FET, the FET does not conduct the start voltage of the time constant change voltage of the time constant circuit. This is made to substantially match the maximum gate voltage.
[0019]
The invention according to claim 2 of the present invention is characterized in that an FET is inserted in series with a load having a capacitive characteristic, and a gate voltage of the FET is changed by a time constant change voltage by a time constant circuit. In the inrush current prevention circuit for preventing the inrush current by gradually changing the conduction current of the FET due to the change of the gate voltage, the resistor has a resistor inserted in series with the time constant circuit, according to the resistance value of the resistor The gate voltage of the FET is changed by a time constant change voltage having a non-zero constant value as a start voltage.
[0020]
According to a third aspect of the present invention, an FET is inserted in series with a load having a capacitive characteristic, and the gate voltage of the FET is changed by a time constant changing voltage by a time constant circuit. A rush current prevention circuit for preventing an inrush current by gradually changing a conduction current of the FET by a change in a gate voltage of the FET, having a Zener diode for limiting a gate voltage of the FET, and changing a time constant of the time constant circuit. The time constant circuit is set so that the final voltage of the voltage is higher than the final voltage applied to the gate of the FET, and the gate voltage of the FET, which changes according to the time constant changing voltage of the time constant circuit, is This is limited by a diode.
[0021]
According to a fourth aspect of the present invention, an FET is inserted in series with a load having a capacitive characteristic, and the gate voltage of the FET is changed by a time constant changing voltage by a time constant circuit. In the operation method of the inrush current prevention circuit for preventing the inrush current by gradually changing the conduction current of the FET by the change of the gate voltage of the FET, the change rate of the voltage applied to the load to the time constant change voltage of the time constant circuit Is added.
[0022]
According to a fifth aspect of the present invention, an FET is inserted in series with a load having a capacitive characteristic, and a gate voltage of the FET is changed by a time constant change voltage by a time constant circuit. A rush current prevention circuit for preventing a rush current by gradually changing a conduction current of the FET according to a change in a gate voltage of the FET, including a differentiation circuit for detecting a change speed of a drain voltage of the FET, wherein the differentiation circuit detects The change rate of the drain voltage of the FET described above is added to the time constant change voltage by the time constant circuit, and negative feedback is provided to the gate of the FET.
[0023]
In the invention according to claim 6 of the present invention, in the invention according to claim 5 of the present invention, the differentiating circuit includes a capacitor and a resistor. It has a diode inserted in parallel with a resistor, and the diode rapidly charges the capacitor with a necessary voltage immediately after power is turned on.
[0024]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, an example of an embodiment of an inrush current prevention circuit and an inrush current prevention circuit according to the present invention will be described in detail with reference to the accompanying drawings.
[0025]
First, an example of an embodiment of an operation method of an inrush current prevention circuit according to the present invention will be described. An example of an embodiment of an operation method of the inrush current prevention circuit according to the present invention is as shown in FIG. Since the present invention can be used when operating a conventional inrush current prevention circuit, it will be described with reference to FIG. 6 to facilitate understanding.
[0026]
That is, in the method of operating the inrush current prevention circuit according to the present invention, the FET is inserted in series with a load having a capacitive characteristic as shown in FIG. A method of operating an inrush current prevention circuit that gradually changes a conduction current of an FET to prevent an inrush current by changing the start voltage of a time constant change voltage of a time constant circuit to a maximum gate at which the FET does not conduct. This is made to substantially match the voltage.
[0027]
Specifically, when the inrush current prevention circuit 106 as shown in FIG. 6 is operated, the maximum gate voltage at which the FET 106a does not conduct is changed to the time constant change by the CR time constant circuit constituted by the capacitor 106b and the resistor 106c. The start voltages of the voltages are made to substantially match.
[0028]
Here, an ordinary FET, which is generally commercially available, is set such that no current flows between the drain and the source at a gate voltage of 1.5 V or less. Therefore, when such an FET is used as the FET 106a of the inrush current prevention circuit 106, when the voltage (time constant change voltage) changes according to the time constant of the CR time constant circuit constituted by the capacitor 106b and the resistor 106c. No current flows between the drain and the source of the FET 106a at all when the gate voltage of the FET 106a is 0 to 1.5 V, and during this period, it does not function at all to prevent an inrush current.
[0029]
However, for example, by using a circuit configuration as shown in FIG. 1 described below, the starting voltage of the time constant changing voltage of the CR time constant circuit constituted by the capacitor 106b and the resistor 106c is changed to the maximum gate voltage at which the FET 106a does not conduct. If the voltage is made equal to 1.5 V, and the change in the time constant changing voltage of the CR time constant circuit is started with 1.5 V as an initial value, a wasteful function that does not function to prevent an inrush current is generated. The rush current prevention time can be shortened by the time required to raise the gate voltage of the FET 106a from 0 to 1.5 V at first.
[0030]
Next, an example of an embodiment of an inrush current prevention circuit according to the present invention will be described with reference to FIG.
[0031]
Note that, in the circuit configuration shown in FIG. 1 illustrating an example of an embodiment of the present invention, the same reference numerals as those used in FIG. 6 denote the same or corresponding components as those used in the circuit configuration shown in FIG. By using and showing, the overlapping description of the configuration and operation is omitted.
[0032]
FIG. 1 is an explanatory diagram of a circuit configuration of an inrush current prevention circuit according to an example of an embodiment of an inrush current prevention circuit according to the present invention.
[0033]
The inrush current prevention circuit 10 shown in FIG. 1 includes a resistor (Rs) 12 connected in series to a CR time constant circuit composed of a capacitor 106b and a resistor 106c. This is different from the inrush current prevention circuit 106.
[0034]
More specifically, the resistor 12 is connected in series between the negative terminal 100a of the DC power supply 100 and the capacitor 106b constituting the CR time constant circuit.
[0035]
Therefore, since the inrush current prevention circuit 10 shown in FIG. 1 includes the resistor 12, the starting voltage Vs of the gate voltage Vg of the FET 106a becomes
Vs = E · Rs / (R1 // R2) Equation (1)
It becomes.
[0036]
The CR time constant τ of the CR time constant circuit constituted by the capacitor 106b and the resistor 106c is
τ = C1 · (Rs + R1 // R2) Equation (2)
It becomes.
[0037]
In the above equations (1) and (2), “E” represents the power supply voltage of the DC power supply 100, “Rs” represents the resistance value of the resistor 12, and “R1 // R2” represents the resistance 106c. It represents a parallel resistance value with the resistor 106d, and "C1" represents the capacitance of the capacitor 106b.
[0038]
Therefore, by using the above equations (1) and (2), the necessary CR time constant in the CR time constant circuit constituted by the capacitor 106b and the resistor 106c and the required starting voltage of the gate voltage of the FET 106a are determined. Can be determined.
[0039]
Therefore, if the inrush current prevention circuit shown in FIG. 1 is used, the initial value of the time constant change voltage of the CR time constant circuit constituted by the capacitor 106b and the resistor 106c is a non-zero constant value (for example, 1.5 V). ), And it is possible to change the gate voltage of the FET 106a by this time constant change voltage.
[0040]
That is, in the inrush current prevention circuit shown in FIG. 1, the starting voltage (initial value) of the time constant change voltage of the CR time constant circuit constituted by the capacitor 106b and the resistor 106c is set to the maximum gate voltage at which the FET does not conduct. , And the time for preventing inrush current can be shortened.
[0041]
Next, another embodiment of the inrush current prevention circuit according to the present invention will be described with reference to FIG.
[0042]
In addition, in the circuit configuration shown in FIG. 2 showing another example of the embodiment of the present invention, the same or equivalent configuration as the configuration used in the circuit configuration shown in FIG. 1 and FIG. By using the same reference numerals as those used, redundant description of the configuration and operation will be omitted.
[0043]
FIG. 2 is a circuit diagram illustrating an inrush current prevention circuit according to another embodiment of the inrush current prevention circuit according to the present invention.
[0044]
The inrush current prevention circuit 20 shown in FIG. 2 is different from the inrush current prevention circuit 10 according to the present invention shown in FIG. 1 in that a zener diode (CR1) 22 is connected instead of the resistor 106d.
[0045]
Here, in the CR time constant circuit constituted by the capacitor 106b and the resistor 106c, when the time constant change voltage approaches the final attained voltage, the voltage change speed becomes slow, and the final attained voltage is not easily reached. Therefore, the time constant of the CR time constant circuit is increased to increase the final attained voltage of the time constant change voltage, and the time constant change voltage of the CR time constant circuit reaches the final voltage applied to the gate of the FET 106a. By limiting the change in the time constant change voltage at the time, the entire inrush current prevention time can be shortened without changing the change speed of the time constant change voltage in a necessary range.
[0046]
FIG. 2 shows that the time constant of the CR time constant circuit is increased to increase the final attained voltage of the time constant change voltage so that the time constant change voltage of the CR time constant circuit reaches the final voltage applied to the gate of the FET 106a. At the point in time, a circuit for realizing that the inrush current prevention time can be shortened without changing the change speed of the time constant change voltage in a necessary range by limiting the change of the time constant change voltage. 1 shows an example of a configuration.
[0047]
That is, in the rush current prevention circuit shown in FIG. 2, the time constant of the CR time constant circuit constituted by the capacitor 106b and the resistor 106c is made larger than that in FIG. 1, and the Zener diode 22 applies the time constant to the FET 106a. Voltage is limited.
[0048]
Specifically, the Zener diode 22 functions as a voltage limiting diode, and limits the change in the time constant change voltage when the time constant change voltage of the CR time constant circuit reaches the final voltage applied to the gate of the FET 106a. ing.
[0049]
FIG. 3 shows a time change A of the gate voltage of the FET 106a by the rush current prevention circuit 10 shown in FIG. 1 (indicated by a dashed line A in FIG. 3), and the change of the gate voltage of the FET 106a by the rush current prevention circuit 20 shown in FIG. A time change B (shown by a solid line B in FIG. 3) and a time change C of the gate voltage of the FET 106a when the inrush current prevention circuit 20 shown in FIG. 2 does not include the Zener diode 22 (shown by a two-dot chain line C in FIG. 3). 6 and a graph showing a time change D (shown by a broken line D in FIG. 3) of the gate voltage of the FET 106a by the rush current prevention circuit 106 shown in FIG.
[0050]
Note that the graph of the time change of the gate voltage shown in FIG. 3 shows the start voltage of the time constant change voltage of the CR time constant circuit composed of the capacitor 106b and the resistor 106c in the inrush current prevention circuit 20 shown in FIG. , Starting from the maximum gate voltage at which the FET 106a does not conduct.
[0051]
As is clear from the graph of the time change of the gate voltage shown in FIG. 3, the time required to reach the final attained voltage of the time constant change voltage is shortened in the order of “time change D → time change A → time change B”. In addition, the rush current prevention time can be shortened.
[0052]
Next, still another example of the embodiment of the inrush current prevention circuit according to the present invention will be described with reference to FIG.
[0053]
In the circuit configuration shown in FIG. 4 showing still another example of the embodiment of the present invention, the same or corresponding configurations as those used in the circuit configurations shown in FIG. 1, FIG. 2 and FIG. 2 and FIG. 6, the same reference numerals are used to omit redundant description of the configuration and operation.
[0054]
FIG. 4 is an explanatory diagram showing a circuit configuration of an inrush current prevention circuit according to still another embodiment of the inrush current prevention circuit according to the present invention.
[0055]
The inrush current prevention circuit 30 shown in FIG. 4 includes a FET 106a, a capacitor 106b, a resistor 106c, a Zener diode 22, a differential circuit including a resistor (R3) 32 and a capacitor (C2) 34, and a resistance of the differential circuit. 32 and a diode (CR2) 36 inserted in parallel.
[0056]
More specifically, in the inrush current prevention circuit 30 described above, the resistor 32 and the capacitor 34 are differentiating circuits for deriving the differential coefficient of the drain voltage of the FET 106a. 106c and is added to the C1 · R1 time constant change voltage obtained from this. That is, when the load current increases significantly, the drain voltage of the FET 106a greatly decreases, and the gate voltage Vg of the FET 106a decreases in the negative direction. When the gate voltage Vg of the FET 106a decreases, an increase in the current of the FET 106a is suppressed.
[0057]
Further, the diode 36 is a protection diode for preventing the gate voltage Vg from fluctuating positively by the current charging the capacitor 34 immediately after the power is turned on.
[0058]
Here, as described in the section of "Prior Art", the drain-source current of the FET 106a largely changes in only a part of the change region of the gate voltage. On the other hand, in order to make the power supply current equal to or less than the specified value, the time constant of the change in the gate voltage of the FET 106a must be sufficiently large. That is, a large inrush current prevention time is required before the normal operation is started after the power is turned on.
[0059]
For this reason, in the rush current prevention circuit 30 shown in FIG. By applying negative feedback so as to reduce the current, the inrush current is suppressed to a specified value or less. Thus, the time constant of the time constant circuit including the capacitor 106b and the resistor 106c can be reduced. FIG. 4 shows such an operation, that is, an operation of adding a voltage proportional to a change speed of the voltage applied to the capacitive load 104 to a C1 · R1 time constant change voltage obtained from the capacitor 106b and the resistor 106c. 1 shows an example of the circuit configuration.
[0060]
In the circuit shown in FIG. 4, since the capacitance of the capacitor is generally “capacitor (C) 104a≫capacitor (C1) 106b≫capacitor (C2) 34”, “1 / C2: 1 / C1 = (E−Vs): Vs ”, the start voltage of the time constant change voltage can be set to Vs.
[0061]
FIG. 5 shows a time change E (shown by a solid line E in FIG. 5) of the gate voltage of the FET 106a by the inrush current prevention circuit 30 shown in FIG. 4 and a time of the gate voltage of the FET 106a by the inrush current prevention circuit 106 shown in FIG. A graph showing a change D (indicated by a broken line D in FIG. 5) is shown.
[0062]
In the rush current prevention circuit 30 shown in FIG. 4 shown in the graph of the time change of the gate voltage shown in FIG. 5, the gate voltage Vg rises at the beginning with a small time constant, but the drain-source is changed due to the gate voltage change. In the range where the inter-current greatly changes, negative feedback is applied, and the rising speed of the gate voltage Vg decreases, and finally increases at the original speed.
[0063]
The above-described embodiment can be appropriately modified as described in the following (1) and (2).
[0064]
(1) In the above embodiment, the case where the N-type MOS-FET is used as the FET has been described. However, the present invention is not limited to this, and all the voltage polarities in the circuit are inverted. Of course, a P-type FET may be used.
[0065]
(2) Needless to say, the above-described embodiment and the modification shown in (1) may be appropriately combined.
[0066]
【The invention's effect】
Since the present invention is configured as described above, it has an excellent effect that it can be completed in a short time while exhibiting a necessary inrush current preventing function with a relatively simple circuit.
[0067]
That is, according to the present invention, there is an excellent effect that the rush current can be suppressed to the specified value and the resistance value of the FET can be reduced to a required value in a short time.
[0068]
In other words, according to the present invention, there is an excellent effect that the convergence time of the inrush current prevention circuit can be significantly reduced as compared with the related art.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram of a circuit configuration of an example of an embodiment of an inrush current prevention circuit according to the present invention.
FIG. 2 is an explanatory diagram of a circuit configuration of another example of the inrush current prevention circuit according to the embodiment of the present invention;
FIG. 3 is a graph showing a time change of a gate voltage of an FET by an inrush current prevention circuit.
FIG. 4 is an explanatory diagram of a circuit configuration of another example of the inrush current prevention circuit according to the embodiment of the present invention;
FIG. 5 is a graph showing a time change of a gate voltage of an FET by an inrush current prevention circuit.
FIG. 6 is an explanatory diagram of a circuit configuration of a conventional inrush current prevention circuit.
[Explanation of symbols]
10, 20, 30, 106 Inrush current prevention circuit 12 Resistance (Rs)
22 Zener diode (CR1)
32 resistance (R3)
34 Capacitor (C2)
36 Diode (CR2)
100 DC power supply 100a Negative terminal 102 Switch (SW)
104 capacitive load 104a capacitive component (C)
104b Load component (LOAD)
106a FET
106b Capacitor (C1)
106c resistance (R1)
106d resistance (R2)

Claims (6)

An FET is inserted in series with a load having a capacitive characteristic, the gate voltage of the FET is changed by a time constant change voltage by a time constant circuit, and the conduction current of the FET is gradually changed by a change in the gate voltage of the FET. In the operation method of the inrush current prevention circuit that prevents the inrush current by
Method of operating an inrush current prevention circuit in which a start voltage of a time constant change voltage of the time constant circuit is substantially equal to a maximum gate voltage at which the FET does not conduct. An FET is inserted in series with a load having a capacitive characteristic, the gate voltage of the FET is changed by a time constant change voltage by a time constant circuit, and the conduction current of the FET is gradually changed by a change in the gate voltage of the FET. Inrush current prevention circuit that prevents inrush current by
Having a resistor inserted in series with the time constant circuit,
An inrush current prevention circuit for changing a gate voltage of the FET by a time constant changing voltage having a fixed value other than zero as a starting voltage according to a resistance value of the resistor. An FET is inserted in series with a load having a capacitive characteristic, the gate voltage of the FET is changed by a time constant change voltage by a time constant circuit, and the conduction current of the FET is gradually changed by a change in the gate voltage of the FET. Inrush current prevention circuit that prevents inrush current by
A Zener diode for limiting a gate voltage of the FET,
The time constant circuit is set such that the final voltage of the time constant change voltage of the time constant circuit is higher than the final voltage applied to the gate of the FET,
An inrush current prevention circuit for limiting a gate voltage of the FET, which changes according to a time constant change voltage of the time constant circuit, by the Zener diode. An FET is inserted in series with a load having a capacitive characteristic, the gate voltage of the FET is changed by a time constant change voltage by a time constant circuit, and the conduction current of the FET is gradually changed by a change in the gate voltage of the FET. In the operation method of the inrush current prevention circuit that prevents the inrush current by
Method of operating an inrush current prevention circuit for adding a voltage proportional to a change rate of a voltage applied to a load to a time constant change voltage of the time constant circuit An FET is inserted in series with a load having a capacitive characteristic, the gate voltage of the FET is changed by a time constant change voltage by a time constant circuit, and the conduction current of the FET is gradually changed by a change in the gate voltage of the FET. Inrush current prevention circuit that prevents inrush current by
A differential circuit for detecting a change speed of the drain voltage of the FET,
An inrush current prevention circuit that adds a change rate of a drain voltage of the FET detected by the differentiating circuit to a time constant change voltage by the time constant circuit and negatively feeds back to a gate of the FET. The inrush current prevention circuit according to claim 5,
The differentiating circuit includes a capacitor and a resistor,
further,
Having a diode inserted in parallel with the resistor of the differentiation circuit,
An inrush current prevention circuit for rapidly charging a voltage required for the capacitor immediately after power-on by the diode;

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