JP2004129377A - Charge pump boosting circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress radio noise caused by current noise in a charging pump type boosting circuit. <P>SOLUTION: This boosting circuit comprises a charge pump circuit which receives a boosting pulse and boosts external power voltage, a comparator circuit which detects that the output voltage boosted by the charge pump circuit drops below a prescribed threshold voltage, and a boosting pulse generating circuit which receives the detection signal of the comparator circuit and generates the boosting pulse. The minimum number of boosting pulses generated when the boosting pulse generating circuit receives the detection signal of the comparator circuit is set so as to be different from that generated when it receives the last detection signal. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a charge pump type booster circuit that obtains a higher voltage source from a low voltage source such as a battery, and more particularly to a booster circuit technology for reducing radio noise generated during charge pump operation.
[0002]
[Prior art]
For example, most of in-vehicle electronic devices use a battery as a drive source, and among them, there are devices such as an EL display panel which require a drive voltage higher than a battery voltage. Also, portable electronic devices such as a video camera, a digital camera, and a mobile phone require a higher voltage than a battery to display liquid crystal. To obtain such a high voltage, a booster circuit is required. Although the booster circuit for the use described above has a drawback that the output voltage fluctuation is slightly large, a booster circuit using a charge pump circuit that can adopt a transformerless structure and can reduce the size of the circuit is often adopted. .
[0003]
FIG. 3 shows an example of a circuit configuration of a conventional booster circuit that obtains a high voltage by using such a charge pump circuit. The booster circuit 1 includes a charge pump circuit 2, a comparator circuit 3, and a boost pulse generating circuit. 4.
The charge pump circuit 2 is a circuit that boosts the external power supply voltage Vin, and includes diodes D21 to D25, capacitors C21 to C25, an inverter Q21, a first non-inverting buffer Q22, and a second non-inverting buffer Q23. .
[0004]
The external power supply voltage Vin is supplied to the anode of the diode D21. The cathodes of the diodes D21 to D24 are connected to the anodes of the diodes D22 to D25, respectively. The anodes of the diodes D22 to D25 are connected to the first terminals of the capacitors C21 to C24, respectively. The second terminals of the capacitors C21 and C23 are connected to the output terminal of the first non-inverting buffer Q22. The second terminals of the capacitors C22 and C24 are connected to the output terminal of the second non-inverting buffer Q23. The second non-inverting buffer Q23 buffers the boosted pulse signal φ1 of the boosted pulse generation circuit 4 and drives the second terminals of the capacitors C22 and C24. The first non-inverting buffer Q22 buffers a pulse obtained by inverting the boosted pulse signal φ1 of the boosted pulse generating circuit 4 by the inverter Q21, and drives the second terminals of the capacitors C21 and C23. The cathode of diode D25 is connected to output node Nout. The voltage Vout of the output node Nout is a boosted output voltage. An output voltage smoothing capacitor C25 is connected between the cathode of the diode D25 and the ground node Vss.
[0005]
In the charge pump circuit 2, the electric charge supplied from the external power supply voltage Vin through the diode D 21 is sequentially transferred to the subsequent stage through the capacitors C 21, C 22 and C 23 in synchronization with the boost pulse signal φ 1 of the boost pulse generating circuit 4. As the charge is transferred, the charging voltage of each capacitor is gradually increased toward the subsequent capacitor, and a boosted output voltage Vout expressed by the following equation is obtained at the output node Nout.
Vout = Vin + (Vφ−VF) × N−VF− (Iout × N) / (C × f)
Here, Vφ is the output voltage of the non-inverting buffers Q22 and Q23, VF is the forward voltage of the diode, Iout is the output current, C is the capacitance of the capacitors C21 to C24, f is the frequency of the boost pulse signal φ1, and N is the diode. This is the number of stages of the boosting circuit (for example, C21 and D22) to which each one of the capacitors is connected. The number N of stages is adjusted according to the required level of boosting.
[0006]
The obtained output voltage Vout is guided to the comparator circuit 3 and is divided by resistors R31 and R32 connected in series. The divided voltage is input to the inverting input terminal of the comparator COMP31 as the feedback voltage Vf. The reference voltage Vref generated by the reference voltage generation circuit 31 is input to the non-inverting input terminal of the comparator COMP31. When the output voltage Vout decreases and the feedback voltage Vf becomes lower than the reference voltage Vref, the comparator COMP31 outputs a “High” level (logic “1”) signal as an active signal, and conversely, the output voltage Vout increases. When the feedback voltage Vf becomes higher than the reference voltage Vref, an operation of generating a “Low” level (logic “0”) signal as an inactive signal and sending the signal to the boost pulse generating circuit 4 is performed.
[0007]
Basically, the boost pulse generating circuit 4 generates the boost pulse signal φ1 and causes the charge pump circuit 2 to perform the boost operation when the output of the comparator COMP31 is at the “High” level. Conversely, when the output of the comparator COMP31 is at the “Low” level, the circuit serves to stop the generation of the boosting pulse signal φ1 and stop the boosting operation of the charge pump circuit 2.
[0008]
The boost pulse generating circuit 4 shown in FIG. 3 includes a shift register 42 including master-slave D-type flip-flops DF41, DF42, and DF43, a three-input OR circuit Q41, a two-input AND circuit Q42, a non-inverting buffer Q43, and an inverter. Q44.
Immediately after the circuit power is turned on, a reset signal RST is output from a reset pulse generating circuit (not shown). The data is inverted by the inverter circuit Q44 and applied to the reset terminals of the three flip-flops DF41 to DF43, thereby returning each flip-flop to the initial state.
[0009]
On the other hand, the clock signal CLOCK generated by the clock pulse generation circuit 41 is buffered by the non-inverting buffer Q43 and then input to each clock input terminal CL of the flip-flops DF41 to DF43. Each of the flip-flops DF41 to DF43 reads the logic state of the data input terminal D at that moment at the rising edge of the clock pulse applied to the clock input terminal CL, and reads the read logic state at the falling edge of the clock pulse. An operation of outputting to each output terminal Q is performed. The flip-flops DF41 to DF43 are cascade-connected (the output terminal Q of the previous stage is connected to the data input terminal D of the flip-flop of the next stage) to constitute the shift register 42. Therefore, every time a clock pulse of the clock signal CLOCK is input, an operation is performed in which data read from the data input terminal D of the first-stage flip-flop DF41 is sequentially shifted to the subsequent-stage flip-flop. In FIG. 4, the shift register 42 is constituted by three flip-flops DF41 to DF43, but this is merely an example, and the number of flip-flops (the number of bits of the shift register 42) may be increased or decreased as necessary.
[0010]
Each output signal of the flip-flops DF41 to DF43 is applied to an input terminal of a three-input OR circuit Q41, and the output signal is applied to a first input terminal of a two-input AND circuit Q42 and to a second input terminal of Q42. The clock signal CLOCK is input. The output of Q42 is a boost pulse signal φ1. Therefore, if there is at least one "High" level signal among the signals of the output terminals D of the DF41 to DF43, the output of Q41 becomes the "High" level. In this state, when the next clock pulse is input as the clock signal CLOCK, a boost pulse having the same waveform as the clock pulse appears as the boost pulse signal φ1. Then, the boosting pulse is input to the charge pump circuit 2 to perform the boosting operation.
[0011]
Since the shift register 42 including the flip-flops DF41 to DF43 is provided, the output of the comparator COMP31 becomes the “High” level, and when the signal is latched by the DF41 in synchronization with the clock pulse, at least Three boosting pulses are output as boosting pulse signal φ1. Also, even after the output of the comparator COMP31 has been at the "Low" level after continuing the "High" level for a long time, at least three boosted pulses are output as the boosted pulse signal φ1 thereafter.
[0012]
The reason why the shift register 42 is provided to perform the operation of extending the output signal of the comparator COMP31 in such a case is that in such a case, a short pulse is generated in the output of the comparator COMP31 by the operation of the charge pump circuit 2. Noise, which may cause other circuits to malfunction. Since the short pulse is not synchronized with the clock pulse, if the signal and the clock signal CLOCK are directly ANDed by the two-input AND circuit Q42, a boost pulse having a pulse width narrower than the clock pulse width of the clock signal CLOCK is obtained. This is because the operation of the charge pump circuit 2 may be unstable due to the generation of the signal φ1.
[0013]
From this, the normal operation of the circuit in FIG. 3 is as shown in the timing chart of the main part signals in FIG. The timing chart of FIG. 4 is a diagram in the case where a constant output current Iout is supplied to the load from the output node Nout.
[0014]
Since the output current Iout is supplied from the smoothing capacitor C25, the flow of the output current Iout causes the output voltage Vout to decrease. When the output voltage Vout becomes lower than the predetermined threshold voltage Vth, the reference voltage Vref is set so that the feedback voltage Vf obtained by dividing the output voltage Vout becomes lower than the reference voltage Vref. Immediately changes to the "High" level.
[0015]
Then, the flip-flop DF41 latches the “High” level signal by the clock pulse of the clock signal CLOCK immediately after that, and outputs the “High” level to the output terminal D. When the output of the DF 41 becomes the “High” level in this way, the output of the Q 41 also becomes the “High” level, and a boost pulse having the same waveform as the clock pulse appears as the boost pulse signal φ 1 of the output of the Q 42 by the next clock pulse. When the boosting pulse is input to charge pump circuit 2 and the boosting operation is performed once, output voltage Vout increases and exceeds predetermined threshold voltage Vth.
When the output voltage Vout exceeds the threshold voltage Vth, the feedback voltage Vf becomes higher than the reference voltage Vref, and the output of the comparator COMP31 immediately returns to the “Low” level. Therefore, at the next clock pulse, the DF 41 latches the "Low" level, and its output returns to the "Low" level, and its logical state is shifted by the subsequent clock pulse.
[0016]
However, the “High” level signal latched in the flip-flop DF1 by the clock pulse immediately after the output of the comparator COMP31 first becomes the “High” level disappears after being shifted to DF42 and DF43 by the subsequent clock pulse. Accordingly, while the “High” level signal is held at any of DF1 to DF3, the output of Q41 continues to be maintained at the “High” level, so that the boosted pulse signal φ1 output from Q42 is eventually Three boost pulses appear.
[0017]
The charge pump circuit 2 receives these three boosting pulses and performs a boosting operation, and the output voltage Vout is boosted to a voltage higher than the threshold voltage Vth. The boosting operation is stopped by stopping the generation of the boosting pulse. Thereafter, the output current Iout flows again, and the output voltage Vout starts to decrease. Then, when the output voltage Vout falls below the predetermined threshold voltage Vth, the comparator COMP31 outputs a "High" level signal again. As a result, the same boosting operation as described above is started again. As a result of such an operation, an operation of repeating a periodic waveform as shown in the timing chart of FIG. 4 is performed.
[0018]
[Problems to be solved by the invention]
A problem in the process of the boosting operation as described above is current noise generated when the charge pump circuit 2 performs the boosting operation. Each time the outputs of the non-inverting buffers Q22 and Q23 perform an inverting operation in response to the boost pulse, a large amount of charge movement occurs instantaneously in each part of the charge pump circuit 2 each time. Then, current noise due to the instantaneous movement of the electric charge is generated at a timing as shown in FIG.
[0019]
When the output current Iout is substantially constant, the current noise at the time of the boosting operation is generated intermittently in a cycle T1 as shown in (4) of FIG. The noise spectrum of the current noise having such a waveform exhibits a spectrum composed of a plurality of harmonics having a fundamental period of T1. Therefore, when an AM radio in the medium wave band (535 to 1605 kHz) is present around the booster circuit 1 that generates such noises, their harmonics are mixed into the AM radio as radio noise and interfere with the broadcast radio waves. Cause a problem that a beat sound is generated.
[0020]
The present invention has been made in view of the above circumstances, and an object of the present invention is to reduce the magnitude of the radio noise generated by the boosting operation of the boosting circuit 1 when the output current is substantially constant. is there.
[0021]
[Means for Solving the Problems]
In order to achieve the above object, the invention according to claim 1 includes a charge pump circuit that receives a boost pulse to boost an external power supply voltage, and an output voltage boosted by the charge pump circuit is higher than a predetermined threshold voltage. A charge pump type booster circuit comprising: a comparator circuit which detects a drop and outputs a detection signal; and a boost pulse generating circuit which receives the detection signal of the comparator circuit and generates the boost pulse. The boosted pulse generating circuit receives the detection signal of the comparator circuit, and a minimum number of the generated boost pulses generated when the detection signal is received last time is different from a minimum number of generated pulses. This is a charge pump type booster circuit.
[0022]
With this configuration, when a signal that detects that the output voltage has dropped below the threshold voltage is received, the minimum number of boosting pulses generated by the boosting pulse generation circuit is reduced every time the detection signal is received. , Different from the previous minimum number of occurrences. Therefore, since the cycle of the generated current noise waveform is different each time, the peak value of the noise spectrum is reduced and the effect of reducing the radio noise is obtained.
[0023]
A second aspect of the present invention is a charge pump type booster circuit including a charge pump circuit, a comparator circuit, and a boost pulse generating circuit. The charge pump circuit is configured to boost an external power supply voltage by receiving a boost pulse from the boost pulse generating circuit. The comparator circuit compares the output voltage boosted by the charge pump circuit with a predetermined threshold voltage, and outputs an active signal when the output voltage is lower than the threshold voltage. It is configured to output an inactive signal when the voltage is higher than the threshold voltage. Further, the boost pulse generating circuit is a circuit for generating the boost pulse in response to an output signal of the comparator circuit, wherein the information latched by the first-stage flip-flop is synchronized with a clock pulse generated by an internal clock pulse generating circuit. , And first and second shift registers having different numbers of bits for shifting data, and flip-flops whose output states are inverted each time an active signal is received from the comparator circuit. When the output of the flip-flop is inactive and the output of the comparator circuit is active, the first shift register synchronizes the inactive signal with the clock pulse and the second shift register synchronizes the inactive signal with the clock pulse. On the contrary, when the output of the flip-flop is active and the output of the comparator circuit is active, the first shift register outputs an inactive signal and the second shift register outputs an active signal to the clock pulse. It is configured to latch synchronously. Further, when any one of the bit outputs of the first and second shift registers is active, the boosting pulse is generated in synchronization with the clock pulse. It is a booster circuit.
[0024]
With such a configuration, as in the first aspect of the present invention, when receiving a signal indicating that the output voltage has dropped below the threshold voltage, the boost pulse generating circuit generates the minimum boost pulse. Every time the detection signal is received, the number of occurrences differs from the previous minimum number of occurrences. Therefore, since the cycle of the generated current noise waveform is different each time, the peak value of the noise spectrum is reduced and the effect of reducing the lio noise is obtained.
[0025]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is an electrical configuration diagram showing an example of an embodiment of the present invention. The same or corresponding portions as those in FIG. 3 are denoted by the same reference numerals, and description thereof will not be repeated.
[0026]
The charge pump type booster circuit 1 shown in FIG. 1 includes a charge pump circuit 2, a comparator circuit 3, and a boost pulse generating circuit 4. The configurations of the charge pump circuit 2 and the comparator circuit 3 are the same as those of the charge pump circuit 2 and the comparator circuit 3 in FIG.
[0027]
Hereinafter, the configuration and operation of the boost pulse generating circuit 4 in FIG. 1 which is different from that in FIG. 3 will be described in detail. DF44 to DF49 in FIG. 1 are master-slave type D-type flip-flops. DF45 to DF47 constitute a 3-bit shift register 42, and the operation is the same as that of the shift register 42 composed of DF41 to DF43 in FIG. Similarly, DF48 and DF49 constitute a 2-bit shift register 43, and the operation is the same as that of the 3-bit shift register 42 composed of DF45 to DF47, except that the number of bits is one bit smaller. The clock signal CLOCK generated by the clock pulse generation circuit 41 is buffered by a non-inverting buffer Q43 and applied to each clock input terminal of DF45 to DF49.
[0028]
A signal obtained by inverting a reset signal RST for resetting the DF45 to DF49 when the circuit power is turned on by the inverter Q44 is applied to each reset terminal (negative logic input terminal) of the DF45 to DF49.
[0029]
The outputs of the flip-flops DF45 to DF47 constituting the 3-bit shift register 42 are input to a three-input OR circuit Q47. When at least one output of the DF45 to DF47 is at the “High” level, the output of Q47 is It becomes the “High” level. Similarly, the outputs of DF48 and DF49 are input to a two-input OR circuit Q48. When at least one of the outputs of DF48 and DF49 is at "High" level, the output of Q48 is at "High" level. The outputs of Q47 and Q48 are input to a two-input OR circuit Q46, and when at least one of the outputs of Q47 and Q48 is at "High" level, the output of Q46 also becomes at "High" level. With such a circuit configuration, the output of Q46 is configured to be at the “High” level when at least one of the outputs of DF45 to DF49 is at the “High” level.
[0030]
The output signal of the comparator COMP31 is input to the clock input terminal CL of the flip-flop DF44 and the first input terminals of the two-input AND circuits Q50 and Q51. The output signal of the DF 44 is input to the second input terminal of the two-input AND circuit Q51 and the inverter Q49. The output signal of the inverter Q49 is input to the data input terminal D of the DF44 and the second input terminal of the two-input AND circuit Q50. With such a circuit configuration, the output of the DF 44 repeats the operation of inverting the output state each time a clock pulse is input to the clock input terminal CL.
[0031]
The “High” level signal is applied to the input terminal D of the DF 45 when the comparator COMP 31 outputs an “High” level signal, which is an active signal, when the output of the DF 44 is in a “Low” level state, which is an inactive state. Conversely, a signal of “High” level is applied to the input terminal D of DF48 when the comparator COMP31 outputs “High” level when the output of DF44 is in “High” level state, which is the active state.
[0032]
Next, a normal operation of the booster circuit 1 under such a circuit configuration will be described with reference to a time chart of main signals shown in FIG. The normal operation refers to a state in which a substantially constant output current Iout is supplied from the output node Nout to the load. Since the output current Iout is supplied from the smoothing capacitor C25, the output voltage Vout decreases as the output current Iout flows. When the output voltage Vout becomes lower than the predetermined threshold voltage Vth, the feedback voltage Vf obtained by dividing the output voltage Vout becomes lower than the reference voltage Vref, and the comparator COMP31 outputs the "High" level signal as the active signal. Output.
[0033]
Since the output state of the flip-flop DF44 may start from any of the "High" level and the "Low" level, it is assumed here that the output of the DF44 is initially at the "Low" level. Then, when the output of the comparator COMP31 becomes “High” level, the output of Q50 becomes “High” level, and the “High” level, which is the active signal, is latched in the DF 45 by the first clock pulse following the clock signal CLOCK. Is done. On the other hand, since the output signal of the DF 44 is at the "Low" level, the output of the Q51 remains at the "Low" level, and the "Low" level, which is an inactive signal, is latched in the DF 48.
[0034]
Since the output of flip-flop DF45 attains "High" level, the outputs of Q47 and Q46 also attain "High" level. Therefore, a boosting clock pulse appears in the boosting pulse signal φ1, which is the output signal of Q42, by the clock pulse following the clock signal CLOCK. When this boosting pulse is input to the charge pump circuit 2, the boosting operation is performed once, whereby the output voltage Vout rises and exceeds the threshold voltage Vth. Then, the feedback voltage Vf exceeds the reference voltage Vref, and the output of the comparator COMP31 falls to the “Low” level. Due to such an operation, the output waveform of the comparator COMP31 has a pulse-like waveform that immediately goes to the “High” level and then immediately returns to the “Low” level as shown in the first waveform of FIG. Become.
[0035]
While the output of the comparator COMP31 is at the "Low" level, the outputs of Q50 and Q51 are both maintained at the "Low" level, so that in the subsequent clock pulse of the clock signal CLOCK, both the DF45 and DF48 latch the "Low" level. I do. Then, each time a clock pulse is applied, the logic state is shifted to a flip-flop at a subsequent stage. However, the “High” level signal latched by the DF 45 immediately after the comparator COMP 31 first outputs the “High” level due to the decrease in the output voltage Vout is shifted to DF 46 and DF 47 by the subsequent clock pulse and then disappears. When at least one of the outputs of DF46 to DF47 is at the "High" level, the output of Q46 maintains the "High" level. It appears like the first pulse group of 2 (3).
[0036]
When the charge pump circuit 2 performs the boosting operation three times in response to the three boosting pulses, the output voltage Vout sharply increases as shown by the waveform (2) in FIG. The boosting stops when the generation of the boosting pulse stops. Thereafter, due to the outflow of the load current Iout, the output voltage Vout starts decreasing at a gradient determined by the capacitance of the smoothing capacitor C25 and the value of the output current Iout.
[0037]
Here, the operation of the flip-flop DF44 will be described. The first pulse waveform of (1) in FIG. 2 is applied to the clock input terminal CL of the DF 44 from the comparator COMP31. A signal obtained by inverting the signal of the output terminal Q by the inverter 49 is input to the data input terminal D of the DF 44. Initially, the output of the DF 44 is at the “Low” level, so that a “High” level signal is applied to the data input terminal D. Therefore, a "High" level signal is read into the clock input terminal CL at the rising edge of the pulse signal applied from the comparator COMP31, and the "High" level signal read at the falling edge of the pulse signal is output to the output terminal Q. Will be transferred. Thus, the output of the DF 44 is inverted to the “High” level. Thereafter, when the next pulse signal is applied to the clock input terminal D, the output returns to the original "Low" level. That is, the flip-flop DF44 repeats the operation of inverting the output state each time the comparator COMP31 generates a pulse signal.
[0038]
If the output current Iout continues to flow after the stop of the boosting operation and the output voltage Vout continues to decrease, as shown in the first sawtooth waveform of FIG. Vout becomes lower than the threshold voltage Vth again. Then, the comparator COMP31 outputs the “High” level again. This time, contrary to the above case, the output of the DF 44 is at the “High” level, so that the DF 48 latches the “High” level and the DF 45 at the “Low” level by the next clock pulse of the clock signal CLOCK. Latch. As a result, the outputs of Q48 and Q46 become “High” level, so that a boost pulse appears in the boost pulse signal φ1 by the next clock pulse. The output voltage Vout exceeds the threshold voltage Vth when the charge pump circuit 2 performs the boosting operation again by the boosting pulse. Then, the output of the comparator COMP31 returns to the “Low” level again. By such an operation, the output waveform of the comparator COMP31 becomes the pulse-like waveform shown in the second part of FIG.
[0039]
From the next clock pulse, both the DF 45 and the DF 48 latch the "Low" level, as in the previous clock pulse, and this is shifted. However, the signal latched as the “High” level by the DF 48 disappears after being shifted to the DF 49. Accordingly, in the boost pulse signal φ1 which is the output of Q42, two boost pulses are generated this time as in the second pulse group of (3) in FIG. The value of the output voltage Vout after the boosting by the two boosting pulses is lower than the voltage value after the boosting by the previous three boosting pulses. Therefore, the time T2 until the output voltage Vout decreases due to the boosted output current Iout and becomes equal to or lower than the threshold voltage Vth is shorter than the previous time T1. By such an operation, the output voltage Vout draws a saw-tooth waveform as shown in the second of FIG. 2 (2).
[0040]
After the elapse of the time T2, the output of the DF 44 is again inverted and returns to the first “Low” level state, and the subsequent operation is the same as the operation during the first time T1 described above. By repeating such an operation, the circuit of FIG. 1 performs an operation in which two waveforms of periods T1 and T2 are alternately repeated as shown in the timing chart of FIG. The current noise associated with the boosting operation existing during such an operation process has a waveform as shown in (4) of FIG.
[0041]
Here, the difference between the radio noise due to the current noise waveform in the case of the present embodiment and the radio noise due to the current noise waveform in the case of the conventional circuit shown in FIG. In the case of the conventional circuit, the current noise has a single waveform whose basic period is T1. On the other hand, in the case of the present embodiment, the current noise is a waveform in which two waveforms of the cycle T1 and the cycle T2 are alternately repeated. That is, there are two types of waveforms. However, the frequency of occurrence of each of these waveforms is, on the contrary, half that of the conventional circuit.
[0042]
Considering the noise spectrum of these current noise waveforms, in the case of the conventional circuit, it becomes a spectrum composed of a plurality of harmonics whose basic period is T1. On the other hand, the noise spectrum in the case of the present embodiment is a spectrum in which a spectrum composed of a plurality of harmonics having a fundamental period of T1 and a spectrum composed of a plurality of harmonics having a fundamental period of T2 are combined. That is, the noise spectrum has a shape having two peaks.
[0043]
Since the noise spectrum has two peaks, in the case of the present embodiment, the width of the frequency band having a noise level equal to or higher than a certain level is slightly wider than that of the conventional circuit. However, on the contrary, the noise level of each peak is lower than the case of one peak in the conventional circuit because the frequency of occurrence of each waveform is reduced to half. For this reason, in the case of the booster circuit of the present embodiment, since the frequency of the noise is dispersed and the amplitude is reduced, a good result is obtained in that the radio noise is reduced as compared with the conventional circuit.
[0044]
In the above description, it has been assumed that the load current Iout is constant. This is because radio noise occurs most strongly when the load current Iout is constant. When the load current Iout fluctuates, after the output voltage Vout is boosted, the time from when the output voltage Vout is discharged until it becomes lower than the threshold voltage Vth again fluctuates. That is, the values of the periods T1 and T2 in which the current noise occurs vary. This means that the noise spectrum of the current noise is further dispersed, and the radio noise is further reduced as compared with the case where the load current Iout is constant.
[0045]
Further, in the case of the booster circuit shown in FIG. 1 of the present embodiment, a 3-bit and 2-bit shift register is adopted as the shift registers 42 and 43. However, the number of bits of the shift register is not limited to this, and may be different from these. However, if the two shift registers have the same number of bits, the operation becomes the same as that of the conventional circuit. Further, it is preferable that the number of bits of the shift register having the larger number of bits is not an integer multiple of the number of bits of the smaller number, from the viewpoint of avoiding overlapping of harmonic components.
[Brief description of the drawings]
FIG. 1 is an electrical configuration diagram of a booster circuit according to an embodiment of the present invention.
FIG. 2 is a timing chart of main signals of the circuit shown in FIG. 1;
FIG. 3 is a diagram corresponding to FIG. 1 showing a conventional technique.
FIG. 4 is a diagram corresponding to FIG. 2, showing a conventional technique.
[Explanation of symbols]
In the drawing, 1 is a charge pump type booster circuit, 2 is a charge pump circuit, 3 is a comparator circuit, 4 is a boost pulse generating circuit, 31 is a reference voltage generating circuit, 41 is a clock pulse generating circuit, and 42 is a first shift register , 43 are second shift registers, DF41 to DF49 are D-type flip-flops, COMP31 is a comparator, Vout is an output voltage, Vref is a reference voltage, Vf is a feedback voltage, Vin is an external power supply voltage, Iout is an output current, and CLOCK is an output current. The clock signal φ1 indicates a boost pulse signal.

Claims (2)

A charge pump circuit that receives a boost pulse to boost an external power supply voltage, a comparator circuit that detects that the output voltage boosted by the charge pump circuit has dropped below a predetermined threshold voltage, and outputs a detection signal, A boosting pulse generating circuit that receives the detection signal of the comparator circuit and generates the boosting pulse, wherein the boosting pulse generating circuit receives the detection signal of the comparator circuit. A charge pump type booster circuit characterized in that the minimum number of the boost pulses generated in the step (c) is different from the minimum number of the boost pulses generated when the previous detection signal is received. A charge pump type booster circuit including a charge pump circuit, a comparator circuit, and a boost pulse generating circuit,
The charge pump circuit is a circuit configured to boost an external power supply voltage by receiving a boost pulse from the boost pulse generating circuit,
The comparator circuit compares the output voltage boosted by the charge pump circuit with a predetermined threshold voltage, and outputs an active signal when the output voltage is lower than the threshold voltage. A circuit configured to output an inactive signal when the voltage is higher than the threshold voltage,
The boosting pulse generation circuit is a circuit that receives the output signal of the comparator circuit and generates the boosting pulse, and stores information latched by a first-stage flip-flop in synchronization with a clock pulse generated by an internal clock pulse generation circuit. First and second shift registers having different numbers of bits to be shifted, and a flip-flop whose output state is inverted each time an active signal is received from the comparator circuit, wherein the output of the flip-flop is inactive and the comparator circuit is inactive. When the output of the flip-flop is in the active state, the first shift register latches the active signal, and the second shift register latches the inactive signal in synchronization with the clock pulse. When the output of the comparator circuit is in the active state The first shift register is configured to latch an inactive signal, the second shift register is configured to latch an active signal in synchronization with the clock pulse, and any one of the first and second shift registers A charge pump type booster circuit comprising: a circuit configured to generate the boost pulse in synchronization with the clock pulse when a bit output is active.

Images