CN106067787B - Clock generation circuit applied to charge pump system - Google Patents
Clock generation circuit applied to charge pump system Download PDFInfo
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- CN106067787B CN106067787B CN201610566318.5A CN201610566318A CN106067787B CN 106067787 B CN106067787 B CN 106067787B CN 201610566318 A CN201610566318 A CN 201610566318A CN 106067787 B CN106067787 B CN 106067787B
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- 101100113692 Caenorhabditis elegans clk-2 gene Proteins 0.000 claims description 18
- 101100508840 Daucus carota INV3 gene Proteins 0.000 claims description 16
- 101150070189 CIN3 gene Proteins 0.000 claims description 14
- 101100003180 Colletotrichum lindemuthianum ATG1 gene Proteins 0.000 claims description 14
- 101100286980 Daucus carota INV2 gene Proteins 0.000 claims description 9
- 101100397045 Xenopus laevis invs-b gene Proteins 0.000 claims description 9
- 101150110971 CIN7 gene Proteins 0.000 claims description 6
- 101150110298 INV1 gene Proteins 0.000 claims description 6
- 101100397044 Xenopus laevis invs-a gene Proteins 0.000 claims description 6
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/04—Shaping pulses by increasing duration; by decreasing duration
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/14—Arrangements for reducing ripples from DC input or output
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of DC power input into DC power output
- H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
- H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
- H02M3/06—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
- H02M3/073—Charge pumps of the Schenkel-type
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
- H03K3/03—Astable circuits
- H03K3/0315—Ring oscillators
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of DC power input into DC power output
- H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
- H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
- H02M3/06—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
- H02M3/073—Charge pumps of the Schenkel-type
- H02M3/077—Charge pumps of the Schenkel-type with parallel connected charge pump stages
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Manipulation Of Pulses (AREA)
Abstract
The invention discloses a clock generation circuit applied to a charge pump, which comprises a bias circuit, a ring oscillator, a duty cycle adjusting circuit, a latch processing circuit and a buffer stage, wherein the bias circuit is connected with the ring oscillator; the bias circuit is used for generating a bias voltage of the ring oscillator. The ring oscillator is formed by connecting odd oscillating units end to end, and can adopt a current starvation type ring oscillator. The duty cycle adjustment circuit can process the clock signal clk0 generated by the ring oscillator, and adjust the duty cycle to 50%, and can be implemented by using a D flip-flop. When the enabling signal is high, the latch processing circuit can generate two paths of clock signals with 50% duty ratio and complementary phases; when the enabling signal is changed from high to low, the latch processing circuit can latch the state of the clock generating circuit at the moment before the clock generating circuit stops working, so that the problems that the clock duty ratio is locally distorted, the output current is in burrs and the output voltage ripple is increased due to the fact that the output clock signal is pulled up to a power supply or pulled down to the ground are avoided.
Description
[ field of technology ]
The invention relates to a clock generation circuit applied to a charge pump system.
[ background Art ]
The charge pump is used for obtaining an internal voltage higher than a power supply voltage, and is widely applied to chips such as memories and display drivers. The charge pump system mainly comprises a clock generating circuit, a charge pump and a voltage regulator. In order to effectively suppress the ripple of the output voltage, two charge pumps are generally used for performing a time-sharing ping-pong operation, as shown in fig. 1.
The level inputs VIN of the charge pump 1 and the charge pump 2 are both connected to the power supply voltage vext, the clock input CK of the charge pump 1 receives an oscillation signal Clk, and the clock input CK of the charge pump 2 receives another oscillation signal Clkn. The oscillation signals Clk and Clkn have a duty ratio of 50% and are diametrically opposite in phase. The output terminals of both charge pump 1 and charge pump 2 are connected to an output signal Vout. The sum of the output current iout1 of the charge pump 1 and the output current iout2 of the charge pump 2 is the total output current iout_total. The output signal Vout can be output to the capacitor C and the load.
When the oscillation signals Clk and Clkn are maintained at a fixed level, the output signal Vout gradually falls; conversely, when the oscillation signals Clk and Clkn change at high and low levels, the output signal Vout can be gradually increased according to the rising edges (rising edges) of the oscillation signals Clk and Clkn.
The voltage regulator generally includes a voltage divider circuit (voltage dividing circuit) composed of a resistor R1 and a resistor R2 and a comparator (comparator). The voltage dividing circuit receives the output signal Vout and generates a feedback signal Vfb; the negative input of the comparator receives the feedback signal Vfb, the positive input receives the reference voltage Vref, and the output generates the control signal en_osc, as shown in fig. 2.
The enable terminal of the clock generation circuit is connected to the control signal en_osc to generate clock signals Clk and Clkn required for the operation of the charge pump.
When the conventional clock generation circuit stops operating, the output clock signals Clk and Clkn are pulled up to the power supply (high level) or pulled down to the ground (low level). This may locally distort the duty cycle of the clock signal, thereby generating a glitch on the output voltage Vout and increasing the output ripple. In the following, when the clock generation circuit stops operating, the output clock signal Clk is pulled down to ground (low level), and Clkn is pulled up to power supply (high level), for example.
As shown in fig. 3A, if the output signal Clk of the clock generation circuit is at a low level and Clkn is at a high level before the enable signal en_osc is changed from high to low, the clock signal Clk continues to be kept at a low level and Clkn continues to be kept at a high level after the enable signal en_osc is changed from high to low, and at this time, neither of the Clk and Clkn signals has a local distortion of the duty ratio. During the period when the enable signal en_osc is high and changes from high to low, the charge pump 1 and the charge pump 2 always output current pulses every other clock cycle. The current pulse always occurs every half clock cycle on the total output current iout_total.
As shown in fig. 3B, if the output signal Clk of the clock generation circuit is at a high level and Clkn is at a low level before the enable signal en_osc is changed from high to low, the clock signal Clk is pulled down to a low level and Clkn is pulled up to a high level after the enable signal en_osc is changed from high to low, and at this time, the Clk and Clkn signals are inverted again since half a period has not been reached since the last inversion, so that a local distortion occurs in the duty ratio. During the period when the enable signal en_osc is at a high level and changes from a high level to a low level, the charge pump 2 does not always output a current pulse every other clock cycle, and a current pulse is output again after less than one clock cycle from the last output current pulse, and after the current pulse is overlapped with the output current iout1 of the charge pump 1, a glitch appears on the total output current iout_total, which will cause a voltage glitch on the output signal Vout, so that the ripple thereof is increased.
In the above, when the clock generation circuit stops operating, the output clock signal Clk is pulled down to ground (low level), and Clkn is pulled up to the power supply (high level). For the case where the output clock signal Clk is pulled up to the power supply (high level) and Clkn is pulled down to the ground (low level) when the clock generation circuit stops operating, similar to this.
[ invention ]
The invention aims to solve the problem that the output voltage ripple is increased due to the existing circuit, and provides a clock generating circuit applied to a charge pump system, which can avoid the increase of the output voltage ripple caused by the local distortion of the clock duty ratio.
In order to achieve the above purpose, the invention is realized by adopting the following technical scheme:
a clock generation circuit for a charge pump, the clock generation circuit comprising:
a bias circuit for generating a bias voltage of the ring oscillator;
the ring oscillator is formed by connecting odd oscillating units end to end and generates a clock signal clk0;
a duty ratio adjustment circuit for processing the clock signal clk0 generated by the ring oscillator and adjusting the duty ratio to 50%;
a buffer stage generating complementary clock signals clk and clkn and enhancing their driving capabilities;
the latch processing circuit inverts the clock signal clk1 with the adjusted duty ratio and outputs a clock signal clk2 when the enable signal En_osc of the clock generating circuit is at a high level; when the enable signal en_osc of the clock generation circuit changes from high level to low level, the state latch at the previous time is changed and then the clock signal clk2 is outputted.
The invention is further improved in that:
the ring oscillator adopts a current starvation type ring oscillator.
The duty cycle adjustment circuit adjusts the duty cycle of the clock signal clk0 to 50% using a D flip-flop.
The latch processing circuit includes a transmission gate TG1, a transmission gate TG2, an inverter INV1, an inverter INV2, an inverter INV3, and an inverter INV4; the output end of the duty ratio adjusting circuit is connected with the input end of the transmission gate TG1, and the output end of the transmission gate TG1 is respectively connected with the input end of the inverter INV3 and the output end of the transmission gate TG 2; the output end of the inverter INV3 is divided into two paths, one path is the output end of the latch processing circuit, the clock signal clk2 is output, the other path is connected with the input end of the inverter INV4, and the output end of the inverter INV4 is connected with the input end of the transmission gate TG 2; the enabling signal En_osc is divided into three paths through an inverter INV1, wherein the first path is connected with an inversion control end of a transmission gate TG1, the second path is connected with an input end of an inverter INV2, and the third path is connected with a control end of the transmission gate TG 2; the output end of the inverter INV2 is divided into two paths, one path is connected with the control end of the transmission gate TG1, and the other path is connected with the inversion control end of the transmission gate TG 2.
When the transmission gate TG2 is turned on, the inverter INV3, the inverter INV4, and the transmission gate TG2 constitute a latch in which the state immediately before the enable signal en_osc is changed from the high level to the low level is held and output to the buffer stage.
The buffer stage comprises an inverter INV5, an inverter INV6 and an inverter INV7, wherein a clock signal clk2 is respectively connected with the input ends of the inverter INV5 and the inverter INV6, the output end of the inverter INV5 outputs the clock signal clk, the output end of the inverter INV6 is connected with the input end of the inverter INV7, and the output end of the inverter INV7 outputs the clock signal clkn.
Compared with the prior art, the invention has the following beneficial effects:
the invention adopts a latch processing circuit composed of two transmission gates and a plurality of inverters, when the enabling signal is high, two paths of clock signals with 50% duty ratio and complementary phases can be generated; when the enabling signal is changed from high to low, the state of the clock generating circuit at the moment before the clock generating circuit stops working can be latched, so that the problems that the clock duty ratio is locally distorted, the output current is in burrs and the output voltage ripple is increased due to the fact that the output clock signal is pulled up to a power supply or pulled down to the ground are avoided.
[ description of the drawings ]
FIG. 1 is a schematic circuit diagram of a prior art charge pump system;
FIG. 2 is a schematic circuit diagram of a voltage regulator in a prior art charge pump;
fig. 3A is a waveform diagram of an operation of the conventional clock generation circuit under the condition that the clock signal Clk is low level when the enable signal en_osc is changed from high to low;
fig. 3B is a waveform diagram of an operation of the conventional clock generation circuit under the condition that the clock signal Clk is at a high level when the enable signal en_osc is changed from high to low;
FIG. 4 is a schematic circuit diagram of the present invention;
fig. 5A is a waveform diagram of the operation of the clock generation circuit of the present invention under the condition that the clock signal clk1 is low when the enable signal en_osc is changed from high to low;
fig. 5B is a waveform chart of the operation of the clock generation circuit of the present invention under the condition that the clock signal clk1 is at the high level when the enable signal en_osc is changed from high to low.
[ detailed description ] of the invention
The invention is described in further detail below with reference to the attached drawing figures:
referring to fig. 4, the present invention includes a bias circuit, a ring oscillator, a duty cycle adjustment circuit, a latch processing circuit, and a buffer stage; the output end of the bias circuit is connected with the bias voltage input end of the ring oscillator, the output end of the ring oscillator is connected with the input end of the duty cycle adjusting circuit, the output end of the duty cycle adjusting circuit is connected with the input end of the latch processing circuit, the output end of the latch processing circuit is connected with the input end of the buffer stage, and the two output ends of the buffer stage respectively output a clock signal clk and a clock signal clkn. The bias circuit is used for generating a bias voltage of the ring oscillator. The ring oscillator is formed by connecting odd oscillating units end to end, generates a clock signal clk0, and can adopt a current starvation type ring oscillator. The duty cycle adjustment circuit can process the clock signal clk0 generated by the ring oscillator, and adjust the duty cycle to 50%, and can be implemented by using a D flip-flop. The buffer stage is used to generate and enhance the driving capabilities of the complementary clock signals clk and clkn.
The latch processing circuit includes a transmission gate TG1, a transmission gate TG2, an inverter INV1, an inverter INV2, an inverter INV3, and an inverter INV4. The output end of the duty ratio adjusting circuit is connected with the input end of the transmission gate TG1, and the output end of the transmission gate TG1 is respectively connected with the input end of the inverter INV3 and the output end of the transmission gate TG 2; the output end of the inverter INV3 is divided into two paths, one path is the output end of the latch processing circuit, the clock signal clk2 is output, the other path is connected with the input end of the inverter INV4, and the output end of the inverter INV4 is connected with the input end of the transmission gate TG 2; the enabling signal En_osc is divided into three paths through an inverter INV1, wherein the first path is connected with an inversion control end of a transmission gate TG1, the second path is connected with an input end of an inverter INV2, and the third path is connected with a control end of the transmission gate TG 2; the output end of the inverter INV2 is divided into two paths, one path is connected with the control end of the transmission gate TG1, and the other path is connected with the inversion control end of the transmission gate TG 2. When the enable signal en_osc of the clock generating circuit is at a high level, the latch processing circuit inverts the clock signal clk1 with the duty ratio adjusted and outputs the clock signal clk2. When the enable signal en_osc of the clock generating circuit is changed from high level to low level, the latch processing circuit latches the state before the change, and outputs the state to obtain the clock signal clk2.
The buffer stage comprises an inverter INV5, an inverter INV6 and an inverter INV7, wherein the clock signal clk2 is respectively connected with the input ends of the inverter INV5 and the inverter INV6, the output end of the inverter INV5 outputs the clock signal clk, the output end of the inverter INV6 is connected with the input end of the inverter INV7, and the output end of the inverter INV7 outputs the clock signal clkn.
The specific working process of the invention is as follows:
the bias circuit provides bias voltage osc_bias required by the ring oscillator; the ring oscillator generates a clock signal clk0 under the action of the bias voltage osc_bias; the clock signal clk0 is used as an input of a duty ratio adjusting circuit, and the duty ratio adjusting circuit outputs a clock signal clk1 after adjusting the duty ratio to 50%; the clock signal clk1 is used as an input signal of the latch processing circuit; when the enable signal En_osc of the clock generating circuit is at a high level, the transmission gate TG1 is turned on, the transmission gate TG2 is turned off, the clock signal clk1 is output after passing through the transmission gate TG1 and the inverter INV3, and the output signal is clk2; when the enable signal en_osc of the clock generation circuit is at a low level, the transmission gate TG1 is turned off, and the transmission channel of the clock signal clk1 is cut off. However, the transmission gate TG2 is turned on, the inverter INV3, the inverter INV4, and the transmission gate TG2 form a latch, and the enable signal en_osc is stored in the latch and outputted from the state immediately before the high level is changed to the low level, and the output signal clk2 is outputted. The buffer stage inverts the clock signal clk2 through the inverter INV5 and outputs the clock signal clk; the clock signal clk2 is outputted through the inverters INV6 and INV7 to generate the clock signal clkn.
Fig. 5A and 5B are waveforms in the operation of the present invention, when the enable signal en_osc is at a high level, the latch is not formed, and the clock signal clk1 is normally transmitted through the transmission gate TG1 and the inverters INV3, INV5, INV6, and INV7 and generates the clock signals clk and clkn.
When the enable signal en_osc changes from high to low, if the clock signal clk1 is at low, the clock signal clk1 continues to maintain low due to being pulled down after the en_osc changes to low, at which time the inverter INV3, the inverter INV4 and the transmission gate TG2 already form a latch, the clock signal clk2 is latched at high by the latch, the clock output signal clk maintains low and the clkn maintains high, as shown in fig. 5A.
When the enable signal en_osc changes from high to low, if the clock signal clk1 is at high, the clock signal clk1 becomes low after en_osc is pulled down, at which time the inverter INV3, the inverter INV4 and the transmission gate TG2 already constitute a latch, the clock signal clk2 is latched at low by the latch, the clock output signal clk remains at high and the clkn remains at low, as shown in fig. 5B.
After the enable signal en_osc changes from high level to low level, the duty ratios of the output clock signals clk and clkn are not locally distorted, so that no extra glitch is generated and no output voltage ripple is increased.
The above is only for illustrating the technical idea of the present invention, and the protection scope of the present invention is not limited by this, and any modification made on the basis of the technical scheme according to the technical idea of the present invention falls within the protection scope of the claims of the present invention.
Claims (4)
1. A clock generation circuit for a charge pump, the clock generation circuit comprising:
a bias circuit for generating a bias voltage of the ring oscillator;
the ring oscillator is formed by connecting odd oscillating units end to end and generates a clock signal clk0; the ring oscillator adopts a current starvation type ring oscillator;
a duty ratio adjustment circuit for processing the clock signal clk0 generated by the ring oscillator and adjusting the duty ratio to 50%;
a buffer stage generating complementary clock signals clk and clkn and enhancing their driving capabilities;
the latch processing circuit inverts the clock signal clk1 with the adjusted duty ratio and outputs a clock signal clk2 when the enable signal En_osc of the clock generating circuit is at a high level; when the enable signal En_osc of the clock generating circuit is changed from high level to low level, the state latch at the previous moment is changed and then the clock signal clk2 is output;
the latch processing circuit includes a transmission gate TG1, a transmission gate TG2, an inverter INV1, an inverter INV2, an inverter INV3, and an inverter INV4; the output end of the duty ratio adjusting circuit is connected with the input end of the transmission gate TG1, and the output end of the transmission gate TG1 is respectively connected with the input end of the inverter INV3 and the output end of the transmission gate TG 2; the output end of the inverter INV3 is divided into two paths, one path is the output end of the latch processing circuit, the clock signal clk2 is output, the other path is connected with the input end of the inverter INV4, and the output end of the inverter INV4 is connected with the input end of the transmission gate TG 2; the enabling signal En_osc is divided into three paths through an inverter INV1, wherein the first path is connected with an inversion control end of a transmission gate TG1, the second path is connected with an input end of an inverter INV2, and the third path is connected with a control end of the transmission gate TG 2; the output end of the inverter INV2 is divided into two paths, one path is connected with the control end of the transmission gate TG1, and the other path is connected with the inversion control end of the transmission gate TG 2.
2. The clock generation circuit for a charge pump according to claim 1, wherein the duty cycle adjustment circuit adjusts the duty cycle of the clock signal clk0 to 50% using a D flip-flop.
3. The clock generation circuit according to claim 1, wherein when the transmission gate TG2 is turned on, the inverter INV3, the inverter INV4, and the transmission gate TG2 constitute a latch in which a state immediately before the enable signal en_osc is changed from the high level to the low level is held and output to the buffer stage.
4. The clock generation circuit for a charge pump according to claim 1 or 3, wherein the buffer stage comprises an inverter INV5, an inverter INV6 and an inverter INV7, the clock signal clk2 is connected to the input terminals of the inverter INV5 and the inverter INV6, the output terminal of the inverter INV5 outputs the clock signal clk, the output terminal of the inverter INV6 is connected to the input terminal of the inverter INV7, and the output terminal of the inverter INV7 outputs the clock signal clkn.
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| CN106887245A (en) * | 2017-01-04 | 2017-06-23 | 上海华虹宏力半导体制造有限公司 | Charge pump clock controls circuit and method |
| CN107528582A (en) * | 2017-08-31 | 2017-12-29 | 广东工业大学 | A kind of power control circuit for RF switch |
| CN110942786B (en) * | 2018-09-21 | 2022-05-03 | 北京兆易创新科技股份有限公司 | Charge pump system and nonvolatile memory |
| CN110943610B (en) * | 2018-09-21 | 2021-04-02 | 北京兆易创新科技股份有限公司 | Charge pump system and nonvolatile memory |
| CN111490664B (en) * | 2019-01-29 | 2021-07-06 | 合肥格易集成电路有限公司 | Driving circuit |
| CN111613257B (en) * | 2020-05-29 | 2022-07-15 | 西安紫光国芯半导体有限公司 | Gating circuit and method for multi-phase clock signals and electronic equipment |
| CN114884492B (en) * | 2022-06-01 | 2024-07-19 | 北京大学 | Gm-CCO type-based comparator circuit applied to analog-to-digital converter |
| CN115940631B (en) * | 2023-01-10 | 2023-11-17 | 中茵微电子(南京)有限公司 | Low ripple charge pump circuit |
| CN116599499B (en) * | 2023-07-18 | 2024-01-30 | 芯天下技术股份有限公司 | Clock output method, circuit and chip |
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|---|---|---|---|---|
| JPH11243327A (en) * | 1998-02-25 | 1999-09-07 | Hitachi Ltd | Pulse duty correction circuit |
| CN104539286A (en) * | 2014-12-10 | 2015-04-22 | 深圳市国微电子有限公司 | Fundamental frequency clock generation circuit |
| CN205811975U (en) * | 2016-07-18 | 2016-12-14 | 西安紫光国芯半导体有限公司 | It is applied to the clock generation circuit of charge pump system |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106067787A (en) | 2016-11-02 |
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