JP2004077749A - Liquid crystal display - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To strengthen an electric field between a pixel electrode and a counter electrode without increasing electric potential between the pixel electrode and the counter electrode. <P>SOLUTION: A pair of electrodes are disposed adjacent to a pixel region of the surface on a liquid crystal side of one substrate of respective substrates disposed opposite to each other via a liquid crystal. The one electrode and the other electrode are formed at an upper layer and a lower layer of an insulating layer, respectively, and the other electrode is laminated together with an another layer by using the other electrode as an upper layer. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display device called a so-called in-plane switching method.
[0002]
[Prior art]
In a liquid crystal display device called a horizontal electric field method, an electric field is generated between a pixel electrode and a pixel electrode in a pixel region on a liquid crystal side surface of one of the substrates arranged to face each other with liquid crystal interposed therebetween. An opposing electrode is disposed, and the liquid crystal behaves by a component of the electric field that is substantially parallel to the substrate.
[0003]
The one applied to the active matrix type is such that, on the liquid crystal side surface of the one substrate, a plurality of juxtaposed gate signal lines and a plurality of juxtaposed gate signal lines intersecting each of the gate signal lines. Each region surrounded by the drain signal line is a pixel region, and each pixel region has a switching element operated by a scanning signal from a gate signal line, and a switching element from the drain signal line via the switching element. The pixel electrode to which a video signal is supplied and the counter electrode to which a reference signal is supplied via a counter voltage signal line are formed.
[0004]
In this case, the pixel electrode and the counter electrode are formed in different layers because the respective signals are supplied through signal lines crossing each other, and one electrode is formed on an insulating layer. Usually, the other electrode is formed in the lower layer.
[0005]
[Problems to be solved by the invention]
However, in the liquid crystal display device configured as described above, an insulating layer exists on a line connecting the pixel electrode and the counter electrode, and the distance between the pixel electrode and the counter electrode is relatively large. Had been lost.
[0006]
For this reason, the electric field between the pixel electrode and the counter electrode is weakened by the insulating layer, and inconveniences such as the need to increase the potential difference between the pixel electrode and the counter electrode to strengthen the electric field occur. I was
[0007]
The present invention has been made based on such circumstances, and an object of the present invention is to increase an electric field between a pixel electrode and a counter electrode without increasing a potential difference between the pixel electrode and the counter electrode. It is to provide a liquid crystal display device which can be used.
[0008]
[Means for Solving the Problems]
The following is a brief description of an outline of typical inventions disclosed in the present application.
[0009]
Means 1.
In the liquid crystal display device according to the present invention, for example, a pair of electrodes disposed adjacent to a pixel region on a liquid crystal side surface of one of the substrates disposed opposite to each other with a liquid crystal interposed therebetween has an insulating layer on one side. Formed on the upper layer on the other side and on the other side,
Among them, the other electrode is characterized in that it is formed by laminating the other electrode on the other layer.
[0010]
Means 2.
The liquid crystal display device according to the present invention is, for example, based on the configuration of the means 1, wherein the insulating layer is formed of an organic material layer.
[0011]
Means 3.
The liquid crystal display device according to the present invention is, for example, based on the configuration of Means 1, characterized in that the insulating layer is composed of multiple layers, at least one of which is formed of an organic material layer.
[0012]
Means 4.
The liquid crystal display device according to the present invention includes, for example, a plurality of gate signal lines arranged side by side on a liquid crystal side surface of one of the substrates arranged to face each other with the liquid crystal intersecting the gate signal lines. Forming a plurality of drain signal lines arranged side by side,
In each region surrounded by these signal lines, a thin film transistor operated by a scanning signal from a gate signal line, a pixel electrode to which a video signal from a drain signal line is supplied via the thin film transistor, and an adjacent pixel electrode And a counter electrode arranged as
The pixel electrode is formed below the insulating layer, and the counter electrode is formed above the insulating layer,
In addition, the pixel electrode is formed by being stacked on the same material layer as a semiconductor layer constituting the thin film transistor, with the pixel electrode as an upper layer.
[0013]
Means 5.
The liquid crystal display device according to the present invention is, for example, based on the configuration of the means 4, wherein the insulating layer is formed of an organic material layer.
[0014]
Means 6.
The liquid crystal display device according to the present invention is, for example, on the premise of the constitution of the means 4, characterized in that the insulating layer is composed of multiple layers, at least one of which is formed of an organic material layer.
[0015]
Means 7.
The liquid crystal display device according to the present invention includes, for example, a liquid crystal side surface of one of the substrates arranged to face each other with the liquid crystal interposed therebetween.
A plurality of gate signal lines arranged in parallel, a plurality of drain signal lines arranged in parallel to intersect each of these gate signal lines, and a capacitance signal line arranged between each adjacent gate signal line are formed,
A thin film transistor that is activated by a scanning signal from the gate signal line, a video signal from the drain signal line is supplied through the thin film transistor to each region surrounded by the gate signal line and the drain signal line, and the capacitance signal line And a counter electrode disposed adjacent to the pixel electrode,
The capacitance signal line is formed in the same layer as the gate signal line, and an extension portion for laminating the pixel electrode is formed below the pixel electrode.
[0016]
It should be noted that the present invention is not limited to the above configuration, and various changes can be made without departing from the technical idea of the present invention.
[0017]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the liquid crystal display device according to the present invention will be described with reference to the drawings.
[0018]
Embodiment 1 FIG.
《Overall configuration》
FIG. 2 is a schematic configuration diagram showing one embodiment of the liquid crystal display device according to the present invention. Although the figure is shown by an equivalent circuit, it is drawn corresponding to an actual geometrical arrangement.
[0019]
In FIG. 2, there are a pair of transparent substrates SUB1 and SUB2 which are arranged to face each other via a liquid crystal, and the liquid crystal is sealed by a sealing material SL which also serves to fix one transparent substrate SUB1 to the other transparent substrate SUB2.
[0020]
On the liquid crystal side surface of the one transparent substrate SUB1 surrounded by the sealing material SL, the gate signal lines GL extending in the x direction and juxtaposed in the y direction extend in the y direction and are arranged in the x direction. And the provided drain signal line DL.
[0021]
A region surrounded by each gate signal line GL and each drain signal line DL constitutes a pixel region, and a matrix-like aggregate of these pixel regions constitutes a liquid crystal display part AR.
[0022]
Further, in each of the pixel regions arranged in parallel in the x direction, a common counter voltage signal line CL running in each of the pixel regions is formed. The counter voltage signal line CL is a signal line for supplying a reference voltage for a video signal to a later-described counter electrode CT of each pixel region.
[0023]
Furthermore, a common capacitance signal line StL running in each of the pixel regions arranged in the x direction is formed in each of the pixel regions. The capacitance signal line StL is a signal line for forming a capacitance element Cstg between each pixel region and a later-described pixel electrode PX.
[0024]
In each pixel region, a thin film transistor TFT activated by a scanning signal from one gate signal line GL and a pixel electrode PX to which a video signal from one drain signal line DL is supplied via the thin film transistor TFT are formed. Have been.
[0025]
The pixel electrode PX generates an electric field between the counter voltage signal line CL and the connected counter electrode CT, and the electric field controls the light transmittance of the liquid crystal.
[0026]
Further, the pixel electrode PX forms a capacitance element StL between the pixel electrode PX and the capacitance signal line StL, and the video signal supplied to the pixel electrode PX is accumulated by the capacitance element StL for a relatively long time.
[0027]
One end of each of the gate signal lines GL extends beyond the sealing material SL, and the extending end forms a terminal to which an output terminal of the vertical scanning drive circuit V is connected. The input terminal of the vertical scanning drive circuit V is configured to receive a signal from a printed circuit board disposed outside the liquid crystal display panel.
[0028]
The vertical scanning drive circuit V includes a plurality of semiconductor devices, and a plurality of gate signal lines GL adjacent to each other are grouped, and one semiconductor device is assigned to each group.
[0029]
Similarly, one end of each of the drain signal lines DL extends beyond the sealing material SL, and the extending end forms a terminal to which an output terminal of the video signal driving circuit He is connected. . The input terminal of the video signal drive circuit He is adapted to receive a signal from a printed circuit board arranged outside the liquid crystal display panel.
[0030]
The video signal drive circuit He also includes a plurality of semiconductor devices, and a plurality of drain signal lines DL adjacent to each other are grouped, and one semiconductor device is assigned to each of these groups.
The opposed voltage signal lines CL are commonly connected, for example, at the right end in the drawing, and the connection lines extend beyond the seal material SL, and constitute the terminals CLT at the extending ends. From this terminal CLT, a reference voltage for the video signal is supplied.
[0031]
Further, the capacitance signal line StL is commonly connected, for example, at the right end in the drawing, and the connection line extends beyond the sealing material SL, and constitutes a terminal StLT at the extending end. A constant voltage is supplied from this terminal StLT.
[0032]
One of the gate signal lines GL is sequentially selected by a scanning signal from the vertical scanning circuit V.
Further, a video signal is supplied to each of the drain signal lines DL by a video signal driving circuit He in accordance with a timing of selecting the gate signal line GL.
[0033]
In the above-described embodiment, the vertical scanning drive circuit V and the video signal drive circuit He show the semiconductor device mounted on the transparent substrate SUB1, but, for example, extend between the transparent substrate SUB1 and the printed board. The semiconductor device may be a so-called tape carrier type semiconductor device to be connected. Further, when the semiconductor layer of the thin film transistor TFT is made of polycrystalline silicon (p-Si), the transparent substrate SUB1 is made of the polycrystalline silicon. The semiconductor element may be formed together with the wiring layer.
[0034]
<< Pixel configuration >>
FIG. 1 is a configuration diagram showing one embodiment of the pixel region on the transparent substrate SUB1 side, wherein FIG. 1A is a plan view, and FIG. 1B is a cross-sectional view taken along line bb of FIG. Is shown.
FIG. 2 shows two pixel regions adjacent to each other, which have the same configuration.
First, a pair of gate signal lines GL extending in the x direction and juxtaposed in the y direction are formed on the liquid crystal side surface of the transparent substrate SUB1.
[0035]
These gate signal lines GL surround a rectangular region together with a pair of drain signal lines DL described later, and this region is configured as one pixel region.
Further, a capacitance signal line StL running parallel to the gate signal line GL is formed substantially at the center between the gate signal lines GL. This capacitance signal line StL is formed, for example, simultaneously with the formation of the gate signal line GL.
[0036]
On the surface of the transparent substrate SUB1 on which the gate signal lines GL and the capacitance signal lines StL are formed, an insulating film GI made of, for example, SiN is formed so as to cover the gate signal lines GL and the like.
[0037]
The insulating film GI functions as an interlayer insulating film for the gate signal line GL in a region where a drain signal line DL described later is formed, and functions as a gate insulating film in a region where a thin film transistor TFT described later is formed. It has become.
[0038]
A semiconductor layer AS made of, for example, amorphous Si is formed on the surface of the insulating film GI so as to overlap a part of the gate signal line GL.
[0039]
The semiconductor layer AS is that of a thin film transistor TFT, and is formed by forming a drain electrode SD1 and a source electrode SD2 on the upper surface thereof, thereby forming an inverted staggered MIS (metal insulator semiconductor) having a part of a gate signal line as a gate electrode. Type transistor can be configured.
Here, the drain electrode SD1 and the source electrode SD2 are formed simultaneously with the formation of the drain signal line DL.
[0040]
That is, a drain signal line DL extending in the y-direction and juxtaposed in the x-direction is formed, and a part thereof extends to the upper surface of the semiconductor layer AS to form a drain electrode SD1. The source electrode SD2 is formed to be separated from the electrode SD1 by the channel length of the thin film transistor TFT.
The source electrode SD2 is formed integrally with the pixel electrode PX formed in the pixel region.
[0041]
That is, the pixel electrode PX is formed of an electrode extending substantially in the center of the pixel region in the y direction, and one end of the pixel electrode PX also serves as the source electrode SD2. Note that the pixel electrode PX may be composed of a plurality of electrode groups arranged in parallel in the x direction.
[0042]
Although not shown, a thin layer doped with high-concentration impurities is formed at the interface between the semiconductor layer AS and the drain electrode SD1 and the source electrode SD2, and this layer functions as a contact layer. I have.
[0043]
This contact layer has, for example, a high-concentration impurity layer already formed on the surface thereof when the semiconductor layer SD is formed, and is exposed therefrom using the pattern of the drain electrode SD1 and the source electrode SD2 formed on the upper surface thereof as a mask. It can be formed by etching an impurity layer.
[0044]
Here, the pixel electrode PX has a two-layer structure with a semiconductor layer AS 'formed below the pixel electrode PX. More specifically, the center axis of the semiconductor layer AS 'is substantially coincident with the center axis of the pixel electrode PX, and the width of the semiconductor layer AS' is smaller than the width of the pixel electrode PX. In other words, the semiconductor layer AS 'is formed so as to be covered with the pixel electrode PX.
[0045]
That is, the pixel electrode PX is formed at a position higher than the surface of the transparent substrate SUB1 by the thickness of the semiconductor layer AS 'with the semiconductor layer AS' as a base. The effect of this will be described later.
[0046]
As described above, a protective film PAS made of, for example, SiN is formed on the surface of the transparent substrate SUB1 on which the thin film transistor TFT, the drain signal line DL, the drain electrode SD1, the source electrode SD2, and the pixel electrode PX are formed. This protective film PAS is a film for avoiding direct contact of the thin film transistor TFT with the liquid crystal, and is intended to prevent deterioration of characteristics of the thin film transistor TFT.
[0047]
Then, a protective film OPAS made of an organic material layer such as a resin is further formed on the upper surface of the protective film PAS. The reason for using an organic material layer as the material of the protective film OPAS is to reduce the dielectric constant of the entire protective film together with the protective film PAS and to flatten the surface of the protective film OPAS.
[0048]
Further, a counter electrode CT is formed on the upper surface of the protective film OPAS. The counter electrode CT is composed of a plurality of (two in the figure) electrode groups extending in the y direction and juxtaposed in the x direction, and when viewed in plan, each of the electrodes is the pixel electrode PX. Is positioned in between.
[0049]
That is, the counter electrode CT and the pixel electrode PX are arranged at equal intervals from the drain signal line on one side to the drain signal line on the other side in the order of the counter electrode, the pixel electrode, and the counter electrode.
[0050]
Here, the counter electrodes CT positioned on both sides of the pixel region are formed so as to partially overlap the drain signal line DL, and are formed in common with the corresponding counter electrodes CT of the adjacent pixel region. .
[0051]
In other words, the counter electrode CT is superimposed on the drain signal line DL with their central axes substantially coincident with each other, and the width of the counter electrode CT is formed larger than that of the drain signal line DL. The counter electrode CT on the left side with respect to the drain signal line DL constitutes one of the respective counter electrodes CT in the left pixel region, and the right counter electrode CT constitutes one of the respective counter electrodes CT in the right pixel region. It has become.
[0052]
By forming the counter electrode CT wider than the drain signal line DL above the drain signal line DL, the lines of electric force from the drain signal line DL terminate at the counter electrode CT and the pixel electrode CT There is an effect that termination at the PX can be avoided. This is because, when the electric lines of force from the drain signal line DL terminate at the pixel electrode PX, it becomes noise.
[0053]
Each counter electrode CT composed of an electrode group is formed integrally with a counter voltage signal line CL made of the same material and formed sufficiently over the gate signal line GL, and a reference voltage is applied via the counter voltage signal line CL. Is supplied.
[0054]
The pixel electrode PX partially intersects with the capacitance signal line StL, and at this intersection, a capacitance element Cstg having the insulating film GI as a dielectric film is formed.
[0055]
The capacitive element Cstg has a function of storing a video signal supplied to the pixel electrode PX for a relatively long time, for example.
[0056]
Further, an alignment film (not shown) is formed on the upper surface of the transparent substrate SUB1 on which the counter electrode CT is formed so as to cover the counter electrode CT as well. This alignment film is a film that directly contacts the liquid crystal, and determines the initial alignment direction of the molecules of the liquid crystal by rubbing formed on the surface. Since the alignment film is formed on the surface of the protective film OPAS having a flat surface, the rubbing treatment on the surface can be performed with high reliability.
[0057]
As described above, the liquid crystal display device configured as described above generates an electric field between the pixel electrode PX and the counter electrode CT disposed adjacent to the pixel electrode PX. In this case, the pixel electrode PX is formed at a position higher than the surface of the transparent substrate SUB1 by the thickness of the semiconductor layer AS ', based on the semiconductor layer AS'.
[0058]
This means that the height difference between the counter electrode CT and the counter electrode CT is reduced, and the surface of the protective film OPAS on which the counter electrode CT is formed is formed flat. This means that the amount of the protective film OPAS is reduced in the vicinity of the point where the pixel electrodes PX are linearly connected.
[0059]
For this reason, the amount of the electric field generated between the counter electrode CT and the pixel electrode PX can be reduced by the protection film OPAS, and the intensity of the electric field increases accordingly.
Therefore, the electric field between the pixel electrode and the counter electrode can be increased without increasing the potential difference between the pixel electrode and the counter electrode.
[0060]
Further, as described above, since the pixel electrode PX is formed so as to sufficiently cover the semiconductor layer AS ′ serving as the base, the pixel electrode PX has an inclined surface or an arcuate shape in a portion directed toward the counter electrode CT. Is formed in the vicinity of the counter electrode CT, and the above-described effect can be further enhanced.
[0061]
Embodiment 2. FIG.
FIG. 3 is a configuration diagram showing another embodiment of the liquid crystal display device according to the present invention, and corresponds to FIG.
1 is different from FIG. 1 in that the pixel electrode PX is formed on the semiconductor layer AS ′ as in FIG. 1, but the width of the semiconductor layer AS ′ is larger than the width of the pixel electrode PX. It has been formed.
[0062]
That is, the semiconductor layer AS 'extending in a band shape and the pixel electrode PX formed so as to be superimposed on the semiconductor layer AS' are formed so that their central axes substantially coincide with each other, and the width of the pixel electrode PX is It is formed smaller than the width of the semiconductor layer AS ′.
It is needless to say that the same effect as in the case of FIG. 1 can be obtained even with this configuration.
[0063]
In the case of FIG. 3, a high-concentration impurity layer similar to the contact layer in the thin-film transistor TFT is formed on the surface of the semiconductor layer AS ′ immediately below the pixel electrode PX, and the high-concentration impurity layer is illustrated.
[0064]
Embodiment 3 FIG.
FIG. 4 is a configuration diagram showing another embodiment of the configuration of the pixel of the liquid crystal display device according to the present invention, and corresponds to FIG. 1 or FIG. 4A is a plan view, FIG. 4B is a cross-sectional view taken along line bb of FIG. 4A, and FIG. 4C is a cross-sectional view taken along line cc of FIG. FIG.
[0065]
The configuration different from FIG. 1 or FIG. 3 is that the semiconductor layer AS ′ is formed below the drain signal line DL in addition to the semiconductor layer AS ′ formed below the pixel electrode PX. is there.
[0066]
The pixel electrode PX and the semiconductor layer AS 'are arranged so as to completely overlap each other. In other words, the pixel electrode PX and the side wall surface of the semiconductor layer AS 'have a structure without a step at their boundary.
[0067]
With such a configuration, the same effects as those shown in FIG. 1 or FIG. 3 can be obtained, and the device can be manufactured without increasing the number of steps.
[0068]
Hereinafter, one embodiment of a method of manufacturing the liquid crystal display device having the above-described configuration will be described with reference to FIGS.
In each of FIGS. 5 and 6, reference numerals (a) to (l) denote step diagrams in the cross-sectional view of FIG. 4B, and reference numerals (a ′) to (l ′) denote cross-sectional views of FIG. It shows the process drawing in the figure.
[0069]
Step 1. (FIG. 5 (a), FIG. 5 (a '))
First, after forming a gate signal line GL on the liquid crystal side main surface of the transparent substrate SUB1, the insulating film GI, the semiconductor layer ASI, the high-concentration layer n +, the drain signal line DL, and the like also cover the gate signal line GL. Are sequentially laminated.
[0070]
Step 2. (FIG. 5 (b), FIG. 5 (b '))
A photoresist film PR is formed on the surface of the metal layer SD, and the photoresist film PR is left in a region where the drain signal line DL, the drain electrode SD1 and the source electrode SD2 of the thin film transistor TFT are formed by selective exposure.
[0071]
Step 3. (FIG. 5 (c), FIG. 5 (c '))
Using the remaining photoresist film PR as a mask, the metal layer SD exposed therefrom is selectively etched. Thus, the drain signal line DL, the drain electrode SD1 of the thin film transistor TFT, and the source electrode SD2 are formed. In this case, the drain electrode SD1 and the source electrode SD2 are still connected to each other in the channel region.
[0072]
Step 4. (FIG. 5 (d), FIG. 5 (d '))
Further, using the photoresist film PR as a mask, the high concentration layer n + exposed therefrom is selectively etched, and the semiconductor layer ASI is also selectively etched.
[0073]
Step 5. (FIG. 5 (e), FIG. 5 (e '))
The photoresist film PR is stripped.
[0074]
Step 6. (FIG. 5 (f), FIG. 5 (f '))
A photoresist film PR is newly formed, and the photoresist film is left in a portion other than the channel portion of the thin film transistor TFT by selective exposure.
[0075]
Step 7. (FIG. 6 (g), FIG. 6 (g '))
Using the remaining photoresist film PR as a mask, the metal layer SD in the channel portion of the thin film transistor TFT is selectively etched.
[0076]
Step 8. (FIG. 6 (h), FIG. 6 (h ′))
Further, using the photoresist film PR as a mask, the high concentration layer n + in the channel portion of the thin film transistor TFT is selectively etched. As a result, the high concentration layer n + is formed only at the interface between the patterned metal layer SD and the semiconductor layer ASI. Thus, the drain electrode SD1 and the source electrode SD2 of the thin film transistor TFT are formed separately from each other.
[0077]
Step 9. (FIG. 6 (i), FIG. 6 (i '))
The photoresist film PR is stripped.
[0078]
Step 10. (FIG. 6 (j), FIG. 6 (j '))
A protective film PAS made of, for example, SiN is formed on the entire surface of the transparent substrate SUB1 thus processed.
[0079]
Step 11. (FIG. 6 (k), FIG. 6 (k '))
A protective film OPAS made of, for example, a resin is formed on the upper surface of the protective film PAS.
[0080]
Step 12. (FIG. 6 (l), FIG. 6 (l ′))
The counter electrode CT and the counter voltage signal line CL formed integrally therewith are formed on the upper surface of the protective film OPAS.
[0081]
FIG. 7 is a view showing another embodiment of the method of manufacturing the liquid crystal display device.
In the same figure, reference numerals (a) to (g) denote process drawings in the cross-sectional view of FIG. 4B, and reference numerals (a ′) to (g ′) denote process drawings in the cross-sectional view of FIG. The subsequent steps follow (j) and (j ') in FIG.
[0082]
Step 1. (FIG. 7 (a), FIG. 7 (a '))
First, after forming a gate signal line GL on the liquid crystal side main surface of the transparent substrate SUB1, the insulating film GI, the semiconductor layer ASI, the high-concentration layer n +, the drain signal line DL, and the like also cover the gate signal line GL. Are sequentially laminated.
[0083]
Step 2. (FIG. 7 (b), FIG. 7 (b '))
A photoresist film PR is formed on the surface of the metal layer SD, and the photoresist film PR is left in a region where the drain signal line DL, the drain electrode SD1 and the source electrode SD2 of the thin film transistor TFT are formed by selective exposure.
[0084]
In this case, the selective exposure uses a so-called half-exposure method, and between the respective regions (corresponding to a channel region) in order to form the drain electrode SD1 and the source electrode SD2 of the thin film transistor TFT, the other exposure regions are formed. The exposure amount is different, and as a result, the thickness of the photoresist film PR remaining in the channel region is formed to be smaller than the thickness of the photoresist film PR remaining in other regions.
[0085]
Here, the half exposure is performed, for example, by forming a part of the light shielding film on the photomask surface that completely blocks light and a part that partially transmits light by using the pattern of the light shielding film.
[0086]
Step 3. (FIG. 7 (c), FIG. 7 (c '))
Using the remaining photoresist film PR as a mask, the metal layer SD exposed therefrom is selectively etched. Thus, a drain signal line DL is formed.
[0087]
Step 4. (FIG. 7 (d), FIG. 7 (d '))
Further, using the remaining photoresist film PR as a mask, the high concentration layer n + and the semiconductor layer ASI are selectively etched.
At this time, the photoresist film PR is also slightly etched, so that a channel region between the respective regions for exposing the drain electrode SD1 and the source electrode SD2 of the thin film transistor TFT is exposed from the photoresist film PR.
[0088]
Step 5. (FIG. 7 (e), FIG. 7 (e '))
By using the remaining photoresist film PR as a mask, the metal layer SD in the channel region is etched.
[0089]
Step 6. (FIG. 7 (f), FIG. 7 (f '))
Further, using the remaining photoresist film PR as a mask, the high concentration layer n + in the channel region is etched. Thus, the drain electrode SD1 and the source electrode SD2 are separated.
[0090]
Step 7. (FIG. 7 (g), FIG. 7 (g '))
The photoresist film PR is removed.
[0091]
Embodiment 4. FIG.
8A and 8B are configuration diagrams showing another embodiment of the liquid crystal display device according to the present invention. FIG. 8A is a plan view, FIG. 8B is a cross-sectional view taken along line bb of FIG. 8C is a cross-sectional view taken along line cc of FIG. 8A, and FIG. 8D is a cross-sectional view taken along line dd of FIG. 8A.
[0092]
This figure is basically the same as the structure shown in FIG. 4 except that the pixel electrode PX formed on the semiconductor layer AS is formed in a portion which does not substantially function as the pixel electrode PX in the pixel region. It is not configured.
[0093]
That is, the pixel electrode PX is not formed above the capacitance signal line StL and in a portion extending from the source electrode SD2 of the thin film transistor TFT and overlapping with the counter electrode CT.
[0094]
Further, the semiconductor layer ASI is not formed below the drain signal line DL. In this case, a relatively thick protective film OPAS is interposed between the drain signal line DL and the counter electrode CT superimposed on the drain signal line DL. This has the effect of reducing the dielectric constant.
[0095]
9 to 20 are process diagrams showing one embodiment of a method for manufacturing a liquid crystal display device having such a configuration.
[0096]
Step 1.
First, in FIG. 9, FIG. 9A is a plan view, FIG. 9B is a cross-sectional view taken along line bb of FIG. 9A, and FIG. 9C is cc of FIG. It is sectional drawing in a line.
[0097]
The figure shows that a gate signal line GL, an insulating film GI, a semiconductor layer ASI and a high concentration layer n + on the upper surface thereof are already formed on the surface of the transparent substrate SUB1, and the semiconductor layer ASI and the high concentration layer n + on the upper surface thereof are already formed. Is subjected to collective etching to be patterned.
[0098]
The stacked body of the semiconductor layer ASI and the high concentration layer n + on the upper surface of the semiconductor layer ASI disposed below the pixel electrode PX are separated on the capacitance signal line StL and the gate signal line GL, and formed in the formation region of the thin film transistor TFT. The semiconductor layer ASI and the stacked body of the high concentration layer n + on the upper surface thereof are also formed separately.
[0099]
Step 2.
As shown in FIGS. 10 (b) and 10 (c) corresponding to FIGS. 9 (b) and 9 (c), the semiconductor layer ASI and the high concentration layer on the upper surface thereof are formed on the surface of the transparent substrate SUB1. A metal layer SD is formed so as to cover the n + stacked body, and a photoresist film PR is formed on the surface of the metal layer SD.
[0100]
The photoresist film PR is selectively removed by the metal layer SD so as to serve as a mask for forming the drain signal line DL, the drain electrode SD1 and the source electrode SD2 of the thin film transistor TFT, and the pixel electrode PX.
[0101]
Step 3.
As shown in FIG. 11 corresponding to FIG. 9A, the metal layer SD is selectively etched using the remaining photoresist film PR as a mask.
[0102]
Step 4.
As shown in FIG. 12 drawn corresponding to FIG. 11, the semiconductor layer ASI protruding from the pixel electrode PX and the high-concentration layer on the upper surface thereof are formed using the remaining photoresist film PR as a mask. The n + stacked body is selectively etched.
[0103]
Step 5.
As shown in FIGS. 13B and 13C corresponding to FIGS. 12B and 12C, the photoresist film PR is removed.
[0104]
Step 6.
As shown in FIGS. 14 (b) and 14 (c) corresponding to FIGS. 13 (b) and 13 (c), the drain signal line DL and the drain electrode of the thin film transistor TFT are formed on the surface of the transparent substrate SUB1. A photoresist film PR is formed covering the SD1, the source electrode SD2, and the pixel electrode PX.
Then, the photoresist film PR formed in a region (channel region) between the drain electrode SD1 and the source electrode SD2 of the thin film transistor TFT is selectively removed.
[0105]
Step 7.
As shown in FIGS. 15 (b) and 15 (c) corresponding to FIGS. 14 (b) and 14 (c), the remaining photoresist film PR is used as a mask to form a metal in the channel region. The layer SD is selectively etched.
[0106]
Step 8.
As shown in FIGS. 16 (b) and 16 (c) corresponding to FIGS. 15 (b) and 15 (c), using the remaining photoresist film PR as a mask, the height of the channel region is reduced. The concentration layer n + is selectively etched.
[0107]
Step 9.
As shown in FIGS. 17B and 17C corresponding to FIGS. 16B and 16C, the photoresist film PR is removed.
[0108]
Step 10.
As shown in FIGS. 18B and 18C corresponding to FIGS. 17B and 17C, the drain signal line DL and the drain electrode SD1 of the thin film transistor TFT are formed on the surface of the transparent substrate SUB1. , The source electrode SD2, the pixel electrode PX, and the like, to form a protective film PAS.
[0109]
Step 11.
As shown in FIGS. 19 (b) and 19 (c) corresponding to FIGS. 18 (b) and 18 (c), the surface of the transparent substrate SUB1 is covered with a protective film PAS and is made of an organic material layer. A protective film OPAS is formed.
[0110]
Step 12.
As shown in FIGS. 20B and 20C corresponding to FIGS. 19B and 19C, the counter electrode CT is formed on the surface of the protective film OPAS.
[0111]
21 to 26 are process diagrams showing another embodiment of the method of manufacturing the above-described liquid crystal display device.
[0112]
Step 1.
This embodiment uses so-called half exposure, and FIGS. 21 (b) and 21 (c) correspond to FIGS. 12 (b) and 12 (c), respectively. As shown in the figure, after a gate signal line GL is formed on the main surface of the transparent substrate SUB1 on the liquid crystal side, the insulating film GI, the semiconductor layer ASI, the high concentration layer n +, and the gate signal line GL are also covered. The metal layers SD constituting the drain signal lines DL and the like are sequentially stacked.
[0113]
A photoresist film PR is formed on the surface of the metal layer SD, and the photoresist film PR is left in a region for forming the drain signal line DL, the drain electrode SD1 and the source electrode SD2 of the thin film transistor TFT by half exposure, and the thin film transistor. The thickness of the photoresist film PR remaining in the channel region of the TFT is made smaller than the thickness of the photoresist film PR remaining in other regions.
[0114]
Step 2.
As shown in FIGS. 22 (b) and 22 (c) corresponding to FIGS. 21 (b) and 21 (c), the remaining photoresist film PR is used as a mask, and The metal layer SD is selectively etched. Thus, a drain signal line DL is formed.
[0115]
Step 3.
As shown in FIGS. 23 (b) and 23 (c) corresponding to FIGS. 22 (b) and 22 (c), the semiconductor layer ASI is selectively etched.
[0116]
At this time, the photoresist film PR is also slightly etched, so that a channel region between the respective regions for exposing the drain electrode SD1 and the source electrode SD2 of the thin film transistor TFT is exposed from the photoresist film PR.
[0117]
Step 4.
As shown in FIGS. 24 (b) and 24 (c) corresponding to FIGS. 23 (b) and 23 (c), using the remaining photoresist film PR as a mask, the metal layer in the channel region is used. Etch SD.
[0118]
Step 5.
As shown in FIGS. 25 (b) and 25 (c) corresponding to FIGS. 24 (b) and 24 (c), the remaining photoresist film PR is further used as a mask to form the channel region. The high concentration layer n + is etched. Thus, the drain electrode SD1 and the source electrode SD2 are separated.
[0119]
Step 6.
As shown in FIGS. 26B and 26C corresponding to FIGS. 25B and 25C, the photoresist film PR is removed.
[0120]
Embodiment 5 FIG.
FIG. 27 is a configuration diagram showing another embodiment of the liquid crystal display device according to the present invention, and corresponds to FIG.
[0121]
8 is different from that of FIG. 8 in that the separation part of the pixel electrode PX arranged orthogonal to the capacitance signal line StL on the capacitance signal line StL is formed to extend to both sides of the capacitance signal line StL. It is to be.
Needless to say, the same effect can be obtained by doing so.
9 to 20 or FIGS. 21 to 26, etc., are applied as a method of manufacturing such a liquid crystal display device.
[0122]
Embodiment 6 FIG.
FIG. 28 is a configuration diagram showing another embodiment of the liquid crystal display device according to the present invention, and corresponds to FIG.
1 is different from FIG. 1 in that a part of the capacitance signal line StL extends in a direction orthogonal to the direction in which the capacitance signal line StL extends, and the pixel electrode PX is formed so as to overlap the extended part. Is to be.
[0123]
That is, the extension of the capacitance signal line StL is used as a base when the pixel electrode PX is formed at a position higher than the transparent substrate SUB1.
Therefore, in this embodiment, the semiconductor layer ASI is not used as a base of the pixel electrode PX.
9 to 20 or FIGS. 21 to 26, etc., are applied as a method of manufacturing such a liquid crystal display device.
[0124]
Embodiment 7 FIG.
FIG. 29 is a block diagram showing another embodiment of the liquid crystal display device according to the present invention, and corresponds to FIG.
28 is different from FIG. 28 in that the semiconductor layer ASI is arranged between the capacitance signal line StL formed below the pixel electrode PX and the extending portion thereof.
[0125]
That is, the extension of the capacitance signal line StL and the semiconductor layer ASI are used as a base when the pixel electrode PX is formed at a position higher than the transparent substrate SUB1.
9 to 20 or FIGS. 21 to 26, etc., are applied as a method of manufacturing such a liquid crystal display device.
[0126]
Embodiment 8 FIG.
FIG. 30 is a configuration diagram showing another embodiment of the liquid crystal display device according to the present invention, and corresponds to FIG.
The configuration different from FIG. 8 is that the counter electrode CT is formed in the same layer and integrally with the capacitance signal line StL, and is not formed on the protective film OPAS.
[0127]
That is, the counter electrode CT includes being disposed adjacent to the drain signal line DL in the pixel region, and the counter electrode CT is disposed between the pixel electrode PX and the pixel electrode PX formed on the semiconductor layer AS. An electric field is generated.
Then, the pixel electrode PX is formed by being laminated with the semiconductor layer ASI below the pixel electrode PX, and is positioned higher than the transparent substrate SUB1.
9 to 20 or FIGS. 21 to 26, etc., are applied as a method of manufacturing such a liquid crystal display device.
[0128]
【The invention's effect】
As is apparent from the above description, according to the liquid crystal display device of the present invention, the electric field between the pixel electrode and the counter electrode can be increased without increasing the potential difference between the pixel electrode and the counter electrode. .
[Brief description of the drawings]
FIG. 1 is a configuration diagram showing one embodiment of a pixel of a liquid crystal display device according to the present invention.
FIG. 2 is a schematic configuration diagram showing one embodiment of a liquid crystal display device according to the present invention.
FIG. 3 is a configuration diagram showing another embodiment of the pixel of the liquid crystal display device according to the present invention.
FIG. 4 is a configuration diagram showing another embodiment of the pixel of the liquid crystal display device according to the present invention.
FIG. 5 is a process drawing showing one embodiment of a method of manufacturing a liquid crystal display device according to the present invention, which is used together with FIG.
FIG. 6 is a process drawing showing one embodiment of a method for manufacturing a liquid crystal display device according to the present invention, which is used together with FIG.
FIG. 7 is a process chart showing another embodiment of the method of manufacturing the liquid crystal display device according to the present invention.
FIG. 8 is a configuration diagram showing another embodiment of the pixel of the liquid crystal display device according to the present invention.
FIG. 9 is a process diagram showing one embodiment of a method for manufacturing a liquid crystal display device according to the present invention, which is used together with FIGS. 10 to 20;
FIG. 10 is a process drawing showing one embodiment of a method for manufacturing a liquid crystal display device according to the present invention, which is used together with FIGS. 9, 11 to 20;
FIG. 11 is a process drawing showing one embodiment of a method of manufacturing a liquid crystal display device according to the present invention, which is used together with FIGS. 9, 10, 12 to 20;
FIG. 12 is a process drawing showing one embodiment of a method for manufacturing a liquid crystal display device according to the present invention, which is used together with FIGS. 9 to 11 and FIGS. 13 to 20;
FIG. 13 is a process drawing showing one embodiment of a method for manufacturing a liquid crystal display device according to the present invention, which is used together with FIGS. 9 to 12 and FIGS. 14 to 20;
FIG. 14 is a process drawing showing one embodiment of a method for manufacturing a liquid crystal display device according to the present invention, which is used together with FIGS. 9 to 13 and FIGS. 15 to 20;
FIG. 15 is a process diagram showing one embodiment of a method of manufacturing a liquid crystal display device according to the present invention, which is used together with FIGS. 9 to 14 and FIGS. 16 to 20;
FIG. 16 is a process drawing showing one embodiment of a method of manufacturing a liquid crystal display device according to the present invention, which is used together with FIGS. 9 to 15 and FIGS. 17 to 20;
FIG. 17 is a process drawing showing one embodiment of a method of manufacturing a liquid crystal display device according to the present invention, which is used together with FIGS. 9 to 16 and FIGS. 18 to 20;
FIG. 18 is a process drawing showing one embodiment of a method for manufacturing a liquid crystal display device according to the present invention, which is used together with FIGS. 9 to 17 and FIGS.
FIG. 19 is a process diagram showing one embodiment of a method for manufacturing a liquid crystal display device according to the present invention, which is used together with FIGS. 9 to 18 and 20.
FIG. 20 is a process drawing showing one embodiment of a method for manufacturing a liquid crystal display device according to the present invention, which is used together with FIGS. 9 to 19;
FIG. 21 is a process drawing showing another embodiment of the method of manufacturing the liquid crystal display device according to the present invention, which is used together with FIGS. 22 to 26;
FIG. 22 is a process drawing showing another embodiment of the method of manufacturing the liquid crystal display device according to the present invention, which is used together with FIGS. 21, 23 to 26;
FIG. 23 is a process drawing showing another embodiment of the method of manufacturing the liquid crystal display device according to the present invention, which is used together with FIGS. 21, 22, 24 to 26;
FIG. 24 is a process drawing showing another embodiment of a method of manufacturing a liquid crystal display device according to the present invention, which is used together with FIGS. 21 to 23 and 25 to 26.
FIG. 25 is a process drawing showing another embodiment of a method of manufacturing a liquid crystal display device according to the present invention, which is used together with FIGS. 21 to 24 and 26.
FIG. 26 is a process drawing showing another embodiment of the method of manufacturing the liquid crystal display device according to the present invention, which is used together with FIGS. 21 to 25;
FIG. 27 is a configuration diagram showing another embodiment of the pixel of the liquid crystal display device according to the present invention.
FIG. 28 is a configuration diagram showing another embodiment of the pixel of the liquid crystal display device according to the present invention.
FIG. 29 is a configuration diagram showing another embodiment of the pixel of the liquid crystal display device according to the present invention.
FIG. 30 is a configuration diagram showing another embodiment of the pixel of the liquid crystal display device according to the present invention.
[Explanation of symbols]
SUB1 ... Transparent substrate, GL ... Gate signal line, DL ... Drain signal line, StL ... Capacitance signal line, TFT ... Thin film transistor, SD1 ... Drain electrode, SD2 ... Source electrode, PX ... Pixel electrode CT: counter electrode, GI: insulating film, AS ′, ASI: semiconductor layer, PAS: protective film (inorganic material layer), OPAS: protective film (organic material layer) PR: photoresist film.

Claims (7)

A pair of electrodes arranged adjacent to the pixel region on the liquid crystal side surface of one of the substrates arranged opposite to each other with the liquid crystal interposed therebetween is formed on one side above the insulating layer and on the other side below the insulating layer,
A liquid crystal display device wherein the other electrode is formed by laminating the other electrode on the other electrode. The liquid crystal display device according to claim 1, wherein the insulating layer is formed of an organic material layer. 2. The liquid crystal display device according to claim 1, wherein the insulating layer comprises a plurality of layers, at least one of which is formed of an organic material layer. A plurality of gate signal lines arranged in parallel and a plurality of drain signal lines arranged in parallel with each other on the liquid crystal side surface of one of the substrates opposed to each other with the liquid crystal interposed therebetween. Is formed,
In each region surrounded by these signal lines, a thin film transistor operated by a scanning signal from a gate signal line, a pixel electrode to which a video signal from a drain signal line is supplied via the thin film transistor, and an adjacent pixel electrode And a counter electrode arranged as
The pixel electrode is formed below the insulating layer, and the counter electrode is formed above the insulating layer,
In addition, the liquid crystal display device is characterized in that the pixel electrode is formed by laminating the same with the same material layer as a semiconductor layer forming the thin film transistor with the pixel electrode as an upper layer. The liquid crystal display device according to claim 4, wherein the insulating layer is formed of an organic material layer. 5. The liquid crystal display device according to claim 4, wherein the insulating layer has a multilayer structure, and at least one of the insulating layers is formed of an organic material layer. On the liquid crystal side surface of one of the substrates arranged facing each other via the liquid crystal,
A plurality of gate signal lines arranged in parallel, a plurality of drain signal lines arranged in parallel to intersect each of these gate signal lines, and a capacitance signal line arranged between each adjacent gate signal line are formed,
A thin film transistor that is activated by a scanning signal from the gate signal line, a video signal from the drain signal line is supplied through the thin film transistor to each region surrounded by the gate signal line and the drain signal line, and the capacitance signal line And a counter electrode disposed adjacent to the pixel electrode,
The liquid crystal display device, wherein the capacitance signal line is formed in the same layer as the gate signal line, and an extension for laminating the pixel electrode is formed below the pixel electrode.

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