JP2003536239A - Reduced diffusion of mobile species from metal oxide ceramics - Google Patents

Abstract

(57) Abstract: A barrier layer is provided to prevent diffusion of excess mobile species from the metal oxide ceramic into the substrate. A barrier layer is provided below the metal oxide ceramic and separates the metal oxide ceramic from the underlying substrate.

Description

Detailed Description of the Invention

This invention was filed on Dec. 18, 1998 in a United States Partial Continuation Patent Application entitled "Reduced Degradation of Metal Oxide Ceramics by Diffusion of Mobile Species" (Attorney Docket No. 97P7947US01). is there. This application is December 1, 1997
Claim priority of provisional application USSN 60/068040 filed on 8th.

FIELD OF THE INVENTION The present invention relates generally to metal oxide ceramic films used in integrated circuits (ICs). More specifically, the present invention relates to reducing diffusion of mobile species into a substrate.

[0003] Metal oxide ceramic material of the invention, its use in IC has been studied. For example, a metal oxide ceramic that is or is converted to ferroelectric is
It is useful because of its high remanent polarization (2Pr) and reliable long-term storage properties. Non-ferroelectric metal oxide ceramics such as superconductors have also been investigated.

Various techniques have been developed for depositing ferroelectric films on substrates, such as sol-gel, chemical vapor deposition (CVD), sputtering or pulsed laser deposition (PLD). Such techniques are described, for example, in Bud.
Ceram. Soc. Proc. 36, 107 (1985); Brierley et al., Ferroelectrics, 91, 18
1 page (1989), Takayama et al. Appl. Phys. , Volume 65, 166
Page 6 (1989); Morimoto et al. Jap. Appl. Phys. 318
Vol. 9, page 9296 (1992); and co-pending application entitled "Low Temperature CVD Method Using B-Diketonate Bismuth Precursor for Manufacturing Bismuth Ceramic Thin Films for Incorporation in Ferroelectric Memory Devices". US patent USSN
08/975087, USSN 09/107861, entitled "Amorphous Vapor Deposited Metal Oxide Ceramic Films", all of which are incorporated herein by reference for all purposes.

Metal oxide ceramics are often treated with post-deposition heat treatments at relatively high temperatures to produce the resulting material with the desired electrical properties. For example, some Bi-based oxide ceramics, such as strontium bismuth tantalate (SBT), are thermally treated by "ferroanneal". Ferroannealing transforms the as-deposited film into a ferroelectric phase. In order to achieve a good remanent polarization after the as-deposited film is converted to the ferroelectric phase,
Ferroannealing continues to grow the film grain size (eg, greater than about 180 nm). Other types of metal oxide ceramics can be deposited as ferroelectrics. For example, lead zirconium titanate (PZT) is often 500 ° C.
Evaporation is performed at a relatively high temperature as described above to form an as-deposited film having a ferroelectric perovskite phase. Although PZT is deposited as ferroelectric, post-deposition thermal treatments are often needed to improve its electrical properties.

[0006] Typically, metal oxide ceramics have mobile species. The high temperature of the post-deposition heat treatment causes diffusion of mobile species from the metal oxide ceramic layer. The amount of mobile species that diffuses from the metal oxide ceramic layer is determined by the "excess mobile species (exess mo
The mobile species may be in the form of atoms, molecules or compounds. Diffusion of excess mobile species can have a detrimental effect on yield. The mobile species can easily migrate into other areas of the IC, such as the substrate, during post-deposition heat treatment, which can short circuit and / or alter the electrical properties of other device areas, such as diffusion areas. As explained by the above discussion, it is desirable to offset the detrimental effects caused by the diffusion of excess mobile species from the metal oxide ceramic layer.

SUMMARY OF THE INVENTION The present invention relates to metal oxide ceramic films and their application in ICs. More specifically, the present invention reduces diffusion of excess mobile species from metal oxide ceramics into the substrate.

A barrier layer is provided according to the present invention. The barrier layer serves as a diffusion barrier that reduces or minimizes the diffusion of excess mobile species. In one embodiment, the barrier layer is provided on a substrate that separates the metal oxide ceramic and the substrate.

In one embodiment, the barrier comprises a material that reacts with mobile species. The reaction traps the mobile species and blocks them from passing through the barrier layer. In another embodiment, the barrier layer comprises a dense material to prevent the passage of mobile species. Barrier layers made of amorphous materials or materials with very small grain sizes are also useful. Such materials extend the diffusion path for mobile species, making it more difficult for mobile species to diffuse through.

In other embodiments, the barrier layer has a particle surface that has little or no interesting interaction with mobile species. Also useful are barriers having a particle surface with strong activation energy for strong interaction with and migration of mobile species.

In yet another embodiment, the stoichiometry or composition of the metal oxide ceramic is
It is selected to reduce or minimize the diffusion of mobile species without adversely affecting the electrical properties of the material. Additionally, the deposition parameters of the metal oxide ceramic can be controlled to reduce the diffusion of excess mobile species from the metal oxide ceramic. In one embodiment, the ratio of oxidant to oxidant precursor amount is reduced to reduce migration of mobile species.

[0012] DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the application of metal oxide ceramic films and it of the IC. More specifically, the present invention relates to reducing the adverse effects resulting from the diffusion of excess mobile species from metal oxide ceramics.

For purposes of explanation, the present invention will be described in the context of ferroelectric memory cells and ferroelectric transistors. However, the present invention is generally applicable for forming metal oxide ceramics. Other applications, such as ferroelectric transistors with metal oxide ceramic layers, are also useful. The ferroelectric transistor is, for example, a mirror (Mi
Leller) and McWhorter, “Physics of Ferroelectric Nonvolatile Memory Field Effect Transistors”, J. Am. Appl. Physics
73 (12), 5999-6010 (1992); and co-pending application entitled "Amorphous Vapor Deposited Metal Oxide Ceramic Film" in U.S. Pat. No. USSN 09/107861; These are incorporated herein by reference for all purposes.

Referring to FIG. 1, a schematic diagram of a ferroelectric memory cell 100 is shown. As shown, the memory cell includes a transistor 110 and a ferroelectric capacitor 15
It consists of zero. The first electrode 111 of the transistor is coupled to the bit line 125 and the second electrode 112 is coupled to the capacitor. The gate electrode of the transistor is coupled to word line 126.

The ferroelectric capacitor consists of first and second plates 153 and 157 separated by a ferroelectric layer 155. The first plate 153 is coupled to the second electrode of the transistor. The second plate is typically used as the common plate in the memory array.

A plurality of memory cells are interconnected with word lines and bit lines to form an array in the memory IC. Access to the memory cells is accomplished by supplying the appropriate voltages to the word and bit lines, allowing data to be written or read from the capacitors.

Referring to FIG. 2, a cross section of a ferroelectric memory cell 100 according to one embodiment of the present invention is shown. The memory cell consists of a transistor 110 on a substrate 101 such as a semiconductor wafer. The transistor has diffusion regions 111 and 112 separated by a channel 113, with a gate 114 disposed on the channel. A gate oxide (not shown) separates the gate from the channel. The diffusion region contains a dopant that is p-type or n-type. The type of dopant selected depends on the type of transistor desired. For example, n-type dopants such as arsenic (As) or phosphorus (P) are used for n-channel devices, and p-type dopants such as boron (B) are used for p-channel devices. Depending on the direction of current flow between the diffusion regions, one is called the "drain" and the other is called the "source". The terms "drain" and "source" are used interchangeably herein with respect to the diffusion region. Typically, current flows from the source to the drain. The gate represents the word line and one of the diffusion regions 111 is coupled to the bit line by a contact plug (not shown).

Capacitor 150 is coupled to diffusion region 112 by contact plug 140. The capacitor comprises a bottom electrode 1 separated by a metal oxide ceramic layer 155.
53 and the top electrode 157. The metal-ceramic layer, in one embodiment, consists of or can be converted to a ferroelectric phase. The electrodes are made of a conductive material.

The composition or stoichiometry of the metal oxide ceramic layer can be adapted to cause a reduction in the amount of excess mobile species diffusing from it. By reducing the diffusion of excess mobile species, the metal oxide maintains the correct composition to achieve good electrical properties.

Additionally, the deposition parameters of the metal oxide ceramic can be controlled to reduce the amount of excess mobile species diffusing from the metal oxide ceramic. 1
In an embodiment, the ratio of oxidant to oxidant precursor amount is reduced to reduce diffusion of excess mobile species.

In order to isolate different parts of the memory cell, an inter-level dielectric (int)
An erlevel dielectric (ILD) layer 160 is provided.
The ILD layer consists of a silicate glass such as silicon dioxide (SiO ₂ ) or silicon nitride (Si ₃ N ₄ ). Doped silicate glasses such as borophosphosilicate glass (BPSG) or borosilicate glass (BSG) are also useful. Other types of dielectric materials can also be used.

According to one embodiment of the invention, a barrier layer is provided that acts as a diffusion barrier for excess mobile species. In one embodiment, a barrier layer is provided between the metal oxide ceramic layer and the substrate to reduce or minimize diffusion of excess mobile species into the substrate. The barrier layer is formed, for example, on the ILD around the capacitor to protect the substrate from excess mobile species.

3A-B illustrate a method of forming a memory cell according to one embodiment of the present invention. 3A, a substrate 201 having a partially formed device is shown. As shown, the substrate includes transistor 210. The substrate is, for example, a semiconductor wafer made of silicon. Germanium (Ge), gallium arsenide (G)
Other types of substrates such as aAs) or other semiconductor compounds can also be used. Typically, the substrate is lightly doped with a p-type dopant such as B. More heavily doped substrates are also useful. It is also possible to use a heavily doped substrate with a lightly doped epitaxial (epi) layer, such as a p ⁻ / p ⁺ substrate. N-type doped substrates, including lightly doped substrates, heavily doped substrates or heavily doped substrates with lightly doped epi layers are also useful.

If desired, a doped well 270 containing a dopant is provided to prevent perforation. The doped well is formed by selectively implanting a dopant into the substrate in the region where the transistor will be formed. 1
In an embodiment, the doped well is formed by implanting a p-type dopant such as B into the substrate. The p-type doped well (p-well) is used as the doped well for the n-channel device.
N-type doped wells (n containing, for example, As or P-type dopants)
-Well) is also useful for p-channel devices.

Diffusion regions 211 and 212 are formed by selectively implanting a dopant having a second electrical form into desired portions of the substrate. In one embodiment, an n-type dopant is implanted in the p-well used for the n-channel device,
Shaped dopants are used for p-channel devices. The implant includes a channel region 21 between the diffusion regions to adjust the gate threshold voltage (V _T ) of the transistor.
It is also possible to carry out by injecting the dopant into 3. Formation of diffusion regions after gate formation is also useful.

Various layers are deposited on the substrate and patterned to form gates 214. The gate includes, for example, a gate oxide and a layer of polycrystalline silicon (abbreviated as poly). The poly layer is, for example, doped. In some cases, a metal silicide layer is formed on the doped poly layer to form a polysilicon silicide (abbreviated as polycide) layer to reduce the sheet resistance. Molybdenum silicide (MoSi _x), tantalum silicide (TaSi _x), tungsten silicide _(WSi x), titanium silicide (TiSi _x) or cobalt silicide (CoS
Various metal suicides, including i _x ), are useful. Refractory metals such as aluminum or tungsten and molybdenum can be used alone or in combination with silicides or poly.

The contact plug 220 that couples the diffusion region 211 to the bit line 225 and the contact plug 240 that couples to the diffusion region 212 may be used after the completion of the transistor, for example in various single or double damascene technologies. It can be formed using known techniques. Reactive ion etching (RIE) techniques are also useful. A combination of Damassen and etching techniques can also be used. The contact plug is made of a conductive material such as doped poly or tungsten (W). Other conductive materials are also useful. The bit lines are made of, for example, aluminum (Al) or another form of conductive material. The ILD layer 260 separates different parts of the memory cell.

With reference to FIG. 3B, the method continues to form a strong inductive capacitor.
A conductive electrode barrier layer 251 is deposited on the ILD layer. The electrode barrier blocks the passage of oxygen into the plug. The electrode barrier can prevent or reduce migration of atoms between the contact plug 240 and the subsequently formed bottom electrode. The electrode barrier layer is made of, for example, titanium nitride (TiN). IrSi _x O _y , CeO ₂ Ti
Other materials such as Si ₂ or TaSiN _x are also useful.

A conductive layer 253 is deposited on the electrode barrier layer. The conductive layer 253 is used as the bottom electrode. Preferably, the bottom electrode comprises a conductive material that does not react with the subsequently deposited metal oxide ceramic film. In one embodiment, the bottom electrode comprises a noble metal such as Pt, Pd, Au, Ir or Rh. Other materials such as conducting metal oxides, conducting metal nitrides or superconducting oxides are also useful. Preferably, the conductive metal oxide, conductive metal nitride or superconducting oxide does not react with the ferroelectric layer. The conductive oxide may be, for example, IrO _x , RhO _x , RuO _x , OsO _x , ReO _x or WO _x (where x is greater than about 0,
Less than about 2). Conductive metal nitrides include, for example, TiN _x , Zr
N _x (where x is greater than about 0 and less than about 1.1), WN _x or T
aN _x, where x is greater than about 0 and less than about 1.7. Superconducting oxide, for example _YBa 2 _Cu 2 _{O 7 -} including _{x, Bi 2 Sr 2 Ca 2} Cu 3 O x or _{Bi 2 Sr 2 Ca 1 Cu 2} O y.

The electrode barrier layer and conductive layer are patterned to form a bottom electrode stack 280 that is coupled to the contact studs 240. A metal oxide ceramic layer is formed on the bottom electrode stack. In one embodiment, the metal oxide ceramic consists of or can be converted to a ferroelectric phase.

Sol-gel, chemical vapor deposition (CVD) to form a metal oxide ceramic layer
, Sputtering, pulsed laser deposition (PLD) and evaporation are used. Preferably, the metal oxide ceramic layer is formed by CVD. Preferably, the metal oxide ceramic is deposited by low temperature CVD techniques.
Low temperature technology is described in co-pending application US patent USSN08 entitled "Low Temperature CVD Method Using B-Diketonate Bismuth Precursor to Produce Bismuth Ceramic Thin Films for Integration in Ferroelectric Memory Devices". / 975087, which is incorporated herein by reference for all purposes. More preferably, the metal oxide ceramic layer is deposited in amorphous form using CVD. C
The VD amorphous deposited metal oxide layer is a co-pending application entitled "Amorphous Deposited Metal Oxide Ceramic Film" United States Patent USSN 09/10.
7861 (Attorney Docket No. 98P7422), which is incorporated herein by reference for all purposes.

In one embodiment, the metal oxide ceramic comprises a Bi-based metal oxide ceramic. The Bi-based metal oxide layer is generally represented by Y _a Bi _b X ₂ O _c, where Y represents a divalent cation and X represents a pentavalent cation. 1
In an embodiment Y is equal to one or more elements selected from Sr, Ba, Pb, and Ca, and in one embodiment equal to one or more elements selected from Ta and Nb. The subscript "a" refers to the number of Y atoms for all 2X atoms; the subscript "b" refers to the number of Bi atoms for all 2X atoms; and the subscript "c" refers to all 2X atoms. Regarding the number of oxygen atoms to an atom.

Ferroelectric Bi-based metal oxide ceramics are preferably positively charged Bi.
Oxide layer _{[Bi ²} O ^_2] negatively charged perovskite layers separated by ^{_{2n + [A m - 1 B}} m O 3m - 1] 2 - has a laminated perovskite structure with, in the above formula, A is ^{Bi 3 -, L 3+, L} 2+, Ca 2+, Sr 2+, Ba 2+, Na
^{+ (L = Ce 4+, La} 3+, Pr 3+, Ho 3+, Eu 2+, Ub 2+ metal from lanthanide like) and, B is ^{Fe 3+, Al 3+, Y 3+} , L 3 +, Ti 4+ , Nb ⁵⁺ , Ta ⁵⁺ , W ⁶⁺ , Mo ⁶⁺ , and m is 1, 2
3, 4, and 5.

In one embodiment, the Bi-based oxide ceramic comprises Sr. Sr
Bi-based oxides including and Ta are also useful. Preferably, the Bi oxide consists of SBT, commonly represented by Sr _a Bi _b Ta ₂ O _c . SBT
Can be more particularly represented by, for example, SrBi ₂ Ta ₂ O ₉ . Ferroelectric SBT is a negatively charged S separated by a positively charged Bi oxide layer.
It has a laminated perovskite structure having a perovskite layer of r and Ta oxides. The stoichiometry of Sr and Ta oxide is, for example, [SrTa ₂ O ₇ ] ^{2n −} _n.
And the stoichiometry of the Bi oxide layer is, for example, [Bi ₂ O ₂ ] ^{2n -} _n , and the structure of the alternating [SrTa ₂ O ₇ ] ^{2n -} _n layer and the [Bi ₂ O ₂ ] ^{2n -} _n layer is Occurs.

Derivatives of SBT are also useful. SBT _{derivatives, Sr a Bi b Ta 2 -} x Nb x O c (0 <x <2), Sr a Bi b Nb 2 O c, Sr a Bi b Ta 2 O c, S
_{r a - x Ba x Bi b} Ta 2 - y Nb y O c (0 ≦ x ≦ a, 0 ≦ y ≦ 2), Sr a - x Ca x Bi b Ta 2 - y Nb y O 9 (0 ≦ x _{≦ a, 0 ≦ y ≦ 2} ), Sr a - x Pb x Bi b Ta 2 - y Nb y O c (0 ≦ x ≦ a, 0 ≦ y ≦ 2) or _{Sr a - x - y - z} Ba x Ca _y Pb _z Bi _b Ta _{2 − p} Nb _p O _c (0 ≦ x + y +
z ≦ a, 0 ≦ p ≦ 2). Substitution or doping of Bi-based oxides or SBT derivatives with lanthanide-based metals is also useful.

In another embodiment, the Bi-based oxide ceramic consists of Bi ₄ Ti ₃ O ₁₂ or its derivatives. Derivatives of Bi ₄ Ti ₃ O ₁₂ include, for example, PrBi ₃ Ti ₃ O ₁₂ , HoBi ₃ Ti ₃ O ₁₂ , LaBi ₃ Ti ₃ O ₁₂ , Bi ₃ T.
_{iTaO 9, Bi 3 TiNbO 9,} SrBi 4 Ti 4 O 15, CaBi 4 Ti 4 O 15, BaBi 4 Ti 4 O 15, PbBi 4 Ti 4 O 15, Sr 1 - x - y - z Ca x Ba y Pb z Bi ₄ Ti ₄ O ₁₅ (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦
_{1), Sr 2 Bi 4 Ti} 5 O 18, Ca 2 Bi 4 Ti 5 O 18, Ba 2 Bi 4 T
_{i 5 O 18, Pb 2 Bi} 4 Ti 5 O 18, Sr 2 - x - y - z Ca x Ba y Pb z Bi 5 Ti 4 FeO 18 (0 ≦ x ≦ 2,0 ≦ y ≦ 2,0 ≦ z ≦ 2), SrBi ₅ Ti ₄ FeO ₁₈ , CaBi ₅ Ti ₄ FeO ₁₈ , BaBi ₅ Ti ₄ FeO _{1
8, PbBi 5 Ti 4 FeO 18} , Sr 1 - x - y - z Ca x Ba y Pb z Bi 5 Ti 4 FeO 18 (0 ≦ x ≦ 1,0 ≦ y ≦ 1,0 ≦ z ≦ 1), Bi ₅ Ti ₃ F
eO ₁₅ , LaBi ₄ Ti ₃ FeO ₁₅ , PrBi ₄ Ti ₃ FeO ₁₅ and B
i ₆ Ti ₃ FeO ₁₈ and Bi ₉ Ti ₃ Fe ₅ O ₂₇ are included.

In one embodiment, the Bi-based metal oxide ceramic is deposited by a low temperature CVD technique. In a preferred embodiment, the Bi-based metal oxide is CVD.
Is deposited amorphously. The temperature at which the Bi-based metal oxide is deposited is, for example, about 430 ° C or lower, preferably about 385 to 430 ° C.

The precursors and reactive gases used to form the Bi-based oxide ceramics are described in “Bismuth Ceramics for Integration in Ferroelectric Memory Devices,” filed Nov. 20, 1997. Co-pending application US Pat. No. USSN 08/9750876, entitled "Low Temperature CVD Method Using B-Diketonate Bismuth Precursor for Making Thin Films", filed October 30, 1997.
Anhydrous monocyclic tris (β-diketonate) bismuth composition and process for producing the same, USSN 08/960915; filed June 30, 1998,
USSN, entitled "Amorphous Deposition Metal Oxide Ceramic Film"
09/107861, all of which are incorporated herein by reference for all purposes.

The precursors are individually dissolved in the solvent system and stored in the respective reservoirs of the delivery assistance system. The precursors are mixed in precise proportions prior to vapor deposition. It is also useful to mix the precursors in a single reservoir. The precursor should be highly soluble in the solvent system. The solubility of the precursor in the solvent system is, for example, about 0.1-5 mol. About 0.
Solubility of 1-2 or 0.1-1 mol is also useful.

The composition of the Bi-based metal oxide can be adapted to reduce the diffusion of mobile species. Mobile species of Bi-based metal oxide ceramics include, for example, B
i or Bi such as Bi ₂ O ₃ . Experiments have shown that the composition of the Bi-based metal oxide ceramic layer affects the amount of mobile species (Bi) diffusing from the layer. In particular, Bi-based metal oxide ceramic layer having a composition having a Bi ratio (b in the formula _{Y a Bi b X 2 O c} ) for greater 2X than 2.4 produces significant Bi loss or diffusion.

In one embodiment, the Bi-based metal oxide ceramic has a composition with b equal to or less than about 2.4 to reduce diffusion of excess mobile species. Preferably, the composition of the metal oxide ceramic layer has a b-value of about 1.95 to 2.2, more preferably about 2.0 to 2.2.

The content of Y molecules also affects Bi loss from Bi-based metal oxide ceramics. It is believed that the reduced amount of Y atoms (eg, Y-deficient composition) provides additional sites for Bi atoms to occupy, thereby reducing the amount of Bi that can diffuse from the metal oxide ceramic layer. This is advantageous because the resulting layer has a structure that produces good electrical properties. In one embodiment, the composition of the metal oxide ceramic layer is
A ratio of about 0.8 to 1.0 of aY pair 2X (a in the formula _{Y a Bi b X 2 O c} ).
Values equal to about 0.9-1.0 have been found to be useful in reducing diffusion of excess mobile species and do not degrade the electrical properties of Bi-based metal oxide ceramic layers. .

In a preferred embodiment, the Bi-based metal oxide ceramic consists of SBT. SBT has ab value of less than about 2.4. In one embodiment, SB
The composition of T has ab value of about 1.95 to 2.2, preferably about 2.0 to 2.2.
The ratio of Sr to 2Ta (a) in SBT is about 0.8-1.0.

Annealing is performed after the formation of the metal oxide ceramic layer. Annealing transforms the as-deposited metal oxide ceramic into a layer having the desired electrical properties.
In one embodiment, the anneal transforms the as-deposited metal oxide into a ferroelectric layer. Annealing causes the grains of the ferroelectric layer to grow and produce good electrical properties such as high remanent polarization (2Pr). Annealing is typically about 1-6 in an oxygenated atmosphere.
It is carried out at about 750 to 800 ° C. for 0 minutes. Lower temperatures are also useful. For example, the anneal may be performed at about 650-750 ° C. However, lower temperatures may be used for longer annealing (e.g., about 30-) to achieve the desired electrical properties.
120 minutes) is required. The annealing time may vary depending on the electrical properties desired.

A conductive layer 257 is deposited on the metal oxide ceramic layer to form a top electrode. The conductive layer is made of a noble metal such as Pt, Pd, Au, Ir or Rh. Other materials such as those used to form the bottom electrode are also useful. To ensure a well that defines the interface between the metal oxide ceramic and the electrode,
It is also often useful to perform annealing after vapor deposition of the top electrode. Annealing to restore the interface between the metal oxide ceramic and the electrode is typically about 5 slm.
It can be carried out at about 500 to 800 ° C. for about 1 to 30 minutes in an oxygen atmosphere having an O ₂ flow rate of 100 to 800 ° C. Having a well-defined interface between the electrode and the metal oxide ceramic is advantageous, for example because it reduces the leakage current.

After the deposition of the metal oxide ceramic, a pre-annealing is performed to partially or completely form the ferroelectric layer, and after the deposition of the top electrode, the metal oxide ceramic is completely converted into the ferroelectric layer. In order to do so (if not already fully converted), it may be useful to perform other anneals to promote grain growth and to ensure a well defined metal oxide ceramic / electrode interface.

Pre-annealing is typically performed at temperatures below about 750 ° C. In one embodiment, pre-annealing is performed at about 700-750 ° C. The pre-annealing time is about 5-10 minutes. In another embodiment, pre-annealing is performed at 700 ° C or lower. At lower temperatures, longer pre-anneals may be needed to partially or fully convert the metal oxide ceramic to the ferroelectric phase.

The top electrode is typically used as a common electrode to connect other capacitors in the memory array. The top electrode, along with the other layers below, can be patterned to provide contact openings to the bitlines and wordlines, if desired. Additional processing is performed to complete the ferroelectric memory IC. Such additional processing is well known to those skilled in the art. For example, additional processing includes support circuitry, a final passivation layer, formation of contact openings in the passivation layer for testing, and connection and packaging to a lead frame.

4A-C show another embodiment of the present invention. Substrate 2 as shown
01 has a partially formed memory cell similar to the one described, with reference numerals showing similar features.

A barrier layer 275 is deposited on the ILD layer 260. In one embodiment,
The barrier layer consists of a metal that reacts with excess mobile species. In the case of Bi-based metal oxide ceramics, the barrier layer consists of an oxide that reacts with Bi mobile species. In one embodiment, the barrier layer comprises an oxide selected from the group containing early transition metals. Such oxides include, for example, Sc ₂ O ₃ , Y ₂ O ₃ , TiO ₂ , ZrO ₂ , and Hf.
Including _{O 2, V 2 O 5,} Nb 2 O 5, Ta 2 O 5 and TiO _2. In a preferred embodiment, the barrier layer consists of TiO ₂ and Ta ₂ O ₅ . In another embodiment, the barrier layer forms a respective barrier layer _{PrBi 3 Ti 3 O 12, HoBi} 3 Ti 3 O 12 and LaBi ₃ Ti ₃ O ₁₂ after the reaction with an excess of mobile species containing Bi consists _{Pr 2 O 3, Ho 2 O} 3 or lanthanoid oxide and combined transition metal oxides such as _La 2 _{O 3.}

In another embodiment, the barrier layer comprises a titanate (Ti) of the general formula MTiO ₃ (where M is Ca, Sr and Ba). For example, SrTiO ₃ , Ba
Titanate salts such as TiO ₃ , (Ba, Sr) TiO ₃ are useful. Oxides selected from the group of oxides consisting of alkaline earth metals can also be used to form the barrier layer. Such oxides are, for example, MgO, CaO, SrO.
And BaO.

Other materials that react with the Bi-based mobile species, such as nitrides with transition metals, can also be used to form the barrier layer. Transition metal nitrides include, for example, TiN _x , ZrN _x and HfN _x (0 <x <1); TaN _x and NbN _x (0 <x <1.5); WN _x and MoN _x (0 <x <2). Includes. The nitride is oxidized to form the non-conductive barrier layer.

In another embodiment, the barrier comprises a dense material that reduces migration of excess mobile species from the metal oxide ceramic into the substrate. In the case of Bi-based metal oxide ceramics, materials dense enough to reduce diffusion of Bi mobile species include Al ₂ O ₃ ,
Including _{Sc 2 O 3, Y 2 O} 3, MgO, BeO, an oxide such as TiO ₂ and _Ta 2 _{O 5.}

The barrier layer can be formed by various deposition techniques such as sputtering, CVD or physical vapor deposition (PVD). Other vapor deposition techniques may also be useful. In one embodiment, the barrier layer is deposited on the substrate by, for example, sputtering with an oxide target or a metal target in the presence of oxygen. Typically, the temperature at which the barrier layer is sputtered is about 200-400 ° C. For example, about 20
Sputtering temperatures as low as 200 ° C., preferably about 200 ° C., can be advantageous because they result in fine particles, which extend the diffusion path for mobile species. Higher temperatures such as 400 ° C. and above may also be useful.

In a preferred embodiment, the barrier layer is deposited in the metal form by sputtering or CVD. The post-deposition barrier layer is annealed in oxygen to convert the as-deposited layer to an oxide barrier layer. Annealing causes expansion of the as-deposited layer due to oxidation, which increases its density.

In some cases, expansion can create an extreme amount of compressive stress. To offset the effect of compressive stress, the barrier layer can be deposited under tensile stress. The tensile stress is
It can be triggered by depositing the barrier layer at an elevated temperature, for example about 200-400 ° C.

Alternatively, the barrier layer can be deposited with insufficient oxygen content to form a mixture of oxide and metal or suboxide. An anneal is then performed in oxygen to oxidize the barrier layer. As-deposited films consist of suboxides (metals with an oxidation state below their highest oxidation state) or mixtures of oxides and metals, so that the volume expansion is small, which reduces the compressive stress.

In one embodiment, the barrier layer comprises titanium suboxide. The stoichiometry of titanium suboxide is, for example, TiO _x , where x is 0.5 ≦ x ≦ 1.5. During the anneal, the suboxide converts to TiO ₂ . The reaction can be described as follows: A barrier layer consisting of TiO ₂ : TiO _x + yO ₂ → TiO ₂ y = (2-x) / 2 Ta suboxide is also useful. Ta suboxide can be represented as TaO _x , where x is about 0.5 ≦ x ≦ 2.

In another embodiment, the barrier layer comprises a barrier stack having a first barrier layer and a second barrier layer. The first barrier layer is made of a material having a small diffusion constant for mobile species, and the second barrier layer is made of a material having high reactivity for mobile species. The second barrier layer has a tendency to attract mobile species and react with them to form stable compounds. On the other hand, the first barrier layer blocks the passage of mobile species due to its compactness.

In one embodiment, the second barrier layer is formed on the first barrier layer. Excess mobile species react with the second barrier layer and become trapped therein. The lower first barrier layer blocks the passage of excess mobile species due to its compactness.

With reference to FIG. 4B, the barrier and ILD layers are patterned to form openings to the diffusion region 212. A conductive material has been deposited to fill the opening. Excessive conductive material forms, for example, chemical mechanical polishing (CM) to form contact plugs.
It can be removed by P).

Referring to FIG. 4C, a conductive layer 253 serving as a bottom electrode has been deposited on the substrate and covers the barrier layer and contact plug 240. The conductive electrode barrier layer 251 blocks the passage of oxygen into the plug 240 and thus can be formed on the substrate prior to forming the conductive layer. The electrode barrier layer can also be used to reduce atomic migration between the contact plug and the electrode. The electrode barrier and conductive layer are patterned to form the bottom electrode stack 280. The bottom electrode has a contact plug 24
It is connected to the diffusion region 212 by 0.

The metal oxide ceramic layer 255 is formed on the bottom electrode and the ILD layer. The metal oxide ceramics, in one embodiment, consist of or can be converted to ferroelectric. As previously described, the composition of the metal oxide ceramic can be adapted to reduce diffusion of excess mobile species.

Annealing is performed in order to transform the metal oxide ceramic into the desired phase with good electrical properties. A conductive layer 257 is deposited on the metal oxide ceramic to form the top electrode. Performing an anneal after formation of the top electrode 257 may also be useful. Optionally, after deposition of the metal oxide ceramic, a pre-anneal is performed to form the ferroelectric phase, and then after formation of the top electrode, an anneal is performed to achieve the desired electrical properties.

The top electrode is typically used as a common electrode to connect other capacitors in the memory array. The top electrode, along with the other layers below, can be patterned to provide contact openings to bitlines and wordlines if desired. Additional processing is performed to complete the ferroelectric memory IC.

Optionally, as shown in FIG. 4D, an electrode barrier layer is deposited on the ILD layer and patterned to form an electrode barrier 251 on top of the plug 240. A conductive material is deposited and patterned to form bottom electrode 253. The bottom electrode covers the electrode barrier 251 and part of the barrier layer. Continue the method as described in FIG. 4C.

5A-C show another embodiment of the present invention. Substrate 2 as shown
01 has memory cells partially formed as already described.
A barrier layer 275 according to the present invention is formed on the surface of the substrate. The barrier layer is patterned using conventional masking and etching methods to form openings 241 that expose the surface of the contact plug. As shown, the opening 241 exposes only the surface of the plug 240. IL as depicted by dotted line 242
It is also useful to provide an opening 241 that exposes a portion of D. For example, the opening may be the size of the bottom electrode that will be formed next. Other techniques can also be used to remove excess electrode barrier material.

Referring to FIG. 5B, an electrode barrier layer is deposited on the substrate, covering the barrier 275 and the electrodes. The substrate surface can be planarized by CMP to remove excess electrode barrier material from the surface of barrier layer 275. CMP forms a flat top surface 276.

Referring to FIG. 5C, a conductive layer 253 is deposited on the surface of the substrate and patterned to form the bottom electrode. A metal oxide ceramic layer 255 is deposited on the substrate and covers the electrodes and barrier layer 275. The composition can be adapted to reduce the amount of excess mobile species that diffuses.

Annealing is carried out in order to transform the metal oxide ceramic into the desired phase with good electrical properties. A conductive layer 257 is deposited on the metal oxide ceramic to form the top electrode. Alternatively, a pre-anneal is performed after the deposition of the metal oxide ceramic to partially or fully form the ferroelectric phase, and then, if necessary, the metal oxide ceramic is completely converted to the ferroelectric phase. Therefore, an anneal is performed after formation of the top electrode to promote grain growth to achieve the desired electrical properties and to ensure a well defined metal oxide ceramic / electrode interface. Additional processing is performed to complete the ferroelectric memory IC.

6A-B show another embodiment of the present invention. With respect to FIG. 6A, the substrate 201 has partially formed memory cells, as previously described. ILD2
On 60, a barrier layer 275 according to the invention has been deposited.

With reference to FIG. 6B, an additional ILD layer 261 is formed on the barrier phase 275. The additional ILD layer may, but need not, be formed of the same material as ILD layer 260. Contact plug 240 is then formed by patterning ILD layer 261 and underlying layers to expose diffusion region 212. A conductive material has been deposited to fill the opening. Excess conductive material can be removed by chemical mechanical polishing (CMP) to form, for example, contact plug 240.

An electrode barrier layer 251 and a conductive layer 253 are deposited on the substrate and patterned to form a bottom electrode stack 280. The bottom electrode stack is coupled to diffusion region 212 by contact plug 240.

A conductive layer 253 is formed on the ILD layer 260. The conductive layer comprises a conductive material that prevents excess mobile species from diffusing through it. The conductive material preferably does not react with the subsequently formed metal oxide ceramic 255. The conductive layer can be formed by, for example, sputtering, physical vapor deposition or CVD. Other vapor deposition methods for the conductive layer are also useful.

In one embodiment, the conductive material oxidizes during the anneal. The oxide formed can be separated from the base electrode material and fills the interstices between grain boundaries, thereby preventing the diffusion of mobile species. Also, oxides can be incorporated into the base electrode material to form fully or highly miscible materials that react to trap excess mobile species.

In one embodiment, the conductive layer comprises a base conductive material such as a noble metal.
Noble metals include, for example, Pt, Pd, Au, Ir or Rh. Precious metal
Combined with a metal that oxidizes during heat treatment (annealing) to form a conductive layer that inhibits diffusion of the mobile layer. In one embodiment, the noble metal is Ti, Ta, Nb,
In combination with a metal selected from the group consisting of W, Mo, Mg.

A metal oxide ceramic layer 255 is deposited on the substrate and covers the electrodes and barrier layer 275. The composition of the metal oxide ceramic is adapted to reduce the amount of excess mobile species diffusing.

Annealing is performed to convert the metal oxide ceramic to the desired phase with good electrical properties. A conductive layer 257 is deposited on the metal oxide ceramic to form the top electrode. Alternatively, after the metal oxide ceramic is deposited, a pre-anneal is performed to partially or fully form the ferroelectric phase, and then, after formation of the top electrode, the metal oxide ceramic is mixed with the ferroelectric phase if necessary. Annealing is performed to fully transform the metal oxide ceramics, to promote grain growth to achieve the desired electrical properties, and to ensure a well defined metal oxide ceramic / electrode interface. Additional processing is performed to complete the ferroelectric memory IC.

7A-B show yet another embodiment of the present invention. With respect to FIG. 7A, substrate 201
Has a partially formed memory cell as previously described. As shown, the surface of the plug 240 is located in a recess below the surface of the ILD layer 260. An electrode barrier layer is formed on the substrate and fills the substrate and the depression. Excess material is removed by, for example, CMP, leaving an electrode barrier 25 on the plug.
1 remains. Other techniques for removing excess material are also useful.

With reference to FIG. 7B, a barrier layer 275 according to the present invention has been deposited on a substrate and the ILD
And cover the electrode barrier. The barrier layer is patterned to expose the electrode barrier.
A conductive layer 253 is deposited on the substrate and patterned to form the bottom electrode.

A metal oxide ceramic layer 255 is deposited on the substrate and covers the electrodes and barrier layer 275. The composition of the metal oxide ceramic can be adapted to reduce the amount of excess mobile species diffusing. Annealing is performed to convert the metal oxide ceramic to the desired phase with good electrical properties. A conductive layer 257 is deposited on the metal oxide ceramic to form the top electrode. An anneal is then performed to ensure a well defined metal oxide ceramic / electrode interface.

Optionally, after the deposition of the metal oxide ceramic, a pre-annealing is performed to partially or completely form the ferroelectric phase, and then after the formation of the top electrode, the metal oxide ceramic is, if necessary, Annealing is performed to fully convert to the ferroelectric phase, to promote grain growth to achieve the desired electrical properties, and to ensure a well defined metal oxide ceramic / electrode interface. . Additional processing is performed to complete the ferroelectric memory IC.

While the present invention has been particularly shown and described with respect to various embodiments, those skilled in the art will recognize that modifications and changes can be made to the present invention without departing from the spirit and scope of the invention. It Therefore, the scope of the invention should be determined not with reference to the above description, but with their full equivalent scope in the claims.

[Brief description of drawings]

[Figure 1]   1 is a schematic view of an embodiment for explaining the present invention.

[Fig. 2]   It is sectional drawing of one embodiment of this invention.

3A-B are diagrams showing steps of forming a device according to one embodiment of the present invention.

[Figure 4]   4A-4D are diagrams illustrating steps in forming an alternative embodiment of the present invention.

[Figure 5]   5A-5C are diagrams illustrating steps in forming another embodiment of the present invention.

[Figure 6]   6A-6B are diagrams illustrating steps in forming an alternative embodiment of the present invention.

[Figure 7]   7A-7B are diagrams illustrating steps in forming an alternative embodiment of the present invention.

─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 4K029 AA06 BA43 BA48 CA01 CA05                 4M104 BB01 BB18 BB40 CC01 FF14                       GG09 GG10 GG16                 5F033 HH33 HH34 HH35 HH40 JJ04                       JJ19 KK01 LL04 VV10 VV16                       XX28                 5F083 FR02 GA21 GA25 JA17 JA35                       JA36 JA38 JA39 JA40 JA43                       JA45 MA06 MA17 MA19 NA08                       PR22 PR33 PR40

Claims (36)

[Claims] 1. A dielectric layer on a substrate, a conductive layer formed on a portion of the dielectric layer, a metal oxide ceramic layer on the dielectric layer and the bottom electrode, a metal oxide ceramic and for separating the substrate. A semiconductor device comprising a barrier layer on a dielectric layer, the barrier layer reducing diffusion of excess mobile species from a metal oxide ceramic into a substrate. 2. The semiconductor device according to claim 1, wherein the metal oxide ceramic is a Bi-based metal oxide ceramic. 3. The semiconductor device according to claim 2, wherein the excess mobile species comprises Bi. 4. The semiconductor device according to claim 3, wherein the barrier layer is made of a material that reacts with excess mobile species containing Bi. 5. The semiconductor device according to claim 4, wherein the barrier layer comprises an oxide of an early transition metal. 6. The oxide is Sc ₂ O ₃ , Y ₂ O ₃ , TiO ₃ , ZrO ₂ , Hf.
The semiconductor device according to claim 5, wherein the semiconductor device is selected from the group consisting of O ₂ , V ₂ O ₅ , Nb ₂ O ₅ , Ta ₂ O ₅ and TiO ₂ . 7. The semiconductor device according to claim 4, wherein the barrier layer is made of TiO ₂ or Ta ₂ O ₅ . 8. The semiconductor device of claim 7, wherein the early transition metal oxide is further combined with a lanthanoid oxide. 9. barrier layer, after reaction with an excess of mobile species, respectively _{PrBi 3 Ti 3 O 12, HoBi} 3 Ti 3 O 12, and forms a _{LaBi 3 Ti 3 O 12, Pr} 2 O 3, The semiconductor device according to claim 4, comprising an oxide selected from the group consisting of Ho ₂ O ₃ and La ₂ O ₃ . 10. A titanate (Ti) oxide represented by the general formula MTiO _{3 wherein} M represents at least one element selected from the group consisting of Ca, Sr and Ba. The semiconductor device according to claim 4, wherein the semiconductor device comprises an object. 11. The barrier layer comprises SrTiO ₃ , BaTiO ₃ and (Ba, S).
The semiconductor device according to claim 4, comprising an oxide selected from the group consisting of r) TiO ₃ . 12. The semiconductor device according to claim 4, wherein the barrier layer is made of an oxide of an alkaline earth metal. 13. The semiconductor device according to claim 4, wherein the barrier layer is made of an oxide selected from the group consisting of MgO, CaO, SrO and BaO. 14. The semiconductor device according to claim 4, wherein the barrier layer is made of a transition metal nitride. 15. The nitrides are: TiN _x , ZrN _x and HfN _x (0 <x <1), TaN _x and NbN _x (0 <x <1.5) and WN _x and MoN _x (0). 15. The semiconductor device according to claim 14, wherein the semiconductor device is selected from the group consisting of <x <2). 16. The semiconductor device of claim 3, wherein the barrier layer comprises a dense material that reduces migration of excess mobile species of Bi from the metal oxide ceramic into the substrate. 17. The barrier layer comprises Al ₂ O ₃ , Sc ₂ O ₃ , Y ₂ O ₃ , MgO,
Consisting of an oxide selected from the group consisting of BeO, TiO ₂ and Ta ₂ O ₅ ;
The semiconductor device according to claim 16. 18. The barrier layer comprises a barrier stack having a first barrier layer and a second barrier layer, the first barrier layer having a small diffusion constant for excess mobile species and the second barrier layer being mobile. The semiconductor device according to claim 3, which has a high reactivity with a seed. 19. The semiconductor device according to claim 18, wherein the first barrier layer is on the dielectric layer and the second barrier layer is on the first barrier layer. 20. The second barrier layer attracts mobile species to form a stable material and the first barrier layer blocks the passage of excess mobile species due to its compactness. The semiconductor device described. 21. A substrate having a partially formed semiconductor device having a dielectric layer on a surface thereof is provided, a barrier layer is deposited on the dielectric layer, and a conductive layer is deposited on the dielectric layer, Pattern the conductive layer to form the bottom electrode and deposit a metal oxide ceramic layer on the substrate, the metal oxide ceramic layer covers the barrier layer and the bottom electrode, and anneals the substrate to ensure good electrical properties. Comprising forming a metal oxide ceramic having an annealing effect on the diffusion of excess mobile species from the metal oxide ceramic and the barrier layer reducing the diffusion of excess mobile species into the substrate. Method of forming a semiconductor device. 22. The method of claim 21, wherein the metal oxide ceramic comprises a Bi-based metal oxide ceramic. 23. The method of claim 22, wherein the excess mobile species consists of Bi. 24. The method of claim 23, wherein the barrier layer comprises a material that reacts with excess mobile species containing Bi. 25. The method of claim 24, wherein the barrier layer comprises an oxide of an early transition metal. 26. The oxide is Sc ₂ O ₃ , Y ₂ O ₃ , TiO ₃ , ZrO ₂ ,
_{HfO 2, V 2 O 5,} Nb 2 O 5, Ta 2 O 5 and TIO are selected from the group consisting of _2, 26. The method of claim 25. 27. A titanate (Ti) oxide whose barrier layer is represented by the general formula MTiO ₃ [wherein M represents at least one element selected from the group consisting of Ca, Sr and Ba]. 25. The method of claim 24, which comprises: 28. The barrier layer comprises an oxide of an alkaline earth metal.
The method described. 29. The method of claim 24, wherein the barrier layer comprises a transition metal nitride. 30. The method of claim 23, wherein the barrier layer comprises a dense material that reduces migration of excess mobile species of Bi from the metal oxide ceramic into the substrate. 31. The barrier layer comprises Al ₂ O ₃ , Sc ₂ O ₃ , Y ₂ O ₃ , MgO,
Consisting of an oxide selected from the group consisting of BeO, TiO ₂ and Ta ₂ O ₅ ;
31. The method of claim 30. 32. The step of depositing a barrier layer comprises depositing a first barrier layer and a second barrier layer to form a barrier stack, the first barrier layer having a small diffusion constant for excess mobile species. 24. The method of claim 23, wherein the second barrier layer is highly reactive with the mobile species. 33. The method of claim 32, wherein the first barrier layer is on the dielectric layer and the second barrier layer is on the first barrier layer. 34. The second barrier layer attracts mobile species to form a stable material, and the first barrier layer blocks the passage of excess mobile species due to its compactness.
3. The method described in 3. 35. The method of any of claims 25, 26, 27, 28, 29 and 31, wherein the barrier layer is deposited in the form of a metal and oxidized to form the barrier layer. 36. The barrier layer is deposited with insufficient oxygen content to form a suboxide and oxidized to form the barrier layer.
The method described in any one of.