JP2003338509A - Top gate type thin film transistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve characteristics of a polycrystalline silicon TFT. <P>SOLUTION: In a top gate type TFT wherein a gate electrode is formed in an upper layer than an active layer, an interlayer insulation film 40 is so formed as to cover the TFT active layer 24, a gate insulation film 30, and the gate electrode 36. The interlayer insulation film 40 has a multilayer structure of an SiNX film 42 and an SiO<SB>2</SB>film 44 from the active layer side with the thickness of the SiNX film 42 being about 50 to 200 nm, preferably, about 100 nm. By this thickness of the SiNX film 42, a sufficient amount of hydrogen enough to terminate a dangling bond can be supplied to the active layer 24 located in a lower layer which is formed of a semiconductor such as polycrystalline Si, and at the same, the formation accuracy of a contact hole or the like formed in the interlayer insulation film 40 can be kept high. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a top gate type thin film transistor, and more particularly to an insulating film structure.

[0002]

2. Description of the Related Art A liquid crystal display device (LCD) and an organic electroluminescence (OEL) device which has recently been attracting attention.
In display devices and the like, there is known a so-called active matrix type display device in which a switch element is formed in each pixel in order to realize high definition display.

A thin film transistor (TFT) is well known as a switch element formed in each pixel of this active matrix type display device. So-called polycrystalline SiT using polycrystalline silicon (p-Si) as an active layer in a thin film transistor
The FT has better responsiveness because it has higher conductivity than the case where amorphous silicon (a-Si) is used for the active layer,
In addition, since the channel, source and drain regions can be formed in the active layer in a self-aligned manner by using the gate electrode, the element area can be reduced, and further, CMOS (Complementar
y Metal Oxide Semiconductor) circuit is easy to configure. Therefore, it is excellent as a switch for a high-definition display, and a CMOS circuit composed of similar TFTs can be formed on a substrate on which pixel TFTs are formed, and a driver circuit for driving a display unit can be incorporated. Becomes

The polycrystalline Si film can be formed by forming an a-Si film and subjecting it to laser annealing to polycrystallize it. T using such a polycrystalline Si film as an active layer.
FT can be formed on an inexpensive glass substrate having a low melting point, and is very effective for obtaining an active matrix flat panel display device having a large area and low cost.

[0005]

The polycrystalline Si film thus formed by the so-called low temperature process using laser annealing or the like has many unpaired electrons of silicon at crystal grain boundaries in the film. The unpaired electrons (dangling bonds) cause carriers to be trapped to reduce the conductivity, or cause a leak current when the TFT is turned off. Therefore, it has been conventionally known to perform a hydrogenation process for terminating (terminating) dangling bonds in the polycrystalline Si film with hydrogen.

Here, in a so-called top gate type TFT which is one of the structures of the TFT, a gate insulating film covers the active layer, and a gate electrode is further formed thereon. Hydrogenation of the above-mentioned polycrystalline Si film of the top gate type TFT is performed by using an SiO ₂ film formed by a plasma CVD method capable of introducing hydrogen into the film as an interlayer insulating film covering the gate insulating film and the gate electrode. To use. Specifically, after forming the SiO ₂ interlayer insulation film by plasma CVD, by hydrogenation annealing, passed through a gate insulating film SiO ₂
Hydrogen is supplied from the interlayer insulating film to the polycrystalline Si film,
The i film was hydrogenated. However, there is a problem that the SiO ₂ interlayer insulating film does not have sufficient capability as a hydrogen supply source. Further, hydrogen plasma treatment may be performed at the time of forming SiO _{2 in} order to enhance the hydrogen supply ability, but this treatment has a long treatment tact and is not preferable from the viewpoint of production efficiency and production cost.

As the gate insulating film covering the active layer, a single layer of SiO ₂ film is usually used. However, in addition to this SiO ₂ film, a laminated structure with a silicon nitride (SiN _x ) film having a high hydrogen supply capability is adopted. It can be considered to be used for the gate insulating film. A silicon nitride film as a hydrogen supply source has a larger amount of hydrogen contained as the film is thicker. Therefore, the silicon nitride film is preferably thick as a hydrogen supply source. However, when the film thickness of the gate insulating film becomes large, there arises a problem that the operation threshold value of the TFT fluctuates (rises), so that it is impossible to secure a sufficient thickness in the gate insulating film as a hydrogen supply source.

Further, as used in the bottom gate type TFT, the interlayer insulating film is formed of SiO ₂ film and SiN _x.
Even in the case of the laminated structure with the film, in the top gate type TFT as described above, the gate insulating film and the gate electrode depending on the location are provided between the interlayer insulating film and the polycrystalline Si film. Therefore, the hydrogen supply conditions are different.

However, the supply conditions for good hydrogenation to the top gate type TFT have not been proposed so far, and optimization is strongly desired.

In order to solve the above problems, the present invention provides
The purpose is to improve the characteristics of a top-gate thin film transistor.

[0011]

In order to achieve the above-mentioned object, the present invention has been made, and is a top gate type thin film transistor in which a gate electrode is formed in an upper layer than an active layer, and a semiconductor film formed on a substrate, An interlayer insulating film formed to cover the semiconductor film; a gate electrode formed on the gate insulating film; and an interlayer insulating film formed to cover the gate electrode and the gate insulating film. However, it has a laminated structure in which a silicon nitride film and a silicon oxide film are laminated in this order from the gate insulating film side, and the film thickness of the silicon nitride film is 50 nm or more and 200 nm or less.

In another aspect of the present invention, in the top gate type thin film transistor, the silicon nitride film has a film thickness of about 100 nm.

In another aspect of the present invention, in the top gate type thin film transistor, the silicon nitride film is
It is a hydrogen supply source for the semiconductor film made of polycrystalline silicon.

By forming the silicon nitride film having such a thickness on the gate insulating film side of the interlayer insulating film, the dangling existing inside the silicon nitride film with respect to the active layer made of polycrystalline silicon or the like. Sufficient hydrogen can be supplied to terminate the ring bond. Further, in the case of forming a contact hole in the interlayer insulating film with the silicon nitride film having such a thickness, the accuracy of forming the contact hole can be ensured, and the contact density can be increased.
It is also possible to support high definition.

Another aspect of the present invention relates to a top gate type thin film transistor in which a gate electrode is formed above an active layer, and a buffer layer formed so as to cover a substrate and a semiconductor film formed on the buffer layer. A gate insulating film covering the semiconductor film, a gate electrode formed on the gate insulating film, and an interlayer insulating film covering the gate electrode and the gate insulating film, The layer has a laminated structure in which a silicon nitride film and a silicon oxide film are laminated in this order from the substrate side, and the gate insulating film has a silicon oxide film and a silicon nitride film laminated in this order from the semiconductor side. The interlayer insulating film has a laminated structure in which a silicon nitride film and a silicon oxide film are laminated in this order from the gate insulating film side.

In another aspect of the present invention, in the top gate type thin film transistor, the film thickness of the silicon nitride film of the interlayer insulating film is 50 nm or more and 200 nm or less.

As described above, the buffer layer, the gate insulating film, and the interlayer insulating film each have a laminated structure, and these layers are formed into an optimal stacking order by the combination of the silicon nitride film and the silicon oxide film. Top gate type TFT with improved characteristics and reliability and high integration.
Can be formed. Specifically, since the silicon nitride film exists above and below the thin film transistor, the diffusion of impurities into the thin film transistor can be reliably blocked by this silicon nitride film. Further, each of the above-mentioned interlayer insulating film and each silicon nitride film of the gate insulating film as the hydrogen supply source can be arranged close to the polycrystalline silicon active layer of the thin film transistor, and the hydrogen can be efficiently supplied to the polycrystalline silicon. Further, since the gate insulating film has a multi-layer structure and a dense silicon nitride film exists, the breakdown voltage of the thin film transistor can be improved. The interlayer insulating film also has a multi-layered structure and the presence of the silicon nitride film, so that it is possible to further improve the blocking function against the contaminants from the outside together with the gate insulating film. Further, when the amorphous silicon is polycrystallized by laser annealing, since the buffer layer exists under the silicon film, the margin such as the laser output intensity can be expanded, and the operation threshold (Vth) of the thin film transistor can be increased. The control of is reliable. In addition, it is possible to adjust the tint of the display device by using this buffer layer, which is also useful for improving the quality of the display device.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION Preferred embodiments of the present invention (hereinafter referred to as embodiments) will be described below with reference to the drawings.

[First Embodiment] FIG. 1 shows a sectional structure of a TFT according to an embodiment of the present invention. As shown in FIG. 1, the TFT is formed at the same time as a pixel TFT as a switch element adopted for each pixel in an active matrix type display device (LCD or OEL display device) or on the same substrate as this switch element. Driver circuit CM
It can be used for a TFT having an OS structure.

The TFT according to this embodiment is a top gate type TFT in which the gate electrode 36 is formed above the active layer 24, and SiN _{x is used} as the interlayer insulating film 40 that covers the gate insulating film 30 and the gate electrode 36. Film 42 and SiO ₂ film 4
A laminated film with 4 is adopted. Further, the film thickness of the SiN _x film 42 arranged on the gate insulating film 30 side and functioning as a hydrogen supply source for the active layer 24 is set to 50 nm to 200 nm, more preferably about 100 nm.

FIG. 2 shows a manufacturing process of such a TFT, which will be described below with reference to FIGS. An insulating substrate or a semiconductor substrate can be used as the substrate for forming the TFT, but the transparent glass substrate 10 having a low melting point is adopted here.
An active layer pattern made of polycrystalline Si of TFT is formed on the glass substrate 10. Specifically, FIG.
As shown in (a), an a-Si film 22 having a thickness of about 40 nm to 50 nm is formed on the glass substrate 10. Further, in order to prevent ablation from occurring in the subsequent annealing, the a-Si film 22 is annealed for dehydrogenation. Next, the a-Si film 22 is irradiated with a beam of an excimer laser to be annealed for polycrystallization. The polycrystalline Si film obtained by annealing is patterned into the shape of the active layer 24 of the TFT.

Next, as shown in FIG. 2B, the active layer 2
4, a gate insulating film 30 made of SiO ₂ is formed, a gate electrode material made of a refractory metal such as Cr is formed on the gate insulating film 30, and patterned into a desired shape of the gate electrode 36. .

Here, an n-conductivity type TFT (hereinafter referred to as n-type TF
In the case of T) and forming an LDD (Lightly Doped Drain), as shown in FIG.
The resist layer 200 is selectively left by photolithography so as to cover the electrode length of 6 (horizontal direction in the figure) by a certain distance. When the driver circuit is built in the same substrate, the resist layer 200 covers the active layer of the p-channel TFT of the CMOS circuit. Using the remaining resist layer 200 as a mask, the active layer 24 is doped (implanted) with a high concentration of impurities such as phosphorus through the gate insulating film 30. As a result, a region of the active layer 24 which is not covered with the mask is heavily doped with an n-type impurity, and a high-concentration impurity region (N ⁺ region) which later constitutes the source and drain regions 24s and 24d is formed. It

Next, as shown in FIG. 2D, the resist layer 200 as a mask is removed, and the exposed gate electrode 36 is used as a mask to reduce the concentration of impurities such as phosphorus into the active layer 2.
Dop to 4. As a result, a low-concentration impurity (LD) is formed between the N ⁺ region formed in the first high-concentration impurity doping step, on both sides of the intrinsic region where the impurity is not doped, directly below the gate electrode 36 of the active layer 24. A region (N ⁻ region) is formed. After doping the impurities, annealing treatment is performed by irradiation with an excimer laser or the like to activate the impurities doped in the active layer 24.

After the activation process, as shown in FIG.
An interlayer insulating film 40 is formed so as to cover the entire substrate including the gate insulating film 30 and the gate electrode 36. Interlayer insulating film 40
As described above, SiN from the gate insulating film 30 side
_{The x} film 42 and the SiO ₂ film 44 are both formed in this order by plasma CVD.
Are formed by laminating. Here, in the present embodiment, the SiN _x film 42 has a thickness of 50 nm or more and 200 nm or less. More preferably, the thickness is about 100 nm. With such a thickness, as will be described later, it is possible to exhibit a sufficient hydrogen supply capability to the polycrystalline Si film (active layer) 24 at the time of hydrogenation annealing and to satisfy the etching characteristics required when forming the contact hole. It is possible. The thickness of the SiO ₂ film 44 is not particularly limited,
As an example, it is about 500 nm.

After the interlayer insulating film 40 is formed, annealing (hydrogenation annealing) is performed in a nitrogen atmosphere, and hydrogen ions contained in the film are removed from the SiN _x film 42 of the interlayer insulating film 40 through the gate insulating film 16. It is introduced into the crystalline Si active layer 24.
The annealing temperature is such that hydrogen ions can move sufficiently and the substrate 10 is not damaged by thermal deformation or the like. When glass is used as the substrate as in this embodiment, the annealing temperature is, for example, 350 ° C to 450 ° C. By such hydrogenation annealing, the SiN _x is passed through the polycrystalline Si active layer 24 through the gate insulating film 30.
Hydrogen is supplied from the film 42 and dangling bonds in the polycrystalline Si active layer are terminated by this hydrogen. Here, the gate electrode 36 itself made of a metal material hardly permeates hydrogen, but the SiN _x film 42 is formed in the region of the active layer 24 (the later channel region) where the upper part is covered with the gate electrode 36.
Hydrogen from the gate insulating film 3 from the side of the gate electrode 36
Since it is introduced into the region directly under the gate through 0, the defect repair (termination) in the channel region, which has a great influence on the characteristics of the TFT, is surely performed.

After the hydrogenation annealing, next, the interlayer insulating film 40 is formed.
And the source / drain regions 24s of the gate insulating film 30,
Contact hole 4 so as to penetrate the corresponding region of 24d
6 is formed. Next, in the contact hole 46,
A source electrode 50s connected to the source region 24s, a drain electrode 50d connected to the drain region 24d, or a signal wiring integrated with these is formed. Through the above steps, a thin film transistor which can be used for the pixel portion and the peripheral driver portion of the active matrix display device as shown in FIG. 1 can be obtained.

When the obtained thin film transistor is used for a pixel TFT of an active matrix type LCD, for example, after forming the source / drain electrodes 50s and 50d, a flattening insulating film is formed to cover the TFT. A contact hole is opened in the film and IT is formed on the planarization insulating film.
An alignment for controlling the initial alignment of the liquid crystal by forming a pixel electrode such as O and connecting the pixel electrode to the source or drain electrode 50 of the TFT through a contact hole and further covering the entire surface of the substrate as necessary. Form a film. And
An LCD can be obtained by disposing a liquid crystal sandwiched between the element substrate thus obtained and a counter substrate. When the above-mentioned TFT is adopted in the active matrix type OEL display, for example, like the LCD, an ITO pixel electrode (first electrode: anode) is formed and connected to the TFT through a contact hole, and further on the ITO pixel electrode. An organic layer including a light emitting layer, a metal electrode (second electrode: eg cathode)
Are stacked.

FIG. 3 is the top-gate type TFT formed as described above, SiN _x interlayer insulating film 40
The relationship between the film thickness (nm) of the film 42 and the operation threshold value (V) of the p-ch type TFT is shown. Vth is preferably close to 0 V in both the n-ch type TFT and the p-ch type TFT. However, as shown in FIG.
When the iN _x film thickness is 0 nm, that is, only the SiO ₂ film, p-ch
The operation threshold (Vth) of the type TFT is -4V. on the other hand,
When the SiN _x film thickness is 50 nm, p-ch type TFT
The operating threshold value (hereinafter, Vth) has risen (decreased as an absolute value) to about -2.5V.

When the SiN _x film is not used as the interlayer insulating film 40, the Vth is as low as -4 V because the SiO ₂ film alone does not have sufficient hydrogen supply capability and dangling bonds in the polycrystalline Si active layer are affected by hydrogen. This is probably because carriers are not sufficiently terminated and carriers are easily trapped by dangling bonds in the active layer. On the other hand, when the SiN _x film thickness is formed to about 50 nm, Vth is significantly improved to -2.5V. Further, if the SiN _x film thickness is further increased,
Vth is further increased and improved, and SiN _x film thickness is 100 n
When m, Vth is about -2V. Further, when the SiN _x film thickness is 100 nm or more, Vth becomes approximately constant from -2V to -1.9V. From the above, in order to increase the amount of hydrogen supplied to the polycrystalline Si active layer and improve the TFT characteristics, the appropriate film thickness of the interlayer insulating film 40 as the SiN _x film is about 50 nm to 200 nm. . Further, it is more preferable that the film thickness of the SiN _x film is about 100 nm from the viewpoint of obtaining the maximum effect with the minimum film thickness.

Also, SiN_xFilm thickness and S value of TFT
As for the relationship between_xThe film thickness is 5
Range of about 0 nm to 200 nm, more preferably 100
The highest improvement effect can be obtained when the thickness is about nm. This
Here, the gate-source applied voltage Vgs in the Vth region is compared with
The change in drain current Id causes the subthreshold characteristic
And the reciprocal of the slope of this characteristic (ΔVgs) is the S value.
It The smaller the S value, the more the on-characteristics of the TFT.
It means steep. SiN as described above _xOf membrane
The film thickness is larger than 0 nm, preferably 50 nm to 200
In the range of about nm, the S value is small, that is,
The slope of the threshold characteristic increases.

Therefore, by setting the thickness of the SiN _x film to be larger than 0 nm, preferably in the range of about 50 nm to 200 nm, and more preferably about 100 nm, Vth is high (close to 0 V) for the p-th type TFT. In addition, it is possible to obtain a TFT having a sharp subthreshold characteristic and good responsiveness.

In FIG. 3, a p-ch type TFT is used.
The Vth characteristic of the p-ch type TF is evaluated.
The variation of Vth is larger in T than in n-ch type TFT
This is because. The S value of the n-ch type TFT is pc
Similar to h-type TFT, SiN _xFilm thickness from 0 nm to 5
Range of about 0 nm to 200 nm, more preferably 100
It is improved by setting to about nm, that is, subthreshold
It is possible to realize a TFT that can increase the slope of the characteristics and can respond at high speed.
Wear.

FIG. 4 shows the relationship between the film thickness (nm) of the SiN _x film 42 of the interlayer insulating film 40 and the CD (critical dimension) loss (μm). Here, the CD loss is represented by the distance from the opening-side end of the resist mask to the opening-side end of the material to be etched.
This means that there is a large difference between the mask pattern and the material to be etched, which is disadvantageous in terms of integration of TFTs.

As can be seen from FIG. 4, the film thickness of the SiN _x film and the CD loss have a proportional relationship, and the CD loss increases as the film thickness increases. SiN _{x of the} interlayer insulating film 40
The CD loss when the film thickness of the film 42 is 100 nm is 2.
5 μm, whereas when the film thickness becomes 200 nm, C
D loss is 3 μm, and CD loss is 3.5 μ when the film thickness is 300 nm.
rise to m.

A contact hole for connecting the active layer 24 and the source / drain electrode must be formed in the interlayer insulating film 40 as shown in FIG.
If the D loss is large, the diameter of the contact hole that is actually formed becomes very large, which is extremely disadvantageous to the miniaturization of the TFT and also the connection between the electrode wiring material and the active layer 24 in the contact hole. It also leads to a decrease in reliability. In FIG. 5, as in the present embodiment, contact holes are opened in the SiO ₂ gate insulating film 30, the SiN _x film 42 of the interlayer insulating film 40, and the SiO ₂ film 44 formed on the polycrystalline Si active layer 24. The state of the etching cross section at this time is conceptually shown. SiN _x film 4 having a dense film structure
2 has an etching rate of about 1/2 to 1 / th that of the SiO ₂ film with respect to the etchant BHF of SiN _x and SiO _2.
3 low. In addition, since the adhesiveness at the interface between the SiO ₂ film 44 and the resist 200 is not so high, the resist 20
The etching liquid permeates along the interface with 0, and the interface side of the SiO ₂ film 44 is etched in a wider area. Therefore, if the SiN _x film 42 is too thick, it takes time to etch the SiN _x film 42, and as shown in FIG. 5, the SiO ₂ film 44, which is the upper layer of the SiN _x film 42 formed on the resist 200 side, has a planar direction. It is largely etched, the upper diameter of the contact hole becomes large, and eventually the contact hole size becomes large. Therefore, with such a configuration, it is difficult to cope with high density and high definition of the device.
Since the gate insulating film 30 formed of the SiO ₂ film formed under the SiN _x film 42 has a higher etching rate as described above, the side surface near the lower part of the contact hole is S.
The iO ₂ part has a concave shape. It is difficult for the metal material for contact to enter into such an area, which increases the possibility of causing connection failure. Therefore, by setting the thickness of the SiN _x film of the interlayer insulating film 40 to about 50 nm to 200 nm, more preferably about 100 nm as in the present embodiment, CD loss is minimized and contact failure occurs. Polycrystal S while preventing
It is possible to improve the TFT characteristics by hydrogenating the i active layer 24.

[Second Embodiment] FIG. 6 shows a cross-sectional structure of a top gate type TFT according to the second embodiment. Interlayer insulation film 4
0 is a laminated body of the SiN _x film 42 having the hydrogen supply capability from the polycrystalline Si active layer 24 side and the SiO ₂ film 44, which is the same as the above-mentioned embodiment, but in this embodiment, the substrate is The buffer layer 12 having a laminated structure is provided between the active layer 24 and the active layer 24, and the gate insulating film 30 also has a laminated structure.

The buffer layer 12 is formed by laminating the SiN _x film 14 and the SiO ₂ film 16 in this order from the substrate side. Since the SiN _x film is a denser film than the SiO ₂ film as described above, when such an inexpensive alkali glass or the like is used as the substrate by forming such SiN _x film 14 on the substrate side, It is possible to reliably prevent impurities such as sodium ions from entering the TFT active layer and the like from the glass. Further, since the SiO ₂ film 16 having a higher affinity for the polycrystalline Si film than the SiN _x film is formed between the SiN _x film 14 and the polycrystalline Si active layer 24 in contact with the active layer 24, the substrate side It is possible to reduce the introduction of defects into the polycrystalline Si active layer 24 due to the strain of the interface of the.

The gate insulating film 30 is S from the active layer 24 side.
The io ₂ film 32 has a thickness of 60 nm to 100 nm (for example, 80 nm).
the thickness of the SiN _x film 34 is 20 nm to 60 nm.
(For example, about 40 nm) is formed in this order. The SiO ₂ film 3 is formed on the active layer 24 side made of polycrystalline Si.
By disposing No. 2, it is possible to reduce strain generated at the interface with the active layer 24 and prevent defects from being introduced into the active layer 24. In addition, the SiN _x film 34 has a hydrogen supply capacity, though not so much as the SiN _x film of the interlayer insulating film 40.
On the other hand, it has a high impurity blocking function and few pinholes in the film. Further, since the gate insulating film 30 has a laminated structure, it is possible to improve the insulating property (breakdown voltage) between the active layer 24 and the gate electrode 36.

As for the interlayer insulating film 40, the SiN _x film 42 and the SiO ₂ film 4 are arranged from the active layer 24 side as described above.
4 has the laminated structure of S.4.
The film thickness of the iN _x film 42 is about 50 nm to 200 nm (preferably about 100 nm).

As described above, each insulating layer (buffer layer 12,
The gate insulating film 30 and the interlayer insulating film 40) have a laminated structure, and the buffer layer 12 is a SiN _x film / SiO ₂ film in that order from the bottom, and the gate insulating film 30 is a SiO ₂ film / SiN _x film.
By forming the film order and the interlayer insulating film 40 in the stacking order of SiN _x film / SiO ₂ film, a top gate type TFT having excellent reliability and stable characteristics can be realized.

In each of the above embodiments, in the top gate type TFT, the gate insulating film 30 and the gate electrode 3 are formed.
After forming 6, the active layer 24 is doped with impurities. However, in the case of a top gate type TFT having an LDD structure, in order to reduce acceleration energy at the time of doping and prevent hardening of a doping mask, a high concentration is formed in a predetermined region before forming the gate insulating film 30 and the gate electrode 36. After performing the doping and forming the gate electrode 36, the impurities may be lightly doped with the gate electrode 36 as a mask. By adopting such a manufacturing method, the channel region and the LD region, which largely influence the area of the TFT, can be formed in self-alignment with the gate electrode 36. Of course, in this case as well, there is no change in the procedure of hydrogenation annealing using the SiN _x film of the interlayer insulating film 40 as a hydrogen supply source, and it is performed after the formation of the interlayer insulating film 40, for example, simultaneously with the activation treatment of the introduced impurities. be able to.

[0043]

As described above, according to the present invention, in a top gate type TFT using polycrystalline silicon or the like as an active layer, an interlayer insulating film is not deteriorated in etching accuracy and reliability, and the like. Insulating film Si
By supplying a sufficient amount of hydrogen from the N _x film, the dangling bonds in the active layer are surely terminated and T
The operating characteristics of the FT can be improved.

[Brief description of drawings]

FIG. 1 is a diagram showing a schematic cross-sectional structure of a thin film transistor according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a manufacturing process of the thin film transistor shown in FIG.

FIG. 3 is an SiN film of an interlayer insulating film according to an embodiment of the present invention.
It is a figure which shows the relationship between _x film thickness and the operation threshold value of p-ch type TFT.

FIG. 4 is an SiN film of an interlayer insulating film according to an embodiment of the present invention.
It is a figure which shows the relationship between _x film thickness and CD loss.

FIG. 5 is a diagram showing a cross-sectional shape of a contact hole formed through an interlayer insulating film.

FIG. 6 is a diagram showing a schematic sectional structure of a thin film transistor according to a second embodiment of the present invention.

[Explanation of symbols]

10 substrate, 12 buffer layer, 14 S of buffer layer
iN _x film, 16 buffer layer SiO ₂ film, 22 a-S
i film, 24 active layer (polycrystalline Si film), 24s source region, 24d drain region, 30 gate insulating film, 3
2 SiO ₂ film as gate insulating film, 34 SiN _x film as gate insulating film, 36 gate electrode, 40 interlayer insulating film, 42
SiN _x film as an interlayer insulating film, 44 SiO _{2 as an} interlayer insulating film
Film, 50s source electrode, 50d drain electrode, 20
0 resist layer (mask).

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Masaaki Aota             2-5-3 Keihan Hondori, Moriguchi City, Osaka Prefecture             Within Yo Denki Co., Ltd. F term (reference) 2H092 GA29 GA59 JA25 JA35 JA36                       JA46 JB56 JB58 KA04 KA05                       KA12 KA13 KB22 KB25 MA08                       MA13 MA27 MA29 MA30 NA21                 5F110 AA19 AA26 BB02 BB04 CC02                       DD02 DD13 DD14 DD17 EE04                       FF02 FF03 FF09 GG02 GG13                       HJ01 HJ23 HM15 NN04 NN23                       NN24 NN35 NN40 NN72 PP03                       PP35 QQ11 QQ23

Claims (5)

[Claims] 1. A top gate type thin film transistor in which a gate electrode is formed above an active layer, the semiconductor film, a gate insulating film covering the semiconductor film, and a gate electrode formed on the gate insulating film. An interlayer insulating film formed so as to cover the gate electrode and the gate insulating film, the interlayer insulating film being a laminated structure in which a silicon nitride film and a silicon oxide film are laminated in this order from the gate insulating film side. A top-gate thin film transistor having a structure, wherein the thickness of the silicon nitride film is 50 nm or more and 200 nm or less. 2. The top gate type thin film transistor according to claim 1, wherein the silicon nitride film has a film thickness of about 100 nm. 3. The top gate type thin film transistor according to claim 1, wherein the silicon nitride film is a hydrogen supply source for the semiconductor film made of polycrystalline silicon. . 4. A top gate type thin film transistor in which a gate electrode is formed above an active layer, the buffer layer being formed so as to cover a substrate, a semiconductor film formed on the buffer layer, and the semiconductor film. A gate insulating film covering the gate insulating film, a gate electrode formed on the gate insulating film, and an interlayer insulating film covering the gate electrode and the gate insulating film, wherein the buffer layer is the substrate Has a laminated structure in which a silicon nitride film and a silicon oxide film are laminated in this order from the side, and the gate insulating film has a laminated structure in which a silicon oxide film and a silicon nitride film are laminated in this order from the semiconductor side. The inter-layer insulating film has a laminated structure in which a silicon nitride film and a silicon oxide film are laminated in this order from the gate insulating film side. Transistor. 5. The top gate type thin film transistor according to claim 4, wherein the silicon nitride film of the interlayer insulating film has a film thickness of 50 n.
A top-gate thin film transistor having a thickness of m or more and 200 nm or less.