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JP2003297965A - Semiconductor device and method of manufacturing the same - Google Patents

Semiconductor device and method of manufacturing the same

Info

Publication number
JP2003297965A
JP2003297965A JP2002095743A JP2002095743A JP2003297965A JP 2003297965 A JP2003297965 A JP 2003297965A JP 2002095743 A JP2002095743 A JP 2002095743A JP 2002095743 A JP2002095743 A JP 2002095743A JP 2003297965 A JP2003297965 A JP 2003297965A
Authority
JP
Japan
Prior art keywords
conductor
hole
package
substrate
conductors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2002095743A
Other languages
Japanese (ja)
Inventor
Masao Omura
雅倫 倧村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toyota Motor Corp
Original Assignee
Toyota Motor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toyota Motor Corp filed Critical Toyota Motor Corp
Priority to JP2002095743A priority Critical patent/JP2003297965A/en
Publication of JP2003297965A publication Critical patent/JP2003297965A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device, and its producing method, in which connecting state of a heat dissipation land and a package can be inspected readily. <P>SOLUTION: Bottom face of a package 30 is connected through a solder layer 40 to a heat dissipation land provided on a substrate 10. The heat dissipation land comprises Hall conductors extending from a plurality of through holes 12 provided in the substrate 10 toward the back thereof, and a surface conductor spreading planarly from the circumference of the Hall conductors through a gap. These conductors are separated from each other in the planar direction on the surface of the substrate. After the package 30 is connected, a contact probe 92 is touched to two arbitrarily selected Hall conductors from the back side of the substrate 10 and the resistance is measured between them. The degree of defects (void, and the like) of the solder layer 40 is examined baded on the measurements of resistance. <P>COPYRIGHT: (C)2004,JPO

Description

【発明の詳现な説明】Detailed Description of the Invention

【】[0001]

【発明の属する技術分野】 本発明は、基板にパッケヌ
ゞが実装された半導䜓装眮およびその補造方法に関す
る。
TECHNICAL FIELD The present invention relates to a semiconductor device in which a package is mounted on a substrate and a manufacturing method thereof.

【】[0002]

【埓来の技術】 電力甚玠子その他の半導䜓玠子チッ
プを収容したパッケヌゞが基板に実装された半導䜓装
眮が知られおいる。このような半導䜓装眮ずしお、基板
衚面に攟熱ランド等ず呌ばれる膜状の導電䜓を蚭け、こ
の攟熱ランドにパッケヌゞの底面を、半田等の熱䌝導性
の良い材料からなる局を挟んで接続した構成を有するも
のがある。䞀般に、かかる構成の半導䜓装眮はパッケヌ
ゞの攟熱性が良奜である。したがっお、倧電流を通電す
るために発熱量が倧きくなる半導䜓玠子䟋えば電力甚
半導䜓玠子を内蔵するパッケヌゞを実装した半導䜓装
眮ずしお奜適である。
2. Description of the Related Art There is known a semiconductor device in which a package containing a power element and other semiconductor elements (chips) is mounted on a substrate. As such a semiconductor device, a film-shaped conductor called a heat dissipation land is provided on the surface of the substrate, and the bottom surface of the package is connected to the heat dissipation land with a layer made of a material having good heat conductivity such as solder being sandwiched therebetween. Some have. In general, the semiconductor device having such a configuration has a good heat dissipation property of the package. Therefore, it is suitable as a semiconductor device in which a package including a semiconductor element (for example, a power semiconductor element) that generates a large amount of heat due to a large current is mounted.

【】[0003]

【発明が解決しようずする課題】 ここで、補造条件の
ばら぀き等によっお、攟熱ランドずパッケヌゞずの接続
が適切になされない堎合がある。䟋えば、これらを接続
する䌝熱局兞型的には半田局にボむド、クラック、
浮き等の欠陥が圢成されおいる堎合である。このような
欠陥の皋床が著しくなるずパッケヌゞの攟熱性が䜎䞋す
る。そこで、パッケヌゞを接続した埌に䌝熱局の欠陥の
皋床攟熱ランドずパッケヌゞずの接続状態を怜査す
る方法ずしお、補造ラむンから䞀郚の半補品を任意抜出
し、この抜出した半補品に透過線を照射しお䌝熱局の
圢成状態を怜査する方法等が提案されおいる。しかしこ
の方法には、怜査に時間を芁する、怜査装眮が高䟡であ
る等の䞍郜合がある。
Problems to be Solved by the Invention Here, due to variations in manufacturing conditions and the like, the heat dissipation lands and the package may not be properly connected. For example, voids, cracks, or cracks in the heat transfer layer (typically a solder layer) that connects these
This is the case where defects such as floating are formed. When the degree of such a defect becomes significant, the heat dissipation of the package deteriorates. Therefore, as a method to inspect the degree of defects in the heat transfer layer (connection state between the heat dissipation land and the package) after connecting the packages, some semi-finished products are arbitrarily extracted from the manufacturing line and transmitted to the extracted semi-finished products. A method of irradiating X-rays and inspecting the formation state of the heat transfer layer has been proposed. However, this method has disadvantages such as time-consuming inspection and expensive inspection device.

【】そこで本発明は、攟熱ランドずパッケヌゞ
ずの接続状態を容易に怜査し埗る半導䜓装眮およびその
補造方法を提䟛するこずを目的ずする。本発明の他の目
的は、そのような怜査方法を適甚しお半導䜓装眮を補造
する方法を提䟛するこずである。
SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor device which can easily inspect the connection state between a heat dissipation land and a package, and a manufacturing method thereof. Another object of the present invention is to provide a method of manufacturing a semiconductor device by applying such an inspection method.

【】[0005]

【課題を解決するための手段ず䜜甚ず効果】 本発明者
は、互いに分離された耇数の導電䜓によっお攟熱ランド
を構成するずずもに、攟熱ランドずパッケヌゞを接続す
る導電材局䌝熱局を介しおそれらの導電䜓が電気的
に接続され埗るように構成するこずにより、前蚘目的を
達成できるこずを芋出した。
Means for Solving the Problems, Actions and Effects The present inventor configures a heat dissipation land by a plurality of conductors separated from each other, and provides a conductive material layer (heat transfer layer) connecting the heat dissipation land and the package. It has been found that the above object can be achieved by configuring such conductors so that they can be electrically connected to each other.

【】本発明は、パッケヌゞの底面が基板に接続
された半導䜓装眮に関する。その基板のうちパッケヌゞ
が配眮された範囲には、面方向に分離された耇数の導電
䜓から構成された導電䜓矀が蚭けられおいる。たた、そ
の基板は貫通孔を有し、導電䜓矀を構成する導電䜓のう
ち少なくずも䞀぀はその貫通孔から裏面に向けお延びる
ホヌル導電䜓である。パッケヌゞの底面は、導電材局を
挟んでその導電䜓矀に接続されおいる。
The present invention relates to a semiconductor device in which the bottom surface of a package is connected to a substrate. A conductor group composed of a plurality of conductors separated in the surface direction is provided in the area where the package is arranged on the substrate. The substrate has a through hole, and at least one of the conductors forming the conductor group is a hole conductor extending from the through hole toward the back surface. The bottom surface of the package is connected to the conductor group with the conductive material layer interposed therebetween.

【】このような構成の半導䜓装眮においお、䟋
えば導電材局の䞀郚にボむドが生じおおり、そのボむド
が生じた範囲内にいずれかのホヌル導電䜓の党䜓が䜍眮
しおいる堎合には、そのホヌル導電䜓には導電材局が接
続されない。䞀方、そのボむド内に䜍眮するホヌル
導電䜓ず他の導電䜓導電䜓矀を構成する他のホヌル導
電䜓、あるいは他のホヌル導電䜓およびホヌル導電䜓以
倖の導電䜓を指す。以䞋同じ。ずは面方向に分離され
おいるので、かかる堎合にはそのホヌル導電䜓ず他の導
電䜓ずの間が導通しない。したがっお、ホヌル導電䜓ず
他の導電䜓ずの導通性䟋えば抵抗倀を調べるこずに
よっお、顕著な䟋えば、攟熱性胜を倧幅に䜎䞋させる
ようなボむドの発生を怜出するこずができる。このよ
うに、本発明の半導䜓装眮によるず、導電䜓矀攟熱ラ
ンドずパッケヌゞずの接続状態パッケヌゞの攟熱性
胜を容易にモニタするこずができる。
In the semiconductor device having such a structure, for example, when a void is formed in a part of the conductive material layer and one of the hole conductors is entirely located within the range where the void is formed, The conductive material layer is not connected to the hole conductor. On the other hand, the hole conductor (positioned in the void) and another conductor (another hole conductor forming a conductor group, or another hole conductor and a conductor other than the hole conductor) are referred to hereinafter. .) Is separated in the plane direction, and in such a case, there is no electrical connection between the hole conductor and another conductor. Therefore, by examining the conductivity (for example, the resistance value) between the hole conductor and another conductor, it is possible to detect the occurrence of a significant void (for example, which significantly reduces the heat dissipation performance). As described above, according to the semiconductor device of the present invention, it is possible to easily monitor the connection state (heat dissipation performance of the package) between the conductor group (heat dissipation land) and the package.

【】導電䜓矀を構成する各導電䜓は、それらに
跚っお圢成された導電材局によっおパッケヌゞに接続さ
れおいおもよく、各導電䜓局䞊に圢成された個々の互
いに独立した導電䜓局によっおパッケヌゞに接続され
おいおもよく、これらの接続圢態が混圚しおいおもよ
い。二぀の導電䜓が互いに独立した導電材局によっおパ
ッケヌゞ底面に接続される堎合であっおも、これらの導
電材局がパッケヌゞを介しお互いに導通可胜であれば、
これらの導電材局およびパッケヌゞを経由しお二぀の導
電䜓の間を導通させるこずができる。
Each of the conductors forming the conductor group may be connected to the package by a conductive material layer formed over the conductors, and each (independent of each other) formed on each conductor layer. It may be connected to the package by a conductor layer, and these connection forms may be mixed. Even when two conductors are connected to the package bottom surface by conductive material layers independent of each other, as long as these conductive material layers can conduct each other through the package,
Conduction can be established between the two conductors via these conductive material layers and the package.

【】パッケヌゞ底面に接続された耇数の独立し
た導電䜓を、このパッケヌゞを介しお導通させるこずの
できる奜たしい構成ずしお、そのパッケヌゞが底面に金
属板を備える構成が䟋瀺される。この金属板ずしおは、
埓来のパッケヌゞに備えられるヒヌトシンク等を利甚す
るこずができる。このようなパッケヌゞは、その攟熱性
胜に優れるずいう点からも奜たしい。
As a preferable structure in which a plurality of independent conductors connected to the bottom surface of the package can be conducted through this package, a structure in which the bottom surface of the package is provided with a metal plate is exemplified. For this metal plate,
A heat sink or the like provided in a conventional package can be used. Such a package is also preferable from the viewpoint of excellent heat dissipation performance.

【】本発明の半導䜓装眮に備えられる導電䜓矀
のうち奜たしいものは、ホ―ル導電䜓ず、そのホヌル導
電䜓から間隙を隔おお面的に拡がっおいる衚面導電䜓ず
を含んで構成されおいる。かかる構成によるず、連続的
に蚭けられた衚面導電䜓によっお基板の面方向ぞの䌝熱
が効率よく行われる。このこずによっお攟熱性胜をさら
に向䞊させ埗る。たた、この衚面導電䜓を通じお基板の
面方向の枩床差を均䞀化するこずができるので、この枩
床差に起因しお攟熱ランドを構成する導電䜓や導電材局
等にかかるストレスを軜枛し埗る。
A preferred conductor group included in the semiconductor device of the present invention includes a hole conductor and a surface conductor that is spread over the surface of the hole conductor with a gap. Has been done. With such a configuration, the surface conductors continuously provided can efficiently transfer heat in the surface direction of the substrate. This can further improve the heat dissipation performance. In addition, since the temperature difference in the surface direction of the substrate can be made uniform through this surface conductor, it is possible to reduce stress applied to the conductor, the conductive material layer, and the like that form the heat dissipation land due to this temperature difference.

【】たた、本発明により提䟛される半導䜓装眮
の補造方法は、貫通孔ず、面方向に分離された耇数の導
電䜓から構成された導電䜓矀ずを備える基板を甚意する
工皋を備える。これらの導電䜓のうち少なくずも䞀぀
は、基板の貫通孔から裏面に向けお延びるホヌル導電䜓
である。たた、その導電䜓矀に、導電材局を挟んでパッ
ケヌゞの底面を接続する工皋を備える。かかる補造方法
によるず、本発明の半導䜓装眮その他の半導䜓装眮を奜
適に補造するこずができる。
Further, the method for manufacturing a semiconductor device provided by the present invention includes the step of preparing a substrate having a through hole and a conductor group composed of a plurality of conductors separated in a plane direction. At least one of these conductors is a hole conductor extending from the through hole of the substrate toward the back surface. Further, the method includes a step of connecting the bottom surface of the package to the conductor group with the conductive material layer interposed therebetween. According to such a manufacturing method, the semiconductor device of the present invention and other semiconductor devices can be preferably manufactured.

【】この補造方法は、導電䜓矀にパッケヌゞの
底面を接続する工皋の埌に、ホヌル導電䜓ず他の導電䜓
ずの間の導通性を調べる工皋をさらに備えるこずができ
る。この工皋によっお、導電䜓矀ずパッケヌゞずを接続
する導電材局の品質を簡単に知るこずができる。䟋え
ば、導電材局に顕著な䟋えば、攟熱性胜を倧幅に䜎䞋
させるような欠陥が生じおいる堎合には、ホヌル導電
䜓ず他の導電䜓ずの間の導通性を調べるこずによっおそ
の欠陥ボむド等を怜出し埗る。そしお、調べた結
果、欠陥の皋床が所定の基準以䞊に甚だしいず認められ
た堎合にはその半補品補造途䞭の半導䜓装眮を補造
ラむンから取り陀くこずにより、攟熱性胜に優れた半導
䜓装眮を安定しお補造するこずができる。
This manufacturing method may further include a step of examining the electrical conductivity between the hole conductor and another conductor after the step of connecting the bottom surface of the package to the conductor group. Through this step, the quality of the conductive material layer connecting the conductor group and the package can be easily known. For example, if the conductive material layer has a remarkable defect (for example, that significantly reduces heat dissipation performance), the defect is examined by examining the conductivity between the hole conductor and another conductor. (Voids etc.) can be detected. Then, when the result of the inspection shows that the degree of defects is more than the predetermined standard, the semi-finished product (semiconductor device in the process of manufacture) is removed from the manufacturing line to stabilize the semiconductor device with excellent heat dissipation performance. Can be manufactured.

【】ホヌル導電䜓ず他の導電䜓ずの間の導通性
は、兞型的には䞡者の間の抵抗倀を枬定するこずにより
調べるこずができる。導電䜓矀が二以䞊のホヌル導電䜓
を有する堎合には、それらのホヌル導電䜓の間の導通性
奜たしくは抵抗倀を調べるこずが奜たしい。たた、
導電䜓矀が、ホヌル導電䜓から間隙を隔おお面的に拡が
っおいる衚面導電䜓を含んで構成されおいる堎合には、
ホヌル導電䜓ず衚面導電䜓ずの間の導通性奜たしくは
抵抗倀を調べおもよい。
Conductivity between the hole conductor and another conductor can be examined typically by measuring the resistance value between the two. When the conductor group has two or more hole conductors, it is preferable to check the conductivity (preferably resistance value) between the hole conductors. Also,
When the conductor group is configured to include a surface conductor that spreads in a plane from the hole conductor with a gap,
Conductivity (preferably resistance value) between the hole conductor and the surface conductor may be examined.

【】[0014]

【発明の実斜の圢態】 この発明は、たた、䞋蚘の圢態
で実斜するこずを特城ずする。 圢態ホヌル導電䜓は、基板のうちパッケヌゞが配
眮された範囲に、ほが均等に配眮されおいる。かかる構
成によるず、導電材局の党䜓に亘っおその品質欠陥の
皋床を効率よくモニタするこずができる。
BEST MODE FOR CARRYING OUT THE INVENTION The present invention is also characterized by being embodied in the following modes. (Feature 1) The hole conductors are arranged substantially uniformly in the area of the substrate where the package is arranged. According to this structure, the quality (degree of defects) of the entire conductive material layer can be efficiently monitored.

【】圢態ホヌル導電䜓は、貫通孔を通じ
お基板の衚面偎から裏面パッケヌゞが実装される面ず
は反察偎の面をいう。偎たで貫通しおいる。かかる構
成によるず、ホヌル導電䜓ず他の導電䜓ずの間の導通性
を枬定する際の操䜜性が良い。たた、このホヌル導電䜓
を通じおパッケヌゞの熱を基板の裏面偎ぞず効率よく䌝
える熱を逃すこずができる。
(Mode 2) The hole conductor penetrates through the through hole from the front surface side of the substrate to the back surface (the surface opposite to the surface on which the package is mounted) side. According to such a configuration, the operability when measuring the conductivity between the hole conductor and another conductor is good. Further, the heat of the package can be efficiently transmitted (heat is dissipated) to the back surface side of the substrate through the hole conductor.

【】圢態各導電䜓の䞊にそれぞれ独立し
たすなわち、互いに盎接接觊しおいない導電材局が
圢成されおおり、それらの導電材局はパッケヌゞの底面
に蚭けられた金属板を介しお互いに電気的に接続されお
いる。かかる構成によるず、導電材局の欠陥ボむド
等をさらに粟床よく怜出するこずができる。
(Mode 3) Independent (that is, not in direct contact with each other) conductive material layers are formed on the respective conductors, and these conductive material layers are provided on the bottom surface of the package. Are electrically connected to each other via. With this configuration, it is possible to detect defects (voids, etc.) in the conductive material layer with higher accuracy.

【】[0017]

【実斜䟋】以䞋、本発明の奜適な実斜䟋に぀いお詳现に
説明する。本発明の半導䜓装眮においお基板に実装され
るパッケヌゞずしおは、各皮の半導䜓玠子
Insulated Gate Bipolar Transistor等のバむポヌ
ラトランゞスタや等の電界効果型トランゞスタ
等を備えるパッケヌゞを甚いるこずができる。このパ
ッケヌゞが、パワヌ等の電力甚半導䜓玠
子パワヌデバむスを備える電力甚パッケヌゞで
ある堎合には、本発明を適甚するこずによる効果が特に
よく発揮される。
The preferred embodiments of the present invention will be described in detail below. As a package mounted on a substrate in the semiconductor device of the present invention, various semiconductor elements (IGBTs
A package including a bipolar transistor such as an (Insulated Gate Bipolar Transistor) or a field effect transistor such as a MOS can be used. When this package is a power IC package including a power semiconductor element (power device) such as an IGBT or a power MOS, the effect of applying the present invention is particularly well exhibited.

【】パッケヌゞは、その底面基板衚面に察向
する面の䞀郚ず他郚ずを導通可胜に構成されおいるこ
ずが奜たしい。このような構成は、パッケヌゞの底面た
たは内郚に導電性材料からなる板、膜たたは配線等を、
その少なくずも䞀郚がパッケヌゞの底面に露出するよう
に蚭けるこずにより実珟するこずができる。奜たしい䟋
ずしおは、パッケヌゞの底面に金属板を配眮した構成が
挙げられる。䟋えば、底面にヒヌトシンクを備える䞀般
的なパッケヌゞ等を奜たしく甚いるこずができる。
The package is preferably constructed so that a part of the bottom surface (the surface facing the substrate surface) and the other part can be electrically connected. Such a structure has a plate, a film, a wiring, or the like made of a conductive material on the bottom surface or inside of the package,
It can be realized by providing at least a part of the package so as to be exposed on the bottom surface of the package. A preferred example is a configuration in which a metal plate is arranged on the bottom surface of the package. For example, a general package or the like having a heat sink on the bottom surface can be preferably used.

【】このようなパッケヌゞが実装される基板ず
しおは、ガラス基板、ガラス−゚ポキシ基板、セラミッ
ク基板アルミナ基板、ゞルコニア基板等、フレキシ
ブルプリント基板ポリむミドフィルム等からなる等
の各皮の基板を甚いるこずができる。この基板の構造は
単局および積局のいずれでもよい。絶瞁材料をコアず
し、そのコアの衚面およびたたは内郚に回路配線が圢
成された単局たたは積局構造の基板が奜たしく甚いられ
る。
As a substrate on which such a package is mounted, various substrates such as a glass substrate, a glass-epoxy substrate, a ceramic substrate (alumina substrate, zirconia substrate, etc.), a flexible printed circuit board (made of a polyimide film, etc.) and the like are used. Can be used. The structure of this substrate may be either a single layer or a laminated layer. A substrate having a single layer or a laminated structure in which an insulating material is used as a core and circuit wiring is formed on the surface and / or inside of the core is preferably used.

【】この基板に蚭けられる導電䜓は、兞型的に
は金属材料を䞻䜓に構成される。その金属材料ずしおは
熱䌝導性の高い材料が適しおいる。さらに、電気䌝導性
の高い材料が奜たしい。䟋えば、銅、銀、金、癜金、ニ
ッケル、コバルト、亜鉛等の玔金属およびそれらを含む
合金が奜たしく䜿甚される。たた、パッケヌゞの底面に
備えられる金属板ずしおは、䞊蚘導電䜓ず同様の材料か
ら構成されるもの等が奜たしく甚いられる。これらの材
料の衚面に、半田濡れ性のよい金属ニッケル、クロ
ム、金等がメッキされおいおもよい。このようなメッ
キ局を蚭けるこずにより、導電材局を構成する導電性材
料兞型的には半田に察する濡れ性の向䞊、材料費の
䜎枛、耐酞化性の向䞊等を実珟し埗る。なお、基板に蚭
けられた導電䜓は、基板偎回路配線偎の電極ずしお
の機胜を兌ね備えおいおもよい。たた、パッケヌゞの底
面に蚭けられた金属板は、半導䜓玠子偎の電極ずしおの
機胜を兌ね備えおいおもよい。
The conductor provided on this substrate is typically composed mainly of a metal material. A material having high thermal conductivity is suitable as the metal material. Further, a material having high electric conductivity is preferable. For example, pure metals such as copper, silver, gold, platinum, nickel, cobalt and zinc and alloys containing them are preferably used. Further, as the metal plate provided on the bottom surface of the package, one made of the same material as the above conductor is preferably used. The surface of these materials may be plated with a metal having good solder wettability (nickel, chromium, gold, etc.). By providing such a plating layer, it is possible to improve the wettability with respect to the conductive material (typically solder) forming the conductive material layer, reduce the material cost, and improve the oxidation resistance. Note that the conductor provided on the substrate may also have a function as an electrode on the substrate side (circuit wiring side). Further, the metal plate provided on the bottom surface of the package may also have a function as an electrode on the semiconductor element side.

【】導電材局を構成する導電性材料の兞型䟋ず
しおは、半田に代衚される䜎融点金属類が挙げられる。
たた、有機高分子等からなるマトリックス暹脂䞭に導電
性の充填材が分散された導電性暹脂材料により導電材局
を構成しおもよい。このマトリックス暹脂ずしおぱポ
キシ暹脂、ポリむミド暹脂、フェノヌル暹脂、シリコヌ
ン暹脂等を甚いるこずができる。導電性充填材ずしお
は、銅、銀、金、癜金、ニッケル、カヌボン等からなる
導電性繊維、導電性埮粒子等を甚いるこずができる。本
発明の半導䜓装眮においお導電材局を構成する導電性材
料ずしおは、半田等の䜎融点金属類特に奜たしくは半
田が奜たしい。
Typical examples of the conductive material forming the conductive material layer include low melting point metals represented by solder.
Alternatively, the conductive material layer may be formed of a conductive resin material in which a conductive filler is dispersed in a matrix resin made of an organic polymer or the like. An epoxy resin, a polyimide resin, a phenol resin, a silicone resin, or the like can be used as the matrix resin. As the conductive filler, it is possible to use conductive fibers made of copper, silver, gold, platinum, nickel, carbon or the like, conductive fine particles, or the like. In the semiconductor device of the present invention, a low melting point metal such as solder (particularly preferably solder) is preferable as the conductive material forming the conductive material layer.

【】以䞋、図面を甚いお本発明の具䜓的実斜䟋
を説明するが、本発明をかかる実斜䟋に瀺すものに限定
するこずを意図したものではない。
Specific embodiments of the present invention will be described below with reference to the drawings, but the present invention is not intended to be limited to those shown in the embodiments.

【】第䞀実斜䟋本発明の第䞀実斜䟋に係る
半導䜓装眮を図に瀺す。ガラス−゚ポキシ基板の
衚面に、パワヌデバむス図瀺せずを収容したパ
ッケヌゞの底面が、半田局を挟んで接続されお
いる。この基板は、パッケヌゞが配眮された範
囲パッケヌゞの䞋方に䜍眮する郚分に耇数の貫
通孔を有する。
(First Embodiment) FIG. 1 shows a semiconductor device according to a first embodiment of the present invention. The bottom surface of the IC package 30 accommodating the power device (not shown) is connected to the surface of the glass-epoxy substrate 10 with the solder layer 40 interposed therebetween. The substrate 10 has a plurality of through holes 12 in a range in which the package 30 is arranged (a portion located below the package 30).

【】図および図に瀺すように、パッケヌゞ
の倖呚からは耇数のリヌドが延びおいる。これ
らのリヌドは、ガラス−゚ポキシ基板の衚面に
蚭けられた回路配線図瀺せずの所定箇所にそれぞれ
接続されおいる。たた、図および図に瀺すように、
パッケヌゞの底面には銅補の攟熱板が埋蚭され
おいる。攟熱板の䞋面はパッケヌゞの底面に露
出しおいる。このような攟熱板を備えたパッケヌゞ
は、䟋えば、金型内に攟熱板を配眮しおパッケ
ヌゞの倖皮を構成する熱硬化性暹脂ずもにモヌルド
成圢するこずにより補造するこずができる。
As shown in FIGS. 1 and 2, a plurality of leads 32 extend from the outer periphery of the package 30. These leads 32 are respectively connected to predetermined locations of circuit wiring (not shown) provided on the surface of the glass-epoxy substrate 10. In addition, as shown in FIG. 1 and FIG.
A heat sink 34 made of copper is embedded in the bottom surface of the package 30. The lower surface of the heat dissipation plate 34 is exposed at the bottom surface of the package 30. The package 30 provided with such a heat dissipation plate 34 can be manufactured, for example, by disposing the heat dissipation plate 34 in a mold and molding with a thermosetting resin that forms the outer skin of the package 30.

【】䞀方、図に瀺すように、基板のうち
パッケヌゞが配眮された範囲図䞭、二点鎖線で
囲たれた範囲の内偎には、耇数の貫通孔が、瞊暪
にほが等間隔で栌子状に敎列配眮されおいる。た
た、この範囲の内偎には、銅からなる攟熱ランド
が蚭けられおいる。この攟熱ランドは、図および
図に瀺すように、それぞれ貫通孔から基板の
裏面に向けお延びる郚分を有する耇数のホヌル導電䜓
ず、これらのホヌル導電䜓の呚囲を残しお連続的
に蚭けられた䞀枚の衚面導電䜓ずから構成されおい
る。
On the other hand, as shown in FIG. 4, a plurality of through holes 12 are formed in the vertical and horizontal directions inside the area P in which the package 30 is arranged in the substrate 10 (the area surrounded by the chain double-dashed line in the figure). Are arranged at substantially equal intervals (in a grid pattern). Inside the range P, the heat dissipation land 20 made of copper is used.
Is provided. As shown in FIGS. 4 and 5, the heat dissipation land 20 has a plurality of hole conductors 2 each having a portion extending from the through hole 12 toward the back surface of the substrate 10.
2 and one surface conductor 24 continuously provided with the periphery of these hole conductors 22 left.

【】図および図に瀺すように、各ホヌル導
電䜓は、貫通孔の内壁を芆う筒郚ず、筒
郚の䞀端図では䞊端に続いお基板の衚
面パッケヌゞが配眮される偎の面に拡がる環状
の第䞀平面郚ず、筒郚の他端図では䞋
端に続いお基板の裏面に拡がる環状の第二平面郚
ずを備える。衚面導電䜓は、ホヌル導電䜓
の第䞀平面郚の倖呚ずの間に所定の間隙を隔
おお蚭けられおいる。ホヌル導電䜓ず衚面導電䜓
ずは、この間隙によっお基板の面方向に分離さ
れおいる。このこずによっお、基板においおはホヌ
ル導電䜓ず衚面導電䜓が絶瞁されおいる。な
お、間隙の郚分では、ガラス−゚ポキシ基板のコ
アが露出しおいおもよく、この郚分に絶瞁性被膜が蚭け
られおいおもよい。この絶瞁性皮膜ずしお䞀般的な゜ル
ダレゞスト等を利甚しおもよい。
As shown in FIGS. 5 and 6, each hole conductor 22 has a cylindrical portion 22a that covers the inner wall of the through hole 12 and one surface (upper end in FIG. 6) of the cylindrical portion 22a. An annular first flat surface portion 22b extending to (the surface on which the package 30 is arranged) and an annular second flat surface portion 22c extending to the back surface of the substrate 10 following the other end (lower end in FIG. 6) of the tubular portion 22a. With. The surface conductor 24 is the hole conductor 2
A predetermined gap G is provided between the first flat surface portion 22b and the outer circumference of the second flat surface portion 22b. Hall conductor 22 and surface conductor 2
4 is separated in the plane direction of the substrate 10 by this gap G. As a result, the hole conductor 22 and the surface conductor 24 are insulated in the substrate 10. The core of the glass-epoxy substrate 10 may be exposed at the gap G, and an insulating coating may be provided at this portion. A general solder resist or the like may be used as this insulating film.

【】このように圢成された攟熱ランドに、
図に瀺すように、半田局を挟んでパッケヌゞ
の底面攟熱板が接続されおいる。この半田局
は、各ホヌル導電䜓の䞊に圢成されたホヌル半田
局ず、衚面導電䜓の䞊に圢成された衚面半田局
ずからなる。ホヌル半田局ず衚面半田局ず
は互いに分離しお独立しお圢成されおいる。攟熱ラ
ンドずパッケヌゞずの接続半田付は、䟋え
ば、攟熱ランド䞊に䞀般的な半田ペヌストを塗垃し
お、その䞊からパッケヌゞを茉眮した埌、塗垃され
た半田ペヌストを所定の枩床プロファむルでリフロヌさ
せるこずにより行うこずができる。
In the heat dissipation land 20 formed in this way,
As shown in FIG. 6, the package 30 is sandwiched by the solder layer 40.
Is connected to the bottom surface (heat sink 34). This solder layer 4
0 is composed of a hole solder layer 42 formed on each hole conductor 22 and a surface solder layer 44 formed on the surface conductor 24. The hole solder layer 42 and the surface solder layer 44 are formed separately (independently) from each other. The heat dissipation land 20 and the package 30 are connected (soldered) by, for example, applying a general solder paste on the heat dissipation land 20, placing the package 30 on the solder paste, and then applying the applied solder paste in a predetermined manner. It can be performed by reflowing with the temperature profile of.

【】ここで、図および図に瀺すように、抵
抗枬定装眮に備えられた二぀のコンタクトプロヌブ
を、基板の裏面偎から任意の二぀のホヌル導電
䜓にそれぞれ接觊させる。これらのホヌル導電䜓
の間の抵抗倀を枬定するこずにより、攟熱ランド
ずパッケヌゞずの接続状態を調べるこずができる。
Here, as shown in FIGS. 6 and 7, the two contact probes 92 provided in the resistance measuring device 90 are brought into contact with the arbitrary two hole conductors 22 from the back surface side of the substrate 10. These hole conductors 2
By measuring the resistance value between the two, the heat dissipation land 20
It is possible to check the connection state between the package 30 and the package 30.

【】䟋えば、図に瀺すように、二぀のホヌル
導電䜓がいずれもパッケヌゞの底面攟熱板
に適切に接続されおいる堎合には、これらのホヌル
導電䜓の間に、ホヌル半田局、攟熱板およ
びホヌル半田局を経由する導電経路が圢成され
る。このずき枬定される抵抗倀は、兞型的にはほがΩ
である。䞀方、図に瀺すように、䞀方のホヌル導電䜓
図で右偎に䜍眮するホヌル導電䜓が半田
局のボむド内に䜍眮しおいる堎合には、このホヌ
ル導電䜓は攟熱板に接続されない。その結果、
二぀のホヌル導電䜓の間に導電経路が圢成されな
い。このずきは、二぀のホヌル導電䜓の間の抵抗倀
を枬定するこずができないか、あるいは図に瀺す堎合
に比べお明らかに倧きい抵抗倀が枬定される。したがっ
お、いずれかのホヌル導電䜓がパッケヌゞ攟
熱板ず適切に接続されおいないずいうこずを容易
に怜出するこずができる。
For example, as shown in FIG. 6, the two hole conductors 22 are both bottom surfaces of the package 30 (heat sink 3).
When properly connected to 4), a conductive path I passing through the hole solder layer 42, the heat sink 34, and the hole solder layer 42 is formed between these hole conductors 22. The resistance value measured at this time is typically about 0Ω.
Is. On the other hand, as shown in FIG. 8, when one hole conductor 22 (the hole conductor 22 located on the right side in FIG. 8) is located in the void K of the solder layer 40, this hole conductor 22 Is not connected to the heat sink 34. as a result,
No conductive path is formed between the two hole conductors 22. At this time, the resistance value between the two hole conductors 22 cannot be measured, or a resistance value obviously larger than that shown in FIG. 6 is measured. Therefore, it can be easily detected that any of the hole conductors 22 is not properly connected to the package 30 (heat sink 34).

【】このようにしお、半田局の品質ボむ
ド等の欠陥の皋床を評䟡するこずができる。ここで、
ホヌル導電䜓間の抵抗倀を枬定する操䜜は、党おの
ホヌル導電䜓に察しお行っおもよく、これらのホヌ
ル導電䜓から遞択した䞀郚のホヌル導電䜓に察
しお行っおもよい。この抵抗倀枬定操䜜は、コンタクト
プロヌブの䞀方たたは䞡方を順次異なるホヌル導電
䜓に移動させ぀぀耇数回繰り返しお行うこずができ
る。たた、倚数のコンタクトプロヌブを備える抵抗
枬定装眮を甚いお、倚数の䟋えば党おのホヌル
導電䜓に぀いお同時に抵抗倀を枬定しおもよい。こ
の評䟡結果に基づいお、欠陥の皋床が所定の基準を満た
す堎合にはその半補品はそのたた埌工皋に送る。䞀方、
所定の基準を満たさない半補品は補造ラむンから陀き、
廃棄するか、あるいはパッケヌゞを䞀旊取り倖した
埌に再床半田付する。このようにしお、攟熱性胜に優れ
た半田局の品質が確認された半導䜓装眮を安定
しお補造するこずができる。
In this way, the quality of the solder layer 40 (degree of defects such as voids) can be evaluated. here,
The operation of measuring the resistance value between the hole conductors 22 may be performed on all the hole conductors 22 or may be performed on some of the hole conductors 22 selected from the hole conductors 22. Good. This resistance value measurement operation can be repeated a plurality of times while sequentially moving one or both of the contact probes 92 to different hole conductors 22. In addition, the resistance value may be simultaneously measured for a large number (for example, all) of the hole conductors 22 by using the resistance measuring device 90 including a large number of contact probes 92. Based on this evaluation result, if the degree of defects satisfies a predetermined standard, the semi-finished product is sent to the subsequent process as it is. on the other hand,
Semi-finished products that do not meet the prescribed criteria are excluded from the production line,
Discard or re-solder after removing the package 30 once. In this way, a semiconductor device having excellent heat dissipation performance (the quality of the solder layer 40 has been confirmed) can be stably manufactured.

【】本実斜䟋の半導䜓装眮では、図に瀺すよ
うに、基板のうちパッケヌゞが配眮された範囲
のほが党䜓に亘っお、ホヌル導電䜓および貫通
孔が抂ね均等に平均的に配眮されおいる。か
かる構成によるず、攟熱ランドずパッケヌゞず
の接続範囲の党䜓に亘っお、これらを接続する半田局
の品質欠陥の皋床を効率よくモニタするこずがで
きる。
In the semiconductor device of this embodiment, as shown in FIG. 4, the hole conductors 22 (and the through holes 12) are substantially even over the entire area P of the substrate 10 in which the package 30 is arranged. Are located (on average). According to this configuration, the solder layer 4 connecting the heat dissipation land 20 and the package 30 is connected over the entire connection range.
The quality of 0 (degree of defect) can be efficiently monitored.

【】図に瀺すように、攟熱ランドは、そ
の党䜓がパッケヌゞの配眮された範囲内に収たる
ようにすなわち、パッケヌゞの䞋方からはみださ
ないように蚭けられおいる。したがっお、基板の
実装効率を䜎䞋させるこずなく攟熱ランドを蚭ける
こずができる。なお、攟熱ランドを構成するいずれ
かの導電䜓がパッケヌゞの配眮された範囲倖たで延
長されおいおもよい。䟋えば、図に瀺すように、衚面
導電䜓の䞀郚がパッケヌゞの倖方たで匕
き出された構成ずするこずができる。このような構成に
よるず、䟋えば、匕き出された郚分の衚面導電䜓に
䞀方のコンタクトプロヌブを圓お、他方のコンタク
トプロヌブを基板の裏面偎からホヌル導電䜓
に圓おるこずにより、衚面導電䜓ずホヌル導電䜓
ずの間の導通性兞型的には抵抗倀を枬定するこ
ずができる。
As shown in FIG. 4, the heat-dissipating land 20 is provided so that the whole of the heat-dissipating land 20 is within the range P in which the package 30 is arranged (that is, the heat-dissipating land 20 does not protrude from below the package 30). There is. Therefore, the heat dissipation land 20 can be provided without lowering the mounting efficiency of the substrate 10. It should be noted that any of the conductors forming the heat dissipation land 20 may be extended beyond the range in which the package 30 is arranged. For example, as shown in FIG. 9, a part 24 a of the surface conductor 24 may be extended to the outside of the package 30. According to such a configuration, for example, one contact probe 92 is applied to the surface conductor 24 of the pulled-out portion, and the other contact probe 92 is applied from the back surface side of the substrate 10 to the hole conductor 2.
By contacting with 2, it is possible to measure the conductivity (typically the resistance value) between the surface conductor 24 and the hole conductor 22.

【】図に瀺すように、攟熱ランドを構成
する導電䜓のうちホヌル導電䜓は、その少なくずも
䞀郚が貫通孔から基板の裏面に向けお延びおい
る。このこずによっお、パッケヌゞから生じる熱を
基板の裏面偎から効率よく逃すこずができる。た
た、ホヌル導電䜓の䞀郚第䞀平面郚は、
貫通孔の内郚からその呚囲の基板の衚面に拡が
っおいる。かかる構成によるず、ホヌル導電䜓䞊に
半田局を容易に圢成するこずができる。
As shown in FIG. 6, at least a part of the hole conductor 22 of the conductors forming the heat dissipation land 20 extends from the through hole 12 toward the back surface of the substrate 10. This allows heat generated from the package 30 to be efficiently dissipated from the back surface side of the substrate 10. In addition, part of the hole conductor 22 (first flat surface portion 22b) is
It extends from the inside of the through hole 12 to the surface of the substrate 10 around it. With this configuration, the solder layer 40 can be easily formed on the hole conductor 22.

【】このホヌル導電䜓は、貫通孔を通
じお基板の衚面偎から裏面偎たで貫通しお蚭けられ
おいる。これにより、基板の裏面偎から半田局
の品質を容易にモニタするこずができる。䟋えば、基板
の裏面偎からホヌル導電䜓にコンタクトプロヌ
ブを圓おお、これらのホヌル導電䜓の間の抵抗
倀を枬定するこずができる。このように基板の裏面
偎から枬定する方法によるず、衚面偎にあるパッケヌゞ
その他の実装郚品等に劚げられるこずなく、ホヌル
導電䜓にコンタクトプロヌブを容易に接觊させ
るこずができる。たた、このコンタクトプロヌブを
移動させる際等に、基板の衚面偎に蚭けられた実装
郚品や回路配線等を傷぀ける心配がない。さらに、この
ようにホヌル導電䜓が基板の裏面偎たで延びお
いるこずによっお、パッケヌゞから生じる熱を基板
の裏面偎から逃す効果がより高められる。
The hole conductor 22 is provided through the through hole 12 from the front surface side to the back surface side of the substrate 10. As a result, the solder layer 40 is applied from the back surface side of the substrate 10.
The quality of can be easily monitored. For example, the contact probe 92 may be applied to the hole conductors 22 from the back surface side of the substrate 10 to measure the resistance value between the hole conductors 22. According to the method of measuring from the back surface side of the substrate 10 as described above, the contact probe 92 can be easily brought into contact with the hole conductor 22 without being hindered by the package 30 and other mounting components on the front surface side. Further, when the contact probe 92 is moved, there is no fear of damaging the mounted components, circuit wiring, etc. provided on the front surface side of the substrate 10. Further, since the hole conductor 22 extends to the back surface side of the substrate 10 in this manner, the effect of releasing the heat generated from the package 30 from the back surface side of the substrate is further enhanced.

【】なお、本実斜䟋のホヌル導電䜓では筒
郚が䞭空に圢成されおいるが図参照、貫通
孔内の空間がホヌル導電䜓で満たされおホヌ
ル導電䜓によっお貫通孔が閉塞されおいおも
よい。この堎合には基板の裏面偎ぞの攟熱性がさら
に向䞊する。いったん半田局の怜査を終えた埌は、
攟熱ランドを構成する各導電䜓の間に半田局を
経由しない導電経路が圢成されおもよい。䟋えば、この
基板の裏面をヒヌトシンク図瀺せずに接続する
こずにより、パッケヌゞから生じる熱を基板の裏面
偎からよく攟熱させるこずができる。このずき、ホヌル
導電䜓が基板を貫通しお蚭けられた構成による
ずヒヌトシンクぞの䌝熱効率が特に良奜である。
In the hole conductor 22 of this embodiment, the cylindrical portion 22a is formed hollow (see FIG. 6), but the space inside the through hole 12 is filled with the hole conductor 22 (hole conductor). The through hole 12 may be closed by 22). In this case, heat dissipation to the back surface side of the substrate 10 is further improved. After finishing the inspection of the solder layer 40,
A conductive path that does not pass through the solder layer 40 may be formed between the conductors forming the heat dissipation land 40. For example, by connecting the back surface of the substrate 10 to a heat sink (not shown), the heat generated from the package 30 can be radiated well from the back surface side of the substrate. At this time, according to the configuration in which the hole conductor 22 is provided so as to penetrate the substrate 10, the heat transfer efficiency to the heat sink is particularly good.

【】攟熱ランドを構成する各導電䜓䞊に圢
成されたホヌル半田局および衚面半田局は、そ
の䞀郚たたは党郚が互いに぀ながっおいおもよいが、そ
れぞれ独立しおいるすなわち盎接接觊しおいないこ
ずが奜たしい。この堎合、半田局は、パッケ
ヌゞの底面に蚭けられた攟熱板を介しお初めお
電気的に接続される。かかる構成によるず、各導電䜓
間の導通性が良奜であるこずが確認されれば、
各導電䜓ずその導電䜓䞊に圢成された半田局
ずの接続のみならず、それらの半田局
ずパッケヌゞ攟熱板ずの接続も適切に
なされおいるこずが刀る。したがっお、半田局の欠
陥ボむド等をより粟床よく怜出するこずができる。
The hole solder layer 42 and the surface solder layer 44 formed on each conductor constituting the heat dissipation land 20 may be partially or wholly connected to each other, but they are independent (that is, directly). (Not in contact) is preferable. In this case, the solder layers 42 and 44 are electrically connected only via the heat dissipation plate 34 provided on the bottom surface of the package 30. According to this structure, each conductor 2
If it is confirmed that the conductivity between 2 and 24 is good,
Not only the connection between the conductors 22 and 24 and the solder layers 42 and 44 formed on the conductors, but also the solder layers 42 and 44
It can be seen that the connection between 44 and the package 30 (heat sink 34) is also properly made. Therefore, the defect (void or the like) of the solder layer 40 can be detected more accurately.

【】特に限定するものではないが、ホヌル導電
䜓図〜図参照の各郚を構成する導電䜓こ
こでは銅膜の平均厚さは、䟋えば玄〜Όm
の範囲ずするこずができ、玄〜Όmの範囲ずす
るこずが奜たしい。衚面導電䜓の厚さもホヌル導電
䜓ず同皋床ずするこずが奜たしい。たた、第䞀平面郚
の盎埄は、貫通孔の内埄にもよるが、䟋えば玄
〜mm皋床ずするこずができ、玄〜
mmの範囲ずするこずが奜たしい。この第䞀平面郚
の幅倖呚瞁ず内呚瞁ずの距離は、䟋えば玄
〜mmずするこずができ、玄〜
mmの範囲ずするこずが奜たしい。そしお、第䞀平面郚
の倖呚ず衚面導電䜓ずの間の間隙の幅は、䟋
えば玄〜Όmの範囲ずするこずができ、玄
〜Όmの範囲ずするこずが奜たしい。
Although not particularly limited, the average thickness of the conductor (here, copper film) forming each part of the hole conductor 22 (see FIGS. 4 to 6) is, for example, about 10 to 120 ÎŒm.
The range is about 16 to 32 ÎŒm, and the range is preferably about 16 to 32 ÎŒm. It is preferable that the thickness of the surface conductor 24 is similar to that of the hole conductor. In addition, the first flat surface portion 2
The diameter of 2b depends on the inner diameter of the through hole 12, but may be, for example, about 0.4 to 1.2 mm, and about 0.6 to
A range of 1.0 mm is preferable. The width (distance between the outer peripheral edge and the inner peripheral edge) of the first flat surface portion 22b can be set to, for example, about 0.2 to 0.6 mm and is set to about 0.2 to 0.4.
The range of mm is preferable. And the first plane portion 2
The width of the gap G between the outer periphery of 2b and the surface conductor 24 can be, for example, in the range of about 100 to 500 ÎŒm, and preferably in the range of about 200 to 300 ÎŒm.

【】ホヌル導電䜓の数配眮密床を増や
すこずによっお、半田局の欠陥をより粟床よく怜出
し埗る。䞀方、ホヌル導電䜓の数を過剰に倚くする
ず間隙の合蚈面積が倧きくなる。すなわち、攟熱ラン
ドの実効面積ホヌル導電䜓のうち基板衚面に
圢成された郚分第䞀平面郚ず衚面導電䜓
ずの合蚈面積が小さくなる。このため攟熱性胜が䜎䞋
しやすくなる。パッケヌゞの皮類にもよるが、ホヌ
ル導電䜓の奜たしい配眮密床は玄〜個
cm2の範囲であり、玄〜個cm2の範囲が
より奜たしい。たた、攟熱ランドが蚭けられた範囲
の党䜓面積に察しお、その実効面積党䜓面積から間隙
の面積を陀いたものが抂ね〜の範囲
にあるこずが奜たしく、〜の範囲がより奜た
しい。さらに、パッケヌゞが配眮される範囲の面
積に察しお、この範囲内に蚭けられた攟熱ランド
の党䜓面積が抂ね〜の範囲にあるこずが奜
たしく、〜の範囲がより奜たしい。
By increasing the number of hole conductors 22 (arrangement density), defects in the solder layer 40 can be detected more accurately. On the other hand, if the number of hole conductors 22 is excessively increased, the total area of the gap G becomes large. That is, the effective area of the heat dissipation land 20 (the portion of the hole conductor 22 formed on the surface of the substrate (first flat surface portion 22b) and the surface conductor 24).
And the total area) becomes smaller. For this reason, the heat dissipation performance is likely to deteriorate. Although depending on the type of the package 30, the preferable arrangement density of the hole conductors 22 is in the range of about 0.1 to 0.5 pieces / cm 2 , and the range of about 0.2 to 0.3 pieces / cm 2 . More preferable. Further, it is preferable that the effective area (the area excluding the area of the gap G from the entire area) is in the range of approximately 70 to 99.5% with respect to the entire area in which the heat dissipation land 20 is provided. The range of up to 99% is more preferable. Further, with respect to the area of the range P in which the package 30 is arranged, the heat dissipation land 20 provided within this range P
The total area is preferably in the range of 60 to 100%, more preferably in the range of 70 to 100%.

【】第二実斜䟋本実斜䟋は、第䞀実斜䟋に
係る半導䜓装眮ずは攟熱ランドの圢状が異なる䟋であ
る。図に瀺すように、基板のうちパッケヌゞ
が配眮された範囲の内偎には、耇数の貫通孔
が、瞊暪にほが等間隔で栌子状に敎列配眮されおい
る。この範囲の内偎に耇数のホヌル導電䜓が蚭け
られおいる。各ホヌル導電䜓は、貫通孔から基
板の裏面に向けお延びる郚分を有し、その貫通孔
の内郚からその呚囲の基板衚面たで長方圢状に拡がっ
おいる。これらのホヌル導電䜓は、栌子状の間隙
を解しお基板衚面で互いに面方向に分離されおいる。こ
れらのホヌル導電䜓によっお攟熱ランドが構成
されおいる。その他の郚分の構成は第䞀実斜䟋ず同様で
ある。かかる圢状の攟熱ランドを備える半導䜓装眮
においおも、第䞀実斜䟋ず同様に、半田局の品質を容易
にモニタするこずができる。
(Second Embodiment) This embodiment is an example in which the shape of the heat dissipation land is different from that of the semiconductor device according to the first embodiment. As shown in FIG. 10, the package 3 of the substrate 10
Inside the range P in which 0 is arranged, a plurality of through holes 12
, Are aligned vertically and horizontally at substantially equal intervals (in a grid pattern). Inside this range P, a plurality of hole conductors 22 are provided. Each hole conductor 22 has a portion extending from the through hole 12 toward the back surface of the substrate 10.
It extends in a rectangular shape from the inside of 2 to the substrate surface around it. These hole conductors 12 have a grid-like gap G.
The substrate surface is separated from each other in the plane direction. The hole conductor 22 constitutes the heat dissipation land 20. The configuration of the other parts is similar to that of the first embodiment. Also in the semiconductor device including the heat dissipation land 20 having such a shape, the quality of the solder layer can be easily monitored as in the first embodiment.

【】以䞊、本発明の具䜓䟋を詳现に説明した
が、これらは䟋瀺にすぎず、特蚱請求の範囲を限定する
ものではない。特蚱請求の範囲に蚘茉の技術には、以䞊
に䟋瀺した具䜓䟋を様々に倉圢、倉曎したものが含たれ
る。たた、本明现曞たたは図面に説明した技術芁玠は、
単独であるいは各皮の組み合わせによっお技術的有甚性
を発揮するものであり、出願時請求項蚘茉の組み合わせ
に限定されるものではない。たた、本明现曞たたは図面
に䟋瀺した技術は耇数目的を同時に達成するものであ
り、そのうちの䞀぀の目的を達成するこず自䜓で技術的
有甚性を持぀ものである。
Specific examples of the present invention have been described above in detail, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. Further, the technical elements described in the present specification or the drawings are
The technical usefulness is exhibited alone or in various combinations, and is not limited to the combinations described in the claims at the time of filing. In addition, the technique illustrated in the present specification or the drawings achieves a plurality of purposes at the same time, and achieving the one purpose among them has technical utility.

【図面の簡単な説明】[Brief description of drawings]

【図】 第䞀実斜䟋に係る半導䜓装眮を瀺す断面図で
ある。
FIG. 1 is a cross-sectional view showing a semiconductor device according to a first embodiment.

【図】 パッケヌゞを図のII方向から芋た平面図で
ある。
FIG. 2 is a plan view of the package as seen from the direction II in FIG.

【図】 パッケヌゞを図のIII方向から芋た平面図
である。
FIG. 3 is a plan view of the package viewed from the direction III in FIG.

【図】 攟熱ランドの圢状を瀺す平面図である。FIG. 4 is a plan view showing the shape of a heat dissipation land.

【図】 図の郚分の拡倧図である。FIG. 5 is an enlarged view of a V portion of FIG.

【図】 攟熱ランドずパッケヌゞずの接続構造を瀺す
断面図である。
FIG. 6 is a cross-sectional view showing a connection structure between a heat dissipation land and a package.

【図】 ホヌル導電䜓間の抵抗倀を枬定する様子を瀺
す暡匏図である。
FIG. 7 is a schematic diagram showing how the resistance value between hole conductors is measured.

【図】 半田局にボむドが圢成された状態を瀺す断面
図である。
FIG. 8 is a cross-sectional view showing a state where voids are formed in the solder layer.

【図】 第䞀実斜䟋の倉圢䟋を瀺す断面図である。FIG. 9 is a cross-sectional view showing a modified example of the first embodiment.

【図】 第二実斜䟋に係る半導䜓装眮の攟熱ランド
を瀺す平面図である。
FIG. 10 is a plan view showing a heat dissipation land of a semiconductor device according to a second embodiment.

【笊号の説明】[Explanation of symbols]

ガラス−゚ポキシ基板基板 貫通孔 攟熱ランド導電䜓矀 ホヌル導電䜓導電䜓 衚面導電䜓導電䜓 パッケヌゞ 攟熱板金属板 半田局導電材局 コンタクトプロヌブ ボむド 10: Glass-epoxy substrate (substrate) 12: Through hole 20: Heat dissipation land (conductor group) 22: Hall conductor (conductor) 24: Surface conductor (conductor) 30: Package 34: Heat sink (metal plate) 40: Solder layer (conductive material layer) 92: Contact probe K: Void

Claims (7)

【特蚱請求の範囲】[Claims] 【請求項】 貫通孔を有する基板にパッケヌゞの底面
が接続された半導䜓装眮であっお、 その基板のうちパッケヌゞが配眮された範囲には面方向
に分離された耇数の導電䜓から構成された導電䜓矀が蚭
けられおいるずずもに、その導電䜓矀にパッケヌゞの底
面が導電材局を挟んで接続されおおり、 その導電䜓矀を構成する導電䜓のうち少なくずも䞀぀は
貫通孔から裏面に向けお延びるホヌル導電䜓であるこず
を特城ずする半導䜓装眮。
1. A semiconductor device in which a bottom surface of a package is connected to a substrate having a through hole, and a range in which the package is arranged on the substrate is composed of a plurality of conductors separated in a plane direction. A conductor group is provided, and the bottom surface of the package is connected to the conductor group with a conductive material layer sandwiched therebetween, and at least one of the conductors forming the conductor group is connected from the through hole to the back surface. A semiconductor device, which is a hole conductor extending toward a hole.
【請求項】 前蚘パッケヌゞの底面には金属板が備え
られおいる請求項に蚘茉の半導䜓装眮。
2. The semiconductor device according to claim 1, wherein a metal plate is provided on a bottom surface of the package.
【請求項】 前蚘導電䜓矀は、栌子状に配眮された耇
数の前蚘ホヌル導電䜓ず、そのホヌル導電䜓から間隙を
隔おお面的に拡がっおいる衚面導電䜓ずを含んで構成さ
れおいる請求項たたはに蚘茉の半導䜓装眮。
3. The conductor group is configured to include a plurality of the hole conductors arranged in a grid pattern and a surface conductor that is spread in a plane from the hole conductors with a gap. The semiconductor device according to claim 1, wherein
【請求項】 貫通孔ず、面方向に分離された耇数の導
電䜓から構成された導電䜓矀ずを備え、その導電䜓矀を
構成する導電䜓のうち少なくずも䞀぀はその貫通孔から
裏面に向けお延びるホヌル導電䜓である基板を甚意する
工皋ず、 導電材局を挟んでその導電䜓矀にパッケヌゞの底面を接
続する工皋ずを備える半導䜓装眮の補造方法。
4. A through hole and a conductor group composed of a plurality of conductors separated in a surface direction, wherein at least one of the conductors forming the conductor group is a back surface from the through hole. 1. A method of manufacturing a semiconductor device, comprising: a step of preparing a substrate that is a hole conductor extending toward a substrate; and a step of connecting a bottom surface of a package to the conductor group with a conductive material layer interposed therebetween.
【請求項】 前蚘パッケヌゞの底面を接続する工皋の
埌に、前蚘ホヌル導電䜓ず他の導電䜓ずの間の導通性を
調べる工皋をさらに備える請求項に蚘茉の半導䜓装眮
の補造方法。
5. The method of manufacturing a semiconductor device according to claim 4, further comprising a step of examining electrical continuity between the hole conductor and another conductor after the step of connecting the bottom surface of the package.
【請求項】 前蚘導電䜓矀は二以䞊の前蚘ホヌル導電
䜓を有し、それらのホヌル導電䜓の間の抵抗倀を枬定す
るこずにより前蚘導通性を調べるこずを特城ずする請求
項に蚘茉の半導䜓装眮の補造方法。
6. The conductor group has two or more hole conductors, and the conductivity is checked by measuring a resistance value between the hole conductors. A method for manufacturing a semiconductor device as described above.
【請求項】 前蚘導電䜓矀は、前蚘ホヌル導電䜓ず、
そのホヌル導電䜓の呚囲を残しお連続的に蚭けられた衚
面導電䜓ずを含んで構成されおおり、 その衚面導電䜓ず前蚘ホヌル導電䜓ずの間の抵抗倀を枬
定するこずにより前蚘導通性を調べるこずを特城ずする
請求項に蚘茉の半導䜓装眮の補造方法。
7. The conductor group includes the hole conductor,
It is configured to include a surface conductor continuously provided with the periphery of the hole conductor remaining, and the conductivity is measured by measuring a resistance value between the surface conductor and the hole conductor. The method for manufacturing a semiconductor device according to claim 5, further comprising:
JP2002095743A 2002-03-29 2002-03-29 Semiconductor device and method of manufacturing the same Pending JP2003297965A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002095743A JP2003297965A (en) 2002-03-29 2002-03-29 Semiconductor device and method of manufacturing the same

Publications (1)

Publication Number Publication Date
JP2003297965A true JP2003297965A (en) 2003-10-17

Family

ID=29387294

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Link
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2973942A1 (en) * 2011-04-08 2012-10-12 Continental Automotive France ELECTRONIC COMPONENT WITH THERMAL DISSIPATION PASTILLE AND CARD USING THE SAME
KR20140132577A (en) * 2013-05-08 2014-11-18 엘지디슀플레읎 죌식회사 Testing apparatus and method for flat display device
JP2016103604A (en) * 2014-11-28 2016-06-02 ファナック株匏䌚瀟 Printed circuit board with thermal pad in notched shape
JP2017015519A (en) * 2015-06-30 2017-01-19 ゚スアむアむ・セミコンダクタ株匏䌚瀟 Method for inspecting mounting state of semiconductor device, and semiconductor device mounted on mounting board
CN112670254A (en) * 2020-12-30 2021-04-16 华芯嚁半富䜓科技(北京)有限莣任公叞 Packaging structure for improving packaging thermal uniformity of SiC power device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2973942A1 (en) * 2011-04-08 2012-10-12 Continental Automotive France ELECTRONIC COMPONENT WITH THERMAL DISSIPATION PASTILLE AND CARD USING THE SAME
KR20140132577A (en) * 2013-05-08 2014-11-18 엘지디슀플레읎 죌식회사 Testing apparatus and method for flat display device
KR102016076B1 (en) 2013-05-08 2019-10-21 엘지디슀플레읎 죌식회사 Testing apparatus and method for flat display device
JP2016103604A (en) * 2014-11-28 2016-06-02 ファナック株匏䌚瀟 Printed circuit board with thermal pad in notched shape
JP2017015519A (en) * 2015-06-30 2017-01-19 ゚スアむアむ・セミコンダクタ株匏䌚瀟 Method for inspecting mounting state of semiconductor device, and semiconductor device mounted on mounting board
CN112670254A (en) * 2020-12-30 2021-04-16 华芯嚁半富䜓科技(北京)有限莣任公叞 Packaging structure for improving packaging thermal uniformity of SiC power device

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