JP2003297965A - Semiconductor device and method of manufacturing the same - Google Patents
Semiconductor device and method of manufacturing the sameInfo
- Publication number
- JP2003297965A JP2003297965A JP2002095743A JP2002095743A JP2003297965A JP 2003297965 A JP2003297965 A JP 2003297965A JP 2002095743 A JP2002095743 A JP 2002095743A JP 2002095743 A JP2002095743 A JP 2002095743A JP 2003297965 A JP2003297965 A JP 2003297965A
- Authority
- JP
- Japan
- Prior art keywords
- conductor
- hole
- package
- substrate
- conductors
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 41
- 238000004519 manufacturing process Methods 0.000 title claims description 16
- 239000004020 conductor Substances 0.000 claims abstract description 200
- 239000000758 substrate Substances 0.000 claims abstract description 69
- 238000000034 method Methods 0.000 claims abstract description 13
- 229910052751 metal Inorganic materials 0.000 claims description 11
- 239000002184 metal Substances 0.000 claims description 11
- 230000017525 heat dissipation Effects 0.000 abstract description 49
- 229910000679 solder Inorganic materials 0.000 abstract description 41
- 230000007547 defect Effects 0.000 abstract description 14
- 239000000523 sample Substances 0.000 abstract description 10
- 239000011800 void material Substances 0.000 abstract description 8
- 238000005259 measurement Methods 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 58
- 239000000463 material Substances 0.000 description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- 238000012546 transfer Methods 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 239000004593 Epoxy Substances 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- 238000007689 inspection Methods 0.000 description 5
- 239000011265 semifinished product Substances 0.000 description 5
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 4
- 229920005989 resin Polymers 0.000 description 4
- 239000011347 resin Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 2
- 239000011231 conductive filler Substances 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000010419 fine particle Substances 0.000 description 1
- 238000007667 floating Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 229920000620 organic polymer Polymers 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 229920002050 silicone resin Polymers 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
- 239000011701 zinc Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
ãïŒïŒïŒïŒã[0001]
ãçºæã®å±ããæè¡åéã æ¬çºæã¯ãåºæ¿ã«ããã±ãŒ
ãžãå®è£
ãããåå°äœè£
眮ããã³ãã®è£œé æ¹æ³ã«é¢ã
ããTECHNICAL FIELD The present invention relates to a semiconductor device in which a package is mounted on a substrate and a manufacturing method thereof.
ãïŒïŒïŒïŒã[0002]
ãåŸæ¥ã®æè¡ã é»åçšçŽ åãã®ä»ã®åå°äœçŽ åïŒãã
ãïŒãå容ããããã±ãŒãžãåºæ¿ã«å®è£
ãããåå°äœè£
眮ãç¥ãããŠããããã®ãããªåå°äœè£
眮ãšããŠãåºæ¿
衚é¢ã«æŸç±ã©ã³ãçãšåŒã°ããèç¶ã®å°é»äœãèšããã
ã®æŸç±ã©ã³ãã«ããã±ãŒãžã®åºé¢ããåç°çã®ç±äŒå°æ§
ã®è¯ãææãããªãå±€ãæãã§æ¥ç¶ããæ§æãæããã
ã®ããããäžè¬ã«ããããæ§æã®åå°äœè£
眮ã¯ããã±ãŒ
ãžã®æŸç±æ§ãè¯å¥œã§ããããããã£ãŠã倧黿µãéé»ã
ãããã«çºç±éã倧ãããªãåå°äœçŽ åïŒäŸãã°é»åçš
åå°äœçŽ åïŒãå
èµããããã±ãŒãžãå®è£
ããåå°äœè£
眮ãšããŠå¥œé©ã§ããã2. Description of the Related Art There is known a semiconductor device in which a package containing a power element and other semiconductor elements (chips) is mounted on a substrate. As such a semiconductor device, a film-shaped conductor called a heat dissipation land is provided on the surface of the substrate, and the bottom surface of the package is connected to the heat dissipation land with a layer made of a material having good heat conductivity such as solder being sandwiched therebetween. Some have. In general, the semiconductor device having such a configuration has a good heat dissipation property of the package. Therefore, it is suitable as a semiconductor device in which a package including a semiconductor element (for example, a power semiconductor element) that generates a large amount of heat due to a large current is mounted.
ãïŒïŒïŒïŒã[0003]
ãçºæã解決ããããšãã課é¡ã ããã§ãè£œé æ¡ä»¶ã®
ã°ãã€ãçã«ãã£ãŠãæŸç±ã©ã³ããšããã±ãŒãžãšã®æ¥ç¶
ãé©åã«ãªãããªãå ŽåããããäŸãã°ãããããæ¥ç¶
ããäŒç±å±€ïŒå
žåçã«ã¯åç°å±€ïŒã«ãã€ããã¯ã©ãã¯ã
æµ®ãçã®æ¬ é¥ã圢æãããŠããå Žåã§ããããã®ãããª
æ¬ é¥ã®çšåºŠãèãããªããšããã±ãŒãžã®æŸç±æ§ãäœäžã
ããããã§ãããã±ãŒãžãæ¥ç¶ããåŸã«äŒç±å±€ã®æ¬ é¥ã®
çšåºŠïŒæŸç±ã©ã³ããšããã±ãŒãžãšã®æ¥ç¶ç¶æ
ïŒãæ€æ»ã
ãæ¹æ³ãšããŠã補é ã©ã€ã³ããäžéšã®å補åãä»»ææœåº
ãããã®æœåºããå補åã«ééç·ãç
§å°ããŠäŒç±å±€ã®
圢æç¶æ
ãæ€æ»ããæ¹æ³çãææ¡ãããŠããããããã
ã®æ¹æ³ã«ã¯ãæ€æ»ã«æéãèŠãããæ€æ»è£
眮ãé«äŸ¡ã§ã
ãçã®äžéœåããããProblems to be Solved by the Invention Here, due to variations in manufacturing conditions and the like, the heat dissipation lands and the package may not be properly connected. For example, voids, cracks, or cracks in the heat transfer layer (typically a solder layer) that connects these
This is the case where defects such as floating are formed. When the degree of such a defect becomes significant, the heat dissipation of the package deteriorates. Therefore, as a method to inspect the degree of defects in the heat transfer layer (connection state between the heat dissipation land and the package) after connecting the packages, some semi-finished products are arbitrarily extracted from the manufacturing line and transmitted to the extracted semi-finished products. A method of irradiating X-rays and inspecting the formation state of the heat transfer layer has been proposed. However, this method has disadvantages such as time-consuming inspection and expensive inspection device.
ãïŒïŒïŒïŒãããã§æ¬çºæã¯ãæŸç±ã©ã³ããšããã±ãŒãž
ãšã®æ¥ç¶ç¶æ
ã容æã«æ€æ»ãåŸãåå°äœè£
眮ããã³ãã®
è£œé æ¹æ³ãæäŸããããšãç®çãšãããæ¬çºæã®ä»ã®ç®
çã¯ããã®ãããªæ€æ»æ¹æ³ãé©çšããŠåå°äœè£
眮ã補é
ããæ¹æ³ãæäŸããããšã§ãããSUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor device which can easily inspect the connection state between a heat dissipation land and a package, and a manufacturing method thereof. Another object of the present invention is to provide a method of manufacturing a semiconductor device by applying such an inspection method.
ãïŒïŒïŒïŒã[0005]
ã課é¡ã解決ããããã®ææ®µãšäœçšãšå¹æã æ¬çºæè
ã¯ãäºãã«åé¢ãããè€æ°ã®å°é»äœã«ãã£ãŠæŸç±ã©ã³ã
ãæ§æãããšãšãã«ãæŸç±ã©ã³ããšããã±ãŒãžãæ¥ç¶ã
ãå°é»æå±€ïŒäŒç±å±€ïŒãä»ããŠãããã®å°é»äœã黿°ç
ã«æ¥ç¶ããåŸãããã«æ§æããããšã«ãããåèšç®çã
éæã§ããããšãèŠåºãããMeans for Solving the Problems, Actions and Effects The present inventor configures a heat dissipation land by a plurality of conductors separated from each other, and provides a conductive material layer (heat transfer layer) connecting the heat dissipation land and the package. It has been found that the above object can be achieved by configuring such conductors so that they can be electrically connected to each other.
ãïŒïŒïŒïŒãæ¬çºæã¯ãããã±ãŒãžã®åºé¢ãåºæ¿ã«æ¥ç¶
ãããåå°äœè£
眮ã«é¢ããããã®åºæ¿ã®ãã¡ããã±ãŒãž
ãé
眮ãããç¯å²ã«ã¯ã颿¹åã«åé¢ãããè€æ°ã®å°é»
äœããæ§æãããå°é»äœçŸ€ãèšããããŠããããŸããã
ã®åºæ¿ã¯è²«éåãæããå°é»äœçŸ€ãæ§æããå°é»äœã®ã
ã¡å°ãªããšãäžã€ã¯ãã®è²«éåããè£é¢ã«åããŠå»¶ã³ã
ããŒã«å°é»äœã§ãããããã±ãŒãžã®åºé¢ã¯ãå°é»æå±€ã
æãã§ãã®å°é»äœçŸ€ã«æ¥ç¶ãããŠãããThe present invention relates to a semiconductor device in which the bottom surface of a package is connected to a substrate. A conductor group composed of a plurality of conductors separated in the surface direction is provided in the area where the package is arranged on the substrate. The substrate has a through hole, and at least one of the conductors forming the conductor group is a hole conductor extending from the through hole toward the back surface. The bottom surface of the package is connected to the conductor group with the conductive material layer interposed therebetween.
ãïŒïŒïŒïŒããã®ãããªæ§æã®åå°äœè£
眮ã«ãããŠãäŸ
ãã°å°é»æå±€ã®äžéšã«ãã€ããçããŠããããã®ãã€ã
ãçããç¯å²å
ã«ããããã®ããŒã«å°é»äœã®å
šäœãäœçœ®
ããŠããå Žåã«ã¯ããã®ããŒã«å°é»äœã«ã¯å°é»æå±€ãæ¥
ç¶ãããªããäžæ¹ããã®ïŒãã€ãå
ã«äœçœ®ããïŒããŒã«
å°é»äœãšä»ã®å°é»äœïŒå°é»äœçŸ€ãæ§æããä»ã®ããŒã«å°
é»äœããããã¯ä»ã®ããŒã«å°é»äœããã³ããŒã«å°é»äœä»¥
å€ã®å°é»äœãæãã以äžåããïŒãšã¯é¢æ¹åã«åé¢ãã
ãŠããã®ã§ããããå Žåã«ã¯ãã®ããŒã«å°é»äœãšä»ã®å°
é»äœãšã®éãå°éããªãããããã£ãŠãããŒã«å°é»äœãš
ä»ã®å°é»äœãšã®å°éæ§ïŒäŸãã°æµæå€ïŒã調ã¹ãããšã«
ãã£ãŠãé¡èãªïŒäŸãã°ãæŸç±æ§èœã倧å¹
ã«äœäžããã
ãããªïŒãã€ãã®çºçãæ€åºããããšãã§ããããã®ã
ãã«ãæ¬çºæã®åå°äœè£
眮ã«ãããšãå°é»äœçŸ€ïŒæŸç±ã©
ã³ãïŒãšããã±ãŒãžãšã®æ¥ç¶ç¶æ
ïŒããã±ãŒãžã®æŸç±æ§
èœïŒã容æã«ã¢ãã¿ããããšãã§ãããIn the semiconductor device having such a structure, for example, when a void is formed in a part of the conductive material layer and one of the hole conductors is entirely located within the range where the void is formed, The conductive material layer is not connected to the hole conductor. On the other hand, the hole conductor (positioned in the void) and another conductor (another hole conductor forming a conductor group, or another hole conductor and a conductor other than the hole conductor) are referred to hereinafter. .) Is separated in the plane direction, and in such a case, there is no electrical connection between the hole conductor and another conductor. Therefore, by examining the conductivity (for example, the resistance value) between the hole conductor and another conductor, it is possible to detect the occurrence of a significant void (for example, which significantly reduces the heat dissipation performance). As described above, according to the semiconductor device of the present invention, it is possible to easily monitor the connection state (heat dissipation performance of the package) between the conductor group (heat dissipation land) and the package.
ãïŒïŒïŒïŒãå°é»äœçŸ€ãæ§æããåå°é»äœã¯ããããã«
è·šã£ãŠåœ¢æãããå°é»æå±€ã«ãã£ãŠããã±ãŒãžã«æ¥ç¶ã
ããŠããŠããããåå°é»äœå±€äžã«åœ¢æãããåã
ã®ïŒäº
ãã«ç¬ç«ããïŒå°é»äœå±€ã«ãã£ãŠããã±ãŒãžã«æ¥ç¶ãã
ãŠããŠãããããããã®æ¥ç¶åœ¢æ
ãæ··åšããŠããŠãã
ããäºã€ã®å°é»äœãäºãã«ç¬ç«ããå°é»æå±€ã«ãã£ãŠã
ãã±ãŒãžåºé¢ã«æ¥ç¶ãããå Žåã§ãã£ãŠãããããã®å°
黿局ãããã±ãŒãžãä»ããŠäºãã«å°éå¯èœã§ããã°ã
ãããã®å°é»æå±€ããã³ããã±ãŒãžãçµç±ããŠäºã€ã®å°
é»äœã®éãå°éãããããšãã§ãããEach of the conductors forming the conductor group may be connected to the package by a conductive material layer formed over the conductors, and each (independent of each other) formed on each conductor layer. It may be connected to the package by a conductor layer, and these connection forms may be mixed. Even when two conductors are connected to the package bottom surface by conductive material layers independent of each other, as long as these conductive material layers can conduct each other through the package,
Conduction can be established between the two conductors via these conductive material layers and the package.
ãïŒïŒïŒïŒãããã±ãŒãžåºé¢ã«æ¥ç¶ãããè€æ°ã®ç¬ç«ã
ãå°é»äœãããã®ããã±ãŒãžãä»ããŠå°éãããããšã®
ã§ãã奜ãŸããæ§æãšããŠããã®ããã±ãŒãžãåºé¢ã«é
屿¿ãåããæ§æãäŸç€ºãããããã®é屿¿ãšããŠã¯ã
åŸæ¥ã®ããã±ãŒãžã«åããããããŒãã·ã³ã¯çãå©çšã
ãããšãã§ããããã®ãããªããã±ãŒãžã¯ããã®æŸç±æ§
èœã«åªãããšããç¹ããã奜ãŸãããAs a preferable structure in which a plurality of independent conductors connected to the bottom surface of the package can be conducted through this package, a structure in which the bottom surface of the package is provided with a metal plate is exemplified. For this metal plate,
A heat sink or the like provided in a conventional package can be used. Such a package is also preferable from the viewpoint of excellent heat dissipation performance.
ãïŒïŒïŒïŒãæ¬çºæã®åå°äœè£
眮ã«åããããå°é»äœçŸ€
ã®ãã¡å¥œãŸãããã®ã¯ããâã«å°é»äœãšããã®ããŒã«å°
é»äœããééãéãŠãŠé¢çã«æ¡ãã£ãŠãã衚é¢å°é»äœãš
ãå«ãã§æ§æãããŠããããããæ§æã«ãããšãé£ç¶ç
ã«èšãããã衚é¢å°é»äœã«ãã£ãŠåºæ¿ã®é¢æ¹åãžã®äŒç±
ãå¹çããè¡ãããããã®ããšã«ãã£ãŠæŸç±æ§èœããã
ã«åäžããåŸãããŸãããã®è¡šé¢å°é»äœãéããŠåºæ¿ã®
颿¹åã®æž©åºŠå·®ãåäžåããããšãã§ããã®ã§ããã®æž©
床差ã«èµ·å ããŠæŸç±ã©ã³ããæ§æããå°é»äœãå°é»æå±€
çã«ãããã¹ãã¬ã¹ã軜æžãåŸããA preferred conductor group included in the semiconductor device of the present invention includes a hole conductor and a surface conductor that is spread over the surface of the hole conductor with a gap. Has been done. With such a configuration, the surface conductors continuously provided can efficiently transfer heat in the surface direction of the substrate. This can further improve the heat dissipation performance. In addition, since the temperature difference in the surface direction of the substrate can be made uniform through this surface conductor, it is possible to reduce stress applied to the conductor, the conductive material layer, and the like that form the heat dissipation land due to this temperature difference.
ãïŒïŒïŒïŒããŸããæ¬çºæã«ããæäŸãããåå°äœè£
眮
ã®è£œé æ¹æ³ã¯ã貫éåãšã颿¹åã«åé¢ãããè€æ°ã®å°
é»äœããæ§æãããå°é»äœçŸ€ãšãåããåºæ¿ãçšæãã
å·¥çšãåããããããã®å°é»äœã®ãã¡å°ãªããšãäžã€
ã¯ãåºæ¿ã®è²«éåããè£é¢ã«åããŠå»¶ã³ãããŒã«å°é»äœ
ã§ããããŸãããã®å°é»äœçŸ€ã«ãå°é»æå±€ãæãã§ãã
ã±ãŒãžã®åºé¢ãæ¥ç¶ããå·¥çšãåããããããè£œé æ¹æ³
ã«ãããšãæ¬çºæã®åå°äœè£
眮ãã®ä»ã®åå°äœè£
眮ã奜
é©ã«è£œé ããããšãã§ãããFurther, the method for manufacturing a semiconductor device provided by the present invention includes the step of preparing a substrate having a through hole and a conductor group composed of a plurality of conductors separated in a plane direction. At least one of these conductors is a hole conductor extending from the through hole of the substrate toward the back surface. Further, the method includes a step of connecting the bottom surface of the package to the conductor group with the conductive material layer interposed therebetween. According to such a manufacturing method, the semiconductor device of the present invention and other semiconductor devices can be preferably manufactured.
ãïŒïŒïŒïŒããã®è£œé æ¹æ³ã¯ãå°é»äœçŸ€ã«ããã±ãŒãžã®
åºé¢ãæ¥ç¶ããå·¥çšã®åŸã«ãããŒã«å°é»äœãšä»ã®å°é»äœ
ãšã®éã®å°éæ§ã調ã¹ãå·¥çšãããã«åããããšãã§ã
ãããã®å·¥çšã«ãã£ãŠãå°é»äœçŸ€ãšããã±ãŒãžãšãæ¥ç¶
ããå°é»æå±€ã®å質ãç°¡åã«ç¥ãããšãã§ãããäŸã
ã°ãå°é»æå±€ã«é¡èãªïŒäŸãã°ãæŸç±æ§èœã倧å¹
ã«äœäž
ããããããªïŒæ¬ é¥ãçããŠããå Žåã«ã¯ãããŒã«å°é»
äœãšä»ã®å°é»äœãšã®éã®å°éæ§ã調ã¹ãããšã«ãã£ãŠã
ã®æ¬ é¥ïŒãã€ãçïŒãæ€åºãåŸãããããŠã調ã¹ãçµ
æãæ¬ é¥ã®çšåºŠãæå®ã®åºæºä»¥äžã«çã ãããšèªããã
ãå Žåã«ã¯ãã®å補åïŒè£œé éäžã®åå°äœè£
眮ïŒã補é
ã©ã€ã³ããåãé€ãããšã«ãããæŸç±æ§èœã«åªããåå°
äœè£
眮ãå®å®ããŠè£œé ããããšãã§ãããThis manufacturing method may further include a step of examining the electrical conductivity between the hole conductor and another conductor after the step of connecting the bottom surface of the package to the conductor group. Through this step, the quality of the conductive material layer connecting the conductor group and the package can be easily known. For example, if the conductive material layer has a remarkable defect (for example, that significantly reduces heat dissipation performance), the defect is examined by examining the conductivity between the hole conductor and another conductor. (Voids etc.) can be detected. Then, when the result of the inspection shows that the degree of defects is more than the predetermined standard, the semi-finished product (semiconductor device in the process of manufacture) is removed from the manufacturing line to stabilize the semiconductor device with excellent heat dissipation performance. Can be manufactured.
ãïŒïŒïŒïŒãããŒã«å°é»äœãšä»ã®å°é»äœãšã®éã®å°éæ§
ã¯ãå
žåçã«ã¯äž¡è
ã®éã®æµæå€ã枬å®ããããšã«ãã
調ã¹ãããšãã§ãããå°é»äœçŸ€ãäºä»¥äžã®ããŒã«å°é»äœ
ãæããå Žåã«ã¯ããããã®ããŒã«å°é»äœã®éã®å°éæ§
ïŒå¥œãŸããã¯æµæå€ïŒã調ã¹ãããšã奜ãŸããããŸãã
å°é»äœçŸ€ããããŒã«å°é»äœããééãéãŠãŠé¢çã«æ¡ã
ã£ãŠãã衚é¢å°é»äœãå«ãã§æ§æãããŠããå Žåã«ã¯ã
ããŒã«å°é»äœãšè¡šé¢å°é»äœãšã®éã®å°éæ§ïŒå¥œãŸããã¯
æµæå€ïŒã調ã¹ãŠããããConductivity between the hole conductor and another conductor can be examined typically by measuring the resistance value between the two. When the conductor group has two or more hole conductors, it is preferable to check the conductivity (preferably resistance value) between the hole conductors. Also,
When the conductor group is configured to include a surface conductor that spreads in a plane from the hole conductor with a gap,
Conductivity (preferably resistance value) between the hole conductor and the surface conductor may be examined.
ãïŒïŒïŒïŒã[0014]
ãçºæã®å®æœã®åœ¢æ
ã ãã®çºæã¯ããŸããäžèšã®åœ¢æ
ã§å®æœããããšãç¹åŸŽãšããã
ïŒåœ¢æ
ïŒïŒããŒã«å°é»äœã¯ãåºæ¿ã®ãã¡ããã±ãŒãžãé
眮ãããç¯å²ã«ãã»ãŒåçã«é
眮ãããŠããããããæ§
æã«ãããšãå°é»æå±€ã®å
šäœã«äºã£ãŠãã®åè³ªïŒæ¬ é¥ã®
çšåºŠïŒãå¹çããã¢ãã¿ããããšãã§ãããBEST MODE FOR CARRYING OUT THE INVENTION The present invention is also characterized by being embodied in the following modes. (Feature 1) The hole conductors are arranged substantially uniformly in the area of the substrate where the package is arranged. According to this structure, the quality (degree of defects) of the entire conductive material layer can be efficiently monitored.
ãïŒïŒïŒïŒãïŒåœ¢æ
ïŒïŒããŒã«å°é»äœã¯ã貫éåãéã
ãŠåºæ¿ã®è¡šé¢åŽããè£é¢ïŒããã±ãŒãžãå®è£
ãããé¢ãš
ã¯å察åŽã®é¢ããããïŒåŽãŸã§è²«éããŠããããããæ§
æã«ãããšãããŒã«å°é»äœãšä»ã®å°é»äœãšã®éã®å°éæ§
ãæž¬å®ããéã®æäœæ§ãè¯ãããŸãããã®ããŒã«å°é»äœ
ãéããŠããã±ãŒãžã®ç±ãåºæ¿ã®è£é¢åŽãžãšå¹çããäŒ
ããïŒç±ãéãïŒããšãã§ããã(Mode 2) The hole conductor penetrates through the through hole from the front surface side of the substrate to the back surface (the surface opposite to the surface on which the package is mounted) side. According to such a configuration, the operability when measuring the conductivity between the hole conductor and another conductor is good. Further, the heat of the package can be efficiently transmitted (heat is dissipated) to the back surface side of the substrate through the hole conductor.
ãïŒïŒïŒïŒãïŒåœ¢æ
ïŒïŒåå°é»äœã®äžã«ããããç¬ç«ã
ãïŒããªãã¡ãäºãã«çŽæ¥æ¥è§ŠããŠããªãïŒå°é»æå±€ã
圢æãããŠããããããã®å°é»æå±€ã¯ããã±ãŒãžã®åºé¢
ã«èšããããé屿¿ãä»ããŠäºãã«é»æ°çã«æ¥ç¶ãããŠ
ããããããæ§æã«ãããšãå°é»æå±€ã®æ¬ é¥ïŒãã€ã
çïŒãããã«ç²ŸåºŠããæ€åºããããšãã§ããã(Mode 3) Independent (that is, not in direct contact with each other) conductive material layers are formed on the respective conductors, and these conductive material layers are provided on the bottom surface of the package. Are electrically connected to each other via. With this configuration, it is possible to detect defects (voids, etc.) in the conductive material layer with higher accuracy.
ãïŒïŒïŒïŒã[0017]
ã宿œäŸã以äžãæ¬çºæã®å¥œé©ãªå®æœäŸã«ã€ããŠè©³çްã«
説æãããæ¬çºæã®åå°äœè£
眮ã«ãããŠåºæ¿ã«å®è£
ãã
ãããã±ãŒãžãšããŠã¯ãåçš®ã®åå°äœçŽ åïŒïŒ©ïŒ§ïŒ¢ïŒŽ
ïŒInsulated Gate Bipolar TransistorïŒçã®ãã€ããŒ
ã©ãã©ã³ãžã¹ã¿ãïŒïŒ¯ïŒ³çã®é»ç广åãã©ã³ãžã¹ã¿
çïŒãåããããã±ãŒãžãçšããããšãã§ããããã®ã
ãã±ãŒãžãããã¯ãŒïŒïŒ¯ïŒ³çã®é»åçšåå°äœçŽ
åïŒãã¯ãŒããã€ã¹ïŒãåããé»åçšïŒ©ïŒ£ããã±ãŒãžã§
ããå Žåã«ã¯ãæ¬çºæãé©çšããããšã«ãã广ãç¹ã«
ããçºæ®ããããThe preferred embodiments of the present invention will be described in detail below. As a package mounted on a substrate in the semiconductor device of the present invention, various semiconductor elements (IGBTs
A package including a bipolar transistor such as an (Insulated Gate Bipolar Transistor) or a field effect transistor such as a MOS can be used. When this package is a power IC package including a power semiconductor element (power device) such as an IGBT or a power MOS, the effect of applying the present invention is particularly well exhibited.
ãïŒïŒïŒïŒãããã±ãŒãžã¯ããã®åºé¢ïŒåºæ¿è¡šé¢ã«å¯Ÿå
ããé¢ïŒã®äžéšãšä»éšãšãå°éå¯èœã«æ§æãããŠããã
ãšã奜ãŸããããã®ãããªæ§æã¯ãããã±ãŒãžã®åºé¢ãŸ
ãã¯å
éšã«å°é»æ§ææãããªãæ¿ãèãŸãã¯é
ç·çãã
ãã®å°ãªããšãäžéšãããã±ãŒãžã®åºé¢ã«é²åºãããã
ã«èšããããšã«ããå®çŸããããšãã§ããã奜ãŸããäŸ
ãšããŠã¯ãããã±ãŒãžã®åºé¢ã«é屿¿ãé
眮ããæ§æã
æãããããäŸãã°ãåºé¢ã«ããŒãã·ã³ã¯ãåããäžè¬
çãªããã±ãŒãžçã奜ãŸããçšããããšãã§ãããThe package is preferably constructed so that a part of the bottom surface (the surface facing the substrate surface) and the other part can be electrically connected. Such a structure has a plate, a film, a wiring, or the like made of a conductive material on the bottom surface or inside of the package,
It can be realized by providing at least a part of the package so as to be exposed on the bottom surface of the package. A preferred example is a configuration in which a metal plate is arranged on the bottom surface of the package. For example, a general package or the like having a heat sink on the bottom surface can be preferably used.
ãïŒïŒïŒïŒããã®ãããªããã±ãŒãžãå®è£
ãããåºæ¿ãš
ããŠã¯ãã¬ã©ã¹åºæ¿ãã¬ã©ã¹âãšããã·åºæ¿ãã»ã©ãã
ã¯åºæ¿ïŒã¢ã«ããåºæ¿ããžã«ã³ãã¢åºæ¿çïŒããã¬ãã·
ãã«ããªã³ãåºæ¿ïŒããªã€ãããã£ã«ã çãããªãïŒç
ã®åçš®ã®åºæ¿ãçšããããšãã§ããããã®åºæ¿ã®æ§é ã¯
åå±€ããã³ç©å±€ã®ãããã§ããããçµ¶çžææãã³ã¢ãš
ãããã®ã³ã¢ã®è¡šé¢ããã³ïŒãŸãã¯å
éšã«åè·¯é
ç·ã圢
æãããåå±€ãŸãã¯ç©å±€æ§é ã®åºæ¿ã奜ãŸããçšããã
ããAs a substrate on which such a package is mounted, various substrates such as a glass substrate, a glass-epoxy substrate, a ceramic substrate (alumina substrate, zirconia substrate, etc.), a flexible printed circuit board (made of a polyimide film, etc.) and the like are used. Can be used. The structure of this substrate may be either a single layer or a laminated layer. A substrate having a single layer or a laminated structure in which an insulating material is used as a core and circuit wiring is formed on the surface and / or inside of the core is preferably used.
ãïŒïŒïŒïŒããã®åºæ¿ã«èšããããå°é»äœã¯ãå
žåçã«
ã¯é屿æãäž»äœã«æ§æãããããã®é屿æãšããŠã¯
ç±äŒå°æ§ã®é«ãææãé©ããŠãããããã«ã黿°äŒå°æ§
ã®é«ãææã奜ãŸãããäŸãã°ãé
ãéãéãçœéãã
ãã±ã«ãã³ãã«ããäºéçã®çŽéå±ããã³ããããå«ã
åéã奜ãŸãã䜿çšãããããŸããããã±ãŒãžã®åºé¢ã«
åããããé屿¿ãšããŠã¯ãäžèšå°é»äœãšåæ§ã®ææã
ãæ§æããããã®çã奜ãŸããçšããããããããã®æ
æã®è¡šé¢ã«ãåç°æ¿¡ãæ§ã®ããéå±ïŒããã±ã«ãã¯ã
ã ãéçïŒãã¡ãããããŠããŠãããããã®ãããªã¡ã
ãå±€ãèšããããšã«ãããå°é»æå±€ãæ§æããå°é»æ§æ
æïŒå
žåçã«ã¯åç°ïŒã«å¯Ÿããæ¿¡ãæ§ã®åäžãææè²»ã®
äœæžãèé
žåæ§ã®åäžçãå®çŸãåŸãããªããåºæ¿ã«èš
ããããå°é»äœã¯ãåºæ¿åŽïŒåè·¯é
ç·åŽïŒã®é»æ¥µãšããŠ
ã®æ©èœãå
ŒãåããŠããŠãããããŸããããã±ãŒãžã®åº
é¢ã«èšããããé屿¿ã¯ãåå°äœçŽ ååŽã®é»æ¥µãšããŠã®
æ©èœãå
ŒãåããŠããŠããããThe conductor provided on this substrate is typically composed mainly of a metal material. A material having high thermal conductivity is suitable as the metal material. Further, a material having high electric conductivity is preferable. For example, pure metals such as copper, silver, gold, platinum, nickel, cobalt and zinc and alloys containing them are preferably used. Further, as the metal plate provided on the bottom surface of the package, one made of the same material as the above conductor is preferably used. The surface of these materials may be plated with a metal having good solder wettability (nickel, chromium, gold, etc.). By providing such a plating layer, it is possible to improve the wettability with respect to the conductive material (typically solder) forming the conductive material layer, reduce the material cost, and improve the oxidation resistance. Note that the conductor provided on the substrate may also have a function as an electrode on the substrate side (circuit wiring side). Further, the metal plate provided on the bottom surface of the package may also have a function as an electrode on the semiconductor element side.
ãïŒïŒïŒïŒãå°é»æå±€ãæ§æããå°é»æ§ææã®å
žåäŸãš
ããŠã¯ãåç°ã«ä»£è¡šãããäœèç¹éå±é¡ãæããããã
ãŸããææ©é«ååçãããªããããªãã¯ã¹æš¹èäžã«å°é»
æ§ã®å
å¡«æã忣ãããå°é»æ§æš¹èææã«ããå°é»æå±€
ãæ§æããŠãããããã®ãããªãã¯ã¹æš¹èãšããŠã¯ãšã
ãã·æš¹èãããªã€ããæš¹èããã§ããŒã«æš¹èãã·ãªã³ãŒ
ã³æš¹èçãçšããããšãã§ãããå°é»æ§å
å¡«æãšããŠ
ã¯ãé
ãéãéãçœéãããã±ã«ãã«ãŒãã³çãããªã
å°é»æ§ç¹ç¶ãå°é»æ§åŸ®ç²åçãçšããããšãã§ãããæ¬
çºæã®åå°äœè£
眮ã«ãããŠå°é»æå±€ãæ§æããå°é»æ§æ
æãšããŠã¯ãåç°çã®äœèç¹éå±é¡ïŒç¹ã«å¥œãŸããã¯å
ç°ïŒã奜ãŸãããTypical examples of the conductive material forming the conductive material layer include low melting point metals represented by solder.
Alternatively, the conductive material layer may be formed of a conductive resin material in which a conductive filler is dispersed in a matrix resin made of an organic polymer or the like. An epoxy resin, a polyimide resin, a phenol resin, a silicone resin, or the like can be used as the matrix resin. As the conductive filler, it is possible to use conductive fibers made of copper, silver, gold, platinum, nickel, carbon or the like, conductive fine particles, or the like. In the semiconductor device of the present invention, a low melting point metal such as solder (particularly preferably solder) is preferable as the conductive material forming the conductive material layer.
ãïŒïŒïŒïŒã以äžãå³é¢ãçšããŠæ¬çºæã®å
·äœç宿œäŸ
ã説æããããæ¬çºæãããã宿œäŸã«ç€ºããã®ã«éå®
ããããšãæå³ãããã®ã§ã¯ãªããSpecific embodiments of the present invention will be described below with reference to the drawings, but the present invention is not intended to be limited to those shown in the embodiments.
ãïŒïŒïŒïŒãïŒç¬¬äžå®æœäŸïŒæ¬çºæã®ç¬¬äžå®æœäŸã«ä¿ã
åå°äœè£
眮ãå³ïŒã«ç€ºããã¬ã©ã¹âãšããã·åºæ¿ïŒïŒã®
衚é¢ã«ããã¯ãŒããã€ã¹ïŒå³ç€ºããïŒãå容ããã
ãã±ãŒãžïŒïŒã®åºé¢ããåç°å±€ïŒïŒãæãã§æ¥ç¶ãããŠ
ããããã®åºæ¿ïŒïŒã¯ãããã±ãŒãžïŒïŒãé
眮ãããç¯
å²ïŒããã±ãŒãžïŒïŒã®äžæ¹ã«äœçœ®ããéšåïŒã«è€æ°ã®è²«
éåïŒïŒãæããã(First Embodiment) FIG. 1 shows a semiconductor device according to a first embodiment of the present invention. The bottom surface of the IC package 30 accommodating the power device (not shown) is connected to the surface of the glass-epoxy substrate 10 with the solder layer 40 interposed therebetween. The substrate 10 has a plurality of through holes 12 in a range in which the package 30 is arranged (a portion located below the package 30).
ãïŒïŒïŒïŒãå³ïŒããã³å³ïŒã«ç€ºãããã«ãããã±ãŒãž
ïŒïŒã®å€åšããã¯è€æ°ã®ãªãŒãïŒïŒãå»¶ã³ãŠããããã
ãã®ãªãŒãïŒïŒã¯ãã¬ã©ã¹âãšããã·åºæ¿ïŒïŒã®è¡šé¢ã«
èšããããåè·¯é
ç·ïŒå³ç€ºããïŒã®æå®ç®æã«ãããã
æ¥ç¶ãããŠããããŸããå³ïŒããã³å³ïŒã«ç€ºãããã«ã
ããã±ãŒãžïŒïŒã®åºé¢ã«ã¯é
è£œã®æŸç±æ¿ïŒïŒãåèšãã
ãŠãããæŸç±æ¿ïŒïŒã®äžé¢ã¯ããã±ãŒãžïŒïŒã®åºé¢ã«é²
åºããŠããããã®ãããªæŸç±æ¿ïŒïŒãåããããã±ãŒãž
ïŒïŒã¯ãäŸãã°ãéåå
ã«æŸç±æ¿ïŒïŒãé
眮ããŠããã±
ãŒãžïŒïŒã®å€ç®ãæ§æããç±ç¡¬åæ§æš¹èãšãã«ã¢ãŒã«ã
æåœ¢ããããšã«ãã補é ããããšãã§ãããAs shown in FIGS. 1 and 2, a plurality of leads 32 extend from the outer periphery of the package 30. These leads 32 are respectively connected to predetermined locations of circuit wiring (not shown) provided on the surface of the glass-epoxy substrate 10. In addition, as shown in FIG. 1 and FIG.
A heat sink 34 made of copper is embedded in the bottom surface of the package 30. The lower surface of the heat dissipation plate 34 is exposed at the bottom surface of the package 30. The package 30 provided with such a heat dissipation plate 34 can be manufactured, for example, by disposing the heat dissipation plate 34 in a mold and molding with a thermosetting resin that forms the outer skin of the package 30.
ãïŒïŒïŒïŒãäžæ¹ãå³ïŒã«ç€ºãããã«ãåºæ¿ïŒïŒã®ãã¡
ããã±ãŒãžïŒïŒãé
眮ãããç¯å²ïŒ°ïŒå³äžãäºç¹éç·ã§
å²ãŸããç¯å²ïŒã®å
åŽã«ã¯ãè€æ°ã®è²«éåïŒïŒãã瞊暪
ã«ã»ãŒçééã§ïŒæ Œåç¶ã«ïŒæŽåé
眮ãããŠããããŸ
ãããã®ç¯å²ïŒ°ã®å
åŽã«ã¯ãé
ãããªãæŸç±ã©ã³ãïŒïŒ
ãèšããããŠããããã®æŸç±ã©ã³ãïŒïŒã¯ãå³ïŒããã³
å³ïŒã«ç€ºãããã«ããããã貫éåïŒïŒããåºæ¿ïŒïŒã®
è£é¢ã«åããŠå»¶ã³ãéšåãæããè€æ°ã®ããŒã«å°é»äœïŒ
ïŒãšããããã®ããŒã«å°é»äœïŒïŒã®åšå²ãæ®ããŠé£ç¶ç
ã«èšããããäžæã®è¡šé¢å°é»äœïŒïŒãšããæ§æãããŠã
ããOn the other hand, as shown in FIG. 4, a plurality of through holes 12 are formed in the vertical and horizontal directions inside the area P in which the package 30 is arranged in the substrate 10 (the area surrounded by the chain double-dashed line in the figure). Are arranged at substantially equal intervals (in a grid pattern). Inside the range P, the heat dissipation land 20 made of copper is used.
Is provided. As shown in FIGS. 4 and 5, the heat dissipation land 20 has a plurality of hole conductors 2 each having a portion extending from the through hole 12 toward the back surface of the substrate 10.
2 and one surface conductor 24 continuously provided with the periphery of these hole conductors 22 left.
ãïŒïŒïŒïŒãå³ïŒããã³å³ïŒã«ç€ºãããã«ãåããŒã«å°
é»äœïŒïŒã¯ã貫éåïŒïŒã®å
å£ãèŠãçéšïŒïŒïœãšãç
éšïŒïŒïœã®äžç«¯ïŒå³ïŒã§ã¯äžç«¯ïŒã«ç¶ããŠåºæ¿ïŒïŒã®è¡š
é¢ïŒããã±ãŒãžïŒïŒãé
眮ãããåŽã®é¢ïŒã«æ¡ããç°ç¶
ã®ç¬¬äžå¹³é¢éšïŒïŒïœãšãçéšïŒïŒïœã®ä»ç«¯ïŒå³ïŒã§ã¯äž
端ïŒã«ç¶ããŠåºæ¿ïŒïŒã®è£é¢ã«æ¡ããç°ç¶ã®ç¬¬äºå¹³é¢éš
ïŒïŒïœãšãåããã衚é¢å°é»äœïŒïŒã¯ãããŒã«å°é»äœïŒ
ïŒã®ç¬¬äžå¹³é¢éšïŒïŒïœã®å€åšãšã®éã«æå®ã®ééãé
ãŠãŠèšããããŠãããããŒã«å°é»äœïŒïŒãšè¡šé¢å°é»äœïŒ
ïŒãšã¯ããã®ééã«ãã£ãŠåºæ¿ïŒïŒã®é¢æ¹åã«åé¢ã
ããŠããããã®ããšã«ãã£ãŠãåºæ¿ïŒïŒã«ãããŠã¯ããŒ
ã«å°é»äœïŒïŒãšè¡šé¢å°é»äœïŒïŒãçµ¶çžãããŠããããª
ããééã®éšåã§ã¯ãã¬ã©ã¹âãšããã·åºæ¿ïŒïŒã®ã³
ã¢ãé²åºããŠããŠãããããã®éšåã«çµ¶çžæ§è¢«èãèšã
ãããŠããŠãããããã®çµ¶çžæ§ç®èãšããŠäžè¬çãªãœã«
ãã¬ãžã¹ãçãå©çšããŠããããAs shown in FIGS. 5 and 6, each hole conductor 22 has a cylindrical portion 22a that covers the inner wall of the through hole 12 and one surface (upper end in FIG. 6) of the cylindrical portion 22a. An annular first flat surface portion 22b extending to (the surface on which the package 30 is arranged) and an annular second flat surface portion 22c extending to the back surface of the substrate 10 following the other end (lower end in FIG. 6) of the tubular portion 22a. With. The surface conductor 24 is the hole conductor 2
A predetermined gap G is provided between the first flat surface portion 22b and the outer circumference of the second flat surface portion 22b. Hall conductor 22 and surface conductor 2
4 is separated in the plane direction of the substrate 10 by this gap G. As a result, the hole conductor 22 and the surface conductor 24 are insulated in the substrate 10. The core of the glass-epoxy substrate 10 may be exposed at the gap G, and an insulating coating may be provided at this portion. A general solder resist or the like may be used as this insulating film.
ãïŒïŒïŒïŒããã®ããã«åœ¢æãããæŸç±ã©ã³ãïŒïŒã«ã
å³ïŒã«ç€ºãããã«ãåç°å±€ïŒïŒãæãã§ããã±ãŒãžïŒïŒ
ã®åºé¢ïŒæŸç±æ¿ïŒïŒïŒãæ¥ç¶ãããŠããããã®åç°å±€ïŒ
ïŒã¯ãåããŒã«å°é»äœïŒïŒã®äžã«åœ¢æãããããŒã«åç°
å±€ïŒïŒãšã衚é¢å°é»äœïŒïŒã®äžã«åœ¢æããã衚é¢åç°å±€
ïŒïŒãšãããªããããŒã«åç°å±€ïŒïŒãšè¡šé¢åç°å±€ïŒïŒãš
ã¯äºãã«åé¢ããŠïŒç¬ç«ããŠïŒåœ¢æãããŠãããæŸç±ã©
ã³ãïŒïŒãšããã±ãŒãžïŒïŒãšã®æ¥ç¶ïŒåç°ä»ïŒã¯ãäŸã
ã°ãæŸç±ã©ã³ãïŒïŒäžã«äžè¬çãªåç°ããŒã¹ããå¡åžã
ãŠããã®äžããããã±ãŒãžïŒïŒãèŒçœ®ããåŸãå¡åžãã
ãåç°ããŒã¹ããæå®ã®æž©åºŠãããã¡ã€ã«ã§ãªãããŒã
ããããšã«ããè¡ãããšãã§ãããIn the heat dissipation land 20 formed in this way,
As shown in FIG. 6, the package 30 is sandwiched by the solder layer 40.
Is connected to the bottom surface (heat sink 34). This solder layer 4
0 is composed of a hole solder layer 42 formed on each hole conductor 22 and a surface solder layer 44 formed on the surface conductor 24. The hole solder layer 42 and the surface solder layer 44 are formed separately (independently) from each other. The heat dissipation land 20 and the package 30 are connected (soldered) by, for example, applying a general solder paste on the heat dissipation land 20, placing the package 30 on the solder paste, and then applying the applied solder paste in a predetermined manner. It can be performed by reflowing with the temperature profile of.
ãïŒïŒïŒïŒãããã§ãå³ïŒããã³å³ïŒã«ç€ºãããã«ãæµ
ææž¬å®è£
眮ïŒïŒã«åããããäºã€ã®ã³ã³ã¿ã¯ããããŒã
ïŒïŒããåºæ¿ïŒïŒã®è£é¢åŽããä»»æã®äºã€ã®ããŒã«å°é»
äœïŒïŒã«ããããæ¥è§Šãããããããã®ããŒã«å°é»äœïŒ
ïŒã®éã®æµæå€ã枬å®ããããšã«ãããæŸç±ã©ã³ãïŒïŒ
ãšããã±ãŒãžïŒïŒãšã®æ¥ç¶ç¶æ
ã調ã¹ãããšãã§ãããHere, as shown in FIGS. 6 and 7, the two contact probes 92 provided in the resistance measuring device 90 are brought into contact with the arbitrary two hole conductors 22 from the back surface side of the substrate 10. These hole conductors 2
By measuring the resistance value between the two, the heat dissipation land 20
It is possible to check the connection state between the package 30 and the package 30.
ãïŒïŒïŒïŒãäŸãã°ãå³ïŒã«ç€ºãããã«ãäºã€ã®ããŒã«
å°é»äœïŒïŒãããããããã±ãŒãžïŒïŒã®åºé¢ïŒæŸç±æ¿ïŒ
ïŒïŒã«é©åã«æ¥ç¶ãããŠããå Žåã«ã¯ããããã®ããŒã«
å°é»äœïŒïŒã®éã«ãããŒã«åç°å±€ïŒïŒãæŸç±æ¿ïŒïŒãã
ã³ããŒã«åç°å±€ïŒïŒãçµç±ããå°é»çµè·¯ïŒ©ã圢æãã
ãããã®ãšã枬å®ãããæµæå€ã¯ãå
žåçã«ã¯ã»ãŒïŒÎ©
ã§ãããäžæ¹ãå³ïŒã«ç€ºãããã«ãäžæ¹ã®ããŒã«å°é»äœ
ïŒïŒïŒå³ïŒã§å³åŽã«äœçœ®ããããŒã«å°é»äœïŒïŒïŒãåç°
å±€ïŒïŒã®ãã€ãå
ã«äœçœ®ããŠããå Žåã«ã¯ããã®ããŒ
ã«å°é»äœïŒïŒã¯æŸç±æ¿ïŒïŒã«æ¥ç¶ãããªãããã®çµæã
äºã€ã®ããŒã«å°é»äœïŒïŒã®éã«å°é»çµè·¯ã圢æãããª
ãããã®ãšãã¯ãäºã€ã®ããŒã«å°é»äœïŒïŒã®éã®æµæå€
ãæž¬å®ããããšãã§ããªããããããã¯å³ïŒã«ç€ºãå Žå
ã«æ¯ã¹ãŠæããã«å€§ããæµæå€ã枬å®ãããããããã£
ãŠãããããã®ããŒã«å°é»äœïŒïŒãããã±ãŒãžïŒïŒïŒæŸ
ç±æ¿ïŒïŒïŒãšé©åã«æ¥ç¶ãããŠããªããšããããšã容æ
ã«æ€åºããããšãã§ãããFor example, as shown in FIG. 6, the two hole conductors 22 are both bottom surfaces of the package 30 (heat sink 3).
When properly connected to 4), a conductive path I passing through the hole solder layer 42, the heat sink 34, and the hole solder layer 42 is formed between these hole conductors 22. The resistance value measured at this time is typically about 0Ω.
Is. On the other hand, as shown in FIG. 8, when one hole conductor 22 (the hole conductor 22 located on the right side in FIG. 8) is located in the void K of the solder layer 40, this hole conductor 22 Is not connected to the heat sink 34. as a result,
No conductive path is formed between the two hole conductors 22. At this time, the resistance value between the two hole conductors 22 cannot be measured, or a resistance value obviously larger than that shown in FIG. 6 is measured. Therefore, it can be easily detected that any of the hole conductors 22 is not properly connected to the package 30 (heat sink 34).
ãïŒïŒïŒïŒããã®ããã«ããŠãåç°å±€ïŒïŒã®å質ïŒãã€
ãçã®æ¬ é¥ã®çšåºŠïŒãè©äŸ¡ããããšãã§ãããããã§ã
ããŒã«å°é»äœïŒïŒéã®æµæå€ã枬å®ããæäœã¯ãå
šãŠã®
ããŒã«å°é»äœïŒïŒã«å¯ŸããŠè¡ã£ãŠãããããããã®ããŒ
ã«å°é»äœïŒïŒããéžæããäžéšã®ããŒã«å°é»äœïŒïŒã«å¯Ÿ
ããŠè¡ã£ãŠãããããã®æµæå€æž¬å®æäœã¯ãã³ã³ã¿ã¯ã
ãããŒãïŒïŒã®äžæ¹ãŸãã¯äž¡æ¹ãé æ¬¡ç°ãªãããŒã«å°é»
äœïŒïŒã«ç§»åããã€ã€è€æ°åç¹°ãè¿ããŠè¡ãããšãã§ã
ãããŸãã倿°ã®ã³ã³ã¿ã¯ããããŒãïŒïŒãåããæµæ
枬å®è£
眮ïŒïŒãçšããŠã倿°ã®ïŒäŸãã°å
šãŠã®ïŒããŒã«
å°é»äœïŒïŒã«ã€ããŠåæã«æµæå€ã枬å®ããŠããããã
ã®è©äŸ¡çµæã«åºã¥ããŠãæ¬ é¥ã®çšåºŠãæå®ã®åºæºãæºã
ãå Žåã«ã¯ãã®å補åã¯ãã®ãŸãŸåŸå·¥çšã«éããäžæ¹ã
æå®ã®åºæºãæºãããªãå補åã¯è£œé ã©ã€ã³ããé€ãã
廿£ãããããããã¯ããã±ãŒãžïŒïŒãäžæŠåãå€ãã
åŸã«å床åç°ä»ããããã®ããã«ããŠãæŸç±æ§èœã«åªã
ãïŒåç°å±€ïŒïŒã®å質ã確èªãããïŒåå°äœè£
眮ãå®å®
ããŠè£œé ããããšãã§ãããIn this way, the quality of the solder layer 40 (degree of defects such as voids) can be evaluated. here,
The operation of measuring the resistance value between the hole conductors 22 may be performed on all the hole conductors 22 or may be performed on some of the hole conductors 22 selected from the hole conductors 22. Good. This resistance value measurement operation can be repeated a plurality of times while sequentially moving one or both of the contact probes 92 to different hole conductors 22. In addition, the resistance value may be simultaneously measured for a large number (for example, all) of the hole conductors 22 by using the resistance measuring device 90 including a large number of contact probes 92. Based on this evaluation result, if the degree of defects satisfies a predetermined standard, the semi-finished product is sent to the subsequent process as it is. on the other hand,
Semi-finished products that do not meet the prescribed criteria are excluded from the production line,
Discard or re-solder after removing the package 30 once. In this way, a semiconductor device having excellent heat dissipation performance (the quality of the solder layer 40 has been confirmed) can be stably manufactured.
ãïŒïŒïŒïŒãæ¬å®æœäŸã®åå°äœè£
眮ã§ã¯ãå³ïŒã«ç€ºãã
ãã«ãåºæ¿ïŒïŒã®ãã¡ããã±ãŒãžïŒïŒãé
眮ãããç¯å²
ã®ã»ãŒå
šäœã«äºã£ãŠãããŒã«å°é»äœïŒïŒïŒããã³è²«é
åïŒïŒïŒãæŠãåçã«ïŒå¹³åçã«ïŒé
眮ãããŠãããã
ããæ§æã«ãããšãæŸç±ã©ã³ãïŒïŒãšããã±ãŒãžïŒïŒãš
ã®æ¥ç¶ç¯å²ã®å
šäœã«äºã£ãŠãããããæ¥ç¶ããåç°å±€ïŒ
ïŒã®åè³ªïŒæ¬ é¥ã®çšåºŠïŒãå¹çããã¢ãã¿ããããšãã§
ãããIn the semiconductor device of this embodiment, as shown in FIG. 4, the hole conductors 22 (and the through holes 12) are substantially even over the entire area P of the substrate 10 in which the package 30 is arranged. Are located (on average). According to this configuration, the solder layer 4 connecting the heat dissipation land 20 and the package 30 is connected over the entire connection range.
The quality of 0 (degree of defect) can be efficiently monitored.
ãïŒïŒïŒïŒãå³ïŒã«ç€ºãããã«ãæŸç±ã©ã³ãïŒïŒã¯ãã
ã®å
šäœãããã±ãŒãžïŒïŒã®é
眮ãããç¯å²ïŒ°å
ã«åãŸã
ããã«ïŒããªãã¡ãããã±ãŒãžïŒïŒã®äžæ¹ããã¯ã¿ã ã
ãªãããã«ïŒèšããããŠããããããã£ãŠãåºæ¿ïŒïŒã®
å®è£
å¹çãäœäžãããããšãªãæŸç±ã©ã³ãïŒïŒãèšãã
ããšãã§ããããªããæŸç±ã©ã³ãïŒïŒãæ§æããããã
ãã®å°é»äœãããã±ãŒãžïŒïŒã®é
眮ãããç¯å²å€ãŸã§å»¶
é·ãããŠããŠããããäŸãã°ãå³ïŒã«ç€ºãããã«ã衚é¢
å°é»äœïŒïŒã®äžéšïŒïŒïœãããã±ãŒãžïŒïŒã®å€æ¹ãŸã§åŒ
ãåºãããæ§æãšããããšãã§ããããã®ãããªæ§æã«
ãããšãäŸãã°ãåŒãåºãããéšåã®è¡šé¢å°é»äœïŒïŒã«
äžæ¹ã®ã³ã³ã¿ã¯ããããŒãïŒïŒãåœãŠã仿¹ã®ã³ã³ã¿ã¯
ããããŒãïŒïŒãåºæ¿ïŒïŒã®è£é¢åŽããããŒã«å°é»äœïŒ
ïŒã«åœãŠãããšã«ããã衚é¢å°é»äœïŒïŒãšããŒã«å°é»äœ
ïŒïŒãšã®éã®å°éæ§ïŒå
žåçã«ã¯æµæå€ïŒã枬å®ããã
ãšãã§ãããAs shown in FIG. 4, the heat-dissipating land 20 is provided so that the whole of the heat-dissipating land 20 is within the range P in which the package 30 is arranged (that is, the heat-dissipating land 20 does not protrude from below the package 30). There is. Therefore, the heat dissipation land 20 can be provided without lowering the mounting efficiency of the substrate 10. It should be noted that any of the conductors forming the heat dissipation land 20 may be extended beyond the range in which the package 30 is arranged. For example, as shown in FIG. 9, a part 24 a of the surface conductor 24 may be extended to the outside of the package 30. According to such a configuration, for example, one contact probe 92 is applied to the surface conductor 24 of the pulled-out portion, and the other contact probe 92 is applied from the back surface side of the substrate 10 to the hole conductor 2.
By contacting with 2, it is possible to measure the conductivity (typically the resistance value) between the surface conductor 24 and the hole conductor 22.
ãïŒïŒïŒïŒãå³ïŒã«ç€ºãããã«ãæŸç±ã©ã³ãïŒïŒãæ§æ
ããå°é»äœã®ãã¡ããŒã«å°é»äœïŒïŒã¯ããã®å°ãªããšã
äžéšã貫éåïŒïŒããåºæ¿ïŒïŒã®è£é¢ã«åããŠå»¶ã³ãŠã
ãããã®ããšã«ãã£ãŠãããã±ãŒãžïŒïŒããçããç±ã
åºæ¿ïŒïŒã®è£é¢åŽããå¹çããéãããšãã§ããããŸ
ããããŒã«å°é»äœïŒïŒã®äžéšïŒç¬¬äžå¹³é¢éšïŒïŒïœïŒã¯ã
貫éåïŒïŒã®å
éšãããã®åšå²ã®åºæ¿ïŒïŒã®è¡šé¢ã«æ¡ã
ã£ãŠããããããæ§æã«ãããšãããŒã«å°é»äœïŒïŒäžã«
åç°å±€ïŒïŒã容æã«åœ¢æããããšãã§ãããAs shown in FIG. 6, at least a part of the hole conductor 22 of the conductors forming the heat dissipation land 20 extends from the through hole 12 toward the back surface of the substrate 10. This allows heat generated from the package 30 to be efficiently dissipated from the back surface side of the substrate 10. In addition, part of the hole conductor 22 (first flat surface portion 22b) is
It extends from the inside of the through hole 12 to the surface of the substrate 10 around it. With this configuration, the solder layer 40 can be easily formed on the hole conductor 22.
ãïŒïŒïŒïŒããã®ããŒã«å°é»äœïŒïŒã¯ã貫éåïŒïŒãé
ããŠåºæ¿ïŒïŒã®è¡šé¢åŽããè£é¢åŽãŸã§è²«éããŠèšããã
ãŠãããããã«ãããåºæ¿ïŒïŒã®è£é¢åŽããåç°å±€ïŒïŒ
ã®å質ã容æã«ã¢ãã¿ããããšãã§ãããäŸãã°ãåºæ¿
ïŒïŒã®è£é¢åŽããããŒã«å°é»äœïŒïŒã«ã³ã³ã¿ã¯ããããŒ
ãïŒïŒãåœãŠãŠããããã®ããŒã«å°é»äœïŒïŒã®éã®æµæ
å€ã枬å®ããããšãã§ããããã®ããã«åºæ¿ïŒïŒã®è£é¢
åŽããæž¬å®ããæ¹æ³ã«ãããšã衚é¢åŽã«ããããã±ãŒãž
ïŒïŒãã®ä»ã®å®è£
éšåçã«åŠšããããããšãªããããŒã«
å°é»äœïŒïŒã«ã³ã³ã¿ã¯ããããŒãïŒïŒã容æã«æ¥è§Šãã
ãããšãã§ããããŸãããã®ã³ã³ã¿ã¯ããããŒãïŒïŒã
ç§»åãããéçã«ãåºæ¿ïŒïŒã®è¡šé¢åŽã«èšããããå®è£
éšåãåè·¯é
ç·çãå·ã€ããå¿é
ããªããããã«ããã®
ããã«ããŒã«å°é»äœïŒïŒãåºæ¿ïŒïŒã®è£é¢åŽãŸã§å»¶ã³ãŠ
ããããšã«ãã£ãŠãããã±ãŒãžïŒïŒããçããç±ãåºæ¿
ã®è£é¢åŽããéã广ãããé«ãããããThe hole conductor 22 is provided through the through hole 12 from the front surface side to the back surface side of the substrate 10. As a result, the solder layer 40 is applied from the back surface side of the substrate 10.
The quality of can be easily monitored. For example, the contact probe 92 may be applied to the hole conductors 22 from the back surface side of the substrate 10 to measure the resistance value between the hole conductors 22. According to the method of measuring from the back surface side of the substrate 10 as described above, the contact probe 92 can be easily brought into contact with the hole conductor 22 without being hindered by the package 30 and other mounting components on the front surface side. Further, when the contact probe 92 is moved, there is no fear of damaging the mounted components, circuit wiring, etc. provided on the front surface side of the substrate 10. Further, since the hole conductor 22 extends to the back surface side of the substrate 10 in this manner, the effect of releasing the heat generated from the package 30 from the back surface side of the substrate is further enhanced.
ãïŒïŒïŒïŒããªããæ¬å®æœäŸã®ããŒã«å°é»äœïŒïŒã§ã¯ç
éšïŒïŒïœãäžç©ºã«åœ¢æãããŠãããïŒå³ïŒåç
§ïŒã貫é
åïŒïŒå
ã®ç©ºéãããŒã«å°é»äœïŒïŒã§æºããããŠïŒããŒ
ã«å°é»äœïŒïŒã«ãã£ãŠè²«éåïŒïŒãéå¡ãããŠïŒããŠã
ããããã®å Žåã«ã¯åºæ¿ïŒïŒã®è£é¢åŽãžã®æŸç±æ§ããã
ã«åäžããããã£ããåç°å±€ïŒïŒã®æ€æ»ãçµããåŸã¯ã
æŸç±ã©ã³ãïŒïŒãæ§æããåå°é»äœã®éã«åç°å±€ïŒïŒã
çµç±ããªãå°é»çµè·¯ã圢æãããŠããããäŸãã°ããã®
åºæ¿ïŒïŒã®è£é¢ãããŒãã·ã³ã¯ïŒå³ç€ºããïŒã«æ¥ç¶ãã
ããšã«ãããããã±ãŒãžïŒïŒããçããç±ãåºæ¿ã®è£é¢
åŽããããæŸç±ãããããšãã§ããããã®ãšããããŒã«
å°é»äœïŒïŒãåºæ¿ïŒïŒã貫éããŠèšããããæ§æã«ãã
ãšããŒãã·ã³ã¯ãžã®äŒç±å¹çãç¹ã«è¯å¥œã§ãããIn the hole conductor 22 of this embodiment, the cylindrical portion 22a is formed hollow (see FIG. 6), but the space inside the through hole 12 is filled with the hole conductor 22 (hole conductor). The through hole 12 may be closed by 22). In this case, heat dissipation to the back surface side of the substrate 10 is further improved. After finishing the inspection of the solder layer 40,
A conductive path that does not pass through the solder layer 40 may be formed between the conductors forming the heat dissipation land 40. For example, by connecting the back surface of the substrate 10 to a heat sink (not shown), the heat generated from the package 30 can be radiated well from the back surface side of the substrate. At this time, according to the configuration in which the hole conductor 22 is provided so as to penetrate the substrate 10, the heat transfer efficiency to the heat sink is particularly good.
ãïŒïŒïŒïŒãæŸç±ã©ã³ãïŒïŒãæ§æããåå°é»äœäžã«åœ¢
æãããããŒã«åç°å±€ïŒïŒããã³è¡šé¢åç°å±€ïŒïŒã¯ãã
ã®äžéšãŸãã¯å
šéšãäºãã«ã€ãªãã£ãŠããŠãããããã
ãããç¬ç«ããŠããïŒããªãã¡çŽæ¥æ¥è§ŠããŠããªãïŒã
ãšã奜ãŸããããã®å Žåãåç°å±€ïŒïŒïŒïŒïŒã¯ãããã±
ãŒãžïŒïŒã®åºé¢ã«èšããããæŸç±æ¿ïŒïŒãä»ããŠåããŠ
黿°çã«æ¥ç¶ãããããããæ§æã«ãããšãåå°é»äœïŒ
ïŒïŒïŒïŒéã®å°éæ§ãè¯å¥œã§ããããšã確èªãããã°ã
åå°é»äœïŒïŒïŒïŒïŒãšãã®å°é»äœäžã«åœ¢æãããåç°å±€
ïŒïŒïŒïŒïŒãšã®æ¥ç¶ã®ã¿ãªããããããã®åç°å±€ïŒïŒïŒ
ïŒïŒãšããã±ãŒãžïŒïŒïŒæŸç±æ¿ïŒïŒïŒãšã®æ¥ç¶ãé©åã«
ãªãããŠããããšãå€ãããããã£ãŠãåç°å±€ïŒïŒã®æ¬
é¥ïŒãã€ãçïŒããã粟床ããæ€åºããããšãã§ãããThe hole solder layer 42 and the surface solder layer 44 formed on each conductor constituting the heat dissipation land 20 may be partially or wholly connected to each other, but they are independent (that is, directly). (Not in contact) is preferable. In this case, the solder layers 42 and 44 are electrically connected only via the heat dissipation plate 34 provided on the bottom surface of the package 30. According to this structure, each conductor 2
If it is confirmed that the conductivity between 2 and 24 is good,
Not only the connection between the conductors 22 and 24 and the solder layers 42 and 44 formed on the conductors, but also the solder layers 42 and 44
It can be seen that the connection between 44 and the package 30 (heat sink 34) is also properly made. Therefore, the defect (void or the like) of the solder layer 40 can be detected more accurately.
ãïŒïŒïŒïŒãç¹ã«éå®ãããã®ã§ã¯ãªãããããŒã«å°é»
äœïŒïŒïŒå³ïŒãå³ïŒåç
§ïŒã®åéšãæ§æããå°é»äœïŒã
ãã§ã¯é
èïŒã®å¹³ååãã¯ãäŸãã°çŽïŒïŒãïŒïŒïŒÎŒm
ã®ç¯å²ãšããããšãã§ããçŽïŒïŒãïŒïŒÎŒmã®ç¯å²ãšã
ãããšã奜ãŸããã衚é¢å°é»äœïŒïŒã®åããããŒã«å°é»
äœãšåçšåºŠãšããããšã奜ãŸããããŸãã第äžå¹³é¢éšïŒ
ïŒïœã®çŽåŸã¯ã貫éåïŒïŒã®å
åŸã«ãããããäŸãã°çŽ
ïŒïŒïŒãïŒïŒïŒmmçšåºŠãšããããšãã§ããçŽïŒïŒïŒã
ïŒïŒïŒmmã®ç¯å²ãšããããšã奜ãŸããããã®ç¬¬äžå¹³é¢éš
ïŒïŒïœã®å¹
ïŒå€åšçžãšå
åšçžãšã®è·é¢ïŒã¯ãäŸãã°çŽ
ïŒïŒïŒãïŒïŒïŒmmãšããããšãã§ããçŽïŒïŒïŒãïŒïŒïŒ
mmã®ç¯å²ãšããããšã奜ãŸããããããŠã第äžå¹³é¢éšïŒ
ïŒïœã®å€åšãšè¡šé¢å°é»äœïŒïŒãšã®éã®ééã®å¹
ã¯ãäŸ
ãã°çŽïŒïŒïŒãïŒïŒïŒÎŒmã®ç¯å²ãšããããšãã§ããçŽ
ïŒïŒïŒãïŒïŒïŒÎŒmã®ç¯å²ãšããããšã奜ãŸãããAlthough not particularly limited, the average thickness of the conductor (here, copper film) forming each part of the hole conductor 22 (see FIGS. 4 to 6) is, for example, about 10 to 120 ÎŒm.
The range is about 16 to 32 ÎŒm, and the range is preferably about 16 to 32 ÎŒm. It is preferable that the thickness of the surface conductor 24 is similar to that of the hole conductor. In addition, the first flat surface portion 2
The diameter of 2b depends on the inner diameter of the through hole 12, but may be, for example, about 0.4 to 1.2 mm, and about 0.6 to
A range of 1.0 mm is preferable. The width (distance between the outer peripheral edge and the inner peripheral edge) of the first flat surface portion 22b can be set to, for example, about 0.2 to 0.6 mm and is set to about 0.2 to 0.4.
The range of mm is preferable. And the first plane portion 2
The width of the gap G between the outer periphery of 2b and the surface conductor 24 can be, for example, in the range of about 100 to 500 ÎŒm, and preferably in the range of about 200 to 300 ÎŒm.
ãïŒïŒïŒïŒãããŒã«å°é»äœïŒïŒã®æ°ïŒé
眮å¯åºŠïŒãå¢ã
ãããšã«ãã£ãŠãåç°å±€ïŒïŒã®æ¬ é¥ããã粟床ããæ€åº
ãåŸããäžæ¹ãããŒã«å°é»äœïŒïŒã®æ°ãéå°ã«å€ããã
ãšééã®åèšé¢ç©ã倧ãããªããããªãã¡ãæŸç±ã©ã³
ãïŒïŒã®å®å¹é¢ç©ïŒããŒã«å°é»äœïŒïŒã®ãã¡åºæ¿è¡šé¢ã«
圢æãããéšåïŒç¬¬äžå¹³é¢éšïŒïŒïœïŒãšè¡šé¢å°é»äœïŒïŒ
ãšã®åèšé¢ç©ïŒãå°ãããªãããã®ããæŸç±æ§èœãäœäž
ãããããªããããã±ãŒãžïŒïŒã®çš®é¡ã«ãããããããŒ
ã«å°é»äœïŒïŒã®å¥œãŸããé
眮å¯åºŠã¯çŽïŒïŒïŒãïŒïŒïŒå
ïŒcm2ã®ç¯å²ã§ãããçŽïŒïŒïŒãïŒïŒïŒåïŒcm2ã®ç¯å²ã
ãã奜ãŸããããŸããæŸç±ã©ã³ãïŒïŒãèšããããç¯å²
ã®å
šäœé¢ç©ã«å¯ŸããŠããã®å®å¹é¢ç©ïŒå
šäœé¢ç©ããéé
ã®é¢ç©ãé€ãããã®ïŒãæŠãïŒïŒãïŒïŒïŒïŒïŒ
ã®ç¯å²
ã«ããããšã奜ãŸãããïŒïŒãïŒïŒïŒ
ã®ç¯å²ããã奜ãŸ
ãããããã«ãããã±ãŒãžïŒïŒãé
眮ãããç¯å²ïŒ°ã®é¢
ç©ã«å¯ŸããŠããã®ç¯å²ïŒ°å
ã«èšããããæŸç±ã©ã³ãïŒïŒ
ã®å
šäœé¢ç©ãæŠãïŒïŒãïŒïŒïŒïŒ
ã®ç¯å²ã«ããããšã奜
ãŸãããïŒïŒãïŒïŒïŒïŒ
ã®ç¯å²ããã奜ãŸãããBy increasing the number of hole conductors 22 (arrangement density), defects in the solder layer 40 can be detected more accurately. On the other hand, if the number of hole conductors 22 is excessively increased, the total area of the gap G becomes large. That is, the effective area of the heat dissipation land 20 (the portion of the hole conductor 22 formed on the surface of the substrate (first flat surface portion 22b) and the surface conductor 24).
And the total area) becomes smaller. For this reason, the heat dissipation performance is likely to deteriorate. Although depending on the type of the package 30, the preferable arrangement density of the hole conductors 22 is in the range of about 0.1 to 0.5 pieces / cm 2 , and the range of about 0.2 to 0.3 pieces / cm 2 . More preferable. Further, it is preferable that the effective area (the area excluding the area of the gap G from the entire area) is in the range of approximately 70 to 99.5% with respect to the entire area in which the heat dissipation land 20 is provided. The range of up to 99% is more preferable. Further, with respect to the area of the range P in which the package 30 is arranged, the heat dissipation land 20 provided within this range P
The total area is preferably in the range of 60 to 100%, more preferably in the range of 70 to 100%.
ãïŒïŒïŒïŒãïŒç¬¬äºå®æœäŸïŒæ¬å®æœäŸã¯ã第äžå®æœäŸã«
ä¿ãåå°äœè£
眮ãšã¯æŸç±ã©ã³ãã®åœ¢ç¶ãç°ãªãäŸã§ã
ããå³ïŒïŒã«ç€ºãããã«ãåºæ¿ïŒïŒã®ãã¡ããã±ãŒãžïŒ
ïŒãé
眮ãããç¯å²ïŒ°ã®å
åŽã«ã¯ãè€æ°ã®è²«éåïŒïŒ
ãã瞊暪ã«ã»ãŒçééã§ïŒæ Œåç¶ã«ïŒæŽåé
眮ãããŠã
ãããã®ç¯å²ïŒ°ã®å
åŽã«è€æ°ã®ããŒã«å°é»äœïŒïŒãèšã
ãããŠãããåããŒã«å°é»äœïŒïŒã¯ã貫éåïŒïŒããåº
æ¿ïŒïŒã®è£é¢ã«åããŠå»¶ã³ãéšåãæãããã®è²«éåïŒ
ïŒã®å
éšãããã®åšå²ã®åºæ¿è¡šé¢ãŸã§é·æ¹åœ¢ç¶ã«æ¡ãã£
ãŠããããããã®ããŒã«å°é»äœïŒïŒã¯ãæ Œåç¶ã®éé
ãè§£ããŠåºæ¿è¡šé¢ã§äºãã«é¢æ¹åã«åé¢ãããŠãããã
ããã®ããŒã«å°é»äœïŒïŒã«ãã£ãŠæŸç±ã©ã³ãïŒïŒãæ§æ
ãããŠããããã®ä»ã®éšåã®æ§æã¯ç¬¬äžå®æœäŸãšåæ§ã§
ãããããã圢ç¶ã®æŸç±ã©ã³ãïŒïŒãåããåå°äœè£
眮
ã«ãããŠãã第äžå®æœäŸãšåæ§ã«ãåç°å±€ã®å質ã容æ
ã«ã¢ãã¿ããããšãã§ããã(Second Embodiment) This embodiment is an example in which the shape of the heat dissipation land is different from that of the semiconductor device according to the first embodiment. As shown in FIG. 10, the package 3 of the substrate 10
Inside the range P in which 0 is arranged, a plurality of through holes 12
, Are aligned vertically and horizontally at substantially equal intervals (in a grid pattern). Inside this range P, a plurality of hole conductors 22 are provided. Each hole conductor 22 has a portion extending from the through hole 12 toward the back surface of the substrate 10.
It extends in a rectangular shape from the inside of 2 to the substrate surface around it. These hole conductors 12 have a grid-like gap G.
The substrate surface is separated from each other in the plane direction. The hole conductor 22 constitutes the heat dissipation land 20. The configuration of the other parts is similar to that of the first embodiment. Also in the semiconductor device including the heat dissipation land 20 having such a shape, the quality of the solder layer can be easily monitored as in the first embodiment.
ãïŒïŒïŒïŒã以äžãæ¬çºæã®å
·äœäŸã詳现ã«èª¬æãã
ãããããã¯äŸç€ºã«ããããç¹èš±è«æ±ã®ç¯å²ãéå®ãã
ãã®ã§ã¯ãªããç¹èš±è«æ±ã®ç¯å²ã«èšèŒã®æè¡ã«ã¯ã以äž
ã«äŸç€ºããå
·äœäŸãæ§ã
ã«å€åœ¢ã倿Žãããã®ãå«ãŸã
ãããŸããæ¬æçްæžãŸãã¯å³é¢ã«èª¬æããæè¡èŠçŽ ã¯ã
åç¬ã§ãããã¯åçš®ã®çµã¿åããã«ãã£ãŠæè¡çæçšæ§
ãçºæ®ãããã®ã§ãããåºé¡æè«æ±é
èšèŒã®çµã¿åãã
ã«éå®ããããã®ã§ã¯ãªãããŸããæ¬æçްæžãŸãã¯å³é¢
ã«äŸç€ºããæè¡ã¯è€æ°ç®çãåæã«éæãããã®ã§ã
ãããã®ãã¡ã®äžã€ã®ç®çãéæããããšèªäœã§æè¡ç
æçšæ§ãæã€ãã®ã§ãããSpecific examples of the present invention have been described above in detail, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. Further, the technical elements described in the present specification or the drawings are
The technical usefulness is exhibited alone or in various combinations, and is not limited to the combinations described in the claims at the time of filing. In addition, the technique illustrated in the present specification or the drawings achieves a plurality of purposes at the same time, and achieving the one purpose among them has technical utility.
ãå³ïŒã 第äžå®æœäŸã«ä¿ãåå°äœè£
眮ã瀺ãæé¢å³ã§
ãããFIG. 1 is a cross-sectional view showing a semiconductor device according to a first embodiment.
ãå³ïŒã ããã±ãŒãžãå³ïŒã®IIæ¹åããèŠãå¹³é¢å³ã§
ãããFIG. 2 is a plan view of the package as seen from the direction II in FIG.
ãå³ïŒã ããã±ãŒãžãå³ïŒã®IIIæ¹åããèŠãå¹³é¢å³
ã§ãããFIG. 3 is a plan view of the package viewed from the direction III in FIG.
ãå³ïŒã æŸç±ã©ã³ãã®åœ¢ç¶ã瀺ãå¹³é¢å³ã§ãããFIG. 4 is a plan view showing the shape of a heat dissipation land.
ãå³ïŒã å³ïŒã®ïŒ¶éšåã®æ¡å€§å³ã§ãããFIG. 5 is an enlarged view of a V portion of FIG.
ãå³ïŒã æŸç±ã©ã³ããšããã±ãŒãžãšã®æ¥ç¶æ§é ã瀺ã
æé¢å³ã§ãããFIG. 6 is a cross-sectional view showing a connection structure between a heat dissipation land and a package.
ãå³ïŒã ããŒã«å°é»äœéã®æµæå€ã枬å®ããæ§åã瀺
ãæš¡åŒå³ã§ãããFIG. 7 is a schematic diagram showing how the resistance value between hole conductors is measured.
ãå³ïŒã åç°å±€ã«ãã€ãã圢æãããç¶æ
ã瀺ãæé¢
å³ã§ãããFIG. 8 is a cross-sectional view showing a state where voids are formed in the solder layer.
ãå³ïŒã 第äžå®æœäŸã®å€åœ¢äŸã瀺ãæé¢å³ã§ãããFIG. 9 is a cross-sectional view showing a modified example of the first embodiment.
ãå³ïŒïŒã 第äºå®æœäŸã«ä¿ãåå°äœè£
çœ®ã®æŸç±ã©ã³ã
ã瀺ãå¹³é¢å³ã§ãããFIG. 10 is a plan view showing a heat dissipation land of a semiconductor device according to a second embodiment.
ïŒïŒïŒã¬ã©ã¹âãšããã·åºæ¿ïŒåºæ¿ïŒ ïŒïŒïŒè²«éå ïŒïŒïŒæŸç±ã©ã³ãïŒå°é»äœçŸ€ïŒ ïŒïŒïŒããŒã«å°é»äœïŒå°é»äœïŒ ïŒïŒïŒè¡šé¢å°é»äœïŒå°é»äœïŒ ïŒïŒïŒããã±ãŒãž ïŒïŒïŒæŸç±æ¿ïŒé屿¿ïŒ ïŒïŒïŒåç°å±€ïŒå°é»æå±€ïŒ ïŒïŒïŒã³ã³ã¿ã¯ããããŒã ïŒãã€ã 10: Glass-epoxy substrate (substrate) 12: Through hole 20: Heat dissipation land (conductor group) 22: Hall conductor (conductor) 24: Surface conductor (conductor) 30: Package 34: Heat sink (metal plate) 40: Solder layer (conductive material layer) 92: Contact probe K: Void
Claims (7)
ãæ¥ç¶ãããåå°äœè£ 眮ã§ãã£ãŠã ãã®åºæ¿ã®ãã¡ããã±ãŒãžãé 眮ãããç¯å²ã«ã¯é¢æ¹å
ã«åé¢ãããè€æ°ã®å°é»äœããæ§æãããå°é»äœçŸ€ãèš
ããããŠãããšãšãã«ããã®å°é»äœçŸ€ã«ããã±ãŒãžã®åº
é¢ãå°é»æå±€ãæãã§æ¥ç¶ãããŠããã ãã®å°é»äœçŸ€ãæ§æããå°é»äœã®ãã¡å°ãªããšãäžã€ã¯
貫éåããè£é¢ã«åããŠå»¶ã³ãããŒã«å°é»äœã§ããããš
ãç¹åŸŽãšããåå°äœè£ 眮ã1. A semiconductor device in which a bottom surface of a package is connected to a substrate having a through hole, and a range in which the package is arranged on the substrate is composed of a plurality of conductors separated in a plane direction. A conductor group is provided, and the bottom surface of the package is connected to the conductor group with a conductive material layer sandwiched therebetween, and at least one of the conductors forming the conductor group is connected from the through hole to the back surface. A semiconductor device, which is a hole conductor extending toward a hole.
ãããŠããè«æ±é ïŒã«èšèŒã®åå°äœè£ 眮ã2. The semiconductor device according to claim 1, wherein a metal plate is provided on a bottom surface of the package.
æ°ã®åèšããŒã«å°é»äœãšããã®ããŒã«å°é»äœããééã
éãŠãŠé¢çã«æ¡ãã£ãŠãã衚é¢å°é»äœãšãå«ãã§æ§æã
ããŠããè«æ±é ïŒãŸãã¯ïŒã«èšèŒã®åå°äœè£ 眮ã3. The conductor group is configured to include a plurality of the hole conductors arranged in a grid pattern and a surface conductor that is spread in a plane from the hole conductors with a gap. The semiconductor device according to claim 1, wherein
é»äœããæ§æãããå°é»äœçŸ€ãšãåãããã®å°é»äœçŸ€ã
æ§æããå°é»äœã®ãã¡å°ãªããšãäžã€ã¯ãã®è²«éåãã
è£é¢ã«åããŠå»¶ã³ãããŒã«å°é»äœã§ããåºæ¿ãçšæãã
å·¥çšãšã å°é»æå±€ãæãã§ãã®å°é»äœçŸ€ã«ããã±ãŒãžã®åºé¢ãæ¥
ç¶ããå·¥çšãšãåããåå°äœè£ 眮ã®è£œé æ¹æ³ã4. A through hole and a conductor group composed of a plurality of conductors separated in a surface direction, wherein at least one of the conductors forming the conductor group is a back surface from the through hole. 1. A method of manufacturing a semiconductor device, comprising: a step of preparing a substrate that is a hole conductor extending toward a substrate; and a step of connecting a bottom surface of a package to the conductor group with a conductive material layer interposed therebetween.
åŸã«ãåèšããŒã«å°é»äœãšä»ã®å°é»äœãšã®éã®å°éæ§ã
調ã¹ãå·¥çšãããã«åããè«æ±é ïŒã«èšèŒã®åå°äœè£ 眮
ã®è£œé æ¹æ³ã5. The method of manufacturing a semiconductor device according to claim 4, further comprising a step of examining electrical continuity between the hole conductor and another conductor after the step of connecting the bottom surface of the package.
äœãæãããããã®ããŒã«å°é»äœã®éã®æµæå€ã枬å®ã
ãããšã«ããåèšå°éæ§ã調ã¹ãããšãç¹åŸŽãšããè«æ±
é ïŒã«èšèŒã®åå°äœè£ 眮ã®è£œé æ¹æ³ã6. The conductor group has two or more hole conductors, and the conductivity is checked by measuring a resistance value between the hole conductors. A method for manufacturing a semiconductor device as described above.
ãã®ããŒã«å°é»äœã®åšå²ãæ®ããŠé£ç¶çã«èšãããã衚
é¢å°é»äœãšãå«ãã§æ§æãããŠããã ãã®è¡šé¢å°é»äœãšåèšããŒã«å°é»äœãšã®éã®æµæå€ã枬
å®ããããšã«ããåèšå°éæ§ã調ã¹ãããšãç¹åŸŽãšãã
è«æ±é ïŒã«èšèŒã®åå°äœè£ 眮ã®è£œé æ¹æ³ã7. The conductor group includes the hole conductor,
It is configured to include a surface conductor continuously provided with the periphery of the hole conductor remaining, and the conductivity is measured by measuring a resistance value between the surface conductor and the hole conductor. The method for manufacturing a semiconductor device according to claim 5, further comprising:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2002095743A JP2003297965A (en) | 2002-03-29 | 2002-03-29 | Semiconductor device and method of manufacturing the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2002095743A JP2003297965A (en) | 2002-03-29 | 2002-03-29 | Semiconductor device and method of manufacturing the same |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2003297965A true JP2003297965A (en) | 2003-10-17 |
Family
ID=29387294
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2002095743A Pending JP2003297965A (en) | 2002-03-29 | 2002-03-29 | Semiconductor device and method of manufacturing the same |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2003297965A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2973942A1 (en) * | 2011-04-08 | 2012-10-12 | Continental Automotive France | ELECTRONIC COMPONENT WITH THERMAL DISSIPATION PASTILLE AND CARD USING THE SAME |
KR20140132577A (en) * | 2013-05-08 | 2014-11-18 | ìì§ëì€íë ìŽ ì£Œìíì¬ | Testing apparatus and method for flat display device |
JP2016103604A (en) * | 2014-11-28 | 2016-06-02 | ãã¡ããã¯æ ªåŒäŒç€Ÿ | Printed circuit board with thermal pad in notched shape |
JP2017015519A (en) * | 2015-06-30 | 2017-01-19 | ãšã¹ã¢ã€ã¢ã€ã»ã»ãã³ã³ãã¯ã¿æ ªåŒäŒç€Ÿ | Method for inspecting mounting state of semiconductor device, and semiconductor device mounted on mounting board |
CN112670254A (en) * | 2020-12-30 | 2021-04-16 | åè¯åšå富äœç§æ(å京)æéèŽ£ä»»å ¬åž | Packaging structure for improving packaging thermal uniformity of SiC power device |
-
2002
- 2002-03-29 JP JP2002095743A patent/JP2003297965A/en active Pending
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2973942A1 (en) * | 2011-04-08 | 2012-10-12 | Continental Automotive France | ELECTRONIC COMPONENT WITH THERMAL DISSIPATION PASTILLE AND CARD USING THE SAME |
KR20140132577A (en) * | 2013-05-08 | 2014-11-18 | ìì§ëì€íë ìŽ ì£Œìíì¬ | Testing apparatus and method for flat display device |
KR102016076B1 (en) | 2013-05-08 | 2019-10-21 | ìì§ëì€íë ìŽ ì£Œìíì¬ | Testing apparatus and method for flat display device |
JP2016103604A (en) * | 2014-11-28 | 2016-06-02 | ãã¡ããã¯æ ªåŒäŒç€Ÿ | Printed circuit board with thermal pad in notched shape |
JP2017015519A (en) * | 2015-06-30 | 2017-01-19 | ãšã¹ã¢ã€ã¢ã€ã»ã»ãã³ã³ãã¯ã¿æ ªåŒäŒç€Ÿ | Method for inspecting mounting state of semiconductor device, and semiconductor device mounted on mounting board |
CN112670254A (en) * | 2020-12-30 | 2021-04-16 | åè¯åšå富äœç§æ(å京)æéèŽ£ä»»å ¬åž | Packaging structure for improving packaging thermal uniformity of SiC power device |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8350263B2 (en) | Semiconductor package, method of evaluating same, and method of manufacturing same | |
US11715701B2 (en) | Semiconductor device and method of inspecting the same | |
CN104362131B (en) | Semiconductor packages, semiconductor device and portable communication device | |
KR101224329B1 (en) | Semiconductor chip used for evaluation, evaluation system, and repairing method thereof | |
US8669777B2 (en) | Assessing connection joint coverage between a device and a printed circuit board | |
US11099227B2 (en) | Multilayer wiring base plate and probe card using the same | |
CN103675369A (en) | Probe card and method of manufacturing the same | |
US6558168B2 (en) | Probe card | |
TWI645195B (en) | Probe card | |
JP5621664B2 (en) | Semiconductor chip for evaluation, evaluation system, and heat dissipation material evaluation method | |
JP2003297965A (en) | Semiconductor device and method of manufacturing the same | |
CN106206338A (en) | Printed circuit board (PCB) and method of testing thereof and the method manufacturing semiconductor packages | |
CN109786265B (en) | A packaged device, preparation method and signal measurement method | |
CN203773016U (en) | Thermal resistance testing device for SMD-0.5 packaged power semiconductor device | |
TWI224677B (en) | Probe card and method for manufacturing probe card | |
US9793241B2 (en) | Printed wiring board | |
CN113702446B (en) | Micro-resistance testing method for ceramic substrate through hole | |
JP2012141274A (en) | Ceramic substrate for probe card and manufacturing method thereof | |
JP4131137B2 (en) | Interposer substrate continuity inspection method | |
TWI257682B (en) | Substrate having testing router | |
KR20210032479A (en) | Method of manufacturing a conductive member | |
KR20010093811A (en) | IC chip carrier | |
US20220283106A1 (en) | Heat source simulation structure | |
JP2020004858A (en) | Printed wiring board and printed circuit board | |
KR101162506B1 (en) | Printed Circuit Board for Manufacturing Semiconductor Package and Manufacturing Method Thereof |