JP2003273160A - Semiconductor mounting module - Google Patents
Semiconductor mounting moduleInfo
- Publication number
- JP2003273160A JP2003273160A JP2002071876A JP2002071876A JP2003273160A JP 2003273160 A JP2003273160 A JP 2003273160A JP 2002071876 A JP2002071876 A JP 2002071876A JP 2002071876 A JP2002071876 A JP 2002071876A JP 2003273160 A JP2003273160 A JP 2003273160A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- mounting
- bare chip
- recess
- bump
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
- H01L2224/05557—Shape in side view comprising protrusions or indentations
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
- H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
- H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
- H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/1601—Structure
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
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- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8112—Aligning
- H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
- H01L2224/81138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
- H01L2224/81141—Guiding structures both on and outside the body
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- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
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- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
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- H01L2224/818—Bonding techniques
- H01L2224/81897—Mechanical interlocking, e.g. anchoring, hook and loop-type fastening or the like
- H01L2224/81898—Press-fitting, i.e. pushing the parts together and fastening by friction, e.g. by compression of one part against the other
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- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
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Landscapes
- Wire Bonding (AREA)
Abstract
(57)【要約】
【課題】 本発明は半導体ベアチップと実装基板の実装
の位置ずれがなく接続の信頼性に富んだ半導体実装モジ
ュールを提供することを目的とする。
【解決手段】 実装基板１０の接続用電極１２自身に凹
部１１を設け、半導体ベアチップ１４の突起状のバンプ
１６をこの凹部１１にガイドさせて実装する。
(57) Abstract: An object of the present invention is to provide a semiconductor mounting module which is free from positional displacement between a semiconductor bare chip and a mounting substrate and has high connection reliability. SOLUTION: A recess 11 is provided in a connection electrode 12 of a mounting substrate 10 and a bump 16 having a protruding shape of a semiconductor bare chip 14 is guided by the recess 11 and mounted.
Description
【０００１】[0001]
【発明の属する技術分野】本発明は各種電子機器に利用
される半導体実装モジュールに関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor mounting module used in various electronic devices.
【０００２】[0002]
【従来の技術】近年、電子機器は携帯用電子機器に代表
されるように薄型化、小型化の要求が高まってきてお
り、これらの電子機器に用いられる半導体実装モジュー
ルとしても小型化、薄型化に有利な半導体ベアチップを
用いたものが多用されるようになってきている。特に半
導体ベアチップをフェイスダウン実装する構成のものが
増大している。2. Description of the Related Art In recent years, electronic devices have been required to be thin and compact as represented by portable electronic devices, and semiconductor mounting modules used in these electronic devices are also compact and thin. Those using a semiconductor bare chip, which is advantageous to the above, have been widely used. In particular, the number of semiconductor bare chips that are mounted face down is increasing.
【０００３】従来における半導体実装モジュールとして
は、図１２に示すように実装基板１の接続用電極２に半
導体ベアチップ３の端子４に設けた突起状の金や半田か
らなるバンプ５を位置合せして当接させ超音波振動を加
えたり、加熱することによって接続結合して構成してい
た。In a conventional semiconductor mounting module, as shown in FIG. 12, a bump 5 made of gold or solder provided on a terminal 4 of a semiconductor bare chip 3 is aligned with a connecting electrode 2 of a mounting substrate 1. They are configured to be connected and brought into contact with each other by applying ultrasonic vibration or heating.
【０００４】また、図１３（ａ），（ｂ）に示すように
接続用電極２を設けた実装基板１に熱硬化性樹脂層６を
設け、半導体ベアチップ３の突起状のバンプ５を接続用
電極２に位置合せした後、加熱加圧することによりバン
プ５を熱硬化性樹脂層６に貫通させて接続用電極２に当
接させ、しかも熱硬化性樹脂層６の硬化に伴う半導体ベ
アチップ３を実装基板１側に引付ける力によってバンプ
５と接続用電極２とを圧接させて電気的接続をより確実
なものとするとともに実装基板１と半導体ベアチップ３
との結合を行う構成としたものも提案されている。Further, as shown in FIGS. 13 (a) and 13 (b), a thermosetting resin layer 6 is provided on the mounting substrate 1 provided with the connecting electrodes 2, and the projecting bumps 5 of the semiconductor bare chip 3 are connected. After aligning with the electrode 2, the bumps 5 are penetrated through the thermosetting resin layer 6 and brought into contact with the connecting electrodes 2 by heating and pressing, and the semiconductor bare chip 3 associated with the curing of the thermosetting resin layer 6 is formed. The bump 5 and the connection electrode 2 are pressed against each other by a force attracted to the mounting substrate 1 side to make the electrical connection more reliable, and at the same time, the mounting substrate 1 and the semiconductor bare chip 3 are connected.
There is also proposed a configuration in which it is combined with.
【０００５】さらに図１４（ａ），（ｂ）に示すように
半導体ベアチップ３のバンプ５に導電性ペースト７を塗
布し、この導電性ペースト７を実装基板１の接続用電極
２に当接させ、導電性ペースト７を乾燥させて電気的接
続を行った後半導体ベアチップ３と実装基板１間に封止
樹脂８を充填し硬化させることによって両者の結合の強
化を図った半導体実装モジュールも提案されている。Further, as shown in FIGS. 14 (a) and 14 (b), a conductive paste 7 is applied to the bumps 5 of the semiconductor bare chip 3, and the conductive paste 7 is brought into contact with the connection electrodes 2 of the mounting substrate 1. There is also proposed a semiconductor mounting module in which the conductive paste 7 is dried to make electrical connection and then a sealing resin 8 is filled between the semiconductor bare chip 3 and the mounting substrate 1 and cured to strengthen the bonding between the two. ing.
【０００６】また、図１５（ａ），（ｂ）に示すように
バンプ５を半田によって半球面状に形成し、半田ペース
トを表面に塗布した接続用電極２とを当接させ、加熱す
ることによって半田を溶融させ、冷却硬化することによ
って半導体ベアチップ３を実装基板１に接続結合する半
導体実装モジュールも開発されている。Further, as shown in FIGS. 15 (a) and 15 (b), the bumps 5 are formed in a hemispherical shape with solder, and the connection electrodes 2 coated with solder paste are brought into contact with each other and heated. A semiconductor mounting module has also been developed in which the semiconductor bare chip 3 is connected and bonded to the mounting substrate 1 by melting solder and cooling and hardening by soldering.
【０００７】[0007]
【発明が解決しようとする課題】上記のような構成にお
いて、半導体ベアチップ３は近年多機能および高集積化
の傾向にあり、高密度実装を実現する上でこの半導体ベ
アチップ３の接続用電極２の狭ピッチ化が進められてお
り、半導体ベアチップ３と実装基板１との接続の信頼性
向上が一層強く要求されてきている。現在、半導体ベア
チップ３と実装基板１の接続は、１０μｍ程度の実装ず
れも許されなくなってきており、上述の各従来の構成に
おいてはバンプ５を接続用電極２に位置合せして当接さ
せても各々の形状により加圧状態で位置ずれを発生しや
すく、確実な接続が保証しにくいものとなっていた。In the structure as described above, the semiconductor bare chip 3 has been tending to be multifunctional and highly integrated in recent years, and in order to realize high-density mounting, the connection electrode 2 of the semiconductor bare chip 3 has to be formed. As the pitch is becoming narrower, there is a strong demand for improving the reliability of the connection between the semiconductor bare chip 3 and the mounting substrate 1. At present, the connection between the semiconductor bare chip 3 and the mounting substrate 1 is not allowed to have a mounting deviation of about 10 μm. In each of the conventional configurations described above, the bump 5 is aligned with and brought into contact with the connection electrode 2. However, due to their respective shapes, it was easy to cause positional displacement under pressure, and it was difficult to guarantee a reliable connection.
【０００８】また、狭ピッチ化に伴いバンプ５や接続用
電極２もさらに小さくなるため、熱ストレスなどに対す
る接続の信頼性もより厳しいものとなる。特に導電性ペ
ースト７や半田のバンプ５を用いたものは、半導体ベア
チップ３と実装基板１の線膨張係数の差による熱ストレ
スが繰返し加えられた場合接続部が破断してしまうおそ
れを有するものであった。Further, as the pitch becomes narrower, the bumps 5 and the connecting electrodes 2 become smaller, so that the reliability of the connection against heat stress becomes more severe. In particular, the one using the conductive paste 7 or the solder bump 5 has a possibility that the connection portion may be broken when the thermal stress due to the difference in linear expansion coefficient between the semiconductor bare chip 3 and the mounting substrate 1 is repeatedly applied. there were.
【０００９】本発明は以上のような従来の欠点を除去
し、接続の信頼性に富んだ半導体実装モジュールを提供
することを目的とする。An object of the present invention is to eliminate the above-mentioned conventional drawbacks and to provide a semiconductor mounting module having high reliability in connection.
【００１０】[0010]
【課題を解決するための手段】上記課題を解決するため
に本発明の半導体実装モジュールは、実装基板の接続用
電極自身または接続用電極の上部に半導体ベアチップの
突起状のバンプをガイドする凹部を設けた構成とするも
のである。この構成とすることにより、バンプと接続用
電極とが自動的に位置合せされて接続の信頼性の優れた
ものとすることができる。In order to solve the above problems, a semiconductor mounting module of the present invention has a recess for guiding a protruding bump of a semiconductor bare chip on a connection electrode itself of a mounting substrate or on an upper part of the connection electrode. The configuration is provided. With this configuration, the bumps and the connecting electrodes are automatically aligned with each other, and the connection reliability can be improved.
【００１１】[0011]
【発明の実施の形態】本発明の請求項１に記載の発明
は、実装面側の端子に突起状のバンプを設けた半導体ベ
アチップと、この半導体ベアチップのバンプと接続され
る接続用電極を設けた実装基板とからなり、この実装基
板の接続用電極自身または接続用電極の上部に半導体ベ
アチップの突起状のバンプをガイドする凹部を設けた構
成であり、これによりバンプが凹部にガイドされて実装
時に自動的に位置決めが行われ、接続の信頼性の優れた
ものとすることができる。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention is provided with a semiconductor bare chip having a bump on a mounting surface side terminal and a connecting electrode connected to the bump of the semiconductor bare chip. The mounting electrode itself is provided with a recessed portion for guiding the bumps of the semiconductor bare chip on the connection electrode itself or above the connection electrode. Sometimes the positioning is done automatically, which makes the connection highly reliable.
【００１２】請求項２に記載の発明は、凹部を逆円錐台
形状とした構成であり、突起状のバンプが凹部のテーパ
面を滑って、接続用電極の中心部に位置合せされ、接続
の信頼性の高いものとすることができる。According to a second aspect of the present invention, the concave portion has a shape of an inverted truncated cone, and the bump having a projection slides on the tapered surface of the concave portion and is aligned with the central portion of the connecting electrode to make connection. It can be highly reliable.
【００１３】請求項３に記載の発明は、凹部を蟻溝形状
とした構成であり、位置合せが行えるとともにバンプが
蟻溝形状の凹部内にはまりこんで結合強度の優れたもの
とすることができる。According to the third aspect of the present invention, the recess is formed in a dovetail groove shape, and the alignment can be performed, and the bump can be embedded in the dovetail groove-shaped recessed portion to have excellent bonding strength. .
【００１４】請求項４に記載の発明は、凹部を半球面状
とし、バンプを半球面状とした構成であり、両者が半球
面状のため確実にはまり合い、確実な接続を実現するこ
とができる。According to the fourth aspect of the present invention, the concave portion is formed in a hemispherical shape and the bump is formed in a hemispherical shape. Since both of them are hemispherical shapes, they can be securely fitted to each other to realize a reliable connection. it can.
【００１５】請求項５に記載の発明は、凹部を形成した
接続用電極を有する実装基板にあらかじめ形成した熱硬
化性樹脂層により、この熱硬化性樹脂層を貫通するよう
に組込まれた半導体ベアチップのバンプを接続用電極に
当接させて電気的に接続させるとともに実装基板に半導
体ベアチップを機械的に接合した構成であり、熱硬化性
樹脂層を突き破ってバンプが接続用電極の凹部に入りこ
み、熱硬化性樹脂層の硬化時の引付力でより確実に接続
できる。According to a fifth aspect of the present invention, a semiconductor bare chip is incorporated by a thermosetting resin layer formed in advance on a mounting substrate having a connecting electrode having a recess formed so as to penetrate the thermosetting resin layer. Is a structure in which the semiconductor bare chip is mechanically joined to the mounting substrate while the bumps are brought into contact with the connection electrodes to be electrically connected, and the bumps penetrate the thermosetting resin layer and enter the recesses of the connection electrodes, The attracting force at the time of curing the thermosetting resin layer enables more reliable connection.
【００１６】請求項６に記載の発明は、凹部を有する接
続用電極にバンプの表面に形成した導電性ペーストによ
り接続した構成であり、導電性ペーストは接続用電極の
凹部に入りこみ、直接バンプと接続用電極とが接続され
る部分もできるので熱ストレスに対しても安定した接続
が維持できることになる。The invention according to claim 6 is a structure in which a connecting electrode having a concave portion is connected by a conductive paste formed on the surface of the bump, and the conductive paste enters the concave portion of the connecting electrode to directly form a bump. Since a portion to be connected to the connection electrode is also formed, stable connection can be maintained even against thermal stress.
【００１７】請求項７に記載の発明は、接続用電極を有
する実装基板上に上記接続用電極と対応する位置に半導
体ベアチップのバンプをガイドする凹部を有する絶縁膜
を設けた構成であり、接続用電極に凹部を設ける必要が
なく、しかも位置合せは同じように行えることになる。According to a seventh aspect of the present invention, there is provided a mounting substrate having a connecting electrode, and an insulating film having a recess for guiding the bump of the semiconductor bare chip is provided at a position corresponding to the connecting electrode. It is not necessary to provide a recess in the working electrode, and the alignment can be performed in the same manner.
【００１８】請求項８に記載の発明は、絶縁膜に設けた
接続用電極まで達する凹部に接続用電極と電気的に接続
される凹状の金属膜を設けた構成であり、接続用電極に
凹部を形成する必要がなく、容易に凹状の金属膜を形成
することができる。The invention according to claim 8 is a structure in which a concave metal film electrically connected to the connection electrode is provided in the recess reaching the connection electrode provided in the insulating film, and the recess is formed in the connection electrode. The concave metal film can be easily formed without the need to form a metal film.
【００１９】以下、本発明の半導体実装モジュールの実
施の形態について図面を用いて説明する。Embodiments of a semiconductor mounting module of the present invention will be described below with reference to the drawings.
【００２０】（実施の形態１）本発明の実施の形態１の
半導体実装モジュールについて図１〜図３を用いて説明
する。図１は本発明の実施の形態１における半導体実装
モジュールの要部の断面図である。(Embodiment 1) A semiconductor mounting module according to Embodiment 1 of the present invention will be described with reference to FIGS. FIG. 1 is a sectional view of a main part of a semiconductor mounting module according to a first embodiment of the present invention.
【００２１】図１において、１０は合成樹脂やセラミッ
クからなる実装基板であり、この実装基板１０の少なく
とも表面には上面に凹部１１を有する接続用電極１２が
設けられている。また、図示してはいないが、この接続
用電極１２の他に配線パターンや面実装用電子部品を実
装する電極などが形成されている。さらに内部に回路パ
ターンを形成した多層構造の実装基板としてもよい。In FIG. 1, reference numeral 10 denotes a mounting substrate made of synthetic resin or ceramics, and at least the surface of the mounting substrate 10 is provided with a connecting electrode 12 having a recess 11 on the upper surface. Although not shown, in addition to the connecting electrode 12, a wiring pattern, an electrode for mounting a surface mounting electronic component, and the like are formed. Further, a mounting board having a multi-layer structure having a circuit pattern formed therein may be used.
【００２２】１３はこの実装基板１０の表面に設けたエ
ポキシ樹脂などからなる熱硬化性樹脂層である。１４は
上記実装基板１０にフェイスダウンによって実装される
半導体ベアチップであり、この半導体ベアチップ１４の
下面に設けた端子１５には金あるいは半田からなる突起
状のバンプ１６が設けられている。Reference numeral 13 is a thermosetting resin layer formed on the surface of the mounting substrate 10 and made of epoxy resin or the like. Reference numeral 14 denotes a semiconductor bare chip that is mounted face down on the mounting substrate 10. The terminals 15 provided on the lower surface of the semiconductor bare chip 14 are provided with bumps 16 made of gold or solder.
【００２３】この構成の半導体実装モジュールは以下の
ように組立てられる。すなわち、半導体ベアチップ１４
のバンプ１６は図２（ａ）に示すように上記熱硬化性樹
脂層１３を貫通して実装基板１０の接続用電極１２の凹
部１１にガイドされて位置合せされて当接し、実装治具
１７による加熱加圧処理によって図２（ｂ）に示すよう
に凹部１１内にバンプ１６が充填されて接続用電極１２
に電気的に接続されている。また、この加熱加圧による
処理によって熱硬化性樹脂層１３は硬化し、この硬化時
に発生する引付力によって実装基板１０に半導体ベアチ
ップ１４を引付け、バンプ１６と接続用電極１２との接
続をより強固に行い、しかも硬化によって実装基板１０
と半導体ベアチップ１４との機械的結合も強固に行って
いる。The semiconductor mounted module having this structure is assembled as follows. That is, the semiconductor bare chip 14
2A, the bump 16 penetrates through the thermosetting resin layer 13 and is guided by the concave portion 11 of the connecting electrode 12 of the mounting substrate 10 so as to be aligned and abutted thereto. As shown in FIG. 2B, the bumps 16 are filled in the recesses 11 by the heating and pressurizing process by
Electrically connected to. Further, the thermosetting resin layer 13 is hardened by the treatment by the heating and pressurization, and the semiconductor bare chip 14 is attracted to the mounting substrate 10 by the attracting force generated at the time of hardening, so that the bump 16 and the connection electrode 12 are connected. The mounting board 10 is made more rigid and hardened.
And the semiconductor bare chip 14 are mechanically coupled firmly.
【００２４】また、別の例として図３（ａ），（ｂ）に
示すように半導体ベアチップ１４のバンプ１６の表面に
導電性ペースト１８を塗布したものを実装基板１０の接
続用電極１２の凹部１１を利用して位置決めしながら接
合させ、導電性ペースト１８を乾燥させて固化させてバ
ンプ１６と接続用電極１２とを電気的に接続し、その後
実装基板１０と半導体ベアチップ１４との間に封止樹脂
１９を注入して硬化し、実装基板１０と半導体ベアチッ
プ１４との機械的な結合と、上記バンプ１６と接続用電
極１２との電気的接続の保護を行う構成とすることもで
きる。As another example, as shown in FIGS. 3A and 3B, the bumps 16 of the semiconductor bare chip 14 coated with the conductive paste 18 are recessed portions of the connection electrodes 12 of the mounting substrate 10. 11 is used for positioning and bonding, and the conductive paste 18 is dried and solidified to electrically connect the bumps 16 and the connecting electrodes 12, and then the mounting substrate 10 and the semiconductor bare chip 14 are sealed. It is also possible to inject and harden the stop resin 19 to mechanically bond the mounting substrate 10 and the semiconductor bare chip 14 and to protect the electrical connection between the bump 16 and the connection electrode 12.
【００２５】上記いずれの実装構造においては、半導体
ベアチップ１４を実装するときや圧力を加えるとき、さ
らには封止樹脂１９を注入するときに位置ずれを発生す
る可能性が高くなるが、接続用電極１２の凹部１１によ
ってバンプ１６が位置決めされているため半導体ベアチ
ップ１４のバンプ１６が実装基板１０の接続用電極１２
に対して位置ずれを発生することは無くなり、接続の信
頼性の高いものを得ることができる。In any of the mounting structures described above, there is a high possibility that a positional deviation will occur when the semiconductor bare chip 14 is mounted, when pressure is applied, and when the sealing resin 19 is injected, but the connection electrodes are connected. Since the bump 16 is positioned by the recess 11 of the semiconductor chip 12, the bump 16 of the semiconductor bare chip 14 is connected to the connection electrode 12 of the mounting substrate 10.
However, the positional deviation does not occur, and a highly reliable connection can be obtained.
【００２６】（実施の形態２）次に本発明の実施の形態
２の半導体実装モジュールについて図４により説明す
る。この実施の形態２に示すものは、実装基板１０の接
続用電極１２に設ける凹部１１の形状に工夫を加えたも
のである。(Second Embodiment) Next, a semiconductor mounting module according to a second embodiment of the present invention will be described with reference to FIG. In the second embodiment, the shape of the recess 11 provided in the connection electrode 12 of the mounting substrate 10 is modified.
【００２７】すなわち、実施の形態１においては凹部１
１は円柱形としていたが、実施の形態２においてはこの
凹部１１を逆円錐台形状としたものである。この逆円錐
台形状の凹部１１とすることにより、半導体ベアチップ
１４のバンプ１６の先端が少しでも凹部１１内に入りさ
えすれば中心がずれていても凹部１１の傾斜した側面を
滑ってバンプ１６を凹部１１の中央部にくるように半導
体ベアチップ１４を実装することができる。That is, in the first embodiment, the concave portion 1
Although 1 has a cylindrical shape, in the second embodiment, this recess 11 has an inverted truncated cone shape. By forming the concave portion 11 having the shape of an inverted truncated cone, even if the tip of the bump 16 of the semiconductor bare chip 14 is slightly displaced into the concave portion 11, the bump 16 is slid on the inclined side surface of the concave portion 11 even if the center is displaced. The semiconductor bare chip 14 can be mounted so as to come to the center of the recess 11.
【００２８】最終的な実装形態は図２や図３に示した形
態をとることになる。The final mounting form will take the form shown in FIGS.
【００２９】（実施の形態３）次に本発明の実施の形態
３の半導体実装モジュールについて図５（ａ），（ｂ）
を用いて説明する。この実施の形態３も実装基板１０の
接続用電極１２に設ける凹部１１の形状に工夫を加えた
ものである。(Third Embodiment) Next, a semiconductor mounting module according to a third embodiment of the present invention will be described with reference to FIGS.
Will be explained. Also in this third embodiment, the shape of the recess 11 provided in the connection electrode 12 of the mounting substrate 10 is modified.
【００３０】すなわち、接続用電極１２に形成する凹部
１１として、開口部が狭く、内奥部ほど広くなった蟻溝
形状としたものであり、実装時にはこの凹部１１がバン
プ１６のガイドとなって接続用電極１２に正しくはまり
合い、半導体ベアチップ１４の上部から圧力を加えたと
き図５（ｂ）に示すように凹部１１内にバンプ１６が喰
い付き電気的接続、機械的結合の強固なものとすること
ができる。That is, the recess 11 formed in the connection electrode 12 has a dovetail shape with a narrow opening and a wider inner depth. The recess 11 serves as a guide for the bump 16 during mounting. As shown in FIG. 5B, when the pressure is applied from above the semiconductor bare chip 14, the bump 16 bites into the concave portion 11 when the pressure is applied from above the semiconductor bare chip 14, and the electrical connection and the mechanical coupling are strong. can do.
【００３１】本実施の形態３では、熱硬化性樹脂や封止
樹脂の使用は必要ないため、工程が少なくできる。In the third embodiment, since it is not necessary to use the thermosetting resin or the sealing resin, the number of steps can be reduced.
【００３２】（実施の形態４）次に本発明の実施の形態
４の半導体実装モジュールについて図６（ａ）〜（ｃ）
を用いて説明する。(Fourth Embodiment) Next, a semiconductor mounting module according to a fourth embodiment of the present invention will be described with reference to FIGS.
Will be explained.
【００３３】図６（ａ）に示すように実装基板１０の上
面に凹部１１を有さない従来と同様の接続用電極１２を
設けたものを準備し、図６（ｂ）に示すようにこの実装
基板１０の表面に絶縁膜２０を一面に設けた後、図６
（ｃ）に示すように上記接続用電極１２上の絶縁膜２０
に凹部１１を形成する。As shown in FIG. 6 (a), a mounting substrate 10 having a connection electrode 12 similar to the conventional one having no recessed portion 11 on the upper surface thereof is prepared, and as shown in FIG. 6 (b), this is prepared. After the insulating film 20 is provided on the entire surface of the mounting substrate 10, as shown in FIG.
As shown in (c), the insulating film 20 on the connection electrode 12 is formed.
A recess 11 is formed in the.
【００３４】このような実装基板１０を用いて、図６
（ｃ）に示すように半導体ベアチップ１４のバンプ１６
を絶縁膜２０の凹部１１にガイドさせて実装し、加熱加
圧あるいは超音波振動を加えてバンプ１６を接続用電極
１２に接続する。By using such a mounting substrate 10, as shown in FIG.
As shown in (c), the bump 16 of the semiconductor bare chip 14
Is guided and mounted in the concave portion 11 of the insulating film 20, and the bump 16 is connected to the connecting electrode 12 by applying heat and pressure or ultrasonic vibration.
【００３５】上記絶縁膜２０は塗布によって形成し、硬
化させた後、接続用電極１２に対応する位置にレーザを
照射して凹部１１を形成する。この凹部１１の形成はレ
ーザによる形成方法の他にエッチングによっても形成で
きる。また、絶縁膜２０はソルダーレジストやガラスコ
ート膜を用いることができ、樹脂を用いる場合は封止樹
脂としての働きを兼ねさせることもできる。The insulating film 20 is formed by coating and cured, and then the position corresponding to the connection electrode 12 is irradiated with a laser to form the recess 11. The recess 11 can be formed not only by the laser method but also by etching. Further, a solder resist or a glass coat film can be used for the insulating film 20, and when a resin is used, it can also serve as a sealing resin.
【００３６】（実施の形態５）次に本発明の実施の形態
５の半導体実装モジュールについて図７〜図９を用いて
説明する。図７（ａ），（ｂ）は半導体実装モジュール
の実装工程を示す断面図、図８（ａ），（ｂ）は同半導
体実装モジュールに用いる実装基板の製造プロセスを示
す断面図、図９（ａ）〜（ｅ）は他の実装基板の製造プ
ロセスを示す断面図である。(Fifth Embodiment) Next, a semiconductor mounting module according to a fifth embodiment of the present invention will be described with reference to FIGS. 7A and 7B are cross-sectional views showing a mounting process of the semiconductor mounting module, FIGS. 8A and 8B are cross-sectional views showing a manufacturing process of a mounting board used in the semiconductor mounting module, and FIG. 8A to 8E are cross-sectional views showing a manufacturing process of another mounting board.
【００３７】本実施の形態５の半導体実装モジュール
は、図７（ａ），（ｂ）に示すように実施の形態４に示
した実装基板１０の絶縁膜２０に設けた凹部１１内に接
続用電極１２と電気的に接続された凹状の金属膜２１を
設け、この金属膜２１を介して半導体ベアチップ１４の
バンプ１６と接続用電極１２とを接続するものである。As shown in FIGS. 7A and 7B, the semiconductor mounting module according to the fifth embodiment is for connecting in the recess 11 provided in the insulating film 20 of the mounting substrate 10 according to the fourth embodiment. A concave metal film 21 electrically connected to the electrode 12 is provided, and the bump 16 of the semiconductor bare chip 14 and the connection electrode 12 are connected via the metal film 21.
【００３８】この構成においても、半導体ベアチップ１
４のバンプ１６は金属膜２１によってガイドされて実装
されることになり、半導体ベアチップ１４の実装基板１
０との位置ずれは完全に無くすことができる。Also in this configuration, the semiconductor bare chip 1
The bumps 16 of No. 4 are guided and mounted by the metal film 21, and the mounting board 1 of the semiconductor bare chip 14 is mounted.
The positional deviation from 0 can be completely eliminated.
【００３９】上記構成において、図７ではバンプ１６と
して半球面状の半田バンプを用いたが、金属膜２１の材
質として半田付性に優れた金属を選択することにより、
バンプ１６の接続をより確実なものとすることができ
る。In the above-mentioned structure, a hemispherical solder bump is used as the bump 16 in FIG. 7, but by selecting a metal having excellent solderability as the material of the metal film 21,
The connection of the bumps 16 can be made more reliable.
【００４０】本実施の形態５においては、実施の形態１
〜４に示すような実装ずれ防止の効果だけでなく、従来
の半田バンプを用いた実装では熱衝撃時に受ける半田ポ
ストのせん断方向への歪が半田ポストと接続用電極の界
面に集中するため、その界面部で破断が起こる可能性が
高かったが、以上のような構成により半田ポストのせん
断方向への歪が凹部１１の側面部で抑制できるため、接
続信頼性を向上させることもできる。また、実施の形態
１〜４では図示説明は行わなかったが、一般的な実装基
板１０では、接続用電極１２から配線パターンが引き回
されるため、実施の形態１〜４の形態で半田バンプを用
いた実装を実施しようとすると、接続用電極１２だけで
なく配線パターンにも半田が溶融して流れていくため、
半田量が不足し半導体ベアチップ１４と実装基板１０の
接続が得られなくなる可能性があったが、本実施の形態
５に示したような実装基板１０では、凹部１１内の金属
膜２１の内のみで半田溶融するため、半田のバンプ１６
を用いた実装でも容易に使用可能となる。In the fifth embodiment, the first embodiment
In addition to the effect of preventing mounting deviation as shown in 4 to 4, in the mounting using the conventional solder bumps, the strain in the shearing direction of the solder post received at the time of thermal shock is concentrated on the interface between the solder post and the connecting electrode. Although there is a high possibility that breakage will occur at the interface portion, strain in the shearing direction of the solder post can be suppressed at the side surface portion of the recess 11 with the above-described configuration, and therefore connection reliability can also be improved. Although not illustrated in the first to fourth embodiments, since the wiring pattern is laid out from the connection electrodes 12 in the general mounting board 10, the solder bumps are formed in the first to fourth embodiments. When attempting to implement mounting using, the solder melts and flows not only in the connecting electrode 12 but also in the wiring pattern.
There is a possibility that the semiconductor bare chip 14 and the mounting substrate 10 may not be connected due to the insufficient amount of solder, but in the mounting substrate 10 as shown in the fifth embodiment, only the metal film 21 in the recess 11 is formed. The solder bumps 16
It can be easily used even with implementation using.
【００４１】次に、本実施の形態５で示す凹部１１内の
みに金属膜２１を形成する方法として、２種類の方法を
説明する。Next, two types of methods will be described as the method of forming the metal film 21 only in the recess 11 shown in the fifth embodiment.
【００４２】まず、図８（ａ），（ｂ）は凹部１１内の
みに金属膜２１を形成する第１の方法を示す工程図であ
る。First, FIGS. 8A and 8B are process drawings showing a first method of forming the metal film 21 only in the recess 11.
【００４３】第１の方法では、図８（ａ）に示す通り実
施の形態４に示すような接続用電極１２上に絶縁膜２０
に凹部１１を形成した実装基板１０の表面に、メッキを
用いて金属膜２１を形成し、図８（ｂ）に示すように研
磨により凹部１１内を除く絶縁膜２０の表面の金属膜２
１を除去することにより形成する。In the first method, as shown in FIG. 8A, the insulating film 20 is formed on the connecting electrode 12 as shown in the fourth embodiment.
A metal film 21 is formed by plating on the surface of the mounting substrate 10 having the recess 11 formed therein, and the metal film 2 on the surface of the insulating film 20 excluding the inside of the recess 11 is polished as shown in FIG. 8B.
It is formed by removing 1.
【００４４】更に、図９（ａ）〜（ｅ）は凹部１１内の
みに金属膜２１を形成する第２の方法を示す工程図であ
る。図９において、２２はレジスト膜を示す。Further, FIGS. 9A to 9E are process diagrams showing a second method of forming the metal film 21 only in the recess 11. In FIG. 9, 22 indicates a resist film.
【００４５】第２の方法では、図９（ａ）に示す通り従
来の実装基板と同様にフォトリソ工法またはメッキによ
り実装基板１０上に接続用電極１２を形成した後、接続
用電極１２を覆うように絶縁膜２０を塗布、硬化し、更
に、図９（ｂ）に示すように絶縁膜２０の表面に溶剤等
で膨潤させることにより剥離可能なレジスト膜２２を貼
り付け、図９（ｃ）に示すように接続用電極１２上のレ
ジスト膜２２及び絶縁膜２０をレーザにより除去して凹
部１１を形成し接続用電極１２を表出させ、図９（ｄ）
に示すようにレジスト膜２２の表面側にメッキを用いて
金属膜２１を形成し、最後に、図９（ｅ）に示すように
レジスト膜２２を溶剤等で膨潤させて除去することによ
って形成される。In the second method, as shown in FIG. 9A, the connection electrode 12 is formed on the mounting substrate 10 by the photolithography method or plating as in the conventional mounting substrate, and then the connection electrode 12 is covered. 9C, an insulating film 20 is applied and cured, and a resist film 22 that can be peeled off by being swollen with a solvent or the like is attached to the surface of the insulating film 20 as shown in FIG. 9B. As shown in FIG. 9D, the resist film 22 and the insulating film 20 on the connection electrode 12 are removed by a laser to form a recess 11 to expose the connection electrode 12.
9B, the metal film 21 is formed on the surface side of the resist film 22 by plating, and finally, as shown in FIG. 9E, the resist film 22 is swollen with a solvent or the like and removed. It
【００４６】（実施の形態６）次に本発明の実施の形態
６の半導体実装モジュールについて図１０（ａ），
（ｂ）を用いて説明する。(Sixth Embodiment) Next, FIG. 10A shows a semiconductor mounting module according to a sixth embodiment of the present invention.
An explanation will be given using (b).
【００４７】基本的には実施の形態５と同じ構成である
が、絶縁膜２０に設ける凹部１１を半球面状とし、この
凹部１１内に接続用電極１２と電気的に接続される半球
面状の金属膜２１を形成し、半導体ベアチップ１４のバ
ンプ１６も半田により半球面状とし、この両者を位置合
せすることにより半球面状のバンプ１６が自然に半球面
状の金属膜２１内にはまりこみ、確実な位置合せが行え
るとともに接続の信頼性を高めることができる。The structure is basically the same as that of the fifth embodiment, but the recess 11 provided in the insulating film 20 has a hemispherical shape, and the recess 11 has a hemispherical shape electrically connected to the connection electrode 12. Metal film 21 is formed, and the bump 16 of the semiconductor bare chip 14 is also made into a hemispherical shape by soldering. By aligning the two, the hemispherical bump 16 naturally fits into the hemispherical metal film 21. As a result, reliable alignment can be achieved and connection reliability can be improved.
【００４８】なお、この実施の形態６では、絶縁膜２０
に凹部１１を設けたものを例としたが、実施の形態１に
示す構成のものにおいて接続用電極１２の上面に設ける
凹部１１を半球面状としても同様の効果を得ることがで
きる。In the sixth embodiment, the insulating film 20
Although the concave portion 11 is provided as an example, the concave portion 11 provided on the upper surface of the connecting electrode 12 in the structure shown in the first embodiment can have a hemispherical shape and the same effect can be obtained.
【００４９】（実施の形態７）本発明の実施の形態７の
半導体実装モジュールを図１１（ａ）〜（ｄ）を用いて
説明する。(Seventh Embodiment) A semiconductor mounting module according to a seventh embodiment of the present invention will be described with reference to FIGS.
【００５０】この実施の形態７は、実施の形態４に示し
た実装基板１０の絶縁膜２０の上にも配線パターン２３
を形成して多層化した実装基板１０としたものである。In the seventh embodiment, the wiring pattern 23 is formed on the insulating film 20 of the mounting substrate 10 shown in the fourth embodiment.
To form a multi-layered mounting substrate 10.
【００５１】すなわち、図１１（ａ）に示すように上面
に接続用電極１２を形成した実装基板１０を準備し、こ
の実装基板１０上に図１１（ｂ）に示すように樹脂フィ
ルムを貼付けて絶縁膜２０を形成し、次に図１１（ｃ）
に示すように接続用電極１２上にレーザを照射して接続
用電極１２が表出するように凹部１１を設け、続いて図
１１（ｄ）に示すようにこの絶縁膜２０上および凹部１
１内にメッキによって金属膜２１を形成し、必要な部分
を残して他の部分をエッチング除去して配線パターン２
３を形成する。That is, as shown in FIG. 11A, a mounting substrate 10 having connection electrodes 12 formed on its upper surface is prepared, and a resin film is stuck on the mounting substrate 10 as shown in FIG. 11B. An insulating film 20 is formed, and then, FIG.
As shown in FIG. 11, a concave portion 11 is provided so that the connecting electrode 12 is exposed by irradiating a laser, and then the insulating film 20 and the concave portion 1 are formed as shown in FIG.
A metal film 21 is formed by plating in 1 and a wiring pattern 2 is formed by etching away the other portions except the necessary portions.
3 is formed.
【００５２】このような構成とすることにより、凹部１
１に形成された金属膜２１によって半導体ベアチップ１
４のバンプ１６の位置決めが行えて接続の信頼性の向上
が図れるとともに、半導体ベアチップ１４の端子１５が
狭ピッチ化しても実装基板１０の高密度配線化が実現で
き、狭ピッチ化にも十分対応できることになる。With this structure, the recess 1 is formed.
Semiconductor bare chip 1 by the metal film 21 formed on the semiconductor chip 1.
The bumps 16 of No. 4 can be positioned to improve the reliability of connection, and even if the pitch of the terminals 15 of the semiconductor bare chip 14 is narrowed, high density wiring of the mounting substrate 10 can be realized and the pitch can be sufficiently reduced. You can do it.
【００５３】[0053]
【発明の効果】以上のように本発明の半導体実装モジュ
ールは構成されるため、半導体ベアチップと実装基板と
の実装位置のずれが無くなり、接続の信頼性に優れたも
のとすることができる。Since the semiconductor mounting module of the present invention is configured as described above, the mounting position between the semiconductor bare chip and the mounting substrate is eliminated, and the connection reliability can be improved.
【図１】本発明の実施の形態１における半導体実装モジ
ュールの断面図FIG. 1 is a sectional view of a semiconductor mounting module according to a first embodiment of the present invention.
【図２】（ａ），（ｂ）同半導体実装モジュールの実装
プロセスを説明する断面図2A and 2B are cross-sectional views illustrating a mounting process of the same semiconductor mounting module.
【図３】（ａ），（ｂ）同半導体実装モジュールの他の
例の実装プロセスを説明する断面図3A and 3B are cross-sectional views illustrating a mounting process of another example of the semiconductor mounting module.
【図４】本発明の実施の形態２における半導体実装モジ
ュールの実装基板を示す断面図FIG. 4 is a sectional view showing a mounting board of a semiconductor mounting module according to a second embodiment of the present invention.
【図５】（ａ），（ｂ）本発明の実施の形態３における
半導体実装モジュールの実装プロセスを説明する断面図5A and 5B are cross-sectional views illustrating a mounting process of a semiconductor mounting module according to a third embodiment of the present invention.
【図６】（ａ）〜（ｃ）本発明の実施の形態４における
半導体実装モジュールの実装基板の製造プロセスを示す
断面図6A to 6C are cross-sectional views showing a manufacturing process of a mounting board for a semiconductor mounting module according to a fourth embodiment of the present invention.
【図７】（ａ），（ｂ）本発明の実施の形態５における
半導体実装モジュールの実装プロセスを説明する断面図7A and 7B are cross-sectional views illustrating a mounting process of a semiconductor mounting module according to a fifth embodiment of the present invention.
【図８】（ａ），（ｂ）同実施の形態５に用いる実装基
板の製造プロセスを示す断面図8A and 8B are cross-sectional views showing a manufacturing process of a mounting board used in the fifth embodiment.
【図９】（ａ）〜（ｅ）同実施の形態５に用いる実装基
板の他の製造プロセスを示す断面図9A to 9E are cross-sectional views showing another manufacturing process of the mounting board used in the fifth embodiment.
【図１０】（ａ），（ｂ）本発明の実施の形態６におけ
る半導体実装モジュールの実装プロセスを説明する断面
図10A and 10B are cross-sectional views illustrating a mounting process of a semiconductor mounting module according to a sixth embodiment of the present invention.
【図１１】（ａ）〜（ｄ）本発明の実施の形態７におけ
る半導体実装モジュールに用いる実装基板の製造プロセ
スを示す断面図11A to 11D are cross-sectional views showing a manufacturing process of a mounting board used for a semiconductor mounting module according to a seventh embodiment of the present invention.
【図１２】従来の半導体実装モジュールの実装状態を示
す断面図FIG. 12 is a sectional view showing a mounting state of a conventional semiconductor mounting module.
【図１３】（ａ），（ｂ）従来の他の例の実装プロセス
を説明する断面図13A and 13B are cross-sectional views illustrating a mounting process of another example of the related art.
【図１４】（ａ），（ｂ）従来のさらに他の例の実装プ
ロセスを説明する断面図14A and 14B are cross-sectional views illustrating a mounting process of still another example of the related art.
【図１５】（ａ），（ｂ）従来のさらに他の例の実装プ
ロセスを説明する断面図15A and 15B are cross-sectional views illustrating a mounting process of still another example of the related art.
１０ 実装基板 １１ 凹部 １２ 接続用電極 １３ 熱硬化性樹脂層 １４ 半導体ベアチップ １５ 端子 １６ バンプ １７ 実装治具 １８ 導電性ペースト １９ 封止樹脂 ２０ 絶縁膜 ２１ 金属膜 ２２ レジスト膜 ２３ 配線パターン 10 Mounting board 11 recess 12 Connection electrodes 13 Thermosetting resin layer 14 Semiconductor bare chip 15 terminals 16 bumps 17 Mounting jig 18 Conductive paste 19 Sealing resin 20 insulating film 21 metal film 22 Resist film 23 Wiring pattern
Claims (8)
た半導体ベアチップと、この半導体ベアチップのバンプ
と接続される接続用電極を設けた実装基板とからなり、
この実装基板の接続用電極自身または接続用電極の上部
に半導体ベアチップの突起状のバンプをガイドする凹部
を設けた半導体実装モジュール。1. A semiconductor bare chip having a bump on a terminal on the mounting surface side and a mounting substrate having a connecting electrode connected to the bump of the semiconductor bare chip,
A semiconductor mounting module in which a recess for guiding a protruding bump of a semiconductor bare chip is provided on the connection electrode itself or on the connection electrode of the mounting substrate.
載の半導体実装モジュール。2. The semiconductor mounting module according to claim 1, wherein the recess has an inverted truncated cone shape.
半導体実装モジュール。3. The semiconductor mounting module according to claim 1, wherein the recess has a dovetail shape.
とした請求項１に記載の半導体実装モジュール。4. The semiconductor mounting module according to claim 1, wherein the recess has a hemispherical shape and the bump has a hemispherical shape.
基板にあらかじめ形成した熱硬化性樹脂層により、この
熱硬化性樹脂層を貫通するように組込まれた半導体ベア
チップのバンプを接続用電極に当接させて電気的に接続
させるとともに実装基板に半導体ベアチップを機械的に
接合した請求項１に記載の半導体実装モジュール。5. A bump of a semiconductor bare chip, which is incorporated so as to penetrate the thermosetting resin layer, is used as a connection electrode by a thermosetting resin layer previously formed on a mounting board having a connection electrode having a recess. The semiconductor mounting module according to claim 1, wherein the semiconductor bare chip is mechanically bonded to the mounting substrate while being brought into contact with each other to be electrically connected.
に形成した導電性ペーストにより接続した請求項１に記
載の半導体実装モジュール。6. The semiconductor mounting module according to claim 1, wherein the connection electrode having the recess is connected by a conductive paste formed on the surface of the bump.
続用電極と対応する位置に半導体ベアチップのバンプを
ガイドする凹部を有する絶縁膜を設けた請求項１に記載
の半導体実装モジュール。7. The semiconductor mounting module according to claim 1, wherein an insulating film having a concave portion for guiding the bump of the semiconductor bare chip is provided at a position corresponding to the connecting electrode on a mounting substrate having a connecting electrode.
部に接続用電極と電気的に接続される凹状の金属膜を設
けた請求項７に記載の半導体実装モジュール。8. The semiconductor mounting module according to claim 7, wherein a recessed metal film electrically connected to the connection electrode is provided in a recess reaching the connection electrode provided in the insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002071876A JP2003273160A (en) | 2002-03-15 | 2002-03-15 | Semiconductor mounting module |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002071876A JP2003273160A (en) | 2002-03-15 | 2002-03-15 | Semiconductor mounting module |
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| Publication Number | Publication Date |
|---|---|
| JP2003273160A true JP2003273160A (en) | 2003-09-26 |
Family
ID=29202031
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2002071876A Pending JP2003273160A (en) | 2002-03-15 | 2002-03-15 | Semiconductor mounting module |
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| Country | Link |
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| JP (1) | JP2003273160A (en) |
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