JP2003248452A - Method and apparatus for driving field emission display - Google Patents

Abstract

(57) [Summary] [PROBLEMS] A data driver corrects image data output from a data conversion circuit and a drive voltage control circuit from a drive voltage control circuit. The signal is used as input to control the cathode electrode of the FED. The characteristics of the pixels are written in the ROM 5 in advance, and the characteristics can be obtained by measuring in advance the light emission amount of each pixel when a constant luminance is given. The drive voltage control circuit 6 reversely corrects the respective current characteristics from the output from the ROM 5 and outputs a drive voltage correction signal for the data driver.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and apparatus for driving a field emission display.

[0002]

2. Description of the Related Art In recent years, as a flat panel display, a field emission display (hereinafter referred to as FED) using a minute emitter as an electron source has been attracting attention. The FED is composed of a display substrate on which a plurality of pixels each having a field emission type emitter driven by a gate electrode are arranged, and an opposite substrate on which an anode electrode and a phosphor film are formed so as to face the display substrate. It A plurality of gate wirings for commonly driving the pixels in the row direction on the display substrate and a plurality of cathode wirings for commonly driving the field emission emitters of the pixels in the column direction are taken out to the outside. Then, for example, so-called line-sequential drive image display is performed by sequentially driving the gate wirings and applying image data for each line to the cathode wirings in synchronization with this.

When a full-color image display is performed in this type of FED, R (red), G (green) and B (blue) are used.
The three primary color dots are used as one pixel, and phosphor films for R, G and B are formed on the anode electrodes facing the field emission type emitters of the R, G and B dots, respectively. It As the cathode wiring on the display electrode, three wirings for R, G and B are provided for each pixel.

For example, by sequentially applying a positive gate voltage pulse (for example, +25 V) to the gate wiring,
The selection is performed line by line, and in synchronization with this, a negative cathode voltage pulse (for example, -25V) is applied to each cathode line according to the image data. +2 for gate wiring
In the dot where 5V is applied and -25V is applied to the cathode wiring, the gate-cathode voltage becomes 50V, and electrons are emitted at the tip of the emitter, and this electron is on the anode electrode side to which a positive high voltage is applied. The light is emitted when it is accelerated to hit the phosphor film. The gradation display of FED is
PWM (pulse width modulation) of the above-mentioned emitter voltage pulse
It becomes possible by controlling the pulse width as a pulse.

FIG. 5 is a block diagram of a driving circuit in a flat type color FED using a surface emission type electric field cathode, and FIG.
FIG. 4 is a diagram showing the operation timing. In FIG. 5, reference numeral 50 denotes an FED composed of a matrix of m × n pixels, and 51.
Is a clock generator that generates a clock synchronized with the applied synchronization signal, and 52 is a clock generator 51.
A display timing control circuit for controlling display timing using a clock generated from the memory 53, a memory write control circuit 53 for controlling input image data to be written in the video memory 54, and 54 R, G, B image data A frame memory or line memory 54-1 for storing the
A video memory 54-2, 54-3,
Reference numerals 55-2 and 55-3 are buffer registers for holding the R, G, and B image data read from the video memory 54.

Further, 56 is an address counter for generating an address of the video memory 54, 57 is a color selection circuit for selecting one of R, G and B image data, and 58 is data for controlling the gate electrode 3 shifted. Shift register, 59 is a latch circuit for latching the data of the shift register 58, 60 is a gate driver for driving the gate electrode of the FED 50 with the data of the latch circuit 59, and 61 is supplied from the buffer registers 55-1 to 55-3. A shift register in which image data is shifted by a shift clock, a latch circuit 62 for latching the data in the shift register 61, a cathode driver 63 for supplying the image data output of the latch circuit 62 to a cathode electrode, and a display timing control circuit 52. Drive the anode electrode of FED50 based on the control of An anode driver.

In such a drive circuit, the write timing of the input image data is controlled by the memory write control circuit 53, and the clock generator 5
The image data of each color is stored in the video memory 54 in synchronization with the clock generated at 1. Then, from the memories 54-1, 54-2, 54-3 in which the respective image data of R, G, B of the video memory 54 is stored, the color selection circuit 57 is selected.
Under the control of 1. and the image data read based on the address of the address counter 56, the image data is held in the buffer registers 55-1, 55-2, 55-3, respectively.

Buffer registers 55-1, 55-2, 5
The output timing of 5-3 is controlled by the color selection circuit 57, and each image data is supplied to the shift register circuit 61. The shift register 61 is shifted by the shift clock S-CLK from the display timing control circuit 52. When half the number of color data in one row corresponding to the number of striped anode electrodes connected to the anode extraction electrodes A1 in the pixels of one line is shifted to the shift register 61, this color data is displayed. The latch circuit 62 receives the latch pulse from the timing control circuit 52.
Latched on. The output data of the latch circuit 62 is
It is applied to the cathode driver 63.

On the other hand, the display control timing circuit 52 controls the anode driver 64 to apply a positive anode voltage only to the anode extraction electrode A1 as shown in FIGS. Further, the display timing control circuit 52 supplies a latch pulse to the shift register 58 as a shift pulse, and shifts the scan signal supplied from the control circuit 52. The output of the shift register 58 is latched in the latch circuit 59 by the latch pulse, so that the latch circuit 59 outputs a scan signal shifted for each latch pulse. Then, this scan signal is applied to the gate driver 60.

As a result, as shown in FIGS. 6C to 6F, the gate driver 60 sequentially applies the gate drive voltage to the gate extraction electrodes G1, G3, ... G2n-1 of the FED 50, These gate extraction electrodes G1 and G
3, ... G2n-1 is scanned. At this time, from the cathode driver 63, the driven gate extraction electrode G1,
Image data of G, B, R, ... Corresponding to G3 ... G2n-1 is supplied. By sequentially performing such scanning, when the gate lead-out electrode G2n-1 in the last row is scanned, 1/2 of the pixels in one frame are controlled to emit light.

Next, the display timing control circuit 52 controls the anode driver 64 to control the anode extraction electrode A2.
Is controlled such that a positive anode voltage is applied to the gate extraction electrodes G2, G4, ... G in this period, as shown in FIGS. 6 (g) to 6 (j). , These gate extraction electrodes G2, G
4 ... G2n is scanned.

Therefore, in this case, G, B, R, corresponding to the driven gate extraction electrodes G2, G4 ... G2n,
By supplying the image data of ... From the cathode driver 63, the light emission control of the remaining pixels of one frame is performed, and when the gate extraction electrode G2n of the last row is scanned, the image of one frame is displayed on the FED 50. Is displayed.

[0013]

In the FED, a cold cathode device in which about 1000 emitters are integrated per pixel is used. However, the characteristics of each pixel are different due to a minute environmental change in the process. With such a configuration, there is a problem in that brightness unevenness occurs due to variations in current between pixels, and the image quality of the display deteriorates.

Conventionally, there has been proposed a method of devising such a problem in the FED panel itself so as to prevent the variation of the current characteristic, but the manufacturing process becomes complicated and the characteristic varies. The panels could not be used and were wasteful. In view of the above problem, the present invention provides a driving apparatus for a field emission display capable of correcting a variation in luminance caused by a variation in current for each pixel, so that the panel manufacturing method is the same as the conventional method. It is an object of the present invention to enable uniform brightness to be expressed even in a panel having variations in characteristics.

[0015]

In order to solve the above problems, a driving method and apparatus of a field emission display according to the present invention are a memory device storing characteristics of each pixel and a drive pulse corresponding to the characteristics of the pixel. Is provided with a drive voltage control circuit. The brightness characteristic of each pixel of the field emission element is stored in the memory element in advance, and the output of the data driver for driving the field emission element is corrected for each pixel based on the brightness characteristic stored in advance.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION (Embodiment 1) The present invention will be described below based on examples. FIG. 1 is a diagram illustrating a field emission display drive device according to a first embodiment of the present invention, and FIG. 2 is an operation explanatory diagram thereof. The illustrated field emission display expresses luminance gradation by modulating the pulse width (PWM modulation). In FIG. 1, 1 is a video signal, 2 is a synchronization signal, and 3 is a data conversion circuit for inputting the video signal 1 and the synchronization signal 2 and PWM-modulating the video signal to obtain RGB image data. The data conversion circuit 3
A clock generator 5 illustrated in FIG. 5 as a conventional technique.
1, a display timing control circuit 52, a memory write control circuit 53, a frame memory or line memory 54, a buffer 55, an address counter 56, and a color selection circuit 57.

Reference numeral 4 shown in FIG. 1 is a scan driver for controlling the gate electrode of the FED by using the scan signal output from the data conversion circuit 3 as an input. The conventional shift register 58, the latch 59, and the gate driver 60 shown in FIG. It is equivalent to a collection of. Reference numeral 5 is a ROM in which the current characteristics of each pixel of the FED are stored, and 6 is a data driver 7 that inversely corrects the current characteristics of each pixel based on the output from the ROM 5.
2 is a drive voltage control circuit that outputs the drive voltage correction signal. Reference numeral 7 is a data driver that receives the image data output from the data conversion circuit 3 and a signal from the drive voltage control circuit 6 as an input, controls the cathode electrode of the FED, and expresses brightness by pulse width modulation.
Although it corresponds to the shift register 61, the latch 62, and the cathode driver 63 of the conventional FIG. 5, it is different in that it can receive a signal from the drive voltage control circuit 6. As the anode driver (not shown), the same one as the conventional anode driver 64 of FIG. 5 can be used. Regarding the drive device of the field emission display configured as above,
The operation will be described with reference to FIG.

FIG. 2A shows a display screen when a signal of the same luminance is applied to a 4 × 4 FED as an example. S0 to S3 are respective rows and D0 to D3 are respective rows. Shows the columns. 2B shows an output signal from the data conversion circuit 3, and FIG. 2C shows an output signal from the data driver 7. In FIG. 2A, a pixel (G11) in which S1 and D1 intersect due to variations in each pixel, even though the input of the same brightness is applied to the entire surface,
The brightness of the pixel (G23) where S2 and D3 intersect is low. The brightness level at this time is G11> G23.
Is shown. Since the case where the same luminance is applied to the entire surface is shown, the output signal from the data conversion circuit 3 becomes a pulse having a constant width as shown in FIG.

By the way, the characteristics of pixels are written in the ROM 5 in advance in this FED, for example, G11.
Values of 0.8, G23 of 0.5, and 1.0 are written in other pixels. This characteristic is obtained by previously measuring the light emission amount of each pixel when a constant brightness is given.

In order to correct these variations in luminance, the output from the data conversion circuit 3 is further PWM-modulated based on the information written in the ROM 5, and the pulse width of the second pulse of D1 is multiplied by 1.25. The third pulse width of D3 to 2
It can be modulated to double. However, in the illustrated case, the drive voltage control circuit 6 inversely corrects the respective current characteristics from the output from the ROM 5 and outputs the drive voltage correction signal of the data driver. By correcting the amplitude of the PWM modulation signal, even when the maximum brightness is expressed, it is possible to prevent the pulse width from exceeding one field period so that the gradation can be correctly expressed. Become. The data driver 7 receives the PWM-modulated image data output from the data conversion circuit 3 and the drive voltage correction signal output from the drive voltage control circuit 6, and outputs a pulse as shown in FIG. 2C. In FIG. 2C, S1 in the column of D1 including the pixel of G11 is
The signal of the row is corrected by the drive voltage correction signal, and the voltage amplitude is controlled so as to be aV higher than that of other pixels. Similarly, the pixel of G23 is also controlled to increase the bV voltage amplitude. The values of a and b are determined by measuring the electron emission characteristics of each pixel in advance.
In this case, the case where the brightness of a certain pixel is low has been described, but it is also possible that the brightness of a certain pixel is higher than the reference.
In this case, control is performed so as to reduce the drive voltage amplitude. Since the field emission current changes exponentially with respect to the gate voltage, the difference between these voltages a and b is small.

By correcting the drive voltage in this way, it is possible to increase the amount of current in the pixels of G11 and G23 whose brightness has decreased due to the small amount of current in the FED panel, and display an image with the same brightness. Is possible. Here, only the luminance signal as in a monochrome display has been described, but in the case of a color display, similar processing may be performed on each color pixel of RGB.

(Second Embodiment) Next, a second embodiment of the present invention will be described. FIG. 3 shows the second embodiment of the present invention.
FIG. 4 is a diagram illustrating a field emission display driving device of FIG. 4, and FIG. 4 is an operation explanatory diagram thereof. In the first embodiment, a description has been given of the video signal PWM-modulated to express the gradation, but in the second embodiment, an example in which the gradation is expressed by pulse amplitude modulation (hereinafter referred to as PAM modulation). Is.

In FIG. 3, 1 is a video signal, 2 is a synchronization signal, 3 is a data conversion circuit that receives the video signal 1 and the synchronization signal 2 as input, and PAM-modulates the video signal 1 to obtain RGB image data, and 4 is a data conversion. A scan driver for controlling the gate electrode of the FED with the scan signal output from the circuit 3 as an input, 5 is a ROM in which the current characteristics of each pixel of the FED are stored, and 8 is an FE with the output of the ROM 5 as an input.
A drive pulse width control circuit for controlling the voltage of the cathode electrode of D, 7 receives the image data output from the data conversion circuit 3 and a signal from the drive pulse width control circuit 8 to control the cathode electrode of the FED, It is a data driver that expresses brightness by pulse amplitude modulation. The operation of the field emission display driving device configured as described above will be described with reference to FIG.

FIG. 4A shows a display screen when a signal of the same brightness is applied to a 4 × 4 FED.
S0 to S3 indicate respective rows, and D0 to D3 indicate respective columns. 4B shows an output signal from the data conversion circuit 3, and FIG. 4C shows an output signal from the data driver 7. In FIG. 4A, a pixel (G11) where S1 and D1 intersect due to variations in each pixel, and S2 and D, even though the input of the same brightness is applied to the entire surface.
The luminance of the pixel (G23) where 3 intersects is low.
It also indicates that the brightness level at this time is G11> G23. Since the case where the same luminance is applied to the entire surface is shown, the output signal from the data conversion circuit 3 is as shown in FIG.
The pulse has a constant amplitude as shown in (b).

By the way, in this FED, the characteristics of the pixel are written in the ROM 5 in advance, for example, G11.
Values of 0.8, G23 of 0.5, and 1.0 are written in other pixels. This characteristic is obtained by previously measuring the light emission amount of each pixel when a constant brightness is given.
Next, each current characteristic is inversely corrected from the output from the ROM, and the correction signal of the data driver 7 is output. Therefore, although the amplitude of the PAM modulation signal from the data conversion circuit 3 can be inversely corrected, the drive pulse width control circuit 8 controls the data driver 7 based on the output from the ROM in the illustrated configuration. The drive width correction signal is being output. The data driver 7 is the data conversion circuit 3
The PAM-modulated image data output from the drive pulse width control circuit 8 and the drive pulse width correction signal output from the drive pulse width control circuit 8 are input to output a pulse as shown in FIG. In FIG. 4C, the signal in the row S1 in the column D1 including the pixel G11 is corrected by the drive pulse width correction signal, and the pulse width is 1.25 times longer than the other pixels (the reciprocal of 0.8). Controlled to be. Similarly, the pixel of G23 is also controlled to be 2 (reciprocal of 0.5) times longer. Although the case where the brightness of a certain pixel is low has been described in this case, the case where the brightness of a certain pixel is higher than that of another pixel may be considered. In this case, control is performed so that the drive pulse width is shortened.

By correcting the drive pulse width in this way, it is possible to increase the amount of electric charge reaching the anode for the pixels of G11 and G23 whose brightness has decreased due to the small amount of current in the FED panel, and the same image is displayed. It is possible to display with brightness.

[0027]

As described above, according to the present invention, even if the characteristics of each pixel are different due to a minute environmental change in the process or the like, by correcting the pulse of the data driver, the variation in the current of each pixel is reduced. It is possible to correct the variation in the brightness caused by it.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of a drive device for a field emission display according to a first embodiment of the present invention.

FIG. 2 is an operation explanatory diagram according to the first embodiment of the present invention.

FIG. 3 is a block configuration diagram of a field emission display driving device according to a second embodiment of the present invention.

FIG. 4 is an operation explanatory diagram according to the second embodiment of the present invention.

FIG. 5 is a configuration diagram of a drive circuit in a conventional field emission display.

FIG. 6 is an operation timing chart of a drive circuit in a conventional field emission display.

[Explanation of symbols]

1 video signal 2 sync signal 3 Data conversion circuit 4 scan driver 5 memory elements 6 Drive voltage control circuit 7 Data driver 8 Drive pulse width control circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G09G 3/20 642 G09G 3/20 642A H04N 5/68 H04N 5/68 B

Claims (3)

[Claims] 1. Driving a field emission display having an emitter for emitting electrons and a gate for controlling the emission of electrons from the emitter, and comprising a field emission element driven via a data driver according to display data. In the method, the brightness characteristic of each pixel of the field emission device is stored in advance in a memory device, and the output of a data driver for driving the field emission device is
A method for driving a field emission display, characterized in that correction is made for each pixel based on the brightness characteristics stored in advance. 2. A field emission device having an emitter for emitting electrons and a gate for controlling the emission of electrons from the emitter, and driven through a data driver expressing brightness by pulse width modulation according to display data. In a field emission display driving device, a memory device storing the luminance characteristic of each pixel of the field emission device and an output from the memory device are input, and a voltage control signal of the data driver is output for each pixel. And a drive voltage control circuit for driving the field emission device, wherein the output of the data driver for driving the field emission device is corrected for each pixel based on the luminance characteristics stored in the memory device. apparatus. 3. A field emission device having an emitter for emitting electrons and a gate for controlling emission of electrons from the emitter, and driven through a data driver expressing brightness by pulse amplitude modulation according to display data. In the field emission display driving device, a memory element storing the luminance characteristic of each pixel of the field emission element, and a pulse width control signal of the data driver for each pixel using the output from the memory element as an input. And a drive pulse width control circuit for outputting, wherein the output of the data driver for driving the field emission device is corrected for each pixel based on the luminance characteristics stored in the memory device. Drive.