JP4096441B2 - Drive circuit for matrix display device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a driving circuit for a matrix type display device such as a display device using an electron emission source such as a cold cathode electron-emitting device (so-called field emission display device) or an electroluminescence (hereinafter abbreviated as EL) display device. .
[0002]
[Prior art]
As a matrix type display device, a one-row simultaneous display type display device such as a field emission display device or an EL display device using a cold cathode electron-emitting device is known. In the display device of the one-line simultaneous display type, display is performed simultaneously in units of one row, and generally line sequential scanning is performed from top to bottom, and display of each row is performed simultaneously for all the columns during the scanning period.
[0003]
More specifically, the one-line simultaneous display type is a display device that does not display other lines when an arbitrary line is displayed. For example, a plasma display panel, a TFT liquid crystal display device, and the like perform line-sequential driving, but this is not in this category because each cell has a memory function and a plurality of lines are displayed simultaneously. However, in the case where the display device is completely divided into a plurality of wiring blocks, if there is no simultaneous display period of a plurality of rows in each block, the display device is a one-row simultaneous display type.
[0004]
FIG. 4 is a block diagram showing a driving circuit of a matrix type display device which is a conventional one-row simultaneous display type. In FIG. 4, a display panel 10 is a display panel using, for example, a cold cathode electron-emitting device. As shown in FIG. 5, as an example, a plurality of row wirings connected to scan electrodes L1 to LM and data electrodes D1 to D1. The cells 10s constituting the pixels are arranged in a matrix by a plurality of column wirings connected to the DN. Note that the cell 10s includes an electron-emitting device that is an electron-emitting source and a phosphor that receives electron irradiation from the electron-emitting device.
[0005]
The video signal input to the terminal 1 is written to the shift register 2. After one row of data is written in the shift register 2, the data is latched by the latch circuit 3 and the data is input to the modulation circuit 4. The modulation circuit 4 inputs pulses corresponding to the magnitude of data to the data electrodes D1 to DN of the display panel 10.
[0006]
Further, the synchronization signal input to the terminal 7 is input to the timing control circuit 8. The timing control circuit 8 supplies a shift clock to the shift register 2 and supplies a latch clock to the latch circuit 3. The timing control circuit 8 also supplies a pulse of 1 line width to the shift register 9. The shift register 9 sequentially inputs the pulses to the scan electrodes L1 to LM of the display panel 10 as scan pulses from the first row.
[0007]
Further, the operation when the matrix type display device shown in FIG. 4 is driven will be described in detail. As described above, the scan pulse is sequentially applied to the scan electrodes L <b> 1 to LM of the display panel 10 by the shift register 9. Further, a pulse width (PWM) -modulated pulse is applied to the data electrodes D1 to DN of the display panel 10 by the modulation circuit 4 as an example according to the data corresponding to the selected line.
[0008]
That is, for the data of i rows and j columns, a voltage is applied to the data electrode Dj during the period when the scan electrode Li is selected. When the modulation circuit 4 is PWM modulation, the gradation is expressed by the application time (pulse width) of the pulse applied to the data electrodes D1 to DN. The modulation method of the modulation circuit 4 is not limited to the PWM method, and any method that can express the intensity of light emission such as voltage modulation may be used.
[0009]
FIG. 6 is a waveform diagram showing an operation when displaying the j column as an example, and shows a scan pulse applied to the scan electrode and a pulse applied to the data electrode. Here, a case is shown in which the video signal is black in i row and j column, gray in i + 1 row and j column, and white in i + 2 row and j column.
As shown in FIG. 6, in the horizontal scanning period H0 of i row, the voltage -Vs is applied to the scanning electrode Li of i row, and no voltage is applied to the other scanning electrodes. At this time, since the display in the i row and the j column is black, the data electrode Dj in the j column is always at 0 potential.
[0010]
Next, in the horizontal scanning period H1 of the i + 1th row, the voltage −Vs is applied to the scanning electrode L (i + 1) of the i + 1th row, and no voltage is applied to the other scanning electrodes. At this time, since the display in i + 1 row and j column is gray, the voltage + Vd is applied to the data electrode Dj in the j column for about a half period of the horizontal scanning period H1, and becomes 0 potential in the subsequent half period. . Further, in the horizontal scanning period H2 of i + 2 row, the voltage −Vs is applied to the scanning electrode L (i + 2) of i + 2 row, and no voltage is applied to the other scanning electrodes. At this time, since the display in i + 2 rows and j columns is white, the voltage + Vd is applied to the data electrodes Dj in the j columns throughout the horizontal scanning period H2.
[0011]
By the way, in the case of the display panel 10 using the cold cathode electron-emitting device, the electron-emitting device has a threshold value for emitting electrons. The difference between the voltage applied to the scan electrodes L1 to LM and the voltage applied to the data electrodes D1 to DN becomes the display state when the threshold value is exceeded or less, and the display state is made less than that.
In this example, both the voltage Vd and the voltage Vs are set lower than the threshold value Vth, and the voltage (Vd + Vs) is set higher than the threshold value Vth. That is, light emission does not occur when only one of the data electrodes D1 to DN and the scanning electrodes L1 to LM is applied, and light is emitted only when applied to both.
[0012]
Here, only the display process from the i-th row to the i + 2-th row has been described, but actually, scan pulses are sequentially applied to the scan electrodes L1 to LM of the display panel 10 from the 1st row to the M-th row. In synchronization with the scanning timing, a PWM modulated pulse is applied to the data electrodes D1 to DN.
Note that there are 480 scanning electrodes and 640 data electrodes in the case of display of 480 rows × 640 columns of effective pixels, and 1920 data electrodes in the case of color display with an RGB stripe structure.
[0013]
With the configuration and operation as described above, the display timing of each row in one field is as shown in FIG. In this case, the scanning electrodes are 480 rows, and the thick solid line portion is the display period. As shown in FIG. 7, display is sequentially performed from the first line to the 480th line within one field.
[0014]
[Problems to be solved by the invention]
In the one-row simultaneous display type matrix display device described above, display concentrates only in one horizontal scanning period in one field in each row. For this reason, due to continuous electron emission, a change with time (burn-in) occurs in the electron-emitting device and the phosphor (that is, the cell 10s).
Also, due to the phosphor saturation phenomenon, the pulse width (light emission time) and the luminance (light emission intensity) are not proportional to each other, and as shown in FIG. Arise. If the pulse width is x and the emission intensity is y, the characteristic shown in FIG. 11 can be expressed as y = x ^r , where 0 <r <1 and usually 0.7 <r <0.9. is there.
[0015]
The light emission of the phosphor is such that when the electrons existing in the phosphor are excited to a higher level by irradiation with an electron beam and then return to the original level, the energy of the difference is emitted as visible light. If electrons are irradiated one after another before the excited state of the phosphor is recovered, the ratio of the visible light emission to the amount of irradiated electrons decreases. This is called phosphor saturation. The fact that the phosphor has a gamma characteristic as shown in FIG. 8 due to the saturation phenomenon means that the luminance does not double even if the pulse width is doubled. The decrease in brightness was a problem.
[0016]
Furthermore, even if phosphor saturation does not occur, the display time is one horizontal scanning period. Therefore, if the number of pixels increases due to the increase in definition, the display time is shortened and the luminance is reduced. As described above, the conventional matrix type display device has a problem in that the maximum luminance is limited by the display time, and thus the luminance (peak luminance) equal to or higher than that of the cathode ray tube display device cannot be obtained.
[0017]
The present invention has been made in view of such problems, and an object of the present invention is to provide a drive circuit for a matrix display device capable of greatly improving peak luminance.
[0018]
[Means for Solving the Problems]
In order to solve the above-described problems of the related art, the present invention provides cells arranged in a matrix by a plurality of horizontal rows and a plurality of vertical columns, and the cells do not have a memory function. In a drive circuit of a matrix type display device that displays a video signal by scanning a display panel represented by the application time of a pulse applied to the data electrode in units of rows, the display panel is arranged in each column of the display panel. Detection means (5, 11) for detecting whether data of at least two rows of video signal data to be supplied has a common gradation and a white peak, and a common gradation and white by the detection means. When it is not detected that the peak is detected, the video signal data is scanned in units of one line. Matrix display device characterized in that it comprises the data of the video signal, means for scanning along a plurality of rows is detected that is white peak is a common tone within one horizontal scanning period and (6) The drive circuit is provided.
[0019]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a driving circuit of a matrix display device of the present invention will be described with reference to the accompanying drawings. FIG. 1 is a block diagram showing an embodiment of a drive circuit for a matrix type display device according to the present invention, FIG. 2 is a waveform diagram for explaining the operation of the drive circuit for the matrix type display device according to the present invention, and FIG. It is a figure for demonstrating operation | movement of the drive circuit of this matrix type display apparatus. In FIG. 1, the same parts as those in FIG. 4 are denoted by the same reference numerals.
[0020]
In FIG. 1, a display panel 10 is a display panel using, for example, a cold cathode electron-emitting device, and its specific configuration is as described with reference to FIG. The video signal input to the terminal 1 is written to the shift register 2. After one row of data is written in the shift register 2, the data is latched by the latch circuit 3. The data output from the latch circuit 3 is input to the correlation detection circuit 5 and the white peak detection circuit 11 newly added according to the present invention.
[0021]
The correlation detection circuit 5 includes one or a plurality of line memories and a comparison circuit, and detects a correlation in the row direction in each column of data output from the latch circuit 3. If one line memory is provided and two rows of data are compared by the comparison circuit, the correlation between the data of the two rows can be detected. If two or more line memories are provided, data of three rows or more can be detected. Correlation can be detected. A correlation detection signal from the correlation detection circuit 5 is input to one terminal of the AND circuit 12.
[0022]
The white peak detection circuit 11 detects a portion having a predetermined luminance level or higher based on the data output from the latch circuit 3. In this embodiment, as an example, a white peak is detected. A white peak detection signal from the white peak detection circuit 11 is input to the other terminal of the AND circuit 12. Only when the correlation detection signal is input from the correlation detection circuit 5 and the white peak detection signal is input from the white peak detection circuit 11, the AND circuit 12 is newly added to the scan multiphase circuit 6 according to the present invention. The white peak correlation detection signal is input to.
[0023]
Data output from the latch circuit 3 is input to the modulation circuit 4 through the correlation detection circuit 5. The modulation circuit 4 inputs, for example, PWM-modulated pulses to the data electrodes D <b> 1 to DN of the display panel 10 according to the data size.
[0024]
Further, the synchronization signal input to the terminal 7 is input to the timing control circuit 8. The timing control circuit 8 supplies a shift clock to the shift register 2 and supplies a latch clock to the latch circuit 3. The timing control circuit 8 also supplies a pulse of 1 line width to the shift register 9. The shift register 9 inputs the pulse to the scan multiphase circuit 6. The timing control circuit 8 also controls the timing of the correlation detection circuit 5 and the white peak detection circuit 11. The scan multiphase circuit 6 multiphases the input pulse as described later, and inputs the pulse to the scan electrodes L1 to LM of the display panel 10 as a scan pulse.
[0025]
Here, the operation of the drive circuit shown in FIG. 1 will be described in detail with reference to FIG. The operation example of FIG. 2 shows the operation when the video signal is in the state shown in FIG. In the example of FIG. 3, the X and X + 1 columns i row to i + 2 row are correlated with the white peak, and the X + 2 column to X + n column i row to i + 2 row are correlated, but gray, and the X column to The i + 3 row of the X + n column shows the case of black.
[0026]
In the i row to i + 2 row of the X column and the X + 1 column, the correlation detection circuit 5 detects that there is a correlation, and the white peak detection circuit 11 detects that there is a white peak. , The white peak correlation detection signal is supplied to the scan multiphase circuit 6 only during the period from i row to i + 2 row. The scan multiphase circuit 6 multiphases the row to be scanned in the period when the white peak correlation detection signal is supplied from the AND circuit 12.
[0027]
As shown in FIG. 2, when the shift register 9 outputs a scan pulse from the i-th terminal in the i-th horizontal scanning period H0, all data on the i-th row are simultaneously output from the latch circuit 3. Yes. A voltage −Vs is applied to the i-th scanning electrode Li. At this time, since the X and X + 1 columns are white, the voltage + Vd is applied to the data electrodes DX and D (X + 1) in the X and X + 1 columns throughout the horizontal scanning period H0. Since the X + 2 column to the X + n column are gray, the voltage + Vd is applied to the data electrodes D (X + 2) to D (X + n) of the X + 2 column to the X + n column for only about half of the horizontal scanning period H0, and about half of the voltage thereafter. The period is 0 potential.
[0028]
In the horizontal scanning period H0 of i rows, other rows are not conventionally scanned, but in the present invention, it is detected that there is a correlation between white peaks in i rows to i + 2 rows. The circuit 6 applies the voltage −Vs to the scan electrode L (i + 1) in the i + 1 row and the scan electrode L (i + 2) in the i + 2 row, for example, only for the half period H0b of the second half of the horizontal scan period H0. Therefore, in the i + 1th row to the i + 2th row, white light is emitted in the period H0b.
[0029]
Further, in the horizontal scanning period H1 of the i + 1th row, when the shift register 9 outputs a scan pulse from the i + 1th terminal, all data in the i + 1th row are simultaneously output from the latch circuit 3. The voltage −Vs is applied to the scanning electrode L (i + 1) in the i + 1th row. At this time, since the X and X + 1 columns are white, the voltage + Vd is applied to the data electrodes DX and D (X + 1) of the X and X + 1 columns throughout the horizontal scanning period H1. Since the X + 2 column to the X + n column are gray, the voltage + Vd is applied to the data electrodes D (X + 2) to D (X + n) of the X + 2 column to the X + n column for only about half of the horizontal scanning period H1, and about half of the subsequent time. The period is 0 potential.
[0030]
Even horizontal scanning interval H1 smell of the row i + 1, since in the i-th row through i + 2 row has been detected that there is a correlation with the white peak, the scan multiphase circuit 6, i scanning electrodes Li and i + 2 row lines In addition, the voltage −Vs is applied to the scanning electrode L (i + 2) of only the half period H1b of the latter half of the horizontal scanning period H1. Therefore, in the i row and the i + 2 row, white light is emitted in the period H1b.
[0031]
Then, similarly to the horizontal scanning period H2 smell i + 2 row by scan multiphase circuit 6, and also to the i-th row of scan electrodes Li and i + 1 row of scan electrodes L (i + 1), the horizontal scanning interval H1 late The voltage −Vs is applied for a period H2b that is approximately half of the period. Therefore, in the i row and the i + 1 row, white light is emitted in the period H2b. In this embodiment, when a certain row is scanned, when the other rows correlated with the white peak are simultaneously emitted, the light is emitted only for about half of the horizontal scanning period. You may make it longer or shorter.
[0032]
As described above, according to the drive circuit of the present invention, the display panel 10 displays a plurality of correlated rows at the white peak in the same horizontal scanning period. Since a plurality of lines emit light together, when 100% white is displayed (255 data in 8-bit representation), the width of the scan pulse applied to the data for one pixel greatly increases. In the example of FIG. 2, H0 + H1b + H2b in the i-th row, H0b + H1 + H2b in the i + 1-th row, and H0b + H1b + H2 in the i + 2-th row, so that a current can be supplied to the cell 10s for about 2 horizontal scanning periods, which is about twice the conventional. In gray and black, which are not white peaks, the scanning is the same as the conventional one, and the luminance is exactly the same as the conventional one.
[0033]
In the present embodiment, since light is emitted only for about half of the latter half of the horizontal scanning period with respect to other rows correlated with the white peak, in general, all of the horizontal scanning period in one cell 10s. It is possible to prevent light from being emitted continuously, and to provide a pause period (non-display period) that is approximately half of the horizontal scanning period between the light emission in one horizontal scanning period and the light emission in the next horizontal scanning period. Therefore, the excitation state of the phosphor is settled by the rest in the non-display period and is restored to the initial state, so that it is possible to prevent a decrease in luminance due to phosphor saturation. In addition, by providing a pause period that is approximately half the horizontal scanning period, it is possible to have a gamma correction effect.
[0034]
【The invention's effect】
As described above in detail, the drive circuit of the matrix display device of the present invention has at least two rows of video signal data supplied to the display panel in a common gradation in each column of the display panel. The detection means for detecting whether or not there is a white peak, and when the detection means does not detect that the white peak is a common gradation, the video signal data is scanned and detected in units of one line. When it is detected by the means that the common gradation and white peak are detected, the video signal data is divided into a plurality of lines having the common gradation and detected white peak within one horizontal scanning period. And the means for scanning together , the luminance can be compensated for even if the luminance is lowered due to phosphor saturation, and the peak luminance can be greatly improved.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an embodiment of the present invention.
FIG. 2 is a waveform diagram for explaining the operation of the present invention.
FIG. 3 is a diagram for explaining the operation of the present invention.
FIG. 4 is a block diagram showing a conventional example.
FIG. 5 is a diagram showing a configuration of a display panel of a matrix display device.
FIG. 6 is a waveform diagram for explaining the operation of a conventional example.
FIG. 7 is a diagram for explaining display timing according to a conventional example.
FIG. 8 is a diagram showing a relationship between pulse width and light emission intensity according to a conventional example.
[Explanation of symbols]
1 and 7 Terminals 2 and 9 Shift register 3 Latch circuit 4 Modulation circuit 5 Correlation detection circuit 6 Scan multiphase circuit 8 Timing control circuit 10 Display panel 11 White peak detection circuit (luminance detection circuit)
12 AND circuit

Claims (2)

A display in which cells are arranged in a matrix by a plurality of horizontal rows and a plurality of vertical columns, the cells do not have a memory function, and gradation is expressed by the pulse application time applied to the data electrode In a drive circuit of a matrix type display device that displays a video signal by scanning a panel in a row unit,
Detecting means for detecting whether data of at least two rows of video signal data supplied to the display panel in each column of the display panel has a common gradation and a white peak ;
When the detection means does not detect a common gradation and white peak, the video signal data is scanned in units of one line, and the detection means has a common gradation and white peak. If it is detected, the data of the video signal, and means for scanning along a plurality of rows is detected that a white peak is a common tone within one horizontal scanning period
Driving circuit of a matrix type display apparatus comprising: a.   2. The drive circuit for a matrix display device according to claim 1, wherein the matrix display device is a field emission display device or an electroluminescence display device.

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