JP2003158240A - Memory mounting system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory mounting system which can make the route connecting a memory controller and a memory chip to each other ideal and can radiate the heat which increases as the operating speed of the memory chip or memory controller increases and in which the number of memories can be increased easily. SOLUTION: This memory mounting system has connecting terminals on the bottom face of a package, relay terminals on the top face of the package, and a grounding terminal coaxially surrounding the connecting and relay terminals. The number of memories can be increased by piling up packages.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an L such as a memory.
The present invention relates to an SI package mounting method.

[0002]

2. Description of the Related Art FIG. 10 shows, for example, JEDEC Stan.
dard No. FIG. 21 is a diagram showing a conventional memory mounting method shown in FIG. 21-C. In the figure, 10 is a main substrate, and 11
Is a memory controller LSI mounted on the main board 10,
12 is a memory module socket mounted on the main board 10 and provided with terminals for electrically connecting signals, 13 is a memory chip (memory package), and 14 is physically fixed to the main board 10 by the memory module socket 12. ,
A memory module substrate on which the memory chip 13 is mounted, 1
Reference numeral 5 is a wiring for connecting the memory controller LSI 11 and each memory module socket 12.

A memory chip 13 is mounted on a memory module substrate 14, and a memory module substrate 1 is mounted on a main substrate 10.
4 is physically fixed, and a memory module socket 12 having terminals for electrically connecting respective signals is mounted. Further, the main board 10 has a memory controller LSI
11 is mounted, and a wiring 15 for connecting the memory controller LSI 11 and each memory module socket 12 is laid.

Next, the operation will be described. When accessing the memory chip 13 from the memory controller LSI 11, signals from the memory controller LSI 11 are transmitted to the wiring 15 of the main board 10, the memory module socket 12,
It is transmitted to the memory chip 13 via the wiring (not shown) of the memory module substrate 14. Further, the signal from the memory chip 13 to the memory controller LSI 11 is transmitted in the opposite direction on the same path.

[0005]

According to the conventional memory mounting method, the memory controller LSI 11 and the memory chip 13 are used.
The path connecting the two is composed of a plurality of different media, and the distance is physically long.

FIG. 11 is a diagram showing a signal path in the conventional memory mounting method. In the figure, 16 is a memory controller LSI transmission buffer, 17 is a memory controller LSI reception buffer, 18 is wiring on a main board, 19 is wiring in a socket, 20 is wiring on a memory module board, 2
Reference numeral 1 is a memory transmission buffer, and 22 is a memory reception buffer.

For high-speed signals, a transmission line with uniform characteristic impedance and as short a length as possible is ideal. However, in the conventional memory mounting method, the connection is made to the memory module substrate 14 via a plurality of memory module sockets 12. Due to branching or the like, the impedance of the transmission path is not uniform, and the path itself is affected by the physical size of the memory module board 14, and in particular, the wiring 18 on the main board becomes long, so that the signal waveform is distorted. It is easy to occur.

FIG. 12 is a diagram showing an example of waveform distortion at point A shown in FIG. 11. Originally, FIG. 12 (a) is an ideal waveform, but FIG. There is a problem that the waveform becomes distorted as shown in (b), normal communication cannot be performed, and the speeding up of the signal is hindered.

As a result, in order to shorten the wiring 15, the number of mounted memory module sockets 12 is, for example, two.
There was a problem that the expansion capacity of the memory would be limited, because there was no choice but to take measures such as limiting the number to one.

Further, when the signal speed is increased, a radiator is required for each memory chip 13 or memory module substrate 14, but a large number of heat sinks are required, resulting in an increase in cost and mounting of heat sinks. Therefore, it is necessary to widen the mounting interval of the memory module sockets 12, which causes a problem of increasing waveform distortion.

The present invention has been made to solve the above-mentioned problems, and provides a system in which a path connecting a memory controller and a memory chip is in an ideal state, and a memory which increases with speeding up is provided. It is an object of the present invention to provide a method for radiating heat from a chip or a memory controller, and an easy addition / modification method for memory.

[0012]

According to another aspect of the present invention, there is provided a memory mounting system having a connection terminal on a lower surface of a package, a relay terminal on an upper surface of the package, and a ground terminal coaxially surrounding the connection terminal and the relay terminal. It is characterized by adding packages by stacking them.

The memory mounting method according to the present invention is
A feature of the present invention is that the signal connection between the memory packages is a bus connection.

The memory mounting method according to the present invention is
The bus connection is characterized in that the connection terminal and the relay terminal are used.

The memory mounting method according to the present invention is
It has connection terminals on the bottom surface of the package and relay terminals on the top surface of the package, and it is added by stacking the packages. It is characterized by incorporating a relay circuit to the next stage.

The memory mounting method according to the present invention is
In the signal connection between each memory package, only the opposing memory packages are directly connected and the relay circuit to the next stage is built in the memory chip. It is characterized by having a terminal.

The memory mounting method according to the present invention is
It is characterized in that the ground terminal is provided with a slit-shaped opening, and the wiring in the package is connected through the opening.

The memory mounting method according to the present invention is
The grounding terminal is connected to the grounding conductor in the package, is exposed on the upper surface and the lower surface of the package, and is connected between the upper and lower sides when the packages are stacked.

The memory mounting method according to the present invention is
The connection terminal is provided on the lower surface, the relay terminal is provided so as to protrude to the upper surface, and the connection terminal and the relay terminal are directly connected.

The memory mounting method according to the present invention is
It is characterized in that heat is radiated to the ground layer of the substrate through the ground conductor in the package and the ground terminal coaxially surrounding the connection terminal and the relay terminal.

The memory mounting method according to the present invention is
It is characterized in that the ground conductor has a radiator.

The memory mounting method according to the present invention is
The radiator part is also connected when the packages are stacked.

The memory mounting method according to the present invention is
It is characterized in that the connection to the ground layer of the substrate is omitted depending on the amount of heat generated.

The memory mounting method according to the present invention is
It is characterized in that a dedicated radiator is connected to the ground terminal exposed on the top surface of the stacked memory packages to radiate heat.

The memory mounting method according to the present invention is
The connection terminal is made of a flexible conductor.

The memory mounting method according to the present invention is
The connection terminal and the relay terminal are connected to each other in the form of a plug-in connector.

The memory mounting method according to the present invention is
It is characterized in that the ground terminals are connected to each other in the form of a plug-in connector.

[0028]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. Embodiment 1. 1 to 3 are diagrams showing the first embodiment, FIG. 1 is a configuration diagram showing a memory mounting method, FIG. 2 is a diagram showing details of a relay terminal, a connection terminal and a ground terminal, and FIG. 3 is a memory controller LSI and each It is a figure which shows the connection with a memory.

In FIG. 1, 30 is a memory controller LSI, 31 is a memory controller built-in chip, 32 is package wiring, 33 is a substrate, 34-1 to 34-n are memories, 35 is a relay terminal, 36 is a package, and 37. Is a connection terminal, 38 is a memory chip, 42 is a ground conductor in the package 36, and 40 is a ground terminal that coaxially surrounds the relay terminal 35 and the connection terminal 37.

As shown in FIG. 2, a slit-shaped gap is provided in the ground terminal 40, and the wiring 3 in the package is opened from this gap.
Connect two.

The memory controller LSI 3 is provided on the substrate 33.
0 is mounted, and the memories 34-1 to 34-n are stacked and mounted thereon. The package 36 of the memory controller LSI 30 and the memories 34-1 to 34-n has the connection terminal 37 on the lower surface and the relay terminal 35 projects on the upper surface, so that the connection terminal 37 and the relay terminal 35 are directly connected.

The memory controller built-in chip 31 and the memory chip 38 in the package 36 are connected to the connection terminal 37 or the relay terminal 35 by the package wiring 32 to exchange signals.

The opposing packages 36 are electrically connected by bringing the relay terminal 35 of the lower package 36 and the connection terminal 37 of the upper package 36 into contact with each other.

The ground terminal 40 is connected to the ground conductor 42 in the package 36 and is exposed on the upper and lower surfaces of the package, and when the packages are stacked,
The top and bottom are connected.

As shown in FIG. 3, the memory controller L
The SI 30 and the memories 34-1 to 34-n are connected to the bus wiring 5
Connected at 0. In FIG. 1, the bus wiring 50 is composed of a connection terminal 37 and a relay terminal 35.

As described above, the connection terminal 37 and the relay terminal 35 having very short physical dimensions are used to connect a plurality of packages, and the ground terminal 40.
Since the characteristic impedance is controlled in an ideal state by the memory controller LSI 30 and the memory 34-1.
Even if the speed of the signal between ~ 34-n is increased, the distortion of the signal waveform can be prevented, and stable speedup can be achieved.

Further, the wiring 3 in the package of the ground terminal 40
Since the opening for connecting 2 is not formed as a slit-like hole, the variation in impedance generated by passing the wiring in the package is minimized.

Embodiment 2. 4 and 5 are diagrams showing the second embodiment, FIG. 4 is a configuration diagram showing a memory mounting method, and FIG. 5 is a diagram showing a connection between a memory controller LSI and each memory. FIG. 4 is a diagram showing a modified example of the first embodiment, in which the relay terminal 35 and the connection terminal 37 are not directly connected to each other, and the relay circuit 39 in the memory chip 38 is interposed, and the ground terminal. The difference from the first embodiment is that there is no 40.

As shown in FIG. 5, the opposing package 3
Only 6 are directly connected. A relay circuit 39 is provided in the memory chip 38.

Next, the operation will be described. Immediately after the power is turned on, an initialization operation for determining the configuration of the memories 34-1 to 34-n is performed. From the memory controller LSI 30,
The ID1 confirmation signal is transmitted to the opposing memory # 1 (34-1). The memory # 1 (34-1) registers its own ID as 1, and stores the ID in the opposite memory # 2 (34-2).
2 Send a confirmation signal. The memory # 2 (34-2) registers its own ID as 2, and similarly transmits an ID3 confirmation signal to the memory # 3 (34-2) (not shown) facing the other side,
After that, the same operation is repeated. The memory #n (34-n) transmits the IDn + 1 confirmation signal to the relay terminal, but since the memory is not mounted thereafter, after waiting for a certain time, the ID registration of all the memories is completed and the final ID is n. No. is transmitted to the connection terminal side.

The memory # n-1 (34-n-1) (not shown) in the preceding stage, which has received this signal, further notifies this notification to the preceding stage, and thereafter this relay operation is performed in the memory # 1 (34-1).
Until the memory controller LSI30
Receives this signal. Memory controller LSI30
Stores that the number of connected memories is up to n. After that, the normal memory access operation is
Use a number to identify a device.

With the above configuration, the signal path connecting the memory controller LSI 30 and the memories 34-1 to 34-n and the memories 34-1 to 34-n has only one set of relay terminals and connection terminals. Since the change in the impedance of the signal path due to the memory expansion is minimized and the waveform is extremely unlikely to be distorted, it is possible to easily realize high-speed signals and increase the capacity by adding memory. be able to.

Embodiment 3. FIG. 6 is a diagram showing the third embodiment and is a configuration diagram showing a memory mounting method. FIG. 6 is a diagram showing a modified example of the second embodiment, which is different in that a ground terminal 40 that coaxially covers the relay terminal 35 and the connection terminal 37 is added.

The relay terminal 35 and the connection terminal 3 which are signal paths
By covering 7 with the ground terminal 40 to form a coaxial line structure, impedance control is facilitated, and signal speed can be more easily realized.

Fourth Embodiment The ground conductor 42 and the ground terminal 40 shown in the first and third embodiments are used as a heat conduction path for heat dissipation.

The heat generated in the memory chip 38 and the LSI with built-in memory controller 31 is transferred from the ground conductor 42 in each package 36 to the ground plane 43 of the substrate 33 via the ground terminal 40 and is radiated.

Since there is no problem that the signal path is lengthened due to the heat radiation measure, it is possible to achieve both high speed and high temperature heat dissipation. Further, since the ground terminal 40 for impedance control is used, it can be realized at low cost.

Embodiment 5. FIG. 7 is a diagram showing the fifth embodiment and is a configuration diagram showing a memory mounting method. FIG. 7 is a diagram showing a modification of the fourth embodiment, in which 41 is a radiator. A dedicated radiator 41 is connected to the ground terminal 40 exposed on the uppermost surface of the stacked memory packages 36 to radiate heat.

The heat generated in the memory chip 38 and the LSI with built-in memory controller 31 is transferred from the ground conductor 42 in each package 36 to the radiator 41 and the ground plane 43 in the substrate 33 through the ground terminal 40 and is radiated.

Since there is no problem of lengthening the signal path associated with heat dissipation measures, it is possible to achieve both high speed and high speed heat dissipation. In addition, depending on the amount of heat generated, the radiator 4
It is also possible to omit 1 and radiate heat only from the ground plane 43.

Sixth Embodiment FIG. 8 shows the sixth embodiment and is a configuration diagram showing a memory mounting method. FIG. 8 is a diagram showing a modification of the fifth embodiment. As shown in the figure, the ground conductor 42 is provided with a radiator, and this radiator is also connected when the packages 36 are stacked.

Since the ground conductor 42 itself can dissipate heat, the radiator 41 shown in the fifth embodiment is unnecessary. Although FIG. 8 also shows the connection to the ground plane 43, this may be omitted depending on the amount of heat generated.

On the contrary, the radiator 41 can be mounted on the uppermost stage of the stacked packages 36 to improve the heat radiation efficiency.

The degree of freedom in heat radiation design is expanded, and an efficient heat radiation method can be realized.

Embodiment 7. In the above first to sixth embodiments, the connection terminal 37 is a conductor having flexibility.

With such a configuration, the contact between the relay terminal 35 and the connection terminal 37 is stabilized, and a memory mounting method that is resistant to vibration and the like can be realized.

Embodiment 8. FIG. 9 is a diagram showing the eighth embodiment, and is a diagram showing details of a relay terminal, a connection terminal, and a ground terminal. The connection terminal 37 and the relay terminal 35 are connected to each other in the form of a plug-in connector. Further, the ground terminal 40 shown in the first and third embodiments may be the same.

The stability of the electrical connection between the relay terminal 35 and the connection terminal 37 is improved. Further, since the ground terminal 40 also has the same structure, a more reliable coaxial line form can be realized, so that stable signal speed-up can be realized.

[0059]

As described above, according to the present invention, even if the speed of the signal between the memory controller LSI and the memory is increased, the signal waveform can be prevented from being distorted and the speed can be stably increased. In addition, it is possible to easily add memory. Further, the heat of the memory chip and the memory controller, which increases due to the increase in speed, can be efficiently radiated.

[Brief description of drawings]

FIG. 1 is a diagram showing a first embodiment and is a configuration diagram showing a memory mounting method.

FIG. 2 is a diagram showing the first embodiment and is a diagram showing details of a relay terminal, a connection terminal, and a ground terminal.

FIG. 3 is a diagram showing the first embodiment and is a diagram showing a connection between a memory controller LSI and each memory.

FIG. 4 is a diagram illustrating the second embodiment and is a configuration diagram illustrating a memory mounting method.

FIG. 5 is a diagram showing the second embodiment and is a diagram showing a connection between a memory controller LSI and each memory.

FIG. 6 is a diagram showing the third embodiment and is a configuration diagram showing a memory mounting method.

FIG. 7 shows the fifth embodiment and is a configuration diagram showing a memory mounting method.

FIG. 8 is a diagram showing the sixth embodiment and is a configuration diagram showing a memory mounting method;

FIG. 9 is a diagram showing the eighth embodiment and is a diagram showing details of a relay terminal, a connection terminal, and a ground terminal.

FIG. 10 is a diagram showing a conventional memory mounting method.

FIG. 11 is a diagram showing a signal path in a conventional memory mounting method.

12 is a diagram showing an example of waveform distortion at point A shown in FIG.

[Explanation of symbols]

30 memory controller LSI, 31 memory controller built-in chip, 32 package wiring, 33 substrate, 34-1 to 34-n memory, 35 relay terminal, 3
6 package, 37 connection terminal, 38 memory chip, 39 relay circuit, 40 ground terminal, 41 radiator,
42 ground conductors, 43 ground planes, 50 bus wiring.

Claims (16)

[Claims] 1. A memory characterized in that a connection terminal is provided on a lower surface of a package, a relay terminal is provided on an upper surface of the package, and a ground terminal coaxially surrounding the connection terminal and the relay terminal is provided. Implementation method. 2. The memory mounting method according to claim 1, wherein a signal connection form between the memory packages is a bus connection. 3. The memory mounting method according to claim 2, wherein the bus connection is performed at the connection terminal and the relay terminal. 4. A package has a connection terminal on the lower surface of the package and a relay terminal on the upper surface of the package, and is expanded by stacking the packages, and the signal connection form between each memory package is directly connected only between opposing memory packages, A memory mounting method that incorporates a relay circuit to the next stage in the memory chip. 5. The memory mounting method according to claim 4, further comprising a ground terminal that coaxially surrounds the connection terminal and the relay terminal. 6. The memory mounting method according to claim 1, wherein the ground terminal is provided with a slit-shaped opening, and the package wiring is connected from the opening. 7. The grounding terminal is connected to a grounding conductor in the package, is exposed on the upper surface and the lower surface of the package, and is connected between the upper and lower sides when the packages are stacked. Alternatively, the memory mounting method according to claim 5. 8. The connection terminal is provided on a lower surface and the relay terminal is projected to an upper surface, and the connection terminal and the relay terminal are directly connected to each other. Memory mounting method. 9. The memory package according to claim 1, wherein heat is radiated to the ground layer of the substrate through the ground conductor in the package and the ground terminal that coaxially surrounds the connection terminal and the relay terminal. method. 10. The memory mounting method according to claim 9, wherein the ground conductor has a radiator. 11. The memory mounting method according to claim 10, wherein the radiator parts are also connected when the packages are stacked. 12. The memory mounting method according to claim 10, wherein the connection to the ground layer of the substrate is omitted depending on the amount of heat generated. 13. The memory mounting method according to claim 9, wherein a dedicated radiator is connected to the ground terminal exposed on the upper surface of the uppermost stage of the stacked memory packages to radiate heat. 14. The memory mounting method according to claim 1, wherein the connection terminal is a conductor having flexibility. 15. The memory mounting method according to claim 1, wherein the connection terminal and the relay terminal are connected in a plug-in connector shape. 16. The memory mounting method according to claim 1, wherein the ground terminals are connected to each other in a plug-in connector shape.