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JP2003152141A - Ceramic heat dissipation circuit board - Google Patents

Ceramic heat dissipation circuit board

Info

Publication number
JP2003152141A
JP2003152141A JP2001350294A JP2001350294A JP2003152141A JP 2003152141 A JP2003152141 A JP 2003152141A JP 2001350294 A JP2001350294 A JP 2001350294A JP 2001350294 A JP2001350294 A JP 2001350294A JP 2003152141 A JP2003152141 A JP 2003152141A
Authority
JP
Japan
Prior art keywords
circuit board
heat dissipation
solder
bonding layer
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001350294A
Other languages
Japanese (ja)
Inventor
Noriyoshi Hirao
則好 平尾
Setsuo Ando
節夫 安藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Proterial Ltd
Original Assignee
Hitachi Metals Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Metals Ltd filed Critical Hitachi Metals Ltd
Priority to JP2001350294A priority Critical patent/JP2003152141A/en
Publication of JP2003152141A publication Critical patent/JP2003152141A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]

Landscapes

  • Ceramic Products (AREA)
  • Structure Of Printed Boards (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To improve solder wettability by preventing any solder flow and solder void from being formed upon a printed circuit board and a heat dissipation member being joined with a solder. SOLUTION: A ceramic heat dissipation circuit board is adapted such that it comprises a ceramic insulating board 2 to one side of which there is joined a Cu or Al circuit board 3 on which a semiconductor chip is mounted, and to the other side of which a Cu or Al plate 4 is joined, and a heat dissipation member 6 of an Al-SiC composite having an Al coating film 60 on the surface thereof, and a junction layer 64 is formed on the Al coating film of the heat dissipation member 6, and further the junction layer 64 and the Cu or Al plate 4 of the ceramic insulating substrate are joined with a solder 7. In the ceramic heat dissipation circuit board, the junction layer 64 is formed into a layer chiefly comprising Ni, and average surface roughness (Ra) of the surface 65 along a central line of the same is set to range from 0.2 to 1.5 μm with the thickness thereof set to range from 3 to 15 μm.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、主に炭化ケイ素
(SiC)からなる多孔体に、アルミニウム(Al)を
主成分とする金属を含浸して形成した炭化ケイ素とアル
ミニウムの複合体(Al−SiC複合体)と、窒化ケイ
素(Si34)、窒化アルミニウム(AlN)、酸化ア
ルミニウム(Al23)等のセラミックス絶縁基板とを
はんだを用いて接合したセラミックス放熱回路基板に関
するものである。
TECHNICAL FIELD The present invention relates to a composite of silicon carbide and aluminum (Al--, which is formed by impregnating a porous body mainly composed of silicon carbide (SiC) with a metal containing aluminum (Al) as a main component. The present invention relates to a ceramic heat dissipation circuit board in which a (SiC composite) and a ceramic insulating board made of silicon nitride (Si 3 N 4 ), aluminum nitride (AlN), aluminum oxide (Al 2 O 3 ) or the like are joined using solder. .

【0002】[0002]

【従来の技術】近年、産業機器の分野では、半導体スイ
ッチングデバイスを用いて大きな電力を最適な電力に効
率よく交換制御する大電力モジュール装置の開発が進ん
でいる。例えば、電動車輌用インバータとして高電圧、
大電流動作が可能な絶縁ゲート型バイポーラトランジス
タ(IGBT)モジュールがある。このような大電力モ
ジュール化に伴い、半導体チップから発生する熱も増大
している。半導体チップは熱に弱く、発熱が大きくなれ
ば半導体回路の誤動作や破壊を招くことになる。そこ
で、半導体チップなど電子部品を搭載するための回路基
板の裏面にヒートシンクなどの放熱部材を設けて、放熱
部品を介して半導体チップから発生した熱を外部に発散
させ、半導体回路の動作を安定にすることが行われてい
る。電子部品を搭載するための回路基板としては、窒化
ケイ素(Si34)、窒化アルミニウム(AlN)、酸
化アルミニウム(Al23)等のセラミックス絶縁基板
が主に用いられており、このセラミックス絶縁基板の表
面にCu板やAl板をろう材を介して接合して回路基板
となしている。
2. Description of the Related Art In recent years, in the field of industrial equipment, development of a high power module device for efficiently exchanging and controlling a large power to an optimum power by using a semiconductor switching device has been advanced. For example, high voltage as an inverter for electric vehicles,
There is an insulated gate bipolar transistor (IGBT) module capable of high current operation. The heat generated from the semiconductor chip is also increasing in accordance with such a high power module. The semiconductor chip is vulnerable to heat, and if the heat generation increases, malfunction or destruction of the semiconductor circuit will be caused. Therefore, a heat dissipation member such as a heat sink is provided on the back surface of the circuit board for mounting electronic components such as semiconductor chips, and the heat generated from the semiconductor chips is radiated to the outside via the heat dissipation components to stabilize the operation of the semiconductor circuit. Is being done. As a circuit board for mounting electronic parts, a ceramic insulating substrate such as silicon nitride (Si 3 N 4 ), aluminum nitride (AlN), aluminum oxide (Al 2 O 3 ) is mainly used. A Cu plate or an Al plate is joined to the surface of the insulating substrate via a brazing material to form a circuit board.

【0003】この種の回路基板として、良好な熱伝導性
を有する窒化アルミニウム(AlN)からなるセラミッ
クス絶縁基板上に銅(Cu)回路板を接合し、回路を形
成した後、めっきを施して半導体チップを実装したもの
がある。AlN基板とCu回路板との接合は、両者の間
に活性金属を含むろう材を介在させて加熱処理し接合す
る活性金属ろう付け法や、表面が酸化処理されたAlN
基板とCu回路板をCuの融点以下でCu−Oの共晶温
度以上で加熱接合するDBC(Direct BrazingCopper)
法等がある。このCu回路板を接合した基板では、Cu
回路とその表面にはんだでダイボンディングされたシリ
コン半導体チップとの熱膨張差が大きいため、回路の作
動中に繰り返し与えられる熱応力によりチップ直下では
んだにクラックが生じやすい。また、Cu回路板とAl
N基板の熱膨張差が大きいため、その接合部に剥離が生
じたり、AlNにクラックが発生する問題があった。
As a circuit board of this type, a copper (Cu) circuit board is bonded onto a ceramics insulating board made of aluminum nitride (AlN) having good thermal conductivity, a circuit is formed, and then plating is performed to form a semiconductor. Some have a chip mounted. The AlN substrate and the Cu circuit board are joined to each other by an active metal brazing method in which a brazing material containing an active metal is interposed between the AlN substrate and the Cu substrate to perform heat treatment, or AlN whose surface is oxidized.
DBC (Direct Brazing Copper) that heat-bonds the substrate and Cu circuit board below the melting point of Cu and above the eutectic temperature of Cu-O
There are laws etc. In the board to which this Cu circuit board is joined,
Since the difference in thermal expansion between the circuit and the silicon semiconductor chip die-bonded to the surface of the circuit by solder is large, the solder is likely to crack immediately below the chip due to thermal stress repeatedly applied during the operation of the circuit. Also, Cu circuit board and Al
Since the difference in thermal expansion of the N substrate is large, there are problems that peeling may occur at the joint portion and cracks may occur in AlN.

【0004】これに代わり、例えば、特開平10−65
296号ではSi34基板の両面にAl−Si系ろう材
を介してAl回路板を接合したセラミックス回路基板が
開示されている。回路板をCuに替えAlにしたAl回
路板では、Alの変形抵抗がCuより小さいため、回路
とAlNの接合部に働く応力を低く抑えることができ
る。また、シリコン半導体チップとのダイボンディング
部では、Alが塑性変形することにより回路表面の膨張
量がAlNのそれに近くなり、はんだに加わる応力を低
減できる。したがって、Al回路とAlN基板との接合
部が剥離しにくく接合信頼性の高いものが得られる。ま
た、Alの比重2.7g/cmはCuの比重8.9g/cmと比較
して約1/3程度のため回路基板の重量をこれまでの半
分以下に軽量化できるメリットもある。しかしその反
面、Alの比抵抗2.66×10−6ΩcmはCuの比抵抗1.67
×10−6Ωcmより約1.6倍大きく、高耐圧・大電流を
負荷することができず、電気容量の使用範囲に制約があ
るといった問題がある。このため高耐圧・大電流のパワ
ーモジュールに用いる場合には回路部の体積拡大が必要
となり、このため回路基板全体の厚みが増大し、モジュ
ールが大型化してしまう難点がある。以上のようにCu
板とAl板のどちらにしても一長一短があり、回路基板
として用いる際はその用途に合わせて選択することにな
る。
Instead of this, for example, Japanese Patent Laid-Open No. 10-65
No. 296 discloses a ceramics circuit board in which an Al circuit board is joined to both surfaces of a Si 3 N 4 board via an Al—Si brazing material. In the Al circuit board in which the circuit board is replaced with Cu and made of Al, the deformation resistance of Al is smaller than that of Cu, so that the stress acting on the joint between the circuit and AlN can be suppressed to a low level. Further, in the die bonding portion with the silicon semiconductor chip, the plastic deformation of Al causes the expansion amount of the circuit surface to be close to that of AlN, and the stress applied to the solder can be reduced. Therefore, the joint portion between the Al circuit and the AlN substrate is less likely to be peeled off, and the joint reliability is high. Further, since the specific gravity of Al is 2.7 g / cm 3 and is about 1/3 of the specific gravity of Cu which is 8.9 g / cm 3 , there is also an advantage that the weight of the circuit board can be reduced to less than half that of the conventional one. However, on the other hand, the specific resistance of Al is 2.66 × 10 −6 Ωcm and the specific resistance of Cu is 1.67.
It is about 1.6 times larger than × 10 -6 Ωcm, and cannot withstand high withstand voltage and large current, and there is a problem that the usage range of the electric capacity is limited. For this reason, when it is used in a power module with high withstand voltage and large current, it is necessary to enlarge the volume of the circuit portion, which increases the thickness of the entire circuit board and causes the module to be large. As described above, Cu
Both the plate and the Al plate have merits and demerits, and when used as a circuit board, they are selected according to the application.

【0005】他方、放熱部材としては、従来より銅、モ
リブデン、タングステン等の材料を用いたものがある。
しかしながら、モリブデンやタングステンからなる放熱
部品は高価であり、また金属の比重が大きいため放熱部
品の重量が重くなり好ましくない。また、銅あるいは銅
―モリブデン合金、銅―タングステン合金からなる放熱
部材は、セラミックス絶縁基板との熱膨張係数の差が大
きいため、放熱部材とセラミックス絶縁基板とを半田で
接合する際に、また、使用中の熱サイクルにより、半田
層の破壊、熱放散経路の遮断、セラミックス絶縁基板の
割れが生じやすい。そこで、上記の従来材に替わる放熱
部材として、AlまたはAl合金中にSiCを分散させ
た低熱膨張・高熱伝導特性を有するAl−SiC複合体
が注目されている(特公平7−26174号、特開昭6
4−83634号等参照)。Al−SiC複合体は、一
例としてSiC粉末あるいはSiC繊維で形成された多
孔体(プリフォーム)に窒素雰囲気中で加圧もしくは非
加圧で加熱溶融したAl又はAl合金を含浸させた溶融
金属含浸法により複合材としたものがある。これによれ
ば、SiCの含有量を20〜90体積%の範囲で選択
し、熱膨張係数を制御することができる。また、SiC
多孔体の形状の自由度が高く、複雑な形状の製品をニア
ネットシェイプ成形できる利点を有している。
On the other hand, as the heat radiating member, there is conventionally one using a material such as copper, molybdenum, or tungsten.
However, the heat dissipation component made of molybdenum or tungsten is expensive, and the specific gravity of the metal is large, so that the weight of the heat dissipation component becomes heavy, which is not preferable. Further, since the heat dissipation member made of copper or copper-molybdenum alloy, copper-tungsten alloy has a large difference in coefficient of thermal expansion from the ceramics insulating substrate, when the heat dissipation member and the ceramics insulating substrate are joined by soldering, Due to the thermal cycle during use, the solder layer is likely to be broken, the heat dissipation path is blocked, and the ceramic insulating substrate is cracked. Therefore, an Al-SiC composite having low thermal expansion and high thermal conductivity, in which SiC is dispersed in Al or Al alloy, has been attracting attention as a heat dissipation member replacing the above conventional material (Japanese Patent Publication No. 7-26174, Kaisho 6
4-83634 etc.). The Al-SiC composite is, for example, a molten metal impregnation obtained by impregnating a porous body (preform) formed of SiC powder or SiC fibers with Al or Al alloy that is heated and melted under pressure or without pressure in a nitrogen atmosphere. There is a composite material made by the method. According to this, the content of SiC can be selected in the range of 20 to 90% by volume and the thermal expansion coefficient can be controlled. In addition, SiC
The porous body has a high degree of freedom in the shape, and has an advantage that a product having a complicated shape can be molded by near net shape molding.

【0006】以上のことより、Si34、AlN、Al
23等からなるセラミックス絶縁基板にCu板やAl板
をろう材を介して接合した回路基板と、Al−SiC複
合体からなる放熱部材とを半田により接合したセラミッ
クス放熱回路基板が知られている。この様なセラミック
ス放熱回路基板の一例を図1に示す。セラミックス基板
2はAlN、AlまたはSi等からなる絶
縁基板である。セラミックス絶縁基板2の上面にはAg
−Cu−Ti系ろう材を用いてCu回路板3を、下面に
はCu板4がそれぞれ接合されている。尚、回路板3に
Alを用いた場合にはAl−Si系のろう材を用いてセ
ラミックス絶縁基板2と接合する。Cu回路板3の上面
には複数の半導体チップ5が半田により実装されワイヤ
ーで配線されている。一方、放熱部材6はAl−SiC
複合体からなり、表面にAlの皮膜を有している。この
Al皮膜上に半田濡れ性を持たせるために接合層を形成
し、半田7を介して上記Cu板4が接合されている。ま
た、放熱部材6の下面には高熱伝導性グリス等を介在し
て、例えば放熱フィンを有するヒートシンク8がボルト
10で締結されている。このようなセラミックス回路基
板1では、半導体チップ5等から発生した熱はCu回路
板3、セラミックス絶縁基板2、Cu板4、はんだ7、
および放熱基板6を経由してヒートシンク8の表面から
放散される。
From the above, Si 3 N 4 , AlN, Al
A ceramic heat dissipation circuit board is known in which a circuit board in which a Cu plate or an Al plate is joined to a ceramics insulating substrate made of 2 O 3 or the like via a brazing material and a heat dissipation member made of an Al-SiC composite are joined by soldering. There is. An example of such a ceramic heat dissipation circuit board is shown in FIG. The ceramic substrate 2 is an insulating substrate made of AlN, Al 2 O 3, Si 3 N 4, or the like. Ag is on the upper surface of the ceramics insulating substrate 2.
A Cu circuit board 3 and a Cu board 4 are joined to each other using a —Cu—Ti based brazing material. When Al is used for the circuit board 3, it is bonded to the ceramic insulating substrate 2 by using an Al-Si brazing material. A plurality of semiconductor chips 5 are mounted on the upper surface of the Cu circuit board 3 by solder and wired by wires. On the other hand, the heat dissipation member 6 is made of Al-SiC.
It is made of a composite and has an Al film on its surface. A bonding layer is formed on the Al film to have solder wettability, and the Cu plate 4 is bonded via the solder 7. In addition, a heat sink 8 having, for example, heat radiation fins is fastened with bolts 10 on the lower surface of the heat radiation member 6 with high thermal conductive grease or the like interposed. In such a ceramic circuit board 1, the heat generated from the semiconductor chip 5 or the like causes the Cu circuit board 3, the ceramics insulating substrate 2, the Cu plate 4, the solder 7,
And it is radiated from the surface of the heat sink 8 via the heat dissipation substrate 6.

【0007】[0007]

【発明が解決しようとする課題】さて、以上のセラミッ
クス放熱回路基板は、回路基板9(本発明ではセラミッ
クス絶縁基板2にCu回路板3やCu板4を接合したも
のを指す。)とAl−SiC放熱部材6とを、まずそれ
ぞれの条件で空焼きした後、両者の間に板状の低融点半
田7を介在させている。ここで、通常、半導体チップ5
を接合した後の回路基板9と放熱部材6とを接合するの
で、半導体チップ5の接着に用いたろう材に比べ低融点
の半田7で回路基板9と放熱部材6とを接合する必要が
ある。よって、Pb−Sn系またはPb−Sb系半田
等、組成に制約を受けたものを用いざるを得ない。そし
てその後、H雰囲気中で240℃×10分程度の半田
付け工程を行うことによって、回路基板9と放熱部材6
とを一体化したセラミックス放熱回路基板を製造してい
る。
The ceramic heat dissipation circuit board described above has a circuit board 9 (in the present invention, a ceramic circuit board 2 and a Cu circuit board 3 or a Cu board 4 joined together) and Al-. The SiC heat dissipation member 6 and the SiC heat dissipation member 6 are first fired under the respective conditions, and then the plate-shaped low melting point solder 7 is interposed therebetween. Here, normally, the semiconductor chip 5
Since the circuit board 9 and the heat dissipating member 6 are joined together, it is necessary to join the circuit board 9 and the heat dissipating member 6 with the solder 7 having a melting point lower than that of the brazing material used for bonding the semiconductor chip 5. Therefore, there is no choice but to use Pb-Sn-based solder, Pb-Sb-based solder, or the like whose composition is restricted. Then, after that, a soldering process at about 240 ° C. for about 10 minutes is performed in an H 2 atmosphere so that the circuit board 9 and the heat dissipation member 6 are
We manufacture a ceramics heat dissipation circuit board that integrates and.

【0008】ここで次のような問題が生じる。即ち、こ
の半田付け工程において半田がAl−SiC放熱部材6
の周辺にまで流れ出してしまうことがある。この半田流
れにより半田が放熱部材6の隅部のボルト穴近くまで広
がると、半導体チップ5とAl−SiC放熱部材6間の
絶縁が保てずIGBTの機能が損なわれる。また、半田
付け後のヒートシンク8の組立工程に支障をきたす等の
問題があった。さらに、半田流れが生じると半田の層間
に空洞が形成され易くなり、いわゆる半田ボイドと言う
不良が発生していた。半田ボイドの発生率が3%程度を
超えると接合強度の低下および熱伝導性の低下が顕著と
なりIGBTの機能が損なわれると言う問題もあった。
Here, the following problems occur. That is, in this soldering process, the solder is the Al-SiC heat dissipation member 6
It may flow to the area around. If this solder flow spreads the solder near the bolt holes at the corners of the heat dissipation member 6, the insulation between the semiconductor chip 5 and the Al—SiC heat dissipation member 6 cannot be maintained, and the function of the IGBT is impaired. In addition, there is a problem that it interferes with the assembly process of the heat sink 8 after soldering. Furthermore, when a solder flow occurs, cavities are easily formed between the layers of the solder, and a so-called solder void occurs. If the rate of occurrence of solder voids exceeds about 3%, there is also a problem that the joint strength and the thermal conductivity are significantly reduced and the function of the IGBT is impaired.

【0009】そこで、本発明は、回路基板と放熱部材と
を半田で接合する際に生じる半田流れを防止することを
目的とし、さらに半田ボイドの低減と半田濡れ性の改善
を図ったセラミックス放熱回路基板を提供することを目
的とする。
Therefore, the present invention has an object to prevent a solder flow generated when the circuit board and the heat dissipation member are joined by solder, and further, to reduce solder voids and improve solder wettability. It is intended to provide a substrate.

【0010】[0010]

【課題を解決するための手段】本発明は、一方に半導体
チップを搭載するCu又はAlの回路板を、他方にCu
又はAlの板をそれぞれ接合したセラミックス絶縁基板
と、表面にAl皮膜を有するAl−SiC複合体の放熱
部材とからなり、前記放熱部材のAl皮膜上に接合層を
形成し、当該接合層と前記セラミックス絶縁基板のCu
又はAl板とを半田により接合してなるセラミックス放
熱回路基板において、前記接合層をNiを主体とする層
とすると共に、その表面の中心線平均面粗さ(Ra)を
0.2〜1.5μmとしたセラミックス放熱回路基板で
ある。さらに望ましい中心線平均面粗さ(Ra)は0.
5〜1.0μmである。
According to the present invention, a Cu or Al circuit board on which a semiconductor chip is mounted is provided on one side and a Cu or Al circuit board is provided on the other side.
Alternatively, it is composed of a ceramics insulating substrate to which Al plates are respectively joined, and a heat dissipation member of an Al-SiC composite having an Al film on the surface, and a joining layer is formed on the Al film of the heat dissipation member. Cu of ceramics insulating substrate
Alternatively, in a ceramics heat dissipation circuit board formed by joining an Al plate with solder, the joining layer is a layer containing Ni as a main component, and the center line average surface roughness (Ra) of the surface is 0.2 to 1. It is a ceramic heat dissipation circuit board having a thickness of 5 μm. A more desirable center line average surface roughness (Ra) is 0.
It is 5 to 1.0 μm.

【0011】また、本発明のセラミックス放熱回路基板
では、前記接合層の厚さを3〜15μmとすることが望
ましく、さらに望ましくは4〜8μmである。また、前
記接合層は2層からなり、下地層がNi―Pめっきであ
り、表面層がNi―Bめっきであることが望ましい。
In the ceramic heat dissipation circuit board of the present invention, the thickness of the bonding layer is preferably 3 to 15 μm, more preferably 4 to 8 μm. Further, it is preferable that the bonding layer is composed of two layers, the underlayer is Ni—P plating, and the surface layer is Ni—B plating.

【0012】Al−SiC複合体の表面に形成されてい
るAl皮膜にNiを主体とする接合層を形成することに
より、半田濡れ性を向上させており、さらに、その接合
層の中心線平均面粗さRaを0.2〜1.5μmに制御
することにより半田流れを防ぐことが出来る。接合層の
表面粗さは、その下にあるAl皮膜の表面を適宜サンド
ブラスト処理等をして中心線平均面粗さ(Ra)を0.
2〜1.5μmに調整することによって得られる。即
ち、これはAl皮膜の表面粗さがほぼそのまま接合層の
表面粗さになって反映されるためである。この表面粗さ
が1.5μmを超えると半田流れが生じやすくなる。他
方、0.2μm未満であると十分なアンカー効果が得ら
れず接合強度に問題が生じる。また、接合層の形成は半
田接合する上で必要であるが、この厚さは前記表面粗さ
を制御するためにも、また接合強度及び熱伝導の点でも
好ましい範囲がある。即ち、表面性状を調整したAl皮
膜の表面粗さをほぼそのまま接合層の表面に映し出すた
めには、接合層の厚さは15μmを超えないことが必要
である。他方、3μm未満であると密着強度及び膜の劣
化を生じ問題がある。また、接合層は二層構造が好まし
い。Ni−Pめっきを下地層に形成することによって前
記Al皮膜上に半田付けが可能となり、その上にNi−
Bめっき層を施すことによって半田濡れ性が向上する。
以上のように、所定の表面粗さと厚みをもった接合層を
設けることによって、半田流れを防止すると共に、密着
強度を得ることに効果がある。
The solder wettability is improved by forming a bonding layer mainly composed of Ni on the Al film formed on the surface of the Al-SiC composite, and further, the center line average surface of the bonding layer is improved. The flow of solder can be prevented by controlling the roughness Ra to 0.2 to 1.5 μm. Regarding the surface roughness of the bonding layer, the center line average surface roughness (Ra) is 0.
It is obtained by adjusting to 2 to 1.5 μm. That is, this is because the surface roughness of the Al film is reflected as it is in the surface roughness of the bonding layer. If the surface roughness exceeds 1.5 μm, solder flow easily occurs. On the other hand, if it is less than 0.2 μm, a sufficient anchor effect cannot be obtained, and a problem occurs in the bonding strength. Further, the formation of the joining layer is necessary for solder joining, and this thickness has a preferable range in order to control the surface roughness and also in terms of joining strength and heat conduction. That is, the thickness of the bonding layer must not exceed 15 μm in order to project the surface roughness of the Al film whose surface properties have been adjusted almost directly onto the surface of the bonding layer. On the other hand, if it is less than 3 μm, the adhesion strength and the film are deteriorated, which causes a problem. Further, the bonding layer preferably has a two-layer structure. By forming Ni-P plating on the underlayer, soldering can be performed on the Al coating, and Ni-
The solder wettability is improved by applying the B plating layer.
As described above, by providing the bonding layer having the predetermined surface roughness and thickness, it is possible to prevent the solder flow and to obtain the adhesion strength.

【0013】[0013]

【発明の実施の形態】以下、本発明の実施態様を図面と
共に説明する。図1はセラミックス放熱回路基板の一例
を示す断面図であり、図2は本発明の回路基板と放熱部
材との接合部であってAl皮膜と接合層の900倍の顕
微鏡写真を示し、図3は図2の一部を拡大した接合層の
周辺を模式的に示した図である(但し、縮尺は無視して
いる)。実施例のセラミックス放熱回路基板の基本構成
は、上述した図1の回路基板及び放熱部材と同様であ
る。即ち、Cu回路板3とCu板4を接合したセラミッ
クス絶縁基板2とからなる回路基板9と、Al−SiC
複合体からなる放熱部材6とからなり、回路基板9と放
熱部材6とを半田7により接合した後ヒートシンク8を
ボルトで組み立てたものである。本発明では回路基板と
放熱部材を組んだものをセラミックス放熱回路基板と言
っているが、ヒートシンクを含んでいても構わない。こ
こで、実施例のセラミックス絶縁基板2はAlNからな
り、その上面に厚さ0.3mmのCu回路板3をAg−
Cu−Ti系のろう材により接合し、下面には厚さ0.
2mmのCu板4を同じAg−Cu−Ti系のろう材を
介して接合している。
BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a cross-sectional view showing an example of a ceramic heat dissipation circuit board, and FIG. 2 is a 900 times micrograph of an Al film and a bonding layer, which is a bonding portion between a circuit board of the present invention and a heat dissipation member. FIG. 3 is a diagram schematically showing the periphery of the bonding layer, which is an enlarged view of a part of FIG. 2 (however, the scale is ignored). The basic structure of the ceramic heat dissipation circuit board of the embodiment is the same as that of the circuit board and heat dissipation member of FIG. 1 described above. That is, the circuit board 9 including the ceramics insulating substrate 2 in which the Cu circuit board 3 and the Cu board 4 are joined, and the Al-SiC
The heat dissipation member 6 is made of a composite material, and the circuit board 9 and the heat dissipation member 6 are joined with the solder 7 and then the heat sink 8 is assembled with bolts. In the present invention, the combination of the circuit board and the heat dissipation member is called a ceramics heat dissipation circuit board, but a heat sink may be included. Here, the ceramics insulating substrate 2 of the embodiment is made of AlN, and the Cu circuit board 3 having a thickness of 0.3 mm is formed on the upper surface thereof by Ag-.
Bonded with a Cu-Ti-based brazing material, the bottom surface has a thickness of 0.
A 2 mm Cu plate 4 is joined via the same Ag—Cu—Ti based brazing material.

【0014】また、放熱部材6はSiC粉末からなるプ
リフォームに溶融金属含浸法により純Alを37Vol%
含浸して得たもので、その表面に約0.05〜0.1m
m程度のAl皮膜60を有している。このAl皮膜60
の上には図2、図3で示すように接合層64を形成して
いる。本例の接合層64は、Ni−P無電解めっきによ
る第1の層62(下地層)を厚さ4〜5μm程度に形成
し、その上にNi−B無電解めっきによる第2の層63
(表面層)を1〜2μm程度に形成している。Ni−P
の層は主に密着性を改善し、Ni−Bの層は主に半田濡
れ性を改善する。尚、本発明では一層の接合層でも二層
の接合層でも良いが、これら接合層64の総厚さが3〜
15μm、望ましくは4〜8μmになるように制御して
いる。さらにまた、その表面65の中心線平均面粗さ
(Ra)は0.2〜1.5μm、望ましくは0.5〜
1.0μmになるように制御している。
The heat dissipating member 6 is made of SiC powder in a preform of 37% by volume of pure Al by a molten metal impregnation method.
It is obtained by impregnation, and its surface is about 0.05-0.1 m.
It has an Al film 60 of about m. This Al film 60
A bonding layer 64 is formed on the upper surface as shown in FIGS. The bonding layer 64 of this example is formed by forming a first layer 62 (underlayer) having a thickness of about 4 to 5 μm by Ni—P electroless plating, and forming a second layer 63 by Ni—B electroless plating on the first layer 62 (base layer).
The (surface layer) is formed to have a thickness of about 1 to 2 μm. Ni-P
Layer mainly improves adhesion, and the Ni-B layer mainly improves solder wettability. In the present invention, either one bonding layer or two bonding layers may be used, but the total thickness of these bonding layers 64 is 3 to.
The thickness is controlled to 15 μm, preferably 4 to 8 μm. Furthermore, the center line average surface roughness (Ra) of the surface 65 is 0.2 to 1.5 μm, preferably 0.5 to
It is controlled to be 1.0 μm.

【0015】図3は接合層付近の拡大断面を模式的に示
しているが、この実施例では中心線平均面粗さ(Ra)
は約0.9μmであった。図2、図3より接合層の表面
粗さは、Al皮膜60の表面61の表面性状がほぼその
まま接合層64の表面まで沿って現れ反映されることが
分かる。表面性状を調整する方法としては、例えばサン
ドブラスト、ショットブラスト、グリッドブラスト又は
ハイドロブラスト等により結晶粒を機械的に除去する方
法、又は塩酸又は硫酸等の酸エッチング処理により粒界
相から溶出する方法がある。ここでは製造能率やコスト
等から考えてサンドブラストによるものが好ましい。そ
こで、下記するサンドブラスト条件により表面処理した
Al皮膜の表面61の中心線平均面粗さ(Ra)と、こ
のAl皮膜上に形成した接合層64の表面65の中心線
平均面粗さ(Ra)を触針式表面粗さ測定器により距離
2.5mmに渡って測定した。その結果を図4に示す、
ここで(a)はAl皮膜60の表面の面粗さRa=0.
987μmを示し、(b)はその後、第1の層5μmと
第2の層1μmからなる接合層64の表面の面粗さRa
=0.943μmを示している。このようにAl皮膜6
0と接合層64の中心線平均面粗さ(Ra)は、ほぼ同
じものが得られることが確認できた。さらに、これと同
様に接合層の厚さを種々変えてその違いを観察したとこ
ろ、接合層64の総厚さが15μmを超えるとAl皮膜
60の表面性状を反映し難くなり半田流れが生じること
も確認された。また、総厚さが3μm未満であると接合
強度に問題が生じることも分かった。
FIG. 3 schematically shows an enlarged cross section near the bonding layer. In this embodiment, the center line average surface roughness (Ra) is shown.
Was about 0.9 μm. 2 and 3, it can be seen that the surface roughness of the bonding layer appears and reflects the surface texture of the surface 61 of the Al film 60 almost as it is along the surface of the bonding layer 64. As a method of adjusting the surface texture, for example, a method of mechanically removing crystal grains by sandblasting, shot blasting, grid blasting, hydroblasting, or the like, or a method of eluting from the grain boundary phase by an acid etching treatment such as hydrochloric acid or sulfuric acid is used. is there. Here, sand blasting is preferable in view of manufacturing efficiency and cost. Therefore, the centerline average surface roughness (Ra) of the surface 61 of the Al coating surface-treated by the sandblasting conditions described below and the centerline average surface roughness (Ra) of the surface 65 of the bonding layer 64 formed on this Al coating film. Was measured with a stylus type surface roughness measuring device over a distance of 2.5 mm. The result is shown in FIG.
Here, (a) is the surface roughness Ra = 0.
987 μm, and (b) after that, the surface roughness Ra of the surface of the bonding layer 64 composed of the first layer 5 μm and the second layer 1 μm.
= 0.943 μm. In this way, the Al film 6
It was confirmed that the center line average surface roughness (Ra) of 0 and the bonding layer 64 were almost the same. Further, similarly, when the thickness of the bonding layer was variously changed and the difference was observed, when the total thickness of the bonding layer 64 exceeds 15 μm, it becomes difficult to reflect the surface texture of the Al film 60 and a solder flow occurs. Was also confirmed. It was also found that if the total thickness is less than 3 μm, there will be a problem in bonding strength.

【0016】サンドブラスト条件は以下の通りであっ
た。 処理速度:0.35秒/cm ノズルとの距離:100mm ノズルの噴出圧力:0.3MPa 基板表面に対する噴射角度:45° 砥粒:アルミナ製#240 上記したサンドブラスト条件(処理速度、ノズルとの距
離、ノズルの噴出圧力、基板表面に対する噴射角度、砥
粒の種類及び粒度等)を調整すれば、Al皮膜の中心線
平均面粗さ、ひいては接合層の表面粗さを制御できる。
中心線平均面粗さ(Ra)は0.2〜1.5μmの範囲
に制御するが、例えば、粗さを小さくするにはサンドブ
ラスト条件のうち噴出圧力を低くすると良く、逆に荒く
するには噴出圧力を高くすることで調整できる。Raが
1.5μmを超えると半田流れが生じやすくなる。他
方、0.2μm未満であると十分なアンカー効果が得ら
れず接合強度に問題が生じる。
The sandblasting conditions are as follows:
It was Processing speed: 0.35 seconds / cmTwo Distance with nozzle: 100mm Nozzle ejection pressure: 0.3MPa Jet angle to substrate surface: 45 ° Abrasive: Alumina # 240 Sandblast conditions mentioned above (processing speed, distance from nozzle
Separation, jet pressure of nozzle, jet angle to substrate surface, grinding
The center line of the Al film can be adjusted by adjusting the type and size of the grains.
The average surface roughness and thus the surface roughness of the bonding layer can be controlled.
Center line average surface roughness (Ra) is in the range of 0.2 to 1.5 μm
Control, for example, to reduce the roughness
Of the last conditions, it is better to lower the ejection pressure, but conversely
It can be adjusted by increasing the jet pressure. Ra is
If it exceeds 1.5 μm, solder flow easily occurs. other
On the other hand, if it is less than 0.2 μm, a sufficient anchor effect can be obtained.
However, a problem occurs in the bonding strength.

【0017】図5は接合層64の中心線平均面粗さ(R
a)を横軸に、半田拡がり係数を縦軸にとった特性デー
タである。半田拡がり係数とは、初期の半田直径(Dm
m)と加熱したときの半田高さ(Hmm)の差と半田直
径Dの比((D−H)×100/D)を拡がり率(%)で
表したものである(JISZ3197拡がり試験方法参
照)。試験は大気中でホットプレート上に接合層に相当
するめっきを施した試験板を設け、250℃ではんだ溶
融後30秒間加熱により測定したものである。この結果
よりRaが略0.2〜1.5μmの範囲で合格判定であ
る拡がり係数75以上を有している。さらに略0.8〜
1.5μmの範囲では80%以上の拡がり係数を示して
いる。拡がり係数が高いほど半田濡れ性が良好である
が、拡がりすぎても半田流れに通じるため、拡がり係数
は75〜85%が好ましい。また、Raが1.5μm以
上となると拡がり係数が88以上となり、はんだ流れが
見られる。
FIG. 5 shows the center line average surface roughness (R
Characteristic data in which a) is plotted on the horizontal axis and the solder spreading coefficient is plotted on the vertical axis. The solder spread coefficient is the initial solder diameter (Dm
m) and the difference between the solder height (Hmm) when heated and the solder diameter D ((D−H) × 100 / D) are expressed by the spread rate (%) (see JISZ3197 spread test method). ). In the test, a test plate plated with a bonding layer was provided on a hot plate in the atmosphere, and the solder was melted at 250 ° C. and heated for 30 seconds for measurement. From this result, it has a spread coefficient of 75 or more which is a pass judgment in the range of Ra of approximately 0.2 to 1.5 μm. About 0.8 ~
A spread coefficient of 80% or more is shown in the range of 1.5 μm. The higher the spreading coefficient is, the better the solder wettability is. However, the spreading coefficient is preferably 75 to 85% because the solder spreading can be conducted even if the spreading coefficient is excessive. Further, when Ra is 1.5 μm or more, the expansion coefficient is 88 or more, and solder flow is observed.

【0018】(実施例)縦187mm×横137mm×
厚さ3mmのAl−SiC放熱部材6の上に、縦55.
4mm×横57mm×厚さ0.6mmの回路基板9を6
個配置したセラミックス放熱回路基板について以下の試
験を行った。Al−SiC放熱部材6のAl皮膜60の
表面61の中心線平均面粗さ(Ra)及び接合層64の
第1のめっき層62及び第2のめっき層63の材質と厚
さを種々変化させた試料No1〜10を作製した。半田
は縦54.9mm×横56.5mm×厚さ0.2mmの
低融点半田を使用し、回路基板9をH雰囲気で325
℃×10分、放熱部材6をH雰囲気で260℃×10
分でそれぞれ空焼きした後、回路基板9と前記各放熱部
材の間に前記半田板を介在させ250℃×10分の半田
接合を行った。これらについて半田流れの有無、半田ボ
イドの発生率(%)及び接合強度について評価した。
尚、ボイド発生率は超音波映像により回路基板の総面積
あたりのボイド面積の発生率の平均をとった。接合強度
については引っ張り試験を行いめっき層が剥離するか否
かで合格・不合格の判断をした。また、比較例として中
心線平均面粗さ(Ra)と接合層の材質及び厚さを変え
た試料No11〜15を作製し、同様の評価を行った。
尚、その他の回路基板の構成は実施例と比較例共に図1
に示す構造のものを使用した。以上の評価結果を表1に
示す。
(Example) Length 187 mm x width 137 mm x
On the Al-SiC heat dissipation member 6 having a thickness of 3 mm, a length of 55.
6 circuit boards 9 of 4 mm x width 57 mm x thickness 0.6 mm
The following tests were conducted on the individually arranged ceramics heat dissipation circuit boards. The center line average surface roughness (Ra) of the surface 61 of the Al coating 60 of the Al-SiC heat dissipation member 6 and the materials and thicknesses of the first plating layer 62 and the second plating layer 63 of the bonding layer 64 are changed variously. Sample Nos. 1 to 10 were produced. As the solder, a low melting point solder having a length of 54.9 mm, a width of 56.5 mm and a thickness of 0.2 mm is used, and the circuit board 9 is set to 325 in an H 2 atmosphere.
℃ × 10 minutes, heat dissipation member 6 in H 2 atmosphere 260 ℃ × 10
After baking for 5 minutes, the solder plate was interposed between the circuit board 9 and each of the heat radiating members, and soldering was performed at 250 ° C. for 10 minutes. The presence or absence of solder flow, the occurrence rate of solder voids (%), and the bonding strength were evaluated for these.
The void generation rate was obtained by averaging the generation rate of void areas per total area of the circuit board using an ultrasonic image. Regarding the bonding strength, a tensile test was performed and it was judged whether the plating layer was peeled off or not. Further, as comparative examples, sample Nos. 11 to 15 in which the center line average surface roughness (Ra) and the material and thickness of the bonding layer were changed were prepared, and the same evaluation was performed.
The other circuit board configurations are shown in FIG.
The structure shown in was used. Table 1 shows the above evaluation results.

【0019】[0019]

【表1】 [Table 1]

【0020】以上より、中心線平均面粗さ(Ra)が
0.2〜1.5μmにあるものは半田流れが無く、ボイ
ド発生率も抑えられている。その結果、接合強度も全て
合格となった。また、接合層の厚さが3〜15μmの範
囲にあるものは面粗さに反映されて、半田流れが無く、
ボイド発生率も低く接合強度も十分であった。実際には
面粗さと接合層厚さの両方の条件をクリアできているこ
とが必要である。例えば、実施例8からは面粗さが小さ
くなるとボイドの発生率が高くなることが伺える。比較
例1では接合層の厚さが小さいがために強度不足を示し
ている。逆に比較例2では面粗さが大きいがために半田
流れが生じていると考えられる。比較例2、3からは面
粗さの他に接合層の厚さの違いがめっき膜強度に影響を
与え、これが接合強度の合否の差に現れていると考え
る。また、ボイドの発生は半田濡れ性の影響を受けると
考える。
From the above, solder having no center line average surface roughness (Ra) of 0.2 to 1.5 μm has no solder flow and the void generation rate is suppressed. As a result, all the bonding strengths also passed. Further, when the thickness of the bonding layer is in the range of 3 to 15 μm, the surface roughness is reflected, and there is no solder flow,
The void generation rate was low and the bonding strength was sufficient. Actually, it is necessary to satisfy both conditions of surface roughness and bonding layer thickness. For example, it can be seen from Example 8 that the occurrence rate of voids increases as the surface roughness decreases. In Comparative Example 1, the strength is insufficient because the thickness of the bonding layer is small. On the contrary, in Comparative Example 2, it is considered that the solder flow occurs because the surface roughness is large. From Comparative Examples 2 and 3, it is considered that, in addition to the surface roughness, the difference in the thickness of the bonding layer affects the plating film strength, which appears in the difference in the bonding strength pass / fail. Further, it is considered that the generation of voids is affected by the solder wettability.

【0021】[0021]

【発明の効果】本発明によれば、Al−SiC複合体か
らなる放熱部材のAl皮膜上に形成する接合層の中心線
平均面粗さ(Ra)を0.2〜1.5μmとすること、
及び接合層の厚さを3〜15μmにすることによって、
回路基板と放熱部材とを半田で接合する際に生じる半田
流れを防止することができる。また、半田ボイド発生の
低減と半田濡れ性の改善を図ることが出来る。よって、
接合強度、熱伝導性共に安定したセラミックス放熱回路
基板を提供することができた。
According to the present invention, the center line average surface roughness (Ra) of the bonding layer formed on the Al coating of the heat dissipation member made of an Al-SiC composite is 0.2 to 1.5 μm. ,
And by setting the thickness of the bonding layer to 3 to 15 μm,
It is possible to prevent a solder flow that occurs when the circuit board and the heat dissipation member are joined by solder. Further, it is possible to reduce the generation of solder voids and improve the solder wettability. Therefore,
It was possible to provide a ceramics heat dissipation circuit board with stable bonding strength and thermal conductivity.

【図面の簡単な説明】[Brief description of drawings]

【図1】セラミックス放熱回路基板の一例を示す断面図
である。
FIG. 1 is a cross-sectional view showing an example of a ceramics heat dissipation circuit board.

【図2】本発明の回路基板と放熱部材との接合層付近の
電子顕微鏡写真である。
FIG. 2 is an electron micrograph showing the vicinity of the bonding layer between the circuit board of the present invention and the heat dissipation member.

【図3】図2の接合層付近の模式的な断面図である。3 is a schematic cross-sectional view in the vicinity of a bonding layer in FIG.

【図4】本発明の実施例によるAl皮膜の面粗さ(a)
と接合層の面粗さ(b)の測定結果である。
FIG. 4 is a surface roughness (a) of an Al film according to an embodiment of the present invention.
And the surface roughness (b) of the bonding layer.

【図5】本発明の実施例による中心線平均面粗さと半田
拡がり係数との関係を示す特性図である。
FIG. 5 is a characteristic diagram showing a relationship between a centerline average surface roughness and a solder spreading coefficient according to an example of the present invention.

【符号の説明】 1:セラミックス放熱回路基板、2:AlN基板、3:
Cu回路板、4:Cu板、5:半導体チップ、6:Al
−SiC放熱部材、7:半田、8:ヒートシンク、9:
回路基板、10:締結部材、60:Al皮膜、61:A
l皮膜の表面、62:第1のめっき層(下地層)、6
3:第2のめっき層(表面層)、64:接合層、65:
接合層の表面
[Explanation of reference numerals] 1: Ceramic heat dissipation circuit board, 2: AlN board, 3:
Cu circuit board, 4: Cu plate, 5: Semiconductor chip, 6: Al
-SiC heat dissipation member, 7: solder, 8: heat sink, 9:
Circuit board, 10: Fastening member, 60: Al film, 61: A
l coating surface, 62: first plating layer (base layer), 6
3: second plating layer (surface layer), 64: bonding layer, 65:
Bonding layer surface

【手続補正書】[Procedure amendment]

【提出日】平成13年11月28日(2001.11.
28)
[Submission date] November 28, 2001 (2001.11.
28)

【手続補正1】[Procedure Amendment 1]

【補正対象書類名】図面[Document name to be corrected] Drawing

【補正対象項目名】図2[Name of item to be corrected] Figure 2

【補正方法】変更[Correction method] Change

【補正内容】[Correction content]

【図2】 [Fig. 2]

───────────────────────────────────────────────────── フロントページの続き Fターム(参考) 4G026 BA03 BA16 BA17 BB14 BB27 BB31 BC01 BC02 BD02 BD06 BD12 BD14 BF11 BF18 BF42 BF46 BG02 BG28 BH07 5E338 AA01 AA18 BB63 EE02 5F036 AA01 BA23 BB05 BB08    ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 4G026 BA03 BA16 BA17 BB14 BB27                       BB31 BC01 BC02 BD02 BD06                       BD12 BD14 BF11 BF18 BF42                       BF46 BG02 BG28 BH07                 5E338 AA01 AA18 BB63 EE02                 5F036 AA01 BA23 BB05 BB08

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 一方に半導体チップを搭載するCu又は
Alの回路板を、他方にCu又はAlの板をそれぞれ接
合したセラミックス絶縁基板と、表面にAl皮膜を有す
るAl−SiC複合体の放熱部材とからなり、前記放熱
部材のAl皮膜上に接合層を形成し、当該接合層と前記
セラミックス絶縁基板のCu又はAl板とを半田により
接合してなるセラミックス放熱回路基板において、前記
接合層をNiを主体とする層とすると共に、その表面の
中心線平均面粗さ(Ra)を0.2〜1.5μmとした
ことを特徴とするセラミックス放熱回路基板。
1. A heat dissipating member of an Al--SiC composite having a ceramic insulating substrate on which a semiconductor chip is mounted on one side and a Cu or Al plate on the other side, respectively, and an Al film on the surface. And a bonding layer is formed on the Al film of the heat dissipation member, and the bonding layer and the Cu or Al plate of the ceramics insulating substrate are bonded by soldering. And a center line average surface roughness (Ra) of the surface thereof is 0.2 to 1.5 μm.
【請求項2】 前記接合層の厚さが3〜15μmである
ことを特徴とする請求項1記載のセラミックス放熱回路
基板。
2. The ceramic heat dissipation circuit board according to claim 1, wherein the bonding layer has a thickness of 3 to 15 μm.
【請求項3】 前記接合層は2層からなり、下地層がN
i―Pめっき、表面層がNi―Bめっきであることを特
徴とする請求項1又は2記載のセラミックス放熱回路基
板。
3. The bonding layer is composed of two layers, and the underlayer is N
3. The ceramic heat dissipation circuit board according to claim 1, wherein the plating layer is iP and the surface layer is NiB.
JP2001350294A 2001-11-15 2001-11-15 Ceramic heat dissipation circuit board Pending JP2003152141A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001350294A JP2003152141A (en) 2001-11-15 2001-11-15 Ceramic heat dissipation circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001350294A JP2003152141A (en) 2001-11-15 2001-11-15 Ceramic heat dissipation circuit board

Publications (1)

Publication Number Publication Date
JP2003152141A true JP2003152141A (en) 2003-05-23

Family

ID=19162829

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001350294A Pending JP2003152141A (en) 2001-11-15 2001-11-15 Ceramic heat dissipation circuit board

Country Status (1)

Country Link
JP (1) JP2003152141A (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008311296A (en) * 2007-06-12 2008-12-25 Mitsubishi Materials Corp Power module substrate
KR100939760B1 (en) 2009-03-04 2010-02-03 주식회사 옹스트롬 Method for generating a substrate used for heat-radiating pcb and the substrate thereof
WO2015186320A1 (en) * 2014-06-04 2015-12-10 パナソニックIpマネジメント株式会社 Semiconductor package and method for manufacturing same
CN107924889A (en) * 2016-03-31 2018-04-17 富士电机株式会社 The manufacture method of semiconductor device and semiconductor device
CN110351954A (en) * 2019-06-18 2019-10-18 安徽省华腾农业科技有限公司 The processing method and its printed circuit board of printed circuit board

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008311296A (en) * 2007-06-12 2008-12-25 Mitsubishi Materials Corp Power module substrate
KR100939760B1 (en) 2009-03-04 2010-02-03 주식회사 옹스트롬 Method for generating a substrate used for heat-radiating pcb and the substrate thereof
WO2015186320A1 (en) * 2014-06-04 2015-12-10 パナソニックIpマネジメント株式会社 Semiconductor package and method for manufacturing same
CN107924889A (en) * 2016-03-31 2018-04-17 富士电机株式会社 The manufacture method of semiconductor device and semiconductor device
JPWO2017169857A1 (en) * 2016-03-31 2018-07-26 富士電機株式会社 Semiconductor device and manufacturing method of semiconductor device
US10199305B2 (en) 2016-03-31 2019-02-05 Fuji Electric Co., Ltd. Semiconductor device and method of manufacturing semiconductor device
CN107924889B (en) * 2016-03-31 2021-02-12 富士电机株式会社 Semiconductor device and method for manufacturing semiconductor device
CN110351954A (en) * 2019-06-18 2019-10-18 安徽省华腾农业科技有限公司 The processing method and its printed circuit board of printed circuit board
CN114258202A (en) * 2019-06-18 2022-03-29 安徽省华腾农业科技有限公司 Printed circuit board processing method and printed circuit board

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