JPH0831990A - Heat radiating fin - Google Patents
Heat radiating finInfo
- Publication number
- JPH0831990A JPH0831990A JP16372594A JP16372594A JPH0831990A JP H0831990 A JPH0831990 A JP H0831990A JP 16372594 A JP16372594 A JP 16372594A JP 16372594 A JP16372594 A JP 16372594A JP H0831990 A JPH0831990 A JP H0831990A
- Authority
- JP
- Japan
- Prior art keywords
- metal layer
- fin
- ceramic substrate
- ceramic
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、セラミック回路基板に
実装されたシリコン半導体チップから発生する熱を大気
に放散させるための放熱フィンに関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a radiation fin for radiating heat generated from a silicon semiconductor chip mounted on a ceramic circuit board to the atmosphere.
【0002】[0002]
【従来の技術】従来、この種の放熱フィンとして、窒化
アルミニウム(以下、AlNという)等の高熱伝導性セ
ラミックスを切削加工することにより形成されたフィン
本体を接着剤によりシリコン半導体チップ又はセラミッ
ク基板に接着したものが知られている。この放熱フィン
では、フィン本体が半導体チップ又はセラミック基板と
熱膨張係数が整合されているため、半導体チップ又はセ
ラミック基板とフィン本体とに熱が加わっても反りが発
生しないようになっている。2. Description of the Related Art Conventionally, as this type of heat dissipating fin, a fin body formed by cutting a highly heat-conductive ceramic such as aluminum nitride (hereinafter referred to as AlN) is attached to a silicon semiconductor chip or a ceramic substrate with an adhesive. It is known that it is glued. In this radiating fin, the fin body has a coefficient of thermal expansion matched with that of the semiconductor chip or the ceramic substrate, so that warpage does not occur even if heat is applied to the semiconductor chip or the ceramic substrate and the fin body.
【0003】[0003]
【発明が解決しようとする課題】しかし、上記従来の放
熱フィンでは、フィン本体が硬くて脆いAlNを切削加
工して形成されるため、フィン本体の加工工数が増大し
て製造コストを押上げる不具合があり、フィン本体が比
較的小さい衝撃で欠ける恐れがあった。また、上記従来
の放熱フィンの熱伝導率は比較的小さいため、フィン本
体の放熱特性があまり良くない問題点もあった。更に、
上記従来の放熱フィンにて、フィン本体をシリコン半導
体チップ又はセラミック基板にはんだを介して接着する
場合、予め接着面にメタライズ処理を施す必要があり、
これがフィン本体の変形の原因になっていた。However, in the above-mentioned conventional heat radiation fin, the fin body is formed by cutting the hard and brittle AlN, so that the number of machining steps of the fin body increases and the manufacturing cost is increased. However, the fin body may be chipped by a relatively small impact. Further, since the thermal conductivity of the conventional radiating fin is relatively small, there is a problem that the radiating characteristic of the fin body is not so good. Furthermore,
When the fin body is adhered to the silicon semiconductor chip or the ceramic substrate via solder with the conventional heat dissipating fin, it is necessary to perform a metallizing treatment on the adhering surface in advance.
This caused the deformation of the fin body.
【0004】本発明の目的は、熱変形を吸収して反りを
防止でき、フィン本体の加工工数を低減でき、かつ衝撃
が作用しても破損し難い放熱フィンを提供することにあ
る。また本発明の別の目的は、放熱特性を向上でき、か
つセラミック回路基板に半導体チップが実装された後で
も接着できる放熱フィンを提供することにある。An object of the present invention is to provide a radiating fin which can absorb thermal deformation and prevent warping, reduce the number of man-hours required for processing the fin main body, and is less likely to be damaged by impact. Another object of the present invention is to provide a heat dissipation fin which can improve heat dissipation characteristics and can be adhered even after a semiconductor chip is mounted on a ceramic circuit board.
【0005】[0005]
【課題を解決するための手段】上記目的を達成するため
の本発明の構成を、実施例に対応する図1、図3及び図
5〜図7を用いて説明する。本発明の第1は、図1に示
すように表面にチップ12を実装したセラミック回路基
板13の裏面にはんだ又は接着剤を介して直接接着され
る放熱フィン11であって、セラミック回路基板13の
裏面を被覆可能な面積を有するアルミニウム材からなる
第1金属層21と、第1金属層21を被覆可能な面積を
有するセラミック基板18と、セラミック基板18を被
覆可能な面積を有するアルミニウム材からなる第2金属
層22と、第2金属層22を被覆可能な面積を有するア
ルミニウム材からなるフィン本体19とがそれぞれAl
系ろう材を介してこの順に積層接着されたものである。
本発明の第2は、図7に示すように表面にチップ12を
実装したセラミック回路基板13の裏面にはんだ又は接
着剤を介して直接接着される放熱フィン11であって、
セラミック回路基板13の裏面を被覆可能な面積を有す
るアルミニウム材からなる第1金属層21と、第1金属
層21を被覆可能な面積を有するセラミック基板18
と、セラミック基板18を被覆可能な面積を有するアル
ミニウム材からなるフィン本体19とがそれぞれAl系
ろう材を介してこの順に積層接着されたものである。The structure of the present invention for achieving the above object will be described with reference to FIGS. 1, 3 and 5 to 7 corresponding to the embodiments. The first aspect of the present invention is a radiation fin 11 that is directly adhered to the back surface of a ceramic circuit board 13 having a chip 12 mounted on the front surface via solder or an adhesive as shown in FIG. A first metal layer 21 made of an aluminum material having an area capable of covering the back surface, a ceramic substrate 18 having an area capable of coating the first metal layer 21, and an aluminum material having an area capable of coating the ceramic substrate 18. The second metal layer 22 and the fin body 19 made of an aluminum material having an area capable of covering the second metal layer 22 are each made of Al.
These are laminated and adhered in this order through a brazing filler metal.
A second aspect of the present invention is a radiation fin 11 that is directly bonded to the back surface of a ceramic circuit board 13 having a chip 12 mounted on the front surface thereof via solder or an adhesive as shown in FIG.
A first metal layer 21 made of an aluminum material having an area capable of covering the back surface of the ceramic circuit board 13, and a ceramic substrate 18 having an area capable of covering the first metal layer 21.
And a fin body 19 made of an aluminum material having an area capable of covering the ceramic substrate 18 are laminated and adhered in this order through an Al-based brazing material.
【0006】本発明の第3は、図3に示すようにセラミ
ック回路基板13に実装したチップ12の外面にはんだ
又は接着剤を介して直接接着される放熱フィン11であ
って、チップ12の外面を被覆可能な面積を有するアル
ミニウム材からなる第1金属層21と、第1金属層21
を被覆可能な面積を有するセラミック基板18と、セラ
ミック基板18を被覆可能な面積を有するアルミニウム
材からなる第2金属層22と、第2金属層22を被覆可
能な面積を有するアルミニウム材からなるフィン本体1
9とがそれぞれAl系ろう材を介してこの順に積層接着
されたものである。本発明の第4は、セラミック回路基
板に実装したチップの外面にはんだ又は接着剤を介して
直接接着される放熱フィンであって、チップの外面を被
覆可能な面積を有するアルミニウム材からなる第1金属
層と、第1金属層を被覆可能な面積を有するセラミック
基板と、セラミック基板を被覆可能な面積を有するアル
ミニウム材からなるフィン本体とがそれぞれAl系ろう
材を介してこの順に積層接着されたものである。The third aspect of the present invention is, as shown in FIG. 3, a radiation fin 11 which is directly adhered to the outer surface of a chip 12 mounted on a ceramic circuit board 13 via a solder or an adhesive. And a first metal layer 21 made of an aluminum material having an area capable of covering
, A second metal layer 22 made of an aluminum material having an area that can cover the ceramic substrate 18, and a fin made of an aluminum material having an area that can cover the second metal layer 22. Body 1
9 is laminated and adhered in this order through an Al-based brazing material. A fourth aspect of the present invention is a radiating fin that is directly bonded to an outer surface of a chip mounted on a ceramic circuit board via a solder or an adhesive, and is made of an aluminum material having an area capable of covering the outer surface of the chip. A metal layer, a ceramic substrate having an area capable of covering the first metal layer, and a fin body made of an aluminum material having an area capable of covering the ceramic substrate were laminated and adhered in this order through an Al-based brazing material. It is a thing.
【0007】また、図6に示すようにセラミック基板1
8のチップ12に対向する位置に複数の熱伝導用スルー
ホール111を設け、複数の熱伝導用スルーホール11
1にアルミニウム材112をそれぞれ充填することもで
きる。また、第2金属層22の厚さは第1金属層21の
厚さの2/3以下であることが好ましい。更に、図5に
示すようにフィン本体99が凸条99aを有するコルゲ
ートフィンであって、フィン本体99を凸条99aに直
交する方向に切断することにより複数分割することが好
ましい。Further, as shown in FIG. 6, the ceramic substrate 1
8. A plurality of heat conduction through holes 111 are provided at positions facing the chip 12 of FIG.
It is also possible to fill 1 with aluminum material 112, respectively. Further, the thickness of the second metal layer 22 is preferably ⅔ or less of the thickness of the first metal layer 21. Further, as shown in FIG. 5, the fin main body 99 is a corrugated fin having ridges 99a, and it is preferable that the fin main body 99 is cut in a direction orthogonal to the ridges 99a to be divided into a plurality of pieces.
【0008】[0008]
【作用】図1に示される放熱フィンでは、チップ12よ
り発生した熱がセラミック回路基板13を介して熱伝導
率の大きい第1金属層21内で全面に広がるとともに、
セラミック基板18を介して熱伝導率の大きい第2金属
層22に伝わり、更に第2金属層22内で全面に広がっ
てフィン本体19に伝わり、このフィン本体19から大
気に放散される。図3に示される放熱フィンでは、チッ
プ12より発生した熱が直接熱伝導率の大きい第1金属
層21内で全面に広がることを除いて、図1に示される
放熱フィンと同様に放熱が行われる。In the radiating fin shown in FIG. 1, the heat generated from the chip 12 spreads through the ceramic circuit board 13 to the entire surface in the first metal layer 21 having high thermal conductivity, and
It is transmitted to the second metal layer 22 having a large thermal conductivity through the ceramic substrate 18, further spreads over the entire surface in the second metal layer 22 and is transmitted to the fin body 19, and is diffused from the fin body 19 to the atmosphere. The radiating fin shown in FIG. 3 radiates heat similarly to the radiating fin shown in FIG. 1, except that the heat generated by the chip 12 directly spreads over the entire surface in the first metal layer 21 having a large thermal conductivity. Be seen.
【0009】[0009]
【実施例】次に本発明の第1実施例を図面に基づいて詳
しく説明する。図1に示すように、放熱フィン11は表
面にシリコン半導体チップ12を実装する薄膜多層セラ
ミック回路基板13の裏面に接着剤を介して直接接着さ
れる。セラミック回路基板13は複数のAl2O3基板1
4と回路を形成する複数のタングステン導体16とを1
600℃前後の高温で同時焼成して積層接着することに
より形成される。セラミック回路基板13の表面には半
導体チップ12がAl−Siはんだを用いて420℃で
ダイボンディングされた後、300℃でAuワイヤ17
によりワイヤボンディングを行うことにより実装され
る。この例では半導体チップ12はセラミック回路基板
13の表面に所定の間隔をあけて3個実装される。これ
らの半導体チップ12は一辺が33mmの正方形をな
す。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described in detail with reference to the drawings. As shown in FIG. 1, the heat radiation fin 11 is directly adhered to the back surface of the thin film multilayer ceramic circuit board 13 on which the silicon semiconductor chip 12 is mounted via an adhesive. The ceramic circuit board 13 is composed of a plurality of Al 2 O 3 boards 1.
4 and a plurality of tungsten conductors 16 forming a circuit,
It is formed by simultaneous firing at a high temperature of around 600 ° C. and laminating and adhering. The semiconductor chip 12 is die-bonded to the surface of the ceramic circuit board 13 using Al-Si solder at 420 ° C., and then the Au wire 17 is applied at 300 ° C.
It is mounted by wire bonding. In this example, three semiconductor chips 12 are mounted on the surface of the ceramic circuit board 13 with a predetermined gap. These semiconductor chips 12 form a square having a side of 33 mm.
【0010】放熱フィン11はセラミック回路基板13
の裏面のうち半導体チップ12に対向する位置に配設さ
れセラミック回路基板13の裏面を被覆可能な面積を有
する3枚の第1金属層21と、3枚の第1金属層21を
それぞれ被覆可能な面積を有する3枚のセラミック基板
18と、3枚のセラミック基板18を被覆可能な面積を
有する3枚の第2金属層22と、3枚の第2金属層22
を被覆可能な面積を有する3個のフィン本体19とを備
える。第1及び第2金属層21,22は97%以上のア
ルミニウムを含むアルミニウム合金により形成され、セ
ラミック基板18はこの例ではAl2O3により形成され
る。第1金属層21、第2金属層22及びセラミック基
板18は一辺が40mmの正方形をなし、第1金属層2
1、第2金属層22及びセラミック基板18の厚さはそ
れぞれ0.2mm、0.4mm及び0.635mmであ
る。The radiation fin 11 is a ceramic circuit board 13.
The three first metal layers 21 and the three first metal layers 21 each having a surface area which can be covered with the ceramic circuit board 13 and is disposed at a position facing the semiconductor chip 12 on the back surface of Ceramic substrates 18 having different areas, three second metal layers 22 having an area capable of covering the three ceramic substrates 18, and three second metal layers 22
And three fin bodies 19 having an area capable of covering The first and second metal layers 21 and 22 are made of an aluminum alloy containing 97% or more of aluminum, and the ceramic substrate 18 is made of Al 2 O 3 in this example. The first metal layer 21, the second metal layer 22 and the ceramic substrate 18 form a square having a side of 40 mm.
The thicknesses of the first and second metal layers 22 and the ceramic substrate 18 are 0.2 mm, 0.4 mm and 0.635 mm, respectively.
【0011】第1金属層21の上にセラミック基板18
が厚さ30μmのAl−7.5%Si箔(重量%、以下
同じ)を挟んで載せられ、このセラミック基板18の上
に第2金属層22が厚さ30μmのAl−7.5%Si
箔を挟んで載せられ、この状態でこれらに2kgf/c
m2の荷重を加えて真空炉中で630℃、30分加熱す
ることにより、第1金属層21とセラミック基板18と
第2金属層22とが積層接着される。A ceramic substrate 18 is formed on the first metal layer 21.
Is placed with an Al-7.5% Si foil (weight%, the same applies hereinafter) having a thickness of 30 μm sandwiched therebetween, and the second metal layer 22 is provided on the ceramic substrate 18 with a thickness of 30 μm of Al-7.5% Si.
It is placed with a foil sandwiched between them, and in this state 2 kgf / c
By applying a load of m 2 and heating in a vacuum furnace at 630 ° C. for 30 minutes, the first metal layer 21, the ceramic substrate 18, and the second metal layer 22 are laminated and bonded.
【0012】フィン本体19は図1及び図2に示すよう
に、横方向に所定の間隔をあけて設けられた複数の第1
突起19aと、第1突起19aに連設され第1突起19
aより横方向に所定の距離だけずらして設けられた複数
の第2突起19bと、第1及び第2突起19a,19b
間に形成された窓19cとを有するアルミニウム製のコ
ルゲートルーバフィンである。第1突起19aと第2突
起19bは縦方向に交互に連設される。フィン本体19
は厚さ0.3mmの87%以上のアルミニウムを含むア
ルミニウム合金板をプレス加工することにより形成さ
れ、その縦及び横は上記金属層21,22と略同一寸法
であり、高さは6mmである。上記積層接着された第2
金属層22の上にフィン本体19が60μmのAl−
7.5%Si箔を挟んで載せられ、この状態でこれらに
20g/cm2の荷重を加えて真空炉中で630℃、3
0分加熱することにより、フィン本体19が第2金属層
22に接着されて放熱フィン11が形成される。上記3
個の放熱フィン19は第1金属層21をセラミック回路
基板13の裏面、即ち最も下方に位置するAl2O3基板
14の裏面に3個の半導体チップ12の真下にそれぞれ
位置するように接着剤であるエポキシ系の樹脂により接
着することによりセラミック回路基板13に直接接着さ
れる。As shown in FIGS. 1 and 2, the fin main body 19 is composed of a plurality of first fins 19 which are provided laterally at predetermined intervals.
The protrusion 19a and the first protrusion 19a are connected to the first protrusion 19a.
a plurality of second protrusions 19b provided laterally offset from a by a predetermined distance, and first and second protrusions 19a, 19b
It is a corrugated louver fin made of aluminum having a window 19c formed therebetween. The first projections 19a and the second projections 19b are alternately arranged in the vertical direction. Fin body 19
Is formed by pressing an aluminum alloy plate having a thickness of 0.3 mm and containing 87% or more of aluminum, and the length and width thereof are substantially the same as those of the metal layers 21 and 22, and the height thereof is 6 mm. . The above laminated and laminated second
On the metal layer 22, the fin body 19 is Al-having a thickness of 60 μm.
A 7.5% Si foil is sandwiched between them, and a load of 20 g / cm 2 is applied to them in this state at 630 ° C. for 3 hours in a vacuum furnace.
By heating for 0 minutes, the fin body 19 is bonded to the second metal layer 22 to form the heat radiation fin 11. 3 above
The heat dissipating fins 19 are adhesive so that the first metal layer 21 is located on the back surface of the ceramic circuit board 13, that is, on the back surface of the Al 2 O 3 substrate 14 located at the lowermost position, directly below the three semiconductor chips 12. It is directly bonded to the ceramic circuit board 13 by bonding with an epoxy resin.
【0013】このように構成された放熱フィンの動作を
説明する。シリコン半導体チップ12より発生した熱
は、薄膜多層セラミック回路基板13を介して熱伝導率
の大きい第1金属層21内で全面に広がるとともに、セ
ラミック基板18を介して熱伝導率の大きい第2金属層
22に伝わる。この熱は更に第2金属層22内で全面に
広がってフィン本体19に伝わり、このフィン本体19
から大気にスムーズに放散される。この結果、半導体チ
ップ12の温度上昇を低く抑えることができる。またセ
ラミック回路基板13及びフィン本体19は熱膨張係数
に違いがあるが、セラミック基板18の両面に変形抵抗
の小さい第1及び第2金属層21,22を接着し、かつ
セラミック基板18の熱膨張係数がセラミック回路基板
13と略同等であるため、接着材で接着しても、その接
着面での熱サイクルによる剥がれを防止できる。The operation of the radiation fin thus constructed will be described. The heat generated from the silicon semiconductor chip 12 spreads over the entire surface in the first metal layer 21 having a large thermal conductivity through the thin film multilayer ceramic circuit board 13 and also through the ceramic substrate 18, the second metal having a large thermal conductivity. It is transmitted to layer 22. This heat further spreads over the entire surface in the second metal layer 22 and is transmitted to the fin body 19,
Smoothly dissipates into the atmosphere. As a result, the temperature rise of the semiconductor chip 12 can be suppressed low. Although the ceramic circuit board 13 and the fin body 19 have different thermal expansion coefficients, the first and second metal layers 21 and 22 having small deformation resistance are adhered to both surfaces of the ceramic substrate 18, and the thermal expansion of the ceramic substrate 18 is increased. Since the coefficient is substantially the same as that of the ceramic circuit board 13, even if they are adhered by an adhesive material, it is possible to prevent the adhered surfaces from peeling due to a thermal cycle.
【0014】図3は本発明の第2実施例を示す。図3に
おいて図1と同一符号は同一部品を示す。この例では、
放熱フィン11は第1実施例と同様に形成された薄膜多
層セラミック回路基板13に実装したシリコン半導体チ
ップ12の外面にはんだを介して直接接着される。半導
体チップ12はセラミック回路基板13の表面にはんだ
バンプ51を介して実装される。はんだバンプ51は半
導体チップ12の表面の電極上にはんだを突起状に盛り
上げたものであり、Ni及びAuの複合めっきが施され
たCuボールにより、或いはPb及びSnの合金により
形成される。半導体チップ12の電極上に盛り上げられ
たはんだバンプ51をセラミック回路基板13のタング
ステン導体16の端子にフラックスの粘着力で仮固定
し、この状態で加熱してはんだバンプ51を溶融するこ
とにより、半導体チップ12がセラミック回路基板13
に実装される。半導体チップ12は一辺が33mmの正
方形をなす。FIG. 3 shows a second embodiment of the present invention. 3, the same reference numerals as those in FIG. 1 indicate the same parts. In this example,
The heat radiation fin 11 is directly adhered to the outer surface of the silicon semiconductor chip 12 mounted on the thin film multilayer ceramic circuit board 13 formed in the same manner as in the first embodiment via solder. The semiconductor chip 12 is mounted on the surface of the ceramic circuit board 13 via solder bumps 51. The solder bumps 51 are formed by projecting solder on the electrodes on the surface of the semiconductor chip 12, and are formed of Cu balls plated with Ni and Au composite plating, or of an alloy of Pb and Sn. The solder bumps 51 raised on the electrodes of the semiconductor chip 12 are temporarily fixed to the terminals of the tungsten conductor 16 of the ceramic circuit board 13 by the adhesive force of the flux, and the solder bumps 51 are melted by heating in this state. Chip 12 is ceramic circuit board 13
Will be implemented in. The semiconductor chip 12 has a square shape with one side of 33 mm.
【0015】放熱フィン19は半導体チップ12の外面
を被覆可能な面積を有する第1金属層21と、第1金属
層21を被覆可能な面積を有するセラミック基板18
と、セラミック基板18を被覆可能な面積を有する第2
金属層22と、第2金属層22を被覆可能な面積を有す
るフィン本体19とを備える。第1金属層21、第2金
属層22及びセラミック基板18は第1実施例の第1金
属層、第2金属層及びセラミック基板とそれぞれ同一材
料により同一寸法に形成され、第1金属層21、第2金
属層22及びセラミック基板18は第1実施例の第1金
属層、第2金属層及びセラミック基板と同様にして積層
接着される。The radiation fin 19 has a first metal layer 21 having an area capable of covering the outer surface of the semiconductor chip 12, and a ceramic substrate 18 having an area capable of covering the first metal layer 21.
And a second having an area capable of covering the ceramic substrate 18.
The metal layer 22 and the fin body 19 having an area capable of covering the second metal layer 22 are provided. The first metal layer 21, the second metal layer 22, and the ceramic substrate 18 are made of the same material and have the same dimensions as the first metal layer, the second metal layer, and the ceramic substrate of the first embodiment. The second metal layer 22 and the ceramic substrate 18 are laminated and adhered in the same manner as the first metal layer, the second metal layer and the ceramic substrate of the first embodiment.
【0016】またフィン本体19は第1実施例と同一材
料により同一形状に形成されたコルゲートルーバフィン
であり、フィン本体19は第1実施例と同様にして上記
積層接着された第2金属層22の上に接着されて放熱フ
ィン11が形成される。放熱フィン19のうち半導体チ
ップ12の外面にはんだを介して接着される面、即ち第
1金属層21の裏面には予めNiめっきが施され、半導
体チップ12の外面には予めNiメタライズ等の裏面処
理が施される。放熱フィン19は半導体チップ12の外
面に厚さ50〜100μmのSn−3.5%Agはんだ
箔を介して載せられ、この状態で10g/cm2の荷重
を加えてリフロー炉中で260℃、1〜3分加熱するこ
とにより、半導体チップ12の外面に直接接着される。Further, the fin main body 19 is a corrugated louver fin formed in the same shape with the same material as in the first embodiment, and the fin main body 19 is laminated and adhered to the second metal layer 22 in the same manner as in the first embodiment. The heat radiation fins 11 are formed by being adhered on the above. The surface of the heat dissipation fin 19 that is bonded to the outer surface of the semiconductor chip 12 via solder, that is, the back surface of the first metal layer 21 is pre-plated with Ni, and the outer surface of the semiconductor chip 12 is back surface with Ni metallization or the like in advance. Processing is performed. The radiating fin 19 is placed on the outer surface of the semiconductor chip 12 via a Sn-3.5% Ag solder foil having a thickness of 50 to 100 μm, and in this state, a load of 10 g / cm 2 is applied to the radiating fin 19 in a reflow furnace at 260 ° C. It is directly bonded to the outer surface of the semiconductor chip 12 by heating for 1 to 3 minutes.
【0017】このように構成された放熱フィンでは、シ
リコン半導体チップ12より発生した熱が直接熱伝導率
の大きい第1金属層21内で全面に広がることを除い
て、動作が第1実施例と同様であるので、繰返しの説明
を省略する。In the radiation fin thus constructed, the operation is the same as that of the first embodiment except that the heat generated from the silicon semiconductor chip 12 is directly spread over the entire surface of the first metal layer 21 having a large thermal conductivity. Since it is the same, repeated description is omitted.
【0018】なお、上記第1及び第2実施例ではフィン
本体として第1突起と第1突起より横方向にずらして設
けられた第2突起と第1及び第2突起間に形成された窓
とを有するアルミニウム製のコルゲートルーバフィンを
挙げたが、図4に示すようにフィン本体79が断面略蜂
の巣状のアルミニウム製のコルゲートハニカムフィンで
もよく、また図5に示すようにフィン本体99が横方向
に所定の間隔をあけて縦方向に伸びる複数の凸条99a
とこれらの凸条99aの両端に形成された開口99bと
を有するアルミニウム製のコルゲートフィンでもよい。
このフィン本体99を図1のセラミック基板に第2金属
層を介して接着する場合、凸条99aに直交する方向に
切断することにより複数分割しておくと、フィン本体9
9を上記セラミック基板に接着したときの熱膨張係数の
相違に起因した反りを減少することができ、好ましい。
また図示しないがフィン本体は取付板から多数のピンが
突設されたアルミニウム製のピンフィンでもよい。In the first and second embodiments, the fin main body includes the first projection, the second projection provided laterally offset from the first projection, and the window formed between the first and second projections. Although the corrugated louver fin made of aluminum having the above is given, the fin main body 79 may be a corrugated honeycomb fin made of aluminum having a substantially honeycomb cross section as shown in FIG. A plurality of ridges 99a extending in the vertical direction at predetermined intervals
Alternatively, an aluminum corrugated fin having openings 99b formed at both ends of these ridges 99a may be used.
When the fin main body 99 is adhered to the ceramic substrate of FIG. 1 through the second metal layer, the fin main body 9 can be divided into a plurality of pieces by cutting the fin main body 99 in a direction orthogonal to the ridge 99a.
Warp due to the difference in thermal expansion coefficient when 9 is adhered to the ceramic substrate can be reduced, which is preferable.
Although not shown, the fin body may be an aluminum pin fin having a large number of pins protruding from the mounting plate.
【0019】また、図6に示すように第1実施例のセラ
ミック基板18のチップ12に対向する位置に複数の熱
伝導用スルーホール111を設け、これらのスルーホー
ル111にアルミニウム材112をそれぞれ充填しても
よい。この場合、第1金属層21の熱がアルミニウム材
112を通ってよりスムーズに第2金属層22に伝わる
ことができる。また図示しないが第2実施例のセラミッ
ク基板18にアルミニウム材が充填される熱伝導用スル
ーホールを設けてもよい。また、上記第1実施例では放
熱フィンをエポキシ系の接着剤によりセラミック回路基
板に直接接着したが、厚さ50〜100μmのSn−
3.5%Agはんだを介して直接接着してもよい。ま
た、上記第2実施例では放熱フィンを厚さ50〜100
μmのSn−3.5%Agはんだ箔を介してシリコン半
導体チップの外面に直接接着したが、ペースト状のクリ
ームはんだを介して直接接着してもよく、或いはエポキ
シ系の接着剤により直接接着してもよい。また、上記第
1及び第2実施例では第1及び第2金属層の間に位置す
るセラミック基板としてAl2O3により形成されたもの
を挙げたが、これは一例であってAlN又はSiCによ
り形成してもよい。Further, as shown in FIG. 6, a plurality of heat conduction through holes 111 are provided at positions facing the chips 12 of the ceramic substrate 18 of the first embodiment, and these through holes 111 are filled with aluminum materials 112, respectively. You may. In this case, the heat of the first metal layer 21 can be transferred to the second metal layer 22 more smoothly through the aluminum material 112. Although not shown, the ceramic substrate 18 of the second embodiment may be provided with a through hole for heat conduction filled with an aluminum material. Further, in the first embodiment, the heat radiation fin is directly adhered to the ceramic circuit board by the epoxy adhesive, but the Sn-thickness of 50 to 100 μm is used.
It may be directly bonded via 3.5% Ag solder. In addition, in the second embodiment described above, the radiation fin has a thickness of 50 to 100.
Although it was directly adhered to the outer surface of the silicon semiconductor chip through the Sn-3.5% Ag solder foil of μm, it may be directly adhered through the paste-like cream solder, or directly by the epoxy adhesive. May be. In the first and second embodiments, the ceramic substrate formed between the first and second metal layers is made of Al 2 O 3 , but this is only an example and is made of AlN or SiC. You may form.
【0020】また、上記第1及び第2実施例では第1金
属層、第2金属層及びセラミック基板の厚さをそれぞれ
0.4mm、0.2mm及び0.635mmに形成した
が、第1金属層の厚さは0.1〜1.0mmの範囲内に
あればよく、第2金属層の厚さは第1金属層の厚さの2
/3以下であって0〜0.5mmの範囲内にあればよ
く、更にセラミック基板の厚さは第1金属層の厚さの1
〜10倍であって0.1〜1.0mmの範囲内にあれば
よい。従って、図7に示すように第2金属層を用いずに
セラミック基板18の裏面に直接フィン本体19をAl
系ろう材を介して接着してもよい。この場合、フィン本
体19のセラミック基板18への接着部が第2金属層の
役割を果たす。上記のように厚さを限定したのは、第1
金属層の厚さが0.1mm未満であるとチップにて発生
した熱の放熱性が十分でなく、第1及び第2金属層の厚
さがそれぞれ1.0mm及び0.5mmを越えると接着
後の応力緩和時のクラック、割れが生じ易くなるためで
ある。またセラミック基板の厚さが0.1mm未満であ
ると絶縁特性及び機械的強度に劣り、1.0mmを越え
るとAl2O3の場合は熱抵抗が大きくなる問題点がある
ためである。しかしアルミニウムと同等な高熱伝導性を
有するセラミックスであるAlNやSiCを用いた場合
はこの限りではない。更に、上記第1及び第2実施例で
はAl系ろう材としてAl−7.5%Si箔を例示した
が、これ以外にAl−13%Si、Al−9.5%Si
−1.0%Mg、Al−7.5%Si−10%Ge等か
らなる箔を用いることもできる。In the first and second embodiments, the thicknesses of the first metal layer, the second metal layer and the ceramic substrate are 0.4 mm, 0.2 mm and 0.635 mm, respectively. The thickness of the layer may be in the range of 0.1 to 1.0 mm, and the thickness of the second metal layer is 2 times the thickness of the first metal layer.
The thickness of the ceramic substrate is less than or equal to / 3 and is within the range of 0 to 0.5 mm.
It may be 10 times and 0.1 to 1.0 mm. Therefore, as shown in FIG. 7, the fin body 19 is directly formed on the back surface of the ceramic substrate 18 without using the second metal layer.
You may adhere | attach via a brazing material. In this case, the adhesion portion of the fin body 19 to the ceramic substrate 18 serves as the second metal layer. The thickness is limited as described above
If the thickness of the metal layer is less than 0.1 mm, the heat dissipation performance of the heat generated in the chip is not sufficient, and if the thickness of the first and second metal layers exceeds 1.0 mm and 0.5 mm, respectively, the adhesion occurs. This is because cracks and fractures are likely to occur during subsequent stress relaxation. If the thickness of the ceramic substrate is less than 0.1 mm, the insulation properties and mechanical strength will be poor, and if it exceeds 1.0 mm, the thermal resistance will increase in the case of Al 2 O 3 . However, this is not the case when AlN or SiC, which is a ceramic having high thermal conductivity equivalent to that of aluminum, is used. Further, although Al-7.5% Si foil is exemplified as the Al-based brazing material in the first and second embodiments, other than this, Al-13% Si and Al-9.5% Si foils are used.
A foil made of -1.0% Mg, Al-7.5% Si-10% Ge, etc. can also be used.
【0021】[0021]
【発明の効果】以上述べたように、本発明によれば、表
面にチップを実装したセラミック回路基板の裏面に、ア
ルミニウム材からなる第1金属層、セラミック基板、ア
ルミニウム材からなる第2金属層及びフィン本体をこの
順にそれぞれAl系ろう材を介して積層接着したので、
フィン本体とセラミック基板との熱膨張係数の差による
熱変形を変形抵抗の小さい第1及び第2金属層により吸
収できる。また放熱フィンのベース部分であるセラミッ
ク基板をセラミック回路基板と略同等の熱膨張係数を有
する材料により形成したので、放熱フィンをセラミック
回路基板に直接接着しても、熱サイクルにより剥がれを
生ずることはない。またAlNにより形成されたフィン
本体を有する従来の放熱フィンと比較して、本発明では
フィン本体の加工工数を低減でき、フィン本体に衝撃が
作用しても破損し難く、更にフィン本体の放熱特性を向
上できる。As described above, according to the present invention, the first metal layer made of an aluminum material, the ceramic substrate, and the second metal layer made of an aluminum material are formed on the back surface of the ceramic circuit board on which the chip is mounted. Since the fin body and the fin body are laminated and adhered in this order through the Al-based brazing material,
The thermal deformation due to the difference in thermal expansion coefficient between the fin body and the ceramic substrate can be absorbed by the first and second metal layers having low deformation resistance. Further, since the ceramic substrate, which is the base portion of the heat radiation fin, is made of a material having a coefficient of thermal expansion substantially equal to that of the ceramic circuit board, even if the heat radiation fin is directly adhered to the ceramic circuit board, peeling does not occur due to thermal cycles. Absent. Further, as compared with the conventional heat dissipating fin having a fin body formed of AlN, the present invention can reduce the number of man-hours for processing the fin body, are less likely to be damaged even when an impact is applied to the fin body, and further dissipate heat of the fin body. Can be improved.
【0022】またセラミック回路基板に半導体チップを
実装した後でも、半導体チップやセラミック回路基板の
既にはんだ付けされた箇所が溶け剥がれることなくセラ
ミック回路基板に放熱フィンを接着できる。またセラミ
ック基板のチップに対向する位置に複数の熱伝導用スル
ーホールを設け、これらのスルーホールにアルミニウム
材をそれぞれ充填すれば、第1金属層の熱がアルミニウ
ム材を通ってよりスムーズに第2金属層又はフィン本体
に伝わる。更にセラミック回路基板に実装したチップの
外面に、アルミニウム材からなる第1金属層、セラミッ
ク基板、アルミニウム材からなる第2金属層及びフィン
本体をこの順にそれぞれAl系ろう材を介して積層接着
しても、上記と同様の効果が得られる。Further, even after the semiconductor chip is mounted on the ceramic circuit board, the radiation fins can be bonded to the ceramic circuit board without melting and peeling off the already soldered portions of the semiconductor chip and the ceramic circuit board. If a plurality of through holes for heat conduction are provided at positions facing the chip of the ceramic substrate, and these through holes are filled with aluminum materials, respectively, the heat of the first metal layer passes through the aluminum materials and the second heat is smoothly transferred. It is transmitted to the metal layer or the fin body. Further, a first metal layer made of an aluminum material, a ceramic substrate, a second metal layer made of an aluminum material, and a fin body are laminated and adhered in this order on the outer surface of the chip mounted on the ceramic circuit board through an Al-based brazing material. Also, the same effect as described above can be obtained.
【図1】本発明第1実施例の放熱フィンを含むセラミッ
ク回路基板の断面図。FIG. 1 is a sectional view of a ceramic circuit board including a radiation fin according to a first embodiment of the present invention.
【図2】図1のA矢視図。FIG. 2 is a view on arrow A in FIG.
【図3】本発明の第2実施例を示す図1に対応する断面
図。FIG. 3 is a sectional view corresponding to FIG. 1 showing a second embodiment of the present invention.
【図4】本発明の第3実施例を示すフィン本体の断面
図。FIG. 4 is a sectional view of a fin body showing a third embodiment of the present invention.
【図5】本発明の第4実施例を示す図4に対応する断面
図。FIG. 5 is a sectional view corresponding to FIG. 4, showing a fourth embodiment of the present invention.
【図6】本発明の第5実施例を示す図1に対応する断面
図。FIG. 6 is a sectional view corresponding to FIG. 1 showing a fifth embodiment of the present invention.
【図7】本発明の第6実施例を示す図1に対応する断面
図。FIG. 7 is a sectional view corresponding to FIG. 1 showing a sixth embodiment of the present invention.
11,79,99 放熱フィン 12 シリコン半導体チップ 13 薄膜多層セラミック回路基板 18 セラミック基板 19 フィン本体 21 第1金属層 22 第2金属層 111 熱伝導用スルーホール 112 アルミニウム材 11, 79, 99 Heat dissipation fin 12 Silicon semiconductor chip 13 Thin film multilayer ceramic circuit board 18 Ceramic substrate 19 Fin body 21 First metal layer 22 Second metal layer 111 Heat conduction through hole 112 Aluminum material
Claims (7)
回路基板(13)の裏面にはんだ又は接着剤を介して直接接
着される放熱フィン(11)であって、 前記セラミック回路基板(13)の裏面を被覆可能な面積を
有するアルミニウム材からなる第1金属層(21)と、前記
第1金属層(21)を被覆可能な面積を有するセラミック基
板(18)と、前記セラミック基板(18)を被覆可能な面積を
有するアルミニウム材からなる第2金属層(22)と、前記
第2金属層(22)を被覆可能な面積を有するアルミニウム
材からなるフィン本体(19)とがそれぞれAl系ろう材を
介してこの順に積層接着されたことを特徴とする放熱フ
ィン。1. A radiating fin (11) directly bonded to the back surface of a ceramic circuit board (13) having a chip (12) mounted on the front surface through a solder or an adhesive, the ceramic circuit board (13) A first metal layer (21) made of an aluminum material having an area capable of covering the back surface of the ceramic substrate, a ceramic substrate (18) having an area capable of coating the first metal layer (21), and the ceramic substrate (18) The second metal layer (22) made of an aluminum material having an area capable of coating the aluminum and the fin body (19) made of an aluminum material having an area capable of coating the second metal layer (22) are each made of an Al-based solder. A radiating fin characterized by being laminated and adhered in this order through a material.
回路基板(13)の裏面にはんだ又は接着剤を介して直接接
着される放熱フィン(11)であって、 前記セラミック回路基板(13)の裏面を被覆可能な面積を
有するアルミニウム材からなる第1金属層(21)と、前記
第1金属層(21)を被覆可能な面積を有するセラミック基
板(18)と、前記セラミック基板(18)を被覆可能な面積を
有するアルミニウム材からなるフィン本体(19)とがそれ
ぞれAl系ろう材を介してこの順に積層接着された請求
項1記載の放熱フィン。2. A heat dissipation fin (11) directly bonded to the back surface of a ceramic circuit board (13) having a chip (12) mounted on the front surface via solder or an adhesive, the ceramic circuit board (13) A first metal layer (21) made of an aluminum material having an area capable of covering the back surface of the ceramic substrate, a ceramic substrate (18) having an area capable of coating the first metal layer (21), and the ceramic substrate (18) The radiating fin according to claim 1, wherein a fin body (19) made of an aluminum material having an area capable of covering the above is laminated and adhered in this order via an Al-based brazing material.
プ(12)の外面にはんだ又は接着剤を介して直接接着され
る放熱フィン(11)であって、 前記チップ(12)の外面を被覆可能な面積を有するアルミ
ニウム材からなる第1金属層(21)と、前記第1金属層(2
1)を被覆可能な面積を有するセラミック基板(18)と、前
記セラミック基板(18)を被覆可能な面積を有するアルミ
ニウム材からなる第2金属層(22)と、前記第2金属層(2
2)を被覆可能な面積を有するアルミニウム材からなるフ
ィン本体(19)とがそれぞれAl系ろう材を介してこの順
に積層接着されたことを特徴とする放熱フィン。3. A radiation fin (11) directly bonded to the outer surface of a chip (12) mounted on a ceramic circuit board (13) via a solder or an adhesive, and covering the outer surface of the chip (12). A first metal layer (21) made of an aluminum material having a possible area, and the first metal layer (2)
(1) a ceramic substrate (18) having an area capable of coating, a second metal layer (22) made of an aluminum material having an area capable of coating the ceramic substrate (18), and the second metal layer (2)
A radiating fin characterized in that the fin body (19) made of an aluminum material having an area capable of covering 2) is laminated and adhered in this order via an Al-based brazing material.
プ(12)の外面にはんだ又は接着剤を介して直接接着され
る放熱フィン(11)であって、 前記チップ(12)の外面を被覆可能な面積を有するアルミ
ニウム材からなる第1金属層(21)と、前記第1金属層(2
1)を被覆可能な面積を有するセラミック基板(18)と、前
記セラミック基板(18)を被覆可能な面積を有するアルミ
ニウム材からなるフィン本体(19)とがそれぞれAl系ろ
う材を介してこの順に積層接着された請求項3記載の放
熱フィン。4. A heat radiation fin (11) directly bonded to the outer surface of a chip (12) mounted on a ceramic circuit board (13) via a solder or an adhesive, and covering the outer surface of the chip (12). A first metal layer (21) made of an aluminum material having a possible area, and the first metal layer (2)
The ceramic substrate (18) having an area capable of coating 1) and the fin body (19) made of an aluminum material having an area capable of coating the ceramic substrate (18) are respectively arranged in this order via an Al-based brazing material. The radiation fin according to claim 3, which is laminated and adhered.
する位置に複数の熱伝導用スルーホール(111)が設けら
れ、前記複数の熱伝導用スルーホール(111)にアルミニ
ウム材(112)がそれぞれ充填された請求項1ないし4い
ずれか記載の放熱フィン。5. A plurality of heat conduction through holes (111) are provided at positions of the ceramic substrate (18) facing the chips (12), and the plurality of heat conduction through holes (111) are made of an aluminum material (112). ) The radiation fins according to any one of claims 1 to 4, each of which is filled with.
の厚さの2/3以下である請求項1ないし5いずれか記
載の放熱フィン。6. The thickness of the second metal layer (22) is the first metal layer (21).
The radiating fin according to any one of claims 1 to 5, wherein the radiating fin has a thickness of ⅔ or less.
ルゲートフィンであって、前記フィン本体(99)が前記凸
条(99a)に直交する方向に切断することにより複数分割
された請求項1ないし6いずれか記載の放熱フィン。7. The fin body (99) is a corrugated fin having ridges (99a), and the fin body (99) is divided into a plurality of pieces by cutting in a direction orthogonal to the ridges (99a). The radiation fin according to any one of claims 1 to 6.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16372594A JP3139523B2 (en) | 1994-07-15 | 1994-07-15 | Radiation fin |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16372594A JP3139523B2 (en) | 1994-07-15 | 1994-07-15 | Radiation fin |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0831990A true JPH0831990A (en) | 1996-02-02 |
JP3139523B2 JP3139523B2 (en) | 2001-03-05 |
Family
ID=15779484
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16372594A Expired - Fee Related JP3139523B2 (en) | 1994-07-15 | 1994-07-15 | Radiation fin |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP3139523B2 (en) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006004961A (en) * | 2004-06-15 | 2006-01-05 | Hitachi Ltd | Semiconductor module |
JP2008177622A (en) * | 2008-04-14 | 2008-07-31 | Denki Kagaku Kogyo Kk | Module structure |
JP2008288411A (en) * | 2007-05-18 | 2008-11-27 | Calsonic Kansei Corp | Heat dissipator |
JPWO2008078788A1 (en) * | 2006-12-26 | 2010-04-30 | 京セラ株式会社 | Heat dissipation board and electronic device using the same |
JP2013115202A (en) * | 2011-11-28 | 2013-06-10 | Toyota Industries Corp | Semiconductor device |
WO2023149774A1 (en) * | 2022-02-07 | 2023-08-10 | 주식회사 아모그린텍 | Ceramic substrate unit and manufacturing method therefor |
WO2023163423A1 (en) * | 2022-02-23 | 2023-08-31 | 주식회사 아모그린텍 | Ceramic substrate unit and method for manufacturing same |
-
1994
- 1994-07-15 JP JP16372594A patent/JP3139523B2/en not_active Expired - Fee Related
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006004961A (en) * | 2004-06-15 | 2006-01-05 | Hitachi Ltd | Semiconductor module |
JPWO2008078788A1 (en) * | 2006-12-26 | 2010-04-30 | 京セラ株式会社 | Heat dissipation board and electronic device using the same |
JP5202333B2 (en) * | 2006-12-26 | 2013-06-05 | 京セラ株式会社 | Heat dissipation board and electronic device using the same |
JP2008288411A (en) * | 2007-05-18 | 2008-11-27 | Calsonic Kansei Corp | Heat dissipator |
JP2008177622A (en) * | 2008-04-14 | 2008-07-31 | Denki Kagaku Kogyo Kk | Module structure |
JP4692908B2 (en) * | 2008-04-14 | 2011-06-01 | 電気化学工業株式会社 | Module structure |
JP2013115202A (en) * | 2011-11-28 | 2013-06-10 | Toyota Industries Corp | Semiconductor device |
WO2023149774A1 (en) * | 2022-02-07 | 2023-08-10 | 주식회사 아모그린텍 | Ceramic substrate unit and manufacturing method therefor |
WO2023163423A1 (en) * | 2022-02-23 | 2023-08-31 | 주식회사 아모그린텍 | Ceramic substrate unit and method for manufacturing same |
Also Published As
Publication number | Publication date |
---|---|
JP3139523B2 (en) | 2001-03-05 |
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